Skip to content
Snippets Groups Projects
Commit c80eb3ab authored by Sergi Hernandez's avatar Sergi Hernandez
Browse files

Added the usart communication module for the F4 family.

parent 98ac3e1e
No related branches found
No related tags found
No related merge requests found
#ifndef USART1_F4_H
#define USART1_F4_H
#include "comm.h"
/* public functions */
void usart1_init(TComm *comm_dev);
#endif
#ifndef USART2_F4_H
#define USART2_F4_H
#include "usart_common.h"
#include "comm.h"
/* public functions */
void usart2_init(TComm *comm_dev,TUSART_IRQ_Priorities *priorities);
/* IRQ functions */
unsigned char usart2_send_irq(unsigned char *data,unsigned int length);
unsigned char usart2_receive_irq(unsigned int length);
unsigned char usart2_cancel_receive_irq(void);
/* DMA functions */
unsigned char usart2_send_dma(unsigned char *data,unsigned int lenght);
unsigned char usart2_receive_dma(unsigned int length);
unsigned char usart2_cancel_receive_dma(void);
#endif
#ifndef USART_COMMON_F4_H
#define USART_COMMON_F4_H
typedef struct
{
unsigned char irq_priority;
unsigned char irq_subpriority;
unsigned char dma_rx_priority;
unsigned char dma_rx_subpriority;
unsigned char dma_tx_priority;
unsigned char dma_tx_subpriority;
}TUSART_IRQ_Priorities;
#endif
#include "usart1.h"
/* public functions*/
void usart1_init(TComm *comm_dev)
{
}
#include "usart2.h"
#define USART USART2
#define USART_CLK RCC_APB1Periph_USART2
#define USART_CLK_INIT RCC_APB1PeriphClockCmd
#define USART_IRQn USART2_IRQn
#define USART_IRQHandler USART2_IRQHandler
#define USART_TX_PIN GPIO_Pin_2
#define USART_TX_GPIO_PORT GPIOA
#define USART_TX_GPIO_CLK RCC_AHB1Periph_GPIOA
#define USART_TX_SOURCE GPIO_PinSource2
#define USART_TX_AF GPIO_AF_USART2
#define USART_RX_PIN GPIO_Pin_3
#define USART_RX_GPIO_PORT GPIOA
#define USART_RX_GPIO_CLK RCC_AHB1Periph_GPIOA
#define USART_RX_SOURCE GPIO_PinSource3
#define USART_RX_AF GPIO_AF_USART2
#define USART_DMA DMA1
#define USART_DMA_CLK RCC_AHB1Periph_DMA1
#define USART_TX_DMA_CHANNEL DMA_Channel_4
#define USART_TX_DMA_STREAM DMA1_Stream6
#define USART_TX_DMA_FLAG_FEIF DMA_FLAG_FEIF6
#define USART_TX_DMA_FLAG_DMEIF DMA_FLAG_DMEIF6
#define USART_TX_DMA_FLAG_TEIF DMA_FLAG_TEIF6
#define USART_TX_DMA_FLAG_HTIF DMA_FLAG_HTIF6
#define USART_TX_DMA_FLAG_TCIF DMA_FLAG_TCIF6
#define USART_RX_DMA_CHANNEL DMA_Channel_4
#define USART_RX_DMA_STREAM DMA1_Stream5
#define USART_RX_DMA_FLAG_FEIF DMA_FLAG_FEIF5
#define USART_RX_DMA_FLAG_DMEIF DMA_FLAG_DMEIF5
#define USART_RX_DMA_FLAG_TEIF DMA_FLAG_TEIF5
#define USART_RX_DMA_FLAG_HTIF DMA_FLAG_HTIF5
#define USART_RX_DMA_FLAG_TCIF DMA_FLAG_TCIF5
#define USART_DMA_TX_IRQn DMA1_Stream6_IRQn
#define USART_DMA_RX_IRQn DMA1_Stream5_IRQn
#define USART_DMA_TX_IRQHandler DMA1_Stream6_IRQHandler
#define USART_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler
// private variables
DMA_InitTypeDef DMA_TX_InitStructure;
DMA_InitTypeDef DMA_RX_InitStructure;
TComm *usart2_comm_dev;
// interrupt handlers
void USART_IRQHandler(void)
{
unsigned char data;
if(USART_GetITStatus(USART, USART_IT_RXNE) != RESET)
{
USART_ClearFlag(USART,USART_FLAG_RXNE);
data=USART_ReceiveData(USART);
// call the reception function
if(!comm_do_irq_receive(usart2_comm_dev,data))
USART_ITConfig(USART, USART_IT_RXNE, DISABLE);
}
if(USART_GetITStatus(USART, USART_IT_TC) != RESET)
{
USART_ClearFlag(USART,USART_FLAG_TC);
if(comm_do_irq_send(usart2_comm_dev,&data))
USART_SendData(USART,data);
else
USART_ITConfig(USART, USART_IT_TC, DISABLE);
}
if(USART_GetITStatus(USART,USART_FLAG_ORE) != RESET)// overrun error
{
// cancel any pending reception
USART_ITConfig(USART, USART_IT_RXNE, DISABLE);
usart2_comm_dev->irq_receiving=0x00;
}
if(USART_GetITStatus(USART,USART_IT_PE) != RESET)// parity error
{
// cancel any pending reception
USART_ITConfig(USART, USART_IT_RXNE, DISABLE);
usart2_comm_dev->irq_receiving=0x00;
}
}
void USART_DMA_TX_IRQHandler(void)
{
DMA_Cmd(USART_TX_DMA_STREAM,DISABLE);
DMA_ClearFlag(USART_TX_DMA_STREAM,USART_TX_DMA_FLAG_TCIF);
DMA_ClearITPendingBit(USART_TX_DMA_STREAM,USART_TX_DMA_FLAG_TCIF);
USART_DMACmd(USART, USART_DMAReq_Tx, DISABLE);
// call the user function
}
void USART_DMA_RX_IRQHandler(void)
{
DMA_Cmd(USART_RX_DMA_STREAM,DISABLE);
DMA_ClearFlag(USART_RX_DMA_STREAM,USART_RX_DMA_FLAG_TCIF);
DMA_ClearITPendingBit(USART_RX_DMA_STREAM,USART_RX_DMA_FLAG_TCIF);
USART_DMACmd(USART, USART_DMAReq_Rx, DISABLE);
// call the user function
}
/* public functions*/
void usart2_init(TComm *comm_dev,TUSART_IRQ_Priorities *priorities)
{
GPIO_InitTypeDef GPIO_InitStructure;
NVIC_InitTypeDef NVIC_InitStructure;
/* Enable GPIO clock */
USART_CLK_INIT(USART_CLK, ENABLE);
USART_TX_GPIO_CLK(USART_TX_GPIO_CLK,ENABLE)
USART_RX_GPIO_CLK(USART_RX_GPIO_CLK,ENABLE);
/* Connect USART pins to AF7 */
GPIO_PinAFConfig(USART_TX_GPIO_PORT, USART_TX_SOURCE, USART_TX_AF);
GPIO_PinAFConfig(USART_RX_GPIO_PORT, USART_RX_SOURCE, USART_RX_AF);
/* Configure USART Tx and Rx as alternate function push-pull */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_InitStructure.GPIO_Pin = USART_TX_PIN;
GPIO_Init(USART_TX_GPIO_PORT, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = USART_RX_PIN;
GPIO_Init(USART_RX_GPIO_PORT, &GPIO_InitStructure);
/* configure the interrupts */
NVIC_InitStructure.NVIC_IRQChannel = USART_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = priorities->irq_priority;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = priorities->irq_subpriority;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
USART_ITConfig(USART, USART_IT_RXNE |
USART_IT_ORE |
USART_IT_TXE |
USART_IT_CTS |
USART_IT_LBD |
USART_IT_IDLE |
USART_IT_PE |
USART_IT_ERR |
USART_IT_TC, DISABLE);
/* Clear all USART interrupt flags */
USART_ClearFlag(USART,USART_FLAG_RXNE |
USART_FLAG_ORE |
USART_FLAG_TXE |
USART_FLAG_CTS |
USART_FLAG_LBD |
USART_FLAG_IDLE |
USART_FLAG_PE |
USART_FLAG_TC);
/* Clear all USART interrupt pending bits */
USART_ClearITPendingBit(USART, USART_FLAG_RXNE |
USART_FLAG_ORE |
USART_FLAG_TXE |
USART_FLAG_CTS |
USART_FLAG_LBD |
USART_FLAG_IDLE |
USART_FLAG_PE |
USART_FLAG_TC);
// configure the DMA channels
if(comm_dev->use_dma)
{
/* enable the DMA clock */
USART_DMA_CLK(USART_DMA_CLK, ENABLE);
/* Configure TX DMA */
DMA_DeInit(USART_TX_DMA_STREAM);
DMA_TX_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
DMA_TX_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
DMA_TX_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
DMA_TX_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_TX_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_TX_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_TX_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) (&(USART->DR));
DMA_TX_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
DMA_TX_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_TX_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_TX_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_TX_InitStructure.DMA_Channel = USART_TX_DMA_CHANNEL;
DMA_TX_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
/* initialize DMA interrupts */
NVIC_InitStructure.NVIC_IRQChannel = USART_DMA_TX_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = priorities->dma_tx_priority;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = priorities->dma_tx_subpriority;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
DMA_ITConfig(USART_TX_DMA_STREAM,DMA_IT_TC,ENABLE);
DMA_ITConfig(USART_TX_DMA_STREAM,DMA_IT_HT | DMA_IT_TE | DMA_IT_FE | DMA_IT_DME,DISABLE);
/* Configure RX DMA */
DMA_DeInit(USART_RX_DMA_STREAM);
DMA_RX_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
DMA_RX_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
DMA_RX_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
DMA_RX_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_RX_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_RX_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_RX_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) (&(USART->DR));
DMA_RX_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
DMA_RX_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_RX_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_RX_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_RX_InitStructure.DMA_Channel = USART_RX_DMA_CHANNEL;
DMA_RX_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
/* initialize DMA interrupts */
NVIC_InitStructure.NVIC_IRQChannel = USART_DMA_RX_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = priorities->dma_rx_priority;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = priority->dma_rx_subpriority;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
DMA_ITConfig(USART_RX_DMA_STREAM,DMA_IT_TC,ENABLE);
DMA_ITConfig(USART_RX_DMA_STREAM,DMA_IT_HT | DMA_IT_TE | DMA_IT_FE | DMA_IT_DME,DISABLE);
}
/* Initialize the comm structure */
comm_dev->receive=usart2_receive;
comm_dev->send_irq=usart2_send_irq;
comm_dev->receive_irq=usart2_receive_irq;
comm_dev->cancel_receive_irq=usart2_cancel_receive_irq;
if(comm_dev->use_dma)
{
comm_dev->send_dma=usart2_send_dma;
comm_dev->receive_dma=usart2_receive_dma;
comm_dev->cancel_receive_dma=usart2_cancel_receive_dma;
}
comm_dev->irq_send_cb=0x00000000;
comm_dev->irq_receive_cb=0x00000000;
comm_dev->dma_send_cb=0x00000000;
comm_dev->dma_receive_cb=0x00000000;
/* initialize internal variables */
usart2_comm_dev=comm_dev;
/* Enable the USART2 */
USART_Cmd(USART, ENABLE);
}
/* IRQ functions */
unsigned char usart2_send_irq(unsigned char *data,unsigned int length)
{
}
unsigned char usart2_receive_irq(unsigned int length)
{
}
unsigned char usart2_cancel_receive_irq(void)
{
}
/* DMA functions */
unsigned char usart2_send_dma(unsigned char *data,unsigned int lenght)
{
}
unsigned char usart2_receive_dma(unsigned int length)
{
}
unsigned char usart2_cancel_receive_dma(void)
{
}
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment