Added the _SIM macro to avoid some simulation build warnings.

f4/include/core/core_cm4.h

@@ -1910,7 +1910,11 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
  */
 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
 {
+  #ifndef _SIM
   uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  #else
+  uint32_t *vectors = (uint32_t *)&SCB->VTOR;
+  #endif
   vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
   /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
 }
@@ -1926,7 +1930,11 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
  */
 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
 {
+  #ifndef _SIM
   uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  #else
+  uint32_t *vectors = (uint32_t *)&SCB->VTOR;
+  #endif
   return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
 }
 

f4/include/devices/stm32f4xx.h

@@ -216,8 +216,10 @@ typedef enum
 
 #define CLEAR_REG(REG)        ((REG) = (0x0))
 
-#ifndef WRITE_REG
+#ifndef _SIM 
   #define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+#else
+  #define WRITE_REG(REG, VAL)
 #endif
 
 #define READ_REG(REG)         ((REG))

f4/include/stm32f4xx_hal_pcd.h

@@ -203,9 +203,12 @@ typedef struct
 #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \
   *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
 
-#ifndef __HAL_PCD_GATE_PHYCLOCK
-  #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \
-    *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
+#ifndef _SIM
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \
+  *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
+#else
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \
+  *(__IO uint32_t *)(((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
 #endif
 
 #define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \

f4/include/stm32f4xx_ll_adc.h

@@ -293,9 +293,12 @@ extern "C" {
   * @param  __REG_OFFFSET__ Offset to be applied (unit number of registers).
   * @retval Pointer to register address
   */
-#ifndef __ADC_PTR_REG_OFFSET
+#ifndef _SIM
   #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
    ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
+#else
+  #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
+   ((__IO uint32_t *)(((&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
 #endif
 
 /**
@@ -1868,12 +1871,20 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis
   if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
   {
     /* Retrieve address of register DR */
+    #ifndef _SIM
     data_reg_addr = (uint32_t) & (ADCx->DR);
+    #else
+    data_reg_addr = (uint32_t)(ADCx->DR);
+    #endif
   }
   else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
   {
     /* Retrieve address of register CDR */
+    #ifndef _SIM
     data_reg_addr = (uint32_t) & ((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
+    #else
+    data_reg_addr = (uint32_t) ((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
+    #endif
   }
 
   return data_reg_addr;