Updated the ADC module to be compliant with the new version.

include/adc_dma.h

@@ -6,15 +6,29 @@ extern "C" {
 #endif
 
 #include "stm32f1xx.h"
-#include "adc_dma_registers.h"
 #include "memory.h"
+#include "scheduler.h"
 
 #define      ADC_NUM_CHANNELS      12
 
 typedef enum {ADC_CH1=0,ADC_CH2=1,ADC_CH3=2,ADC_CH4=3,ADC_CH5=4,ADC_CH6=5,ADC_CH7=6,ADC_CH8=7,
               ADC_CH9=8,ADC_CH10=9,ADC_CH12=10} adc_ch_t;
 
-uint8_t adc_init(TMemory *memory);
+typedef struct
+{
+  ADC_HandleTypeDef handle1;
+  ADC_HandleTypeDef handle2;
+  DMA_HandleTypeDef dma_handle;
+  TScheduler *scheduler;
+  /* memory module */
+  TMemory *memory;
+  TMemModule mem_module;
+  unsigned short int ram_base_address;
+  unsigned short int eeprom_base_address;
+  uint32_t data[6];// temporal buffer to store ADC data before conversion
+}TADC;
+
+uint8_t adc_init(TMemory *memory,TScheduler *scheduler,unsigned short int eeprom_base_address,unsigned short int ram_base_address);
 void adc_start(void);
 void adc_set_period(uint8_t period_ms);
 uint8_t adc_get_period(void);

include/adc_dma_registers.h

 #ifndef _ADC_DMA_REGISTERS_H
 #define _ADC_DMA_REGISTERS_H
 
-#ifndef RAM_ADC_DMA_BASE_ADDRESS
-  #define RAM_ADC_DMA_BASE_ADDRESS            ((unsigned short int)0x0000)
-#endif
+#define EEPROM_ADC_DMA_LENGTH                 1
+
+#define ADC_PERIOD_OFFSET                     0
+
+#define adc_eeprom_data(name,section_name,base_address,DEFAULT_PERIOD) \
+unsigned short int name##_eeprom_data[] __attribute__ ((section (section_name))) __attribute__ ((aligned (4)))={ \
+  DEFAULT_PERIOD&0x00FF,base_address+ADC_PERIOD_OFFSET \
+};
 
-#define RAM_ADC_DMA_LENGTH                    26
+#define RAM_ADC_DMA_LENGTH                    25
 
-#define ADC_CNTRL                             RAM_ADC_DMA_BASE_ADDRESS// bit 7 | bit 6 | bit 5 | bit 4 | bit 3 | bit 2 | bit 1 | bit 0
-                                                                      //       |       |       |       |       |       |       | Enable
-#define ADC_PERIOD                            (RAM_ADC_DMA_BASE_ADDRESS+1)
-#define ADC_CH1_VOLTAGE                       (RAM_ADC_DMA_BASE_ADDRESS+2)
-#define ADC_CH2_VOLTAGE                       (RAM_ADC_DMA_BASE_ADDRESS+4)
-#define ADC_CH3_VOLTAGE                       (RAM_ADC_DMA_BASE_ADDRESS+6)
-#define ADC_CH4_VOLTAGE                       (RAM_ADC_DMA_BASE_ADDRESS+8)
-#define ADC_CH5_VOLTAGE                       (RAM_ADC_DMA_BASE_ADDRESS+10)
-#define ADC_CH6_VOLTAGE                       (RAM_ADC_DMA_BASE_ADDRESS+12)
-#define ADC_CH7_VOLTAGE                       (RAM_ADC_DMA_BASE_ADDRESS+14)
-#define ADC_CH8_VOLTAGE                       (RAM_ADC_DMA_BASE_ADDRESS+16)
-#define ADC_CH9_VOLTAGE                       (RAM_ADC_DMA_BASE_ADDRESS+18)
-#define ADC_CH10_VOLTAGE                      (RAM_ADC_DMA_BASE_ADDRESS+20)
-#define ADC_TEMP                              (RAM_ADC_DMA_BASE_ADDRESS+22)
-#define ADC_CH12_VOLTAGE                      (RAM_ADC_DMA_BASE_ADDRESS+24)
+#define ADC_CONTROL_OFFSET                    0// bit 7 | bit 6 | bit 5 |  bit 4  | bit 3 | bit 2 | bit 1 | bit 0
+                                               //       |       |       | running |       |       | stop  | start 
 
 #define ADC_START                             0x01
 #define ADC_STOP                              0x02
 #define ADC_RUNNING                           0x10
+#define ADC_CH1_VOLTAGE_OFFSET                1
+#define ADC_CH2_VOLTAGE_OFFSET                3
+#define ADC_CH3_VOLTAGE_OFFSET                5
+#define ADC_CH4_VOLTAGE_OFFSET                7
+#define ADC_CH5_VOLTAGE_OFFSET                9
+#define ADC_CH6_VOLTAGE_OFFSET                11
+#define ADC_CH7_VOLTAGE_OFFSET                13
+#define ADC_CH8_VOLTAGE_OFFSET                15
+#define ADC_CH9_VOLTAGE_OFFSET                17
+#define ADC_CH10_VOLTAGE_OFFSET               19
+#define ADC_TEMP_OFFSET                       21
+#define ADC_CH12_VOLTAGE_OFFSET               23
 
 #endif

include/darwin_conf.h

@@ -56,6 +56,10 @@
 /* IMU */
 #define RAM_IMU_MM_BASE_ADDRESS                ((unsigned short int)0x0188)
 
+/* ADC */
+#define RAM_ADC_DMA_BASE_ADDRESS               ((unsigned short int)0x0193)
+#define EEPROM_ADC_DMA_BASE_ADDRESS            ((unsigned short int)0x0007)
+
 /* EEPROM default values */
 /* Dynamixel slave */
 #define DARWIN_DEVICE_MODEL                    0x7300
@@ -123,5 +127,6 @@
 #define DEFAULT_WALK_L_ANKLE_ROLL_SERVO_ID     0x0012
 #define DEFAULT_WALK_L_SHOULDER_PITCH_SERVO_ID 0x0002
 
+#define DEFAULT_ADC_PERIOD                     0x000A
 
 #endif

src/CMakeLists.txt

@@ -2,8 +2,9 @@ SET(sources ${CMAKE_CURRENT_SOURCE_DIR}/cm730_fw.c
             ${CMAKE_CURRENT_SOURCE_DIR}/system_stm32f1xx.c
             #${CMAKE_CURRENT_SOURCE_DIR}/gpio.c
             ${CMAKE_CURRENT_SOURCE_DIR}/darwin_sch.c
+            ${CMAKE_CURRENT_SOURCE_DIR}/darwin_sch2.c
             ${CMAKE_CURRENT_SOURCE_DIR}/darwin_time.c
-            #${CMAKE_CURRENT_SOURCE_DIR}/adc_dma.c
+            ${CMAKE_CURRENT_SOURCE_DIR}/adc_dma.c
             ${CMAKE_CURRENT_SOURCE_DIR}/darwin_imu.c
             ${CMAKE_CURRENT_SOURCE_DIR}/darwin_dyn_slave.c
             ${CMAKE_CURRENT_SOURCE_DIR}/darwin_dyn_master.c

src/cm730_fw.c

@@ -2,6 +2,7 @@
 #include "darwin_conf.h"
 #include "memory.h"
 #include "darwin_sch.h"
+#include "darwin_sch2.h"
 #include "darwin_dyn_slave.h"
 #include "darwin_time.h"
 #include "eeprom.h"
@@ -9,10 +10,12 @@
 #include "darwin_motion.h"
 #include "darwin_imu.h"
 #include "darwin_balance.h"
+#include "adc_dma.h"
 
 TMemory *darwin_memory;
 TDynamixelMaster *dyn_master;
-TScheduler *scheduler;
+TScheduler *scheduler_low_priority;
+TScheduler *scheduler_high_priority;
 
 int main(void)
 {
@@ -25,22 +28,24 @@ int main(void)
   // initialize time module
   darwin_time_init();
   /* initialize the scheduler */
-  scheduler=darwin_sch_init();
+  scheduler_low_priority=darwin_sch_init();
+  scheduler_high_priority=darwin_sch2_init();
   /* initialize the GPIO module */
 //  gpio_init(&darwin_memory);
   // initialize adc
-//  adc_init(&darwin_memory);
+  adc_init(darwin_memory,scheduler_low_priority,EEPROM_ADC_DMA_BASE_ADDRESS,RAM_ADC_DMA_BASE_ADDRESS);
   /* initialize the dynamixel slave interface */
-  darwin_dyn_slave_init(&darwin_memory,scheduler);
+  darwin_dyn_slave_init(&darwin_memory,scheduler_high_priority);
   // initialize imu
   imu_init(darwin_memory,RAM_IMU_MM_BASE_ADDRESS);
   // initialize motion manager
-  darwin_mm_init(scheduler,darwin_memory);
+  darwin_mm_init(scheduler_low_priority,darwin_memory);
   /* initialize the ram module */
   ram_init(darwin_memory);
 
   darwin_dyn_slave_start();
 
-  while(1);/* main function does not return */
+  while(1)/* main function does not return */
+    HAL_Delay(1000);
 }