diff --git a/f2/include/Legacy/stm32_hal_legacy.h b/f2/include/Legacy/stm32_hal_legacy.h
new file mode 100644
index 0000000000000000000000000000000000000000..8b45b2c4cefe401d376972bf245cbdee2ec1ee83
--- /dev/null
+++ b/f2/include/Legacy/stm32_hal_legacy.h
@@ -0,0 +1,2940 @@
+/**
+ ******************************************************************************
+ * @file stm32_hal_legacy.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 09-October-2015
+ * @brief This file contains aliases definition for the STM32Cube HAL constants
+ * macros and functions maintained for legacy purpose.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_HAL_LEGACY
+#define __STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define AES_FLAG_RDERR CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP ADC_REGULAR_GROUP
+#define INJECTED_GROUP ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT ADC_AWD_EVENT
+#define AWD1_EVENT ADC_AWD1_EVENT
+#define AWD2_EVENT ADC_AWD2_EVENT
+#define AWD3_EVENT ADC_AWD3_EVENT
+#define OVR_EVENT ADC_OVR_EVENT
+#define JQOVF_EVENT ADC_JQOVF_EVENT
+#define ALL_CHANNELS ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+
+#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define DAC1_CHANNEL_1 DAC_CHANNEL_1
+#define DAC1_CHANNEL_2 DAC_CHANNEL_2
+#define DAC2_CHANNEL_1 DAC_CHANNEL_1
+#define DAC_WAVE_NONE ((uint32_t)0x00000000)
+#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
+#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
+#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW OB_IWDG_SW
+#define OB_WDG_HW OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
+/**
+ * @}
+ */
+
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+ * @{
+ */
+#if defined(STM32L4) || defined(STM32F7)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
+#else
+#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define GET_GPIO_SOURCE GPIO_GET_INDEX
+#define GET_GPIO_INDEX GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
+
+#if defined(STM32L1)
+ #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F3)
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F3 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define KR_KEY_RELOAD IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE IWDG_KEY_ENABLE
+#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define NAND_AddressTypedef NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE NOR_WRITE
+#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA ATA_DATA
+#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD ATA_CARD_HEAD
+#define CF_STATUS_CMD ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FORMAT_BIN RTC_FORMAT_BIN
+#define FORMAT_BCD RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
+/**
+ * @}
+ */
+
+
+ /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
+/**
+ * @}
+ */
+
+ /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1 TIM_DMABASE_CR1
+#define TIM_DMABase_CR2 TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER TIM_DMABASE_DIER
+#define TIM_DMABase_SR TIM_DMABASE_SR
+#define TIM_DMABase_EGR TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER TIM_DMABASE_CCER
+#define TIM_DMABase_CNT TIM_DMABASE_CNT
+#define TIM_DMABase_PSC TIM_DMABASE_PSC
+#define TIM_DMABase_ARR TIM_DMABASE_ARR
+#define TIM_DMABase_RCR TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1 TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2 TIM_DMABASE_OR2
+#define TIM_DMABase_OR3 TIM_DMABASE_OR3
+#define TIM_DMABase_OR TIM_DMABASE_OR
+
+#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
+
+#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED USART_NACK_ENABLE
+#define USARTNACK_DISABLED USART_NACK_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CFR_BASE WWDG_CFR_BASE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
+#define CAN_TXSTATUS_OK ((uint8_t)0x01)
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define VLAN_TAG ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR ((uint32_t)0x00000100)
+#define ETH_MMCRIR ((uint32_t)0x00000104)
+#define ETH_MMCTIR ((uint32_t)0x00000108)
+#define ETH_MMCRIMR ((uint32_t)0x0000010C)
+#define ETH_MMCTIMR ((uint32_t)0x00000110)
+#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C)
+#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150)
+#define ETH_MMCTGFCR ((uint32_t)0x00000168)
+#define ETH_MMCRFCECR ((uint32_t)0x00000194)
+#define ETH_MMCRFAECR ((uint32_t)0x00000198)
+#define ETH_MMCRGUFCR ((uint32_t)0x000001C4)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
+
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+ * @{
+ */
+#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
+
+#define DBP_BitNumber DBP_BIT_NUMBER
+#define PVDE_BitNumber PVDE_BIT_NUMBER
+#define PMODE_BitNumber PMODE_BIT_NUMBER
+#define EWUP_BitNumber EWUP_BIT_NUMBER
+#define FPDS_BitNumber FPDS_BIT_NUMBER
+#define ODEN_BitNumber ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
+#define BRE_BitNumber BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
+
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError TIM_DMAError
+#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+/**
+ * @}
+ */
+
+
+ /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define AES_IT_CC CRYP_IT_CC
+#define AES_IT_ERR CRYP_IT_ERR
+#define AES_FLAG_CCF CRYP_FLAG_CCF
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
+
+#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __ADC_ENABLE __HAL_ADC_ENABLE
+#define __ADC_DISABLE __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
+#define __ADC_IS_ENABLED ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1 ADC_SQR1
+#define __HAL_ADC_SMPR1 ADC_SMPR1
+#define __HAL_ADC_SMPR2 ADC_SMPR2
+#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32F3)
+#define COMP_START __HAL_COMP_ENABLE
+#define COMP_STOP __HAL_COMP_DISABLE
+#define COMP_LOCK __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F373xC) ||defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+# endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+ ((WAVE) == DAC_WAVE_NOISE)|| \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_WRPAREA IS_OB_WRPAREA
+#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE IS_FLASH_TYPEERASE
+#define IS_NBSECTORS IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
+#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
+#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
+#define __HAL_I2C_SPEED I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __IRDA_DISABLE __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
+#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+ * @{
+ */
+
+#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
+#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
+#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
+#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
+#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
+#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
+#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
+#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14 RCC_IT_HSI14RDY
+
+#if defined(STM32L0)
+#define RCC_IT_LSECSS RCC_IT_CSSLSE
+#define RCC_IT_CSS RCC_IT_CSSHSE
+#endif
+
+#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV RCC_MCODIV_1
+#define RCC_MCO_DIV1 RCC_MCODIV_1
+#define RCC_MCO_DIV2 RCC_MCODIV_2
+#define RCC_MCO_DIV4 RCC_MCODIV_4
+#define RCC_MCO_DIV8 RCC_MCODIV_8
+#define RCC_MCO_DIV16 RCC_MCODIV_16
+#define RCC_MCO_DIV32 RCC_MCODIV_32
+#define RCC_MCO_DIV64 RCC_MCODIV_64
+#define RCC_MCO_DIV128 RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
+
+#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB RCC_CR_HSION_BB
+#define CR_CSSON_BB RCC_CR_CSSON_BB
+#define CR_PLLON_BB RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB RCC_CR_MSION_BB
+#define CSR_LSION_BB RCC_CSR_LSION_BB
+#define CSR_LSEON_BB RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB RCC_CR_HSEON_BB
+#define CSR_RMVF_BB RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
+#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif /* STM32F1 */
+
+#define IS_ALARM IS_RTC_ALARM
+#define IS_ALARM_MASK IS_RTC_ALARM_MASK
+#define IS_TAMPER IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
+
+#if defined(STM32F4)
+#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
+#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
+#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
+#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
+#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
+#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
+#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
+#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
+#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
+#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
+#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
+#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
+#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
+#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
+#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
+#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
+#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
+#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
+#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define SDMMC1_IRQn SDIO_IRQn
+#define SDMMC1_IRQHandler SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
+#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
+#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
+#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
+#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
+#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
+#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
+#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
+#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
+#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
+#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
+#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
+#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
+#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
+#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
+#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
+#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define SDIO_IRQn SDMMC1_IRQn
+#define SDIO_IRQHandler SDMMC1_IRQHandler
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
+#define __USART_ENABLE __HAL_USART_ENABLE
+#define __USART_DISABLE __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
+
+#define TIM_TS_ITR0 ((uint32_t)0x0000)
+#define TIM_TS_ITR1 ((uint32_t)0x0010)
+#define TIM_TS_ITR2 ((uint32_t)0x0020)
+#define TIM_TS_ITR3 ((uint32_t)0x0030)
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3))
+
+#define TIM_CHANNEL_1 ((uint32_t)0x0000)
+#define TIM_CHANNEL_2 ((uint32_t)0x0004)
+#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
+
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
+ ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
+
+#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
+
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
+ ((STATE) == TIM_OUTPUTSTATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32_HAL_LEGACY */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/f2/include/core/core_cm3.h b/f2/include/core/core_cm3.h
index 0e215fc059e40459305625aadc9d53fd4777dbc3..d324f9b78764036c28bb07ab66099c2802fa87c8 100755
--- a/f2/include/core/core_cm3.h
+++ b/f2/include/core/core_cm3.h
@@ -1,13 +1,13 @@
/**************************************************************************//**
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
+ * @version V4.10
+ * @date 18. March 2015
*
* @note
*
******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
+/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -39,13 +39,13 @@
#pragma system_include /* treat file as system include file for MISRA check */
#endif
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
#ifdef __cplusplus
extern "C" {
#endif
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
@@ -68,8 +68,8 @@
*/
/* CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
__CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
@@ -81,6 +81,11 @@
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
@@ -90,19 +95,21 @@
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
#endif
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
*/
#define __FPU_USED 0
@@ -111,6 +118,11 @@
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
@@ -121,21 +133,25 @@
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __CORE_CM3_H_GENERIC */
#ifndef __CMSIS_GENERIC
@@ -143,6 +159,10 @@
#ifndef __CORE_CM3_H_DEPENDANT
#define __CORE_CM3_H_DEPENDANT
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM3_REV
@@ -212,13 +232,7 @@ typedef union
{
struct
{
-#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
@@ -228,6 +242,22 @@ typedef union
uint32_t w; /*!< Type used for word access */
} APSR_Type;
+/* APSR Register Definitions */
+#define APSR_N_Pos 31 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27 /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
@@ -241,6 +271,10 @@ typedef union
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
@@ -249,13 +283,7 @@ typedef union
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
@@ -267,6 +295,31 @@ typedef union
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
/** \brief Union type to access the Control Registers (CONTROL).
*/
@@ -276,12 +329,18 @@ typedef union
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
/*@} end of group CMSIS_CORE */
@@ -312,7 +371,7 @@ typedef struct
/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
/*@} end of group CMSIS_NVIC */
@@ -364,7 +423,7 @@ typedef struct
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
@@ -395,7 +454,7 @@ typedef struct
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
#if (__CM3_REV < 0x0201) /* core r2p1 */
@@ -429,7 +488,7 @@ typedef struct
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
@@ -458,7 +517,7 @@ typedef struct
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
@@ -501,7 +560,7 @@ typedef struct
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Registers Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
@@ -511,7 +570,7 @@ typedef struct
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* SCB Hard Fault Status Registers Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
@@ -537,7 +596,7 @@ typedef struct
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
/*@} end of group CMSIS_SCB */
@@ -563,7 +622,7 @@ typedef struct
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
/* Auxiliary Control Register Definitions */
@@ -574,7 +633,7 @@ typedef struct
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
@@ -606,15 +665,15 @@ typedef struct
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
@@ -624,7 +683,7 @@ typedef struct
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
@@ -675,7 +734,7 @@ typedef struct
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
@@ -703,19 +762,19 @@ typedef struct
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
/* ITM Integration Write Register Definitions */
#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
/* ITM Integration Read Register Definitions */
#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
/* ITM Integration Mode Control Register Definitions */
#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
@@ -725,7 +784,7 @@ typedef struct
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
@@ -818,31 +877,31 @@ typedef struct
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
/* DWT Comparator Mask Register Definitions */
#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
@@ -870,7 +929,7 @@ typedef struct
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
/*@}*/ /* end of group CMSIS_DWT */
@@ -913,11 +972,11 @@ typedef struct
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
@@ -930,7 +989,7 @@ typedef struct
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
@@ -941,7 +1000,7 @@ typedef struct
/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
/* TPI Integration ETM Data Register Definitions (FIFO0) */
#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
@@ -963,11 +1022,11 @@ typedef struct
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
@@ -989,15 +1048,15 @@ typedef struct
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
@@ -1016,15 +1075,15 @@ typedef struct
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
-
#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
/*@}*/ /* end of group CMSIS_TPI */
@@ -1060,7 +1119,7 @@ typedef struct
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
@@ -1070,11 +1129,11 @@ typedef struct
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
@@ -1084,7 +1143,7 @@ typedef struct
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
@@ -1115,7 +1174,7 @@ typedef struct
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
@@ -1172,14 +1231,14 @@ typedef struct
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register */
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register */
#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
@@ -1219,7 +1278,7 @@ typedef struct
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
/*@} end of group CMSIS_CoreDebug */
@@ -1291,13 +1350,13 @@ typedef struct
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
SCB->AIRCR = reg_value;
}
@@ -1310,7 +1369,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
*/
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
@@ -1322,7 +1381,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1334,7 +1393,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1350,7 +1409,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
@@ -1362,7 +1421,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1374,7 +1433,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1389,7 +1448,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
@@ -1404,10 +1463,12 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
- if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ if((int32_t)IRQn < 0) {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
}
@@ -1425,10 +1486,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ if((int32_t)IRQn < 0) {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+ }
else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
+ }
}
@@ -1437,7 +1500,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
The function encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
@@ -1446,16 +1509,16 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
@@ -1465,7 +1528,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
The function decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
@@ -1474,15 +1537,15 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
@@ -1492,13 +1555,13 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1) { __NOP(); } /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
@@ -1531,15 +1594,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
}
#endif
@@ -1571,11 +1634,11 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
+ while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+ ITM->PORT[0].u8 = (uint8_t)ch;
}
return (ch);
}
@@ -1618,10 +1681,13 @@ __STATIC_INLINE int32_t ITM_CheckChar (void) {
/*@} end of CMSIS_core_DebugFunctions */
-#endif /* __CORE_CM3_H_DEPENDANT */
-#endif /* __CMSIS_GENERIC */
+
#ifdef __cplusplus
}
#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/f2/include/core/core_cmFunc.h b/f2/include/core/core_cmFunc.h
index 139bc3c5ec98dbf396377dae699a86c7db6732e4..e3c057e65427ddb91ac3ec6b8e2ef53f64a5a362 100755
--- a/f2/include/core/core_cmFunc.h
+++ b/f2/include/core/core_cmFunc.h
@@ -1,13 +1,13 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
- * @version V3.20
- * @date 25. February 2013
+ * @version V4.10
+ * @date 18. March 2015
*
* @note
*
******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
+/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -198,7 +198,7 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
}
-#if (__CORTEX_M >= 0x03)
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
/** \brief Enable FIQ
@@ -242,6 +242,20 @@ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
}
+/** \brief Set Base Priority with condition
+
+ This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xff);
+}
+
+
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
@@ -267,10 +281,10 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
__regFaultMask = (faultMask & (uint32_t)1);
}
-#endif /* (__CORTEX_M >= 0x03) */
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-#if (__CORTEX_M == 0x04)
+#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
/** \brief Get FPSCR
@@ -303,19 +317,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
#endif
}
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
@@ -530,7 +532,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
return(result);
}
@@ -547,6 +549,19 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t v
}
+/** \brief Set Base Priority with condition
+
+ This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
@@ -576,7 +591,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t
#endif /* (__CORTEX_M >= 0x03) */
-#if (__CORTEX_M == 0x04)
+#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
/** \brief Get FPSCR
@@ -616,21 +631,34 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fps
#endif
}
-#endif /* (__CORTEX_M == 0x04) */
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
-
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
-
#endif /* __CORE_CMFUNC_H */
diff --git a/f2/include/core/core_cmInstr.h b/f2/include/core/core_cmInstr.h
index 8946c2c492a32fe16879a81dd0a4bb3ac7e67370..c8e045f56b04c2a54d066e5e19101b40df09abe4 100755
--- a/f2/include/core/core_cmInstr.h
+++ b/f2/include/core/core_cmInstr.h
@@ -1,13 +1,13 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
- * @version V3.20
- * @date 05. March 2013
+ * @version V4.10
+ * @date 18. March 2015
*
* @note
*
******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
+/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -89,24 +89,33 @@
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
-#define __ISB() __isb(0xF)
-
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
-#define __DSB() __dsb(0xF)
-
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
-#define __DMB() __dmb(0xF)
-
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0)
/** \brief Reverse byte order (32 bit)
@@ -171,8 +180,6 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
#define __BKPT(value) __breakpoint(value)
-#if (__CORTEX_M >= 0x03)
-
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
@@ -180,12 +187,42 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\param [in] value Value to reverse
\return Reversed value
*/
-#define __RBIT __rbit
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+ result = value; // r will be reversed bits of v; first get LSB of v
+ for (value >>= 1; value; value >>= 1)
+ {
+ result <<= 1;
+ result |= value & 1;
+ s--;
+ }
+ result <<= s; // shift when v's highest bits are zero
+ return(result);
+}
+#endif
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
/** \brief LDR Exclusive (8 bit)
- This function performs a exclusive LDR command for 8 bit value.
+ This function executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
@@ -195,7 +232,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
/** \brief LDR Exclusive (16 bit)
- This function performs a exclusive LDR command for 16 bit values.
+ This function executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
@@ -205,7 +242,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
/** \brief LDR Exclusive (32 bit)
- This function performs a exclusive LDR command for 32 bit values.
+ This function executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
@@ -215,7 +252,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
/** \brief STR Exclusive (8 bit)
- This function performs a exclusive STR command for 8 bit values.
+ This function executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
@@ -227,7 +264,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
/** \brief STR Exclusive (16 bit)
- This function performs a exclusive STR command for 16 bit values.
+ This function executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
@@ -239,7 +276,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
/** \brief STR Exclusive (32 bit)
- This function performs a exclusive STR command for 32 bit values.
+ This function executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
@@ -279,29 +316,83 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
#define __USAT __usat
-/** \brief Count leading zeros
+/** \brief Rotate Right with Extend (32 bit)
- This function counts the number of leading zeros of a data value.
+ This function moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
+ \param [in] value Value to rotate
+ \return Rotated value
*/
-#define __CLZ __clz
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
-#endif /* (__CORTEX_M >= 0x03) */
+/** \brief LDRT Unprivileged (8 bit)
+ This function executes a Unprivileged LDRT instruction for 8 bit value.
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
-#include <cmsis_iar.h>
+/** \brief LDRT Unprivileged (16 bit)
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
+ This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
-#include <cmsis_ccs.h>
+
+/** \brief LDRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief STRT Unprivileged (8 bit)
+
+ This function executes a Unprivileged STRT instruction for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/** \brief STRT Unprivileged (16 bit)
+
+ This function executes a Unprivileged STRT instruction for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/** \brief STRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged STRT instruction for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
@@ -322,7 +413,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
@@ -333,7 +424,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
@@ -344,7 +435,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
@@ -354,7 +445,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
@@ -366,9 +457,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
{
- __ASM volatile ("isb");
+ __ASM volatile ("isb 0xF":::"memory");
}
@@ -377,9 +468,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
{
- __ASM volatile ("dsb");
+ __ASM volatile ("dsb 0xF":::"memory");
}
@@ -388,9 +479,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
{
- __ASM volatile ("dmb");
+ __ASM volatile ("dmb 0xF":::"memory");
}
@@ -401,7 +492,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
\param [in] value Value to reverse
\return Reversed value
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
@@ -421,7 +512,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value
\param [in] value Value to reverse
\return Reversed value
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
@@ -437,7 +528,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t val
\param [in] value Value to reverse
\return Reversed value
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
@@ -458,9 +549,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value
\param [in] value Number of Bits to rotate
\return Rotated value
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
- return (op1 >> op2) | (op1 << (32 - op2));
+ return (op1 >> op2) | (op1 << (32 - op2));
}
@@ -475,8 +566,6 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1,
#define __BKPT(value) __ASM volatile ("bkpt "#value)
-#if (__CORTEX_M >= 0x03)
-
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
@@ -484,23 +573,48 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1,
\param [in] value Value to reverse
\return Reversed value
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- return(result);
+#else
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+ result = value; // r will be reversed bits of v; first get LSB of v
+ for (value >>= 1; value; value >>= 1)
+ {
+ result <<= 1;
+ result |= value & 1;
+ s--;
+ }
+ result <<= s; // shift when v's highest bits are zero
+#endif
+ return(result);
}
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
/** \brief LDR Exclusive (8 bit)
- This function performs a exclusive LDR command for 8 bit value.
+ This function executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
@@ -512,18 +626,18 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uin
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
- return(result);
+ return ((uint8_t) result); /* Add explicit type cast here */
}
/** \brief LDR Exclusive (16 bit)
- This function performs a exclusive LDR command for 16 bit values.
+ This function executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
@@ -535,18 +649,18 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile ui
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
- return(result);
+ return ((uint16_t) result); /* Add explicit type cast here */
}
/** \brief LDR Exclusive (32 bit)
- This function performs a exclusive LDR command for 32 bit values.
+ This function executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
@@ -557,50 +671,50 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile ui
/** \brief STR Exclusive (8 bit)
- This function performs a exclusive STR command for 8 bit values.
+ This function executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
- This function performs a exclusive STR command for 16 bit values.
+ This function executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
- This function performs a exclusive STR command for 32 bit values.
+ This function executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
@@ -614,7 +728,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t va
This function removes the exclusive lock which is created by LDREX.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
@@ -652,35 +766,149 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
})
-/** \brief Count leading zeros
+/** \brief Rotate Right with Extend (32 bit)
- This function counts the number of leading zeros of a data value.
+ This function moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
+ \param [in] value Value to rotate
+ \return Rotated value
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
{
- uint32_t result;
+ uint32_t result;
- __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
-#endif /* (__CORTEX_M >= 0x03) */
+/** \brief LDRT Unprivileged (8 bit)
+
+ This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/** \brief LDRT Unprivileged (16 bit)
+
+ This function executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/** \brief LDRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/** \brief STRT Unprivileged (8 bit)
+
+ This function executes a Unprivileged STRT instruction for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief STRT Unprivileged (16 bit)
+
+ This function executes a Unprivileged STRT instruction for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief STRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged STRT instruction for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
-
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
diff --git a/f2/include/devices/stm32f205xx.h b/f2/include/devices/stm32f205xx.h
index eb215bc113cd08b953362faaa9b765253d4ae3ac..0bdb6b388376b4cb9c09763df433a3a6fd5ad0d9 100755
--- a/f2/include/devices/stm32f205xx.h
+++ b/f2/include/devices/stm32f205xx.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f205xx.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 25-March-2014
+ * @version V2.1.0
+ * @date 09-October-2015
* @brief CMSIS STM32F205xx Device Peripheral Access Layer Header File.
* This file contains :
* - Data structures and the address mapping for all peripherals
@@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -450,8 +450,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
@@ -607,20 +606,20 @@ typedef struct
__IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
__IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
__IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
- __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
- __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
- __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
- __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
- __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
__IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
__IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
__IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
- __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
- __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
__IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
__IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
- __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
__IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
} SDIO_TypeDef;
@@ -837,19 +836,16 @@ USB_OTG_HostChannelTypeDef;
* @brief Peripheral_memory_map
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
-#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
-#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
-#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
@@ -1671,8 +1667,8 @@ USB_OTG_HostChannelTypeDef;
#define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
-/******************* Bit definition for CAN_FM1R register *******************/
-#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
+/************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
@@ -1687,9 +1683,23 @@ USB_OTG_HostChannelTypeDef;
#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
/******************* Bit definition for CAN_FS1R register *******************/
-#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
@@ -1704,40 +1714,82 @@ USB_OTG_HostChannelTypeDef;
#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
/****************** Bit definition for CAN_FFA1R register *******************/
-#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
-#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
-#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
-#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
-#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
-#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
-#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
-#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
-#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
-#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
-#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
-#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
-#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
-#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
+#define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
/******************* Bit definition for CAN_FA1R register *******************/
-#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
-#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
-#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
-#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
-#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
-#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
-#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
-#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
-#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
-#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
-#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
-#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
-#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
-#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
-#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
+#define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
/******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
@@ -2991,6 +3043,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -3013,6 +3068,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -3035,6 +3093,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -3057,6 +3118,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -3079,6 +3143,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -3101,6 +3168,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -3293,11 +3363,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3334,11 +3408,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3375,11 +3453,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3421,6 +3503,10 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3457,11 +3543,21 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
@@ -3492,11 +3588,21 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
@@ -3527,11 +3633,21 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
@@ -3567,6 +3683,16 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
@@ -4310,6 +4436,24 @@ USB_OTG_HostChannelTypeDef;
#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
/******************************************************************************/
/* */
@@ -4664,7 +4808,7 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
-#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
@@ -6888,12 +7032,12 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/
-#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3))
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3))
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
@@ -7039,7 +7183,7 @@ USB_OTG_HostChannelTypeDef;
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM5))
-/***************** TIM Instances : external trigger input availabe ************/
+/***************** TIM Instances : external trigger input available ***********/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
@@ -7142,7 +7286,7 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == USART3) || \
((INSTANCE) == USART6))
-/********************* UART Instances : Smard card mode ***********************/
+/********************* UART Instances : Smart card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
@@ -7162,6 +7306,19 @@ USB_OTG_HostChannelTypeDef;
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
/**
* @}
diff --git a/f2/include/devices/stm32f207xx.h b/f2/include/devices/stm32f207xx.h
index 3ec30f67a45ad0e89f60ec6f28db5ff7b64af8ec..333878299178b8a1fa7ae0c0e1738b06761a28ee 100755
--- a/f2/include/devices/stm32f207xx.h
+++ b/f2/include/devices/stm32f207xx.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f207xx.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 25-March-2014
+ * @version V2.1.0
+ * @date 09-October-2015
* @brief CMSIS STM32F207xx Device Peripheral Access Layer Header File.
* This file contains :
* - Data structures and the address mapping for all peripherals
@@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -545,8 +545,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
@@ -702,20 +701,20 @@ typedef struct
__IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
__IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
__IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
- __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
- __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
- __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
- __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
- __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
__IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
__IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
__IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
- __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
- __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
__IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
__IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
- __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
__IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
} SDIO_TypeDef;
@@ -931,19 +930,16 @@ USB_OTG_HostChannelTypeDef;
* @brief Peripheral_memory_map
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
-#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
-#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
-#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
@@ -1773,8 +1769,8 @@ USB_OTG_HostChannelTypeDef;
#define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
-/******************* Bit definition for CAN_FM1R register *******************/
-#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
+/************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
@@ -1789,9 +1785,23 @@ USB_OTG_HostChannelTypeDef;
#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
/******************* Bit definition for CAN_FS1R register *******************/
-#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
@@ -1806,40 +1816,82 @@ USB_OTG_HostChannelTypeDef;
#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
/****************** Bit definition for CAN_FFA1R register *******************/
-#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
-#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
-#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
-#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
-#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
-#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
-#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
-#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
-#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
-#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
-#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
-#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
-#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
-#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
+#define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
/******************* Bit definition for CAN_FA1R register *******************/
-#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
-#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
-#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
-#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
-#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
-#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
-#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
-#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
-#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
-#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
-#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
-#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
-#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
-#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
-#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
+#define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
/******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
@@ -3147,6 +3199,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -3169,6 +3224,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -3191,6 +3249,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -3213,6 +3274,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -3235,6 +3299,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -3257,7 +3324,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
-
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
/* FLASH */
@@ -3449,11 +3518,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3490,11 +3563,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3531,11 +3608,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3577,6 +3658,10 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3613,11 +3698,21 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
@@ -3648,11 +3743,21 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
@@ -3683,11 +3788,21 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
@@ -3723,6 +3838,16 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
@@ -4466,6 +4591,25 @@ USB_OTG_HostChannelTypeDef;
#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface */
@@ -4820,7 +4964,7 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
-#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
@@ -6518,7 +6662,7 @@ USB_OTG_HostChannelTypeDef;
/* Ethernet MMC Registers bits definition */
/******************************************************************************/
-/* Bit definition for Ethernet MMC Contol Register */
+/* Bit definition for Ethernet MMC Control Register */
#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
@@ -6538,7 +6682,7 @@ USB_OTG_HostChannelTypeDef;
/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when Rx alignment error counter reaches half the maximum value */
#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
@@ -6558,7 +6702,7 @@ USB_OTG_HostChannelTypeDef;
/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
@@ -6568,7 +6712,7 @@ USB_OTG_HostChannelTypeDef;
/* Ethernet PTP Registers bits definition */
/******************************************************************************/
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+/* Bit definition for Ethernet PTP Time Stamp Control Register */
#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
@@ -6687,7 +6831,7 @@ USB_OTG_HostChannelTypeDef;
#define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
#define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
#define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
- #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
+ #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailable */
#define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
@@ -6695,7 +6839,7 @@ USB_OTG_HostChannelTypeDef;
#define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
#define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
#define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
- #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
+ #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the receive frame into host memory */
#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
@@ -7493,12 +7637,12 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/
-#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3))
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
@@ -7644,7 +7788,7 @@ USB_OTG_HostChannelTypeDef;
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM5))
-/***************** TIM Instances : external trigger input availabe ************/
+/***************** TIM Instances : external trigger input available ***********/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
@@ -7747,7 +7891,7 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == USART3) || \
((INSTANCE) == USART6))
-/********************* UART Instances : Smard card mode ***********************/
+/********************* UART Instances : Smart card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
@@ -7767,6 +7911,19 @@ USB_OTG_HostChannelTypeDef;
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
/**
* @}
diff --git a/f2/include/devices/stm32f215xx.h b/f2/include/devices/stm32f215xx.h
index 6f3abb266ec5334d1c084e8bd5eeff1c7f86ea8c..124b11282ccc26d050cd92105577b5ec547b9ab7 100755
--- a/f2/include/devices/stm32f215xx.h
+++ b/f2/include/devices/stm32f215xx.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f215xx.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 25-March-2014
+ * @version V2.1.0
+ * @date 09-October-2015
* @brief CMSIS STM32F215xx Device Peripheral Access Layer Header File.
* This file contains :
* - Data structures and the address mapping for all peripherals
@@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -451,8 +451,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
@@ -608,20 +607,20 @@ typedef struct
__IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
__IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
__IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
- __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
- __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
- __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
- __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
- __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
__IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
__IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
__IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
- __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
- __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
__IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
__IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
- __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
__IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
} SDIO_TypeDef;
@@ -881,19 +880,17 @@ USB_OTG_HostChannelTypeDef;
* @brief Peripheral_memory_map
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
-#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
-#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
-#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
+
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
@@ -1721,8 +1718,8 @@ USB_OTG_HostChannelTypeDef;
#define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
-/******************* Bit definition for CAN_FM1R register *******************/
-#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
+/************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
@@ -1737,9 +1734,23 @@ USB_OTG_HostChannelTypeDef;
#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
/******************* Bit definition for CAN_FS1R register *******************/
-#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
@@ -1754,40 +1765,82 @@ USB_OTG_HostChannelTypeDef;
#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
/****************** Bit definition for CAN_FFA1R register *******************/
-#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
-#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
-#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
-#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
-#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
-#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
-#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
-#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
-#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
-#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
-#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
-#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
-#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
-#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
+#define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
/******************* Bit definition for CAN_FA1R register *******************/
-#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
-#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
-#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
-#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
-#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
-#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
-#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
-#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
-#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
-#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
-#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
-#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
-#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
-#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
-#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
+#define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
/******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
@@ -3089,6 +3142,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -3111,6 +3167,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -3133,6 +3192,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -3155,6 +3217,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -3177,6 +3242,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -3199,6 +3267,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -3391,11 +3462,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3432,11 +3507,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3473,11 +3552,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3519,6 +3602,10 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3555,11 +3642,21 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
@@ -3590,11 +3687,21 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
@@ -3625,11 +3732,21 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
@@ -3665,6 +3782,16 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
@@ -4408,6 +4535,25 @@ USB_OTG_HostChannelTypeDef;
#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
/******************************************************************************/
/* */
/* HASH */
@@ -4431,17 +4577,28 @@ USB_OTG_HostChannelTypeDef;
#define HASH_CR_LKEY ((uint32_t)0x00010000)
/****************** Bits definition for HASH_STR register *******************/
-#define HASH_STR_NBW ((uint32_t)0x0000001F)
-#define HASH_STR_NBW_0 ((uint32_t)0x00000001)
-#define HASH_STR_NBW_1 ((uint32_t)0x00000002)
-#define HASH_STR_NBW_2 ((uint32_t)0x00000004)
-#define HASH_STR_NBW_3 ((uint32_t)0x00000008)
-#define HASH_STR_NBW_4 ((uint32_t)0x00000010)
+#define HASH_STR_NBLW ((uint32_t)0x0000001F)
+#define HASH_STR_NBLW_0 ((uint32_t)0x00000001)
+#define HASH_STR_NBLW_1 ((uint32_t)0x00000002)
+#define HASH_STR_NBLW_2 ((uint32_t)0x00000004)
+#define HASH_STR_NBLW_3 ((uint32_t)0x00000008)
+#define HASH_STR_NBLW_4 ((uint32_t)0x00000010)
#define HASH_STR_DCAL ((uint32_t)0x00000100)
+/* Aliases for HASH_STR register */
+#define HASH_STR_NBW HASH_STR_NBLW
+#define HASH_STR_NBW_0 HASH_STR_NBLW_0
+#define HASH_STR_NBW_1 HASH_STR_NBLW_1
+#define HASH_STR_NBW_2 HASH_STR_NBLW_2
+#define HASH_STR_NBW_3 HASH_STR_NBLW_3
+#define HASH_STR_NBW_4 HASH_STR_NBLW_4
/****************** Bits definition for HASH_IMR register *******************/
-#define HASH_IMR_DINIM ((uint32_t)0x00000001)
-#define HASH_IMR_DCIM ((uint32_t)0x00000002)
+#define HASH_IMR_DINIE ((uint32_t)0x00000001)
+#define HASH_IMR_DCIE ((uint32_t)0x00000002)
+/* Aliases for HASH_IMR register */
+#define HASH_IMR_DINIM HASH_IMR_DINIE
+#define HASH_IMR_DCIM HASH_IMR_DCIE
+
/****************** Bits definition for HASH_SR register ********************/
#define HASH_SR_DINIS ((uint32_t)0x00000001)
@@ -4802,7 +4959,7 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
-#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
@@ -7034,12 +7191,12 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/
-#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3))
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3))
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
@@ -7185,7 +7342,7 @@ USB_OTG_HostChannelTypeDef;
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM5))
-/***************** TIM Instances : external trigger input availabe ************/
+/***************** TIM Instances : external trigger input available ***********/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
@@ -7288,7 +7445,7 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == USART3) || \
((INSTANCE) == USART6))
-/********************* UART Instances : Smard card mode ***********************/
+/********************* UART Instances : Smart card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
@@ -7308,6 +7465,19 @@ USB_OTG_HostChannelTypeDef;
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
/**
* @}
diff --git a/f2/include/devices/stm32f217xx.h b/f2/include/devices/stm32f217xx.h
index 84b584cf729398e031f6c4d7af076c98e5d0e8e3..1d2745b98cfd67b0d200b2fc64ebead4b7c6a50d 100755
--- a/f2/include/devices/stm32f217xx.h
+++ b/f2/include/devices/stm32f217xx.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f217xx.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 25-March-2014
+ * @version V2.1.0
+ * @date 09-October-2015
* @brief CMSIS STM32F217xx Device Peripheral Access Layer Header File.
* This file contains :
* - Data structures and the address mapping for all peripherals
@@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -546,8 +546,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
@@ -703,20 +702,20 @@ typedef struct
__IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
__IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
__IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
- __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
- __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
- __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
- __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
- __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
__IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
__IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
__IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
- __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
- __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
__IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
__IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
- __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
__IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
} SDIO_TypeDef;
@@ -976,19 +975,16 @@ USB_OTG_HostChannelTypeDef;
* @brief Peripheral_memory_map
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
-#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
-#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
-#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
@@ -1825,8 +1821,8 @@ USB_OTG_HostChannelTypeDef;
#define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
-/******************* Bit definition for CAN_FM1R register *******************/
-#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
+/************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
@@ -1841,9 +1837,23 @@ USB_OTG_HostChannelTypeDef;
#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
/******************* Bit definition for CAN_FS1R register *******************/
-#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
@@ -1858,40 +1868,82 @@ USB_OTG_HostChannelTypeDef;
#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
/****************** Bit definition for CAN_FFA1R register *******************/
-#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
-#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
-#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
-#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
-#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
-#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
-#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
-#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
-#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
-#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
-#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
-#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
-#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
-#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
+#define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
/******************* Bit definition for CAN_FA1R register *******************/
-#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
-#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
-#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
-#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
-#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
-#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
-#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
-#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
-#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
-#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
-#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
-#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
-#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
-#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
-#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
+#define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
/******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
@@ -3248,6 +3300,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -3270,6 +3325,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -3292,6 +3350,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -3314,6 +3375,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -3336,6 +3400,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -3358,6 +3425,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -3550,11 +3620,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3591,11 +3665,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3632,11 +3710,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3678,6 +3760,10 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3714,11 +3800,21 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
@@ -3749,11 +3845,21 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
@@ -3784,11 +3890,21 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
@@ -3824,6 +3940,16 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
@@ -4567,6 +4693,25 @@ USB_OTG_HostChannelTypeDef;
#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
/******************************************************************************/
/* */
/* HASH */
@@ -4590,17 +4735,29 @@ USB_OTG_HostChannelTypeDef;
#define HASH_CR_LKEY ((uint32_t)0x00010000)
/****************** Bits definition for HASH_STR register *******************/
-#define HASH_STR_NBW ((uint32_t)0x0000001F)
-#define HASH_STR_NBW_0 ((uint32_t)0x00000001)
-#define HASH_STR_NBW_1 ((uint32_t)0x00000002)
-#define HASH_STR_NBW_2 ((uint32_t)0x00000004)
-#define HASH_STR_NBW_3 ((uint32_t)0x00000008)
-#define HASH_STR_NBW_4 ((uint32_t)0x00000010)
+#define HASH_STR_NBLW ((uint32_t)0x0000001F)
+#define HASH_STR_NBLW_0 ((uint32_t)0x00000001)
+#define HASH_STR_NBLW_1 ((uint32_t)0x00000002)
+#define HASH_STR_NBLW_2 ((uint32_t)0x00000004)
+#define HASH_STR_NBLW_3 ((uint32_t)0x00000008)
+#define HASH_STR_NBLW_4 ((uint32_t)0x00000010)
#define HASH_STR_DCAL ((uint32_t)0x00000100)
+/* Aliases for HASH_STR register */
+#define HASH_STR_NBW HASH_STR_NBLW
+#define HASH_STR_NBW_0 HASH_STR_NBLW_0
+#define HASH_STR_NBW_1 HASH_STR_NBLW_1
+#define HASH_STR_NBW_2 HASH_STR_NBLW_2
+#define HASH_STR_NBW_3 HASH_STR_NBLW_3
+#define HASH_STR_NBW_4 HASH_STR_NBLW_4
+
/****************** Bits definition for HASH_IMR register *******************/
-#define HASH_IMR_DINIM ((uint32_t)0x00000001)
-#define HASH_IMR_DCIM ((uint32_t)0x00000002)
+#define HASH_IMR_DINIE ((uint32_t)0x00000001)
+#define HASH_IMR_DCIE ((uint32_t)0x00000002)
+/* Aliases for HASH_IMR register */
+#define HASH_IMR_DINIM HASH_IMR_DINIE
+#define HASH_IMR_DCIM HASH_IMR_DCIE
+
/****************** Bits definition for HASH_SR register ********************/
#define HASH_SR_DINIS ((uint32_t)0x00000001)
@@ -4959,7 +5116,7 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
-#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
@@ -6665,7 +6822,7 @@ USB_OTG_HostChannelTypeDef;
/* Ethernet MMC Registers bits definition */
/******************************************************************************/
-/* Bit definition for Ethernet MMC Contol Register */
+/* Bit definition for Ethernet MMC Control Register */
#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
@@ -6685,7 +6842,7 @@ USB_OTG_HostChannelTypeDef;
/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when Rx alignment error counter reaches half the maximum value */
#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
@@ -6705,7 +6862,7 @@ USB_OTG_HostChannelTypeDef;
/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
@@ -6715,7 +6872,7 @@ USB_OTG_HostChannelTypeDef;
/* Ethernet PTP Registers bits definition */
/******************************************************************************/
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+/* Bit definition for Ethernet PTP Time Stamp Control Register */
#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
@@ -6834,7 +6991,7 @@ USB_OTG_HostChannelTypeDef;
#define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
#define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
#define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
- #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
+ #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailable */
#define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
@@ -6842,7 +6999,7 @@ USB_OTG_HostChannelTypeDef;
#define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
#define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
#define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
- #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
+ #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the receive frame into host memory */
#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
@@ -7640,12 +7797,12 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/
-#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3))
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
- ((INSTANCE) == SPI3))
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
@@ -7791,7 +7948,7 @@ USB_OTG_HostChannelTypeDef;
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM5))
-/***************** TIM Instances : external trigger input availabe ************/
+/***************** TIM Instances : external trigger input available ***********/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
@@ -7894,7 +8051,7 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == USART3) || \
((INSTANCE) == USART6))
-/********************* UART Instances : Smard card mode ***********************/
+/********************* UART Instances : Smart card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
@@ -7914,6 +8071,19 @@ USB_OTG_HostChannelTypeDef;
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
/**
* @}
diff --git a/f2/include/devices/stm32f2xx.h b/f2/include/devices/stm32f2xx.h
index c476a04c0a1ebddc1ec8f01e3153ae81ff2daf3b..50eb02fb785a9a6990e3124098595128c117600f 100755
--- a/f2/include/devices/stm32f2xx.h
+++ b/f2/include/devices/stm32f2xx.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 25-March-2014
+ * @version V2.1.0
+ * @date 09-October-2015
* @brief CMSIS STM32F2xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -64,16 +64,25 @@
* @{
*/
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F2)
+#define STM32F2
+#endif /* STM32F2 */
+
/* Uncomment the line below according to the target STM32 device used in your
application
*/
-
#if !defined (STM32F205xx) && !defined (STM32F215xx) && !defined (STM32F207xx) && !defined (STM32F217xx)
- /* #define STM32F205xx */ /*!< STM32Fxx Devices */
- /* #define STM32F215xx */ /*!< STM32Fxx Devices */
- /* #define STM32F207xx */ /*!< STM32Fxx Devices */
- /* #define STM32F217xx */ /*!< STM32Fxx Devices */
+ /* #define STM32F205xx */ /*!< STM32F205RG, STM32F205VG, STM32F205ZG, STM32F205RF, STM32F205VF, STM32F205ZF,
+ STM32F205RE, STM32F205VE, STM32F205ZE, STM32F205RC, STM32F205VC, STM32F205ZC,
+ STM32F205RB and STM32F205VB Devices */
+ /* #define STM32F215xx */ /*!< STM32F215RG, STM32F215VG, STM32F215ZG, STM32F215RE, STM32F215VE and STM32F215ZE Devices */
+ /* #define STM32F207xx */ /*!< STM32F207VG, STM32F207ZG, STM32F207IG, STM32F207VF, STM32F207ZF, STM32F207IF,
+ STM32F207VE, STM32F207ZE, STM32F207IE, STM32F207VC, STM32F207ZC and STM32F207IC Devices */
+ /* #define STM32F217xx */ /*!< STM32F217VG, STM32F217ZG, STM32F217IG, STM32F217VE, STM32F217ZE and STM32F217IE Devices */
#endif
@@ -90,12 +99,12 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.0.1
+ * @brief CMSIS Device version number V2.1.0
*/
-#define __STM32F2xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
-#define __STM32F2xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
+#define __STM32F2xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
+#define __STM32F2xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32F2xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32F2xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F2xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F2xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
@@ -175,7 +184,10 @@ typedef enum
/**
* @}
*/
-
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f2xx_hal.h"
+#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
diff --git a/f2/include/devices/system_stm32f2xx.h b/f2/include/devices/system_stm32f2xx.h
index 1e7ef282e0ab47cf44bc84fb0fc4cb2148006391..12df94570ab9236b020ef71495a4560404b841d6 100755
--- a/f2/include/devices/system_stm32f2xx.h
+++ b/f2/include/devices/system_stm32f2xx.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f2xx.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 25-March-2014
+ * @version V2.1.0
+ * @date 09-October-2015
* @brief CMSIS Cortex-M3 Device System Source File for STM32F2xx devices.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
diff --git a/f2/include/stm32f2xx_hal.h b/f2/include/stm32f2xx_hal.h
index 835dfb236d079fec7606f0a0306de558877c2945..8aeadf060efe78adcc993b6cc2d43b02fd064efb 100755
--- a/f2/include/stm32f2xx_hal.h
+++ b/f2/include/stm32f2xx_hal.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f2xx_hal.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -58,104 +58,149 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+ * @{
+ */
/** @brief Freeze/Unfreeze Peripherals in Debug mode
*/
-#define __HAL_FREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
-#define __HAL_FREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
-#define __HAL_FREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
-#define __HAL_FREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
-#define __HAL_FREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
-#define __HAL_FREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
-#define __HAL_FREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
-#define __HAL_FREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
-#define __HAL_FREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
-#define __HAL_FREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
-#define __HAL_FREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
-#define __HAL_FREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
-#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
-#define __HAL_FREEZE_CAN1_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
-#define __HAL_FREEZE_CAN2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
-#define __HAL_FREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
-#define __HAL_FREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
-#define __HAL_FREEZE_TIM9_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
-#define __HAL_FREEZE_TIM10_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
-#define __HAL_FREEZE_TIM11_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
-
-#define __HAL_UNFREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
-#define __HAL_UNFREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
-#define __HAL_UNFREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
-#define __HAL_UNFREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
-#define __HAL_UNFREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
-#define __HAL_UNFREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
-#define __HAL_UNFREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
-#define __HAL_UNFREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
-#define __HAL_UNFREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
-#define __HAL_UNFREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
-#define __HAL_UNFREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
-#define __HAL_UNFREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
-#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
-#define __HAL_UNFREEZE_CAN1_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
-#define __HAL_UNFREEZE_CAN2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
-#define __HAL_UNFREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
-#define __HAL_UNFREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
-#define __HAL_UNFREEZE_TIM9_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
-#define __HAL_UNFREEZE_TIM10_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
-#define __HAL_UNFREEZE_TIM11_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
+#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
+
+#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
+#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
/** @brief Main Flash memory mapped at 0x00000000
*/
-#define __HAL_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
+#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
/** @brief System Flash memory mapped at 0x00000000
*/
-#define __HAL_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
- SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
- }while(0);
+#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
+ }while(0);
/** @brief Embedded SRAM mapped at 0x00000000
*/
-#define __HAL_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
- SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
- }while(0);
+#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
+ }while(0);
/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
*/
-#define __HAL_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
- SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
- }while(0);
+#define __HAL_SYSCFG_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
+ }while(0);
+
+
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
-
+/** @addtogroup HAL_Exported_Functions
+ * @{
+ */
+/** @addtogroup HAL_Exported_Functions_Group1
+ * @{
+ */
/* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+/**
+ * @}
+ */
+/** @addtogroup HAL_Exported_Functions_Group2
+ * @{
+ */
/* Peripheral Control functions ************************************************/
-void HAL_IncTick(void);
-void HAL_Delay(__IO uint32_t Delay);
+void HAL_IncTick(void);
+void HAL_Delay(__IO uint32_t Delay);
uint32_t HAL_GetTick(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
-void HAL_EnableDBGSleepMode(void);
-void HAL_DisableDBGSleepMode(void);
-void HAL_EnableDBGStopMode(void);
-void HAL_DisableDBGStopMode(void);
-void HAL_EnableDBGStandbyMode(void);
-void HAL_DisableDBGStandbyMode(void);
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
void HAL_EnableCompensationCell(void);
void HAL_DisableCompensationCell(void);
+/**
+ * @}
+ */
/**
* @}
- */
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Variables HAL Private Variables
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Constants HAL Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_adc.h b/f2/include/stm32f2xx_hal_adc.h
index c6a647ffe2839c7a758011c8cd3b53e092a4b322..30013714c57d4e92b110e7ef39e2e71c46ca2fcd 100755
--- a/f2/include/stm32f2xx_hal_adc.h
+++ b/f2/include/stm32f2xx_hal_adc.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_adc.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of ADC HAL extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,154 +55,200 @@
*/
/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */
- HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */
- HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
- HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */
- HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */
- HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */
- HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */
- HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */
- HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */
- HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */
- HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */
- HAL_ADC_STATE_AWD = 0x06 /*!< ADC state analog watchdog */
-
-}HAL_ADC_StateTypeDef;
+/** @defgroup ADC_Exported_Types ADC Exported Types
+ * @{
+ */
/**
- * @brief ADC Init structure definition
- */
+ * @brief Structure definition of ADC and regular group initialization
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
+ * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
+ * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled
+ * - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
+ * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
+ */
typedef struct
{
- uint32_t ClockPrescaler; /*!< Select the frequency of the clock to the ADC. The clock is common for
+ uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
all the ADCs.
This parameter can be a value of @ref ADC_ClockPrescaler */
- uint32_t Resolution; /*!< Configures the ADC resolution dual mode.
+ uint32_t Resolution; /*!< Configures the ADC resolution.
This parameter can be a value of @ref ADC_Resolution */
- uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
- This parameter can be a value of @ref ADC_data_align */
- uint32_t ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multi channels) or
- Single (one channel) mode.
- This parameter can be set to ENABLE or DISABLE */
- uint32_t EOCSelection; /*!< Specifies whether the EOC flag is set
- at the end of single channel conversion or at the end of all conversions.
- This parameter can be a value of @ref ADC_EOCSelection */
- uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode.
+ uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
+ or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
+ This parameter can be a value of @ref ADC_Data_align */
+ uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
+ This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+ If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
+ Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
+ If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
+ Scan direction is upward: from rank1 to rank 'n'.
+ This parameter can be set to ENABLE or DISABLE */
+ uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
+ This parameter can be a value of @ref ADC_EOCSelection.
+ Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
+ Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
+ or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
+ Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
+ If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
+ uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
+ after the selected trigger occurred (software start or external trigger).
This parameter can be set to ENABLE or DISABLE. */
- uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests is performed in Continuous or in Single mode.
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for
- regular channel group.
+ uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
+ To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
- uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous or not
- for regular channels.
+ uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
This parameter can be set to ENABLE or DISABLE. */
- uint32_t NbrOfDiscConversion; /*!< Specifies the number of ADC discontinuous conversions that will be done
- using the sequencer for regular channel group.
+ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
+ If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
- uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger of a regular group.
+ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
+ If set to ADC_SOFTWARE_START, external triggers are disabled.
+ If set to external trigger source, triggering is on event rising edge by default.
+ This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
+ uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
+ If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
- uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion of a regular group.
- This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
+ uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
+ or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
+ Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
+ Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
+ This parameter can be set to ENABLE or DISABLE. */
}ADC_InitTypeDef;
-/**
- * @brief ADC handle Structure definition
- */
-typedef struct
-{
- ADC_TypeDef *Instance; /*!< Register base address */
-
- ADC_InitTypeDef Init; /*!< ADC required parameters */
-
- __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
-
- DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
-
- HAL_LockTypeDef Lock; /*!< ADC locking object */
- __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */
-
- __IO uint32_t ErrorCode; /*!< ADC Error code */
-}ADC_HandleTypeDef;
/**
- * @brief ADC Configuration regular Channel structure definition
+ * @brief Structure definition of ADC channel for regular group
+ * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+ * ADC can be either disabled or enabled without conversion on going on regular group.
*/
typedef struct
{
- uint32_t Channel; /*!< The ADC channel to configure
- This parameter can be a value of @ref ADC_channels */
- uint32_t Rank; /*!< The rank in the regular group sequencer
- This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
- uint32_t SamplingTime; /*!< The sample time value to be set for the selected channel.
- This parameter can be a value of @ref ADC_sampling_times */
- uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
+ uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
+ This parameter can be a value of @ref ADC_channels */
+ uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
+ This parameter can be a value of @ref ADC_sampling_times
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
+ uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
}ADC_ChannelConfTypeDef;
/**
- * @brief ADC Configuration multi-mode structure definition
+ * @brief ADC Configuration multi-mode structure definition
*/
typedef struct
{
uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
- This parameter can be a value of @ref ADC_analog_watchdog_selection. */
+ This parameter can be a value of @ref ADC_analog_watchdog_selection */
uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
This parameter must be a 12-bit value. */
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
This parameter must be a 12-bit value. */
uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
This parameter has an effect only if watchdog mode is configured on single channel
- This parameter can be a value of @ref ADC_channels. */
+ This parameter can be a value of @ref ADC_channels */
uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
is interrupt mode or in polling mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
}ADC_AnalogWDGConfTypeDef;
-/* Exported constants --------------------------------------------------------*/
+/**
+ * @brief HAL ADC state machine: ADC states definition (bitfields)
+ */
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
-/** @defgroup ADC_Exported_Constants
- * @{
- */
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
+ external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */
-/** @defgroup ADC_Error_Code
- * @{
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
+ external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */
+
+/**
+ * @brief ADC handle Structure definition
*/
+typedef struct
+{
+ ADC_TypeDef *Instance; /*!< Register base address */
+
+ ADC_InitTypeDef Init; /*!< ADC required parameters */
+
+ __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
+
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
+
+ HAL_LockTypeDef Lock; /*!< ADC locking object */
+
+ __IO uint32_t State; /*!< ADC communication state */
+
+ __IO uint32_t ErrorCode; /*!< ADC Error code */
+}ADC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+ * @{
+ */
-#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
-#define HAL_ADC_ERROR_OVR ((uint32_t)0x01) /*!< OVR error */
-#define HAL_ADC_ERROR_DMA ((uint32_t)0x02) /*!< DMA transfer error */
+/** @defgroup ADC_Error_Code ADC Error Code
+ * @{
+ */
+#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
+ enable/disable, erroneous state */
+#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */
+#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
/**
* @}
- */
+ */
-/** @defgroup ADC_ClockPrescaler
+/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
* @{
*/
-#define ADC_CLOCKPRESCALER_PCLK_DIV2 ((uint32_t)0x00000000)
-#define ADC_CLOCKPRESCALER_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
-#define ADC_CLOCKPRESCALER_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
-#define ADC_CLOCKPRESCALER_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
-#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV2) || \
- ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV4) || \
- ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV6) || \
- ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV8))
+#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000)
+#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
+#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
+#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
/**
* @}
*/
-/** @defgroup ADC_delay_between_2_sampling_phases
+/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
* @{
*/
#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000)
@@ -221,62 +267,37 @@ typedef struct
#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
-
-#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
/**
* @}
*/
-/** @defgroup ADC_Resolution
+/** @defgroup ADC_Resolution ADC Resolution
* @{
*/
-#define ADC_RESOLUTION12b ((uint32_t)0x00000000)
-#define ADC_RESOLUTION10b ((uint32_t)ADC_CR1_RES_0)
-#define ADC_RESOLUTION8b ((uint32_t)ADC_CR1_RES_1)
-#define ADC_RESOLUTION6b ((uint32_t)ADC_CR1_RES)
-
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \
- ((RESOLUTION) == ADC_RESOLUTION10b) || \
- ((RESOLUTION) == ADC_RESOLUTION8b) || \
- ((RESOLUTION) == ADC_RESOLUTION6b))
+#define ADC_RESOLUTION_12B ((uint32_t)0x00000000)
+#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
+#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
+#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
/**
* @}
*/
-/** @defgroup ADC_External_trigger_edge_Regular
+/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
* @{
*/
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
-
-#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
/**
* @}
*/
-/** @defgroup ADC_External_trigger_Source_Regular
+/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
* @{
- */
+ */
+/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
+/* compatibility with other STM32 devices. */
#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000)
#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
@@ -293,40 +314,21 @@ typedef struct
#define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
#define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
-
-#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11))
+#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1)
/**
* @}
*/
-/** @defgroup ADC_data_align
+/** @defgroup ADC_Data_align ADC Data Align
* @{
*/
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
-
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
- ((ALIGN) == ADC_DATAALIGN_LEFT))
/**
* @}
*/
-/** @defgroup ADC_channels
+/** @defgroup ADC_channels ADC Common Channels
* @{
*/
#define ADC_CHANNEL_0 ((uint32_t)0x00000000)
@@ -349,34 +351,13 @@ typedef struct
#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
-#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)
#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
-#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
- ((CHANNEL) == ADC_CHANNEL_1) || \
- ((CHANNEL) == ADC_CHANNEL_2) || \
- ((CHANNEL) == ADC_CHANNEL_3) || \
- ((CHANNEL) == ADC_CHANNEL_4) || \
- ((CHANNEL) == ADC_CHANNEL_5) || \
- ((CHANNEL) == ADC_CHANNEL_6) || \
- ((CHANNEL) == ADC_CHANNEL_7) || \
- ((CHANNEL) == ADC_CHANNEL_8) || \
- ((CHANNEL) == ADC_CHANNEL_9) || \
- ((CHANNEL) == ADC_CHANNEL_10) || \
- ((CHANNEL) == ADC_CHANNEL_11) || \
- ((CHANNEL) == ADC_CHANNEL_12) || \
- ((CHANNEL) == ADC_CHANNEL_13) || \
- ((CHANNEL) == ADC_CHANNEL_14) || \
- ((CHANNEL) == ADC_CHANNEL_15) || \
- ((CHANNEL) == ADC_CHANNEL_16) || \
- ((CHANNEL) == ADC_CHANNEL_17) || \
- ((CHANNEL) == ADC_CHANNEL_18))
+#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
/**
* @}
*/
-/** @defgroup ADC_sampling_times
+/** @defgroup ADC_sampling_times ADC Sampling Times
* @{
*/
#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000)
@@ -387,46 +368,30 @@ typedef struct
#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
-
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_15CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_28CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_56CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_84CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_480CYCLES))
/**
* @}
*/
- /** @defgroup ADC_EOCSelection
+ /** @defgroup ADC_EOCSelection ADC EOC Selection
* @{
*/
-#define EOC_SEQ_CONV ((uint32_t)0x00000000)
-#define EOC_SINGLE_CONV ((uint32_t)0x00000001)
-#define EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /*!< reserved for future use */
-
-#define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == EOC_SINGLE_CONV) || \
- ((EOCSelection) == EOC_SEQ_CONV) || \
- ((EOCSelection) == EOC_SINGLE_SEQ_CONV))
+#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000)
+#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001)
+#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /*!< reserved for future use */
/**
* @}
*/
-/** @defgroup ADC_Event_type
+/** @defgroup ADC_Event_type ADC Event Type
* @{
*/
-#define AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
-#define OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
-
-#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \
- ((EVENT) == OVR_EVENT))
+#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
+#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
/**
* @}
*/
-/** @defgroup ADC_analog_watchdog_selection
+/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
* @{
*/
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
@@ -436,33 +401,22 @@ typedef struct
#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
-
-#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
/**
* @}
*/
-/** @defgroup ADC_interrupts_definition
+/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
* @{
*/
#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
-
-#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
- ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
/**
* @}
*/
-/** @defgroup ADC_flags_definition
+/** @defgroup ADC_flags_definition ADC Flags Definition
* @{
*/
#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
@@ -475,89 +429,317 @@ typedef struct
* @}
*/
-/** @defgroup ADC_channels_type
+/** @defgroup ADC_channels_type ADC Channels Type
* @{
*/
-#define ALL_CHANNELS ((uint32_t)0x00000001)
-#define REGULAR_CHANNELS ((uint32_t)0x00000002) /*!< reserved for future use */
-#define INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */
-
-#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ALL_CHANNELS) || \
- ((CHANNEL_TYPE) == REGULAR_CHANNELS) || \
- ((CHANNEL_TYPE) == INJECTED_CHANNELS))
+#define ADC_ALL_CHANNELS ((uint32_t)0x00000001)
+#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002) /*!< reserved for future use */
+#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */
/**
* @}
*/
-/** @defgroup ADC_thresholds
- * @{
- */
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFF))
/**
* @}
*/
-/** @defgroup ADC_regular_length
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
* @{
- */
-#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
+ */
+
+/** @brief Reset ADC handle state
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+
+/**
+ * @brief Enable the ADC peripheral.
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
+
+/**
+ * @brief Disable the ADC peripheral.
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
+
+/**
+ * @brief Enable the ADC end of conversion interrupt.
+ * @param __HANDLE__: specifies the ADC Handle.
+ * @param __INTERRUPT__: ADC Interrupt.
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the ADC end of conversion interrupt.
+ * @param __HANDLE__: specifies the ADC Handle.
+ * @param __INTERRUPT__: ADC interrupt.
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
+
+/** @brief Check if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the ADC Handle.
+ * @param __INTERRUPT__: specifies the ADC interrupt source to check.
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Clear the ADC's pending flags.
+ * @param __HANDLE__: specifies the ADC Handle.
+ * @param __FLAG__: ADC flag.
+ * @retval None
+ */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
+
+/**
+ * @brief Get the selected ADC's flag status.
+ * @param __HANDLE__: specifies the ADC Handle.
+ * @param __FLAG__: ADC flag.
+ * @retval None
+ */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
/**
* @}
- */
+ */
+
+/* Include ADC HAL Extension module */
+#include "stm32f2xx_hal_adc_ex.h"
-/** @defgroup ADC_regular_rank
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
* @{
- */
-#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16)))
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ***********************************/
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
/**
* @}
- */
+ */
-/** @defgroup ADC_regular_discontinuous_mode_number
+/** @addtogroup ADC_Exported_Functions_Group2
* @{
- */
-#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
+ */
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
+
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
+
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
+
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
+
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
+
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
/**
* @}
- */
+ */
-/** @defgroup ADC_range_verification
+/** @addtogroup ADC_Exported_Functions_Group3
* @{
- */
-#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
- ((((RESOLUTION) == ADC_RESOLUTION12b) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
- (((RESOLUTION) == ADC_RESOLUTION10b) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
- (((RESOLUTION) == ADC_RESOLUTION8b) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
- (((RESOLUTION) == ADC_RESOLUTION6b) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
+ */
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
/**
* @}
- */
-
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group4
+ * @{
+ */
+/* Peripheral State functions ***************************************************/
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
* @}
- */
+ */
-/* Exported macro ------------------------------------------------------------*/
/**
- * @brief Enable the ADC peripheral.
- * @param __HANDLE__: ADC handle
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+/* Delay for ADC stabilization time. */
+/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
+/* Unit: us */
+#define ADC_STAB_DELAY_US ((uint32_t) 3)
+/* Delay for temperature sensor stabilization time. */
+/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
+/* Unit: us */
+#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
+/**
+ * @}
+ */
+
+/* Private macro ------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Macros ADC Private Macros
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in
+ code of final user */
+
+/**
+ * @brief Verification of ADC state: enabled or disabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (ADC enabled) or RESET (ADC disabled)
+ */
+#define ADC_IS_ENABLE(__HANDLE__) \
+ ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
+ ) ? SET : RESET)
+
+/**
+ * @brief Test if conversion trigger of regular group is software start
+ * or external trigger.
+ * @param __HANDLE__: ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
+ (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+
+/**
+ * @brief Test if conversion trigger of injected group is software start
+ * or external trigger.
+ * @param __HANDLE__: ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
+ (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
+
+/**
+ * @brief Simultaneously clears and sets specific bits of the handle State
+ * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+ * the first parameter is the ADC handle State, the second parameter is the
+ * bit field to clear, the third and last parameter is the bit field to set.
* @retval None
*/
-#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
+#define ADC_STATE_CLR_SET MODIFY_REG
/**
- * @brief Disable the ADC peripheral.
- * @param __HANDLE__: ADC handle
+ * @brief Clear ADC error code (set it to error code: "no error")
+ * @param __HANDLE__: ADC handle
* @retval None
*/
-#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
+ ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+
+#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8))
+#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_10B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_8B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_6B))
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \
+ ((REGTRIG) == ADC_SOFTWARE_START))
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+ ((ALIGN) == ADC_DATAALIGN_LEFT))
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_15CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_28CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_56CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_84CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_480CYCLES))
+#define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV) || \
+ ((EOCSelection) == ADC_EOC_SEQ_CONV) || \
+ ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV))
+#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
+ ((EVENT) == ADC_OVR_EVENT))
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
+#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
+ ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
+ ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFF))
+
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16)))
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
+#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
+ ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
/**
* @brief Set ADC Regular channel sequence length.
* @param _NbrOfConversion_: Regular channel sequence length.
* @retval None
*/
-#define __HAL_ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
+#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
/**
* @brief Set the ADC's sample time for channel numbers between 10 and 18.
@@ -565,7 +747,7 @@ typedef struct
* @param _CHANNELNB_: Channel number.
* @retval None
*/
-#define __HAL_ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
+#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))
/**
* @brief Set the ADC's sample time for channel numbers between 0 and 9.
@@ -573,7 +755,7 @@ typedef struct
* @param _CHANNELNB_: Channel number.
* @retval None
*/
-#define __HAL_ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
+#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
/**
* @brief Set the selected regular channel rank for rank between 1 and 6.
@@ -581,7 +763,7 @@ typedef struct
* @param _RANKNB_: Rank number.
* @retval None
*/
-#define __HAL_ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
+#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))
/**
* @brief Set the selected regular channel rank for rank between 7 and 12.
@@ -589,7 +771,7 @@ typedef struct
* @param _RANKNB_: Rank number.
* @retval None
*/
-#define __HAL_ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
+#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))
/**
* @brief Set the selected regular channel rank for rank between 13 and 16.
@@ -597,128 +779,62 @@ typedef struct
* @param _RANKNB_: Rank number.
* @retval None
*/
-#define __HAL_ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
+#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))
/**
* @brief Enable ADC continuous conversion mode.
* @param _CONTINUOUS_MODE_: Continuous mode.
* @retval None
*/
-#define __HAL_ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
+#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
/**
* @brief Configures the number of discontinuous conversions for the regular group channels.
* @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
* @retval None
*/
-#define __HAL_ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << 13)
+#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
/**
* @brief Enable ADC scan mode.
* @param _SCANCONV_MODE_: Scan conversion mode.
* @retval None
*/
-#define __HAL_ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
+#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
/**
* @brief Enable the ADC end of conversion selection.
* @param _EOCSelection_MODE_: End of conversion selection mode.
* @retval None
*/
-#define __HAL_ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
+#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
/**
* @brief Enable the ADC DMA continuous request.
* @param _DMAContReq_MODE_: DMA continuous request mode.
* @retval None
*/
-#define __HAL_ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
+#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
/**
- * @brief Enable the ADC end of conversion interrupt.
- * @param __HANDLE__: specifies the ADC Handle.
- * @param __INTERRUPT__: ADC Interrupt.
+ * @brief Return resolution bits in CR1 register.
+ * @param __HANDLE__: ADC handle
* @retval None
*/
-#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
+#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
/**
- * @brief Disable the ADC end of conversion interrupt.
- * @param __HANDLE__: specifies the ADC Handle.
- * @param __INTERRUPT__: ADC interrupt.
- * @retval None
- */
-#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
-
-/** @brief Check if the specified ADC interrupt source is enabled or disabled.
- * @param __HANDLE__: specifies the ADC Handle.
- * @param __INTERRUPT__: specifies the ADC interrupt source to check.
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/**
- * @brief Clear the ADC's pending flags.
- * @param __HANDLE__: specifies the ADC Handle.
- * @param __FLAG__: ADC flag.
- * @retval None
+ * @}
*/
-#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) &= ~(__FLAG__))
-/**
- * @brief Get the selected ADC's flag status.
- * @param __HANDLE__: specifies the ADC Handle.
- * @param __FLAG__: ADC flag.
- * @retval None
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup ADC_Private_Functions ADC Private Functions
+ * @{
*/
-#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/**
- * @brief Return resolution bits in CR1 register.
- * @param __HANDLE__: ADC handle
- * @retval None
+ * @}
*/
-#define __HAL_ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
-
-/* Include ADC HAL Extension module */
-#include "stm32f2xx_hal_adc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/* Initialization/de-initialization functions ***********************************/
-HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
-void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
-void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
-
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-
-HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
-
-HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
-
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
-
-HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
-HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
-
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
-
-void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
-
-/* Peripheral Control functions *************************************************/
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
-
-/* Peripheral State functions ***************************************************/
-HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_adc_ex.h b/f2/include/stm32f2xx_hal_adc_ex.h
index 42786c12ec39010efbd204ec8dd6e8fafacd4acd..38e64c6f398891d0922c8ade063e836832b67ea9 100755
--- a/f2/include/stm32f2xx_hal_adc_ex.h
+++ b/f2/include/stm32f2xx_hal_adc_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_adc.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,54 +55,104 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Types ADC Exported Types
+ * @{
+ */
/**
- * @brief ADC Configuration injected Channel structure definition
- */
+ * @brief ADC Configuration injected Channel structure definition
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
+ * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
+ * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
+ * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled
+ * - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
+ * - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
+ */
typedef struct
{
- uint32_t InjectedChannel; /*!< Configure the ADC injected channel
- This parameter can be a value of @ref ADC_channels. */
- uint32_t InjectedRank; /*!< The rank in the injected group sequencer
- This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
- uint32_t InjectedSamplingTime; /*!< The sample time value to be set for the selected channel.
- This parameter can be a value of @ref ADC_sampling_times */
- uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data when convert injected channels.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
- uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for
- injected channel group.
- This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
- uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group
- conversion after regular one */
- uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous mode or not for injected channels.
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t ExternalTrigInjecConvEdge; /*!< Select the external trigger edge and enable the trigger of an injected channels.
- This parameter can be a value of @ref ADC_External_trigger_Source_Injected. */
- uint32_t ExternalTrigInjecConv; /*!< Select the external event used to trigger the start of conversion of a injected channels.
- This parameter can be a value of @ref ADC_External_trigger_Source_Injected */
-}ADC_InjectionConfTypeDef;
+ uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
+ This parameter can be a value of @ref ADC_channels
+ Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
+ uint32_t InjectedRank; /*!< Rank in the injected group sequencer
+ This parameter must be a value of @ref ADCEx_injected_rank
+ Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
+ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
+ This parameter can be a value of @ref ADC_sampling_times
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
+ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
+ Offset value must be a positive number.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits),
+ this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
+ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
+ To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
+ This parameter can be set to ENABLE or DISABLE.
+ Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
+ Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
+ Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
+ To maintain JAUTO always enabled, DMA must be configured in circular mode.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
+ If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
+ If set to external trigger source, triggering is on event rising edge.
+ This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+ If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
+ This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
+ If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+}ADC_InjectionConfTypeDef;
+/**
+ * @}
+ */
/**
- * @brief ADC Configuration multi-mode structure definition
+ * @brief ADC Configuration multi-mode structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
- This parameter can be a value of @ref ADC_Common_mode */
+ This parameter can be a value of @ref ADCEx_Common_mode */
uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
- This parameter can be a value of @ref ADC_Direct_memory_access_mode_for_multi_mode */
+ This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */
uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */
}ADC_MultiModeTypeDef;
-/* Exported constants --------------------------------------------------------*/
+/**
+ * @}
+ */
-/** @defgroup ADCEx_Exported_Constants
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Constants ADC Exported Constants
* @{
*/
-
-/** @defgroup ADCEx_Common_mode
+/** @defgroup ADCEx_Common_mode ADC Common Mode
* @{
*/
#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000)
@@ -118,57 +168,33 @@ typedef struct
#define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
#define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
-
-#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
- ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
- ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
- ((MODE) == ADC_DUALMODE_INJECSIMULT) || \
- ((MODE) == ADC_DUALMODE_REGSIMULT) || \
- ((MODE) == ADC_DUALMODE_INTERL) || \
- ((MODE) == ADC_DUALMODE_ALTERTRIG) || \
- ((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
- ((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \
- ((MODE) == ADC_TRIPLEMODE_INJECSIMULT) || \
- ((MODE) == ADC_TRIPLEMODE_REGSIMULT) || \
- ((MODE) == ADC_TRIPLEMODE_INTERL) || \
- ((MODE) == ADC_TRIPLEMODE_ALTERTRIG))
/**
* @}
*/
-/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode
+/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
* @{
*/
#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA mode disabled */
#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
-
-#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
- ((MODE) == ADC_DMAACCESSMODE_1) || \
- ((MODE) == ADC_DMAACCESSMODE_2) || \
- ((MODE) == ADC_DMAACCESSMODE_3))
/**
* @}
*/
-/** @defgroup ADCEx_External_trigger_edge_Injected
+/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
* @{
*/
#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000)
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
-
-#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \
- ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \
- ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
- ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))
/**
* @}
*/
-/** @defgroup ADCEx_External_trigger_Source_Injected
+/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
* @{
*/
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)0x00000000)
@@ -187,89 +213,156 @@ typedef struct
#define ADC_EXTERNALTRIGINJECCONV_T8_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ((uint32_t)ADC_CR2_JEXTSEL)
-
-#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15))
+#define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1)
/**
* @}
*/
-/** @defgroup ADCEx_injected_channel_selection
+/** @defgroup ADCEx_injected_rank ADC Injected Rank
* @{
*/
#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
-
/**
* @}
*/
-
-/** @defgroup ADCEx_injected_length
- * @{
- */
-#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
-/**
- * @}
- */
-/** @defgroup ADCEx_injected_rank
+/** @defgroup ADCEx_channels ADC Specific Channels
* @{
- */
-#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)4)))
+ */
+#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)
/**
* @}
*/
-
+
+
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+ * @{
+ */
/**
- * @brief Set the selected injected Channel rank.
- * @param _CHANNELNB_: Channel number.
- * @param _RANKNB_: Rank number.
- * @param _JSQR_JL_: Sequence length.
- * @retval None
- */
-#define __HAL_ADC_JSQR(_CHANNELNB_, _RANKNB_,_JSQR_JL_) \
-((_CHANNELNB_) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADCEx_Exported_Functions_Group1
+ * @{
+ */
/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
-uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
-void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
+void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
/* Peripheral Control functions *************************************************/
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADCEx_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADCEx_Private_Macros ADC Private Macros
+ * @{
+ */
+#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
+ ((MODE) == ADC_DUALMODE_INJECSIMULT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT) || \
+ ((MODE) == ADC_DUALMODE_INTERL) || \
+ ((MODE) == ADC_DUALMODE_ALTERTRIG) || \
+ ((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
+ ((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \
+ ((MODE) == ADC_TRIPLEMODE_INJECSIMULT) || \
+ ((MODE) == ADC_TRIPLEMODE_REGSIMULT) || \
+ ((MODE) == ADC_TRIPLEMODE_INTERL) || \
+ ((MODE) == ADC_TRIPLEMODE_ALTERTRIG))
+#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
+ ((MODE) == ADC_DMAACCESSMODE_1) || \
+ ((MODE) == ADC_DMAACCESSMODE_2) || \
+ ((MODE) == ADC_DMAACCESSMODE_3))
+#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)|| \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START))
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)4)))
+
+/**
+ * @brief Set the selected injected Channel rank.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @param _JSQR_JL_: Sequence length.
+ * @retval None
+ */
+#define ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup ADCEx_Private_Functions ADC Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/**
* @}
*/
diff --git a/f2/include/stm32f2xx_hal_can.h b/f2/include/stm32f2xx_hal_can.h
index f3f9ccb4ed626e64a3a74c7ec087a02955daa0df..e9efa3e57c88ee067fed09194fd73af735d53fe0 100755
--- a/f2/include/stm32f2xx_hal_can.h
+++ b/f2/include/stm32f2xx_hal_can.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_can.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,52 +55,55 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup CAN_Exported_Types CAN Exported Types
+ * @{
+ */
-/**
- * @brief HAL State structures definition
- */
+/**
+ * @brief HAL State structures definition
+ */
typedef enum
{
HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */
- HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */
- HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */
+ HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */
HAL_CAN_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */
+ HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */
}HAL_CAN_StateTypeDef;
-/**
+/**
* @brief CAN init structure definition
*/
typedef struct
{
- uint32_t Prescaler; /*!< Specifies the length of a time quantum.
+ uint32_t Prescaler; /*!< Specifies the length of a time quantum.
This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
-
+
uint32_t Mode; /*!< Specifies the CAN operating mode.
This parameter can be a value of @ref CAN_operating_mode */
- uint32_t SJW; /*!< Specifies the maximum number of time quanta
- the CAN hardware is allowed to lengthen or
+ uint32_t SJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
shorten a bit to perform resynchronization.
This parameter can be a value of @ref CAN_synchronisation_jump_width */
- uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
-
+
uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-
+
uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
This parameter can be set to ENABLE or DISABLE. */
-
+
uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
This parameter can be set to ENABLE or DISABLE */
- uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
+ uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
@@ -113,33 +116,33 @@ typedef struct
This parameter can be set to ENABLE or DISABLE */
}CAN_InitTypeDef;
-/**
+/**
* @brief CAN filter configuration structure definition
*/
typedef struct
{
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
-
- uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
+
+ uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
@@ -150,50 +153,50 @@ typedef struct
uint32_t FilterActivation; /*!< Enable or disable the filter.
This parameter can be set to ENABLE or DISABLE. */
-
- uint32_t BankNumber; /*!< Select the start slave bank filter
- This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
-
+
+ uint32_t BankNumber; /*!< Select the start slave bank filter.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
+
}CAN_FilterConfTypeDef;
-/**
- * @brief CAN Tx message structure definition
+/**
+ * @brief CAN Tx message structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
-
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+
uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
-
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
- This parameter can be a value of @ref CAN_identifier_type */
+ This parameter can be a value of @ref CAN_Identifier_Type */
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
- This parameter can be a value of @ref CAN_remote_transmission_request */
+ This parameter can be a value of @ref CAN_remote_transmission_request */
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
- uint32_t Data[8]; /*!< Contains the data to be transmitted.
+ uint8_t Data[8]; /*!< Contains the data to be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
-
+
}CanTxMsgTypeDef;
-/**
- * @brief CAN Rx message structure definition
+/**
+ * @brief CAN Rx message structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
- uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
- This parameter can be a value of @ref CAN_identifier_type */
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
+ This parameter can be a value of @ref CAN_Identifier_Type */
uint32_t RTR; /*!< Specifies the type of frame for the received message.
This parameter can be a value of @ref CAN_remote_transmission_request */
@@ -201,49 +204,52 @@ typedef struct
uint32_t DLC; /*!< Specifies the length of the frame that will be received.
This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
- uint32_t Data[8]; /*!< Contains the data to be received.
+ uint8_t Data[8]; /*!< Contains the data to be received.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
-
- uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
+
+ uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
This parameter can be CAN_FIFO0 or CAN_FIFO1 */
-
+
}CanRxMsgTypeDef;
-/**
- * @brief CAN handle Structure definition
- */
+/**
+ * @brief CAN handle Structure definition
+ */
typedef struct
{
CAN_TypeDef *Instance; /*!< Register base address */
-
+
CAN_InitTypeDef Init; /*!< CAN required parameters */
-
+
CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */
-
+
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
-
+
HAL_LockTypeDef Lock; /*!< CAN locking object */
-
+
__IO uint32_t ErrorCode; /*!< CAN Error code */
-
+
}CAN_HandleTypeDef;
-/* Exported constants --------------------------------------------------------*/
+/**
+ * @}
+ */
-/** @defgroup CAN_Exported_Constants
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CAN_Exported_Constants CAN Exported Constants
* @{
*/
-/** @defgroup HAL CAN Error Code
+/** @defgroup HAL_CAN_Error_Code HAL CAN Error Code
* @{
*/
#define HAL_CAN_ERROR_NONE 0x00 /*!< No error */
-#define HAL_CAN_ERROR_EWG 0x01 /*!< EWG error */
+#define HAL_CAN_ERROR_EWG 0x01 /*!< EWG error */
#define HAL_CAN_ERROR_EPV 0x02 /*!< EPV error */
#define HAL_CAN_ERROR_BOF 0x04 /*!< BOF error */
#define HAL_CAN_ERROR_STF 0x08 /*!< Stuff error */
@@ -254,10 +260,9 @@ typedef struct
#define HAL_CAN_ERROR_CRC 0x100 /*!< LEC transfer error */
/**
* @}
- */
-
+ */
-/** @defgroup CAN_InitStatus
+/** @defgroup CAN_InitStatus CAN InitStatus
* @{
*/
#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */
@@ -266,38 +271,29 @@ typedef struct
* @}
*/
-/** @defgroup CAN_operating_mode
+/** @defgroup CAN_operating_mode CAN Operating Mode
* @{
*/
#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
-
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
- ((MODE) == CAN_MODE_LOOPBACK)|| \
- ((MODE) == CAN_MODE_SILENT) || \
- ((MODE) == CAN_MODE_SILENT_LOOPBACK))
/**
* @}
*/
-
-/** @defgroup CAN_synchronisation_jump_width
+/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
* @{
*/
#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
-
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
- ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
/**
* @}
*/
-/** @defgroup CAN_time_quantum_in_bit_segment_1
+/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
* @{
*/
#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
@@ -316,13 +312,11 @@ typedef struct
#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
-
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
/**
* @}
*/
-/** @defgroup CAN_time_quantum_in_bit_segment_2
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
* @{
*/
#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
@@ -333,138 +327,70 @@ typedef struct
#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
-
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
-/**
- * @}
- */
-
-/** @defgroup CAN_clock_prescaler
- * @{
- */
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_number
- * @{
- */
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
/**
* @}
*/
-/** @defgroup CAN_filter_mode
+/** @defgroup CAN_filter_mode CAN Filter Mode
* @{
*/
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
-
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
- ((MODE) == CAN_FILTERMODE_IDLIST))
/**
* @}
*/
-/** @defgroup CAN_filter_scale
+/** @defgroup CAN_filter_scale CAN Filter Scale
* @{
*/
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
-
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
- ((SCALE) == CAN_FILTERSCALE_32BIT))
/**
* @}
*/
-/** @defgroup CAN_filter_FIFO
+/** @defgroup CAN_filter_FIFO CAN Filter FIFO
* @{
*/
#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
-
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
- ((FIFO) == CAN_FILTER_FIFO1))
-
-/* Legacy defines */
-#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
-#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
-/**
- * @}
- */
-
-/** @defgroup CAN_Start_bank_filter_for_slave_CAN
- * @{
- */
-#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
/**
* @}
*/
-/** @defgroup CAN_Tx
- * @{
- */
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
-#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
-#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
-/**
- * @}
- */
-
-/** @defgroup CAN_identifier_type
+/** @defgroup CAN_Identifier_Type CAN Identifier Type
* @{
*/
#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
-#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
- ((IDTYPE) == CAN_ID_EXT))
/**
* @}
*/
-/** @defgroup CAN_remote_transmission_request
+/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
* @{
*/
#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
-
/**
* @}
*/
-/** @defgroup CAN_transmit_constants
- * @{
- */
-#define CAN_TXSTATUS_FAILED ((uint8_t)0x00) /*!< CAN transmission failed */
-#define CAN_TXSTATUS_OK ((uint8_t)0x01) /*!< CAN transmission succeeded */
-#define CAN_TXSTATUS_PENDING ((uint8_t)0x02) /*!< CAN transmission pending */
-#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_receive_FIFO_number_constants
+/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
* @{
*/
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
-
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
/**
* @}
*/
-/** @defgroup CAN_flags
+/** @defgroup CAN_flags CAN Flags
* @{
*/
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with
CAN_GetFlagStatus() function. */
/* Transmit Flags */
@@ -489,35 +415,20 @@ typedef struct
#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */
#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */
#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
In this case the SLAK bit can be polled.*/
/* Error Flags */
#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */
#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */
#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */
-
-#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_BOF) || \
- ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
- ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_SLAK) || \
- ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
- ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0))
-
-
-#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_SLAK) || ((FLAG) == CAN_FLAG_RQCP2) || \
- ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) || \
- ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
- ((FLAG) == CAN_FLAG_WKU))
/**
* @}
*/
-
-/** @defgroup CAN_interrupts
+/** @defgroup CAN_Interrupts CAN Interrupts
* @{
- */
+ */
#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
/* Receive Interrupts */
@@ -538,45 +449,34 @@ typedef struct
#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
-
-/* Flags named as Interrupts : kept only for FW compatibility */
-#define CAN_IT_RQCP0 CAN_IT_TME
-#define CAN_IT_RQCP1 CAN_IT_TME
-#define CAN_IT_RQCP2 CAN_IT_TME
-
-#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
- ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
- ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
-
-#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
- ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
/**
* @}
*/
-/* Time out for INAK bit */
-#define INAK_TIMEOUT ((uint32_t)0x0000FFFF)
-/* Time out for SLAK bit */
-#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF)
-
-/* Mailboxes definition */
+/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
+ * @{
+ */
#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+/**
+ * @}
+ */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CAN_Exported_Macros CAN Exported Macros
+ * @{
+ */
+
+/** @brief Reset CAN handle state
+ * @param __HANDLE__: specifies the CAN Handle.
+ * @retval None
+ */
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
/**
* @brief Enable the specified CAN interrupts.
@@ -630,7 +530,6 @@ typedef struct
* @arg CAN_FLAG_BOF: Bus-Off Flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define CAN_FLAG_MASK ((uint32_t)0x000000FF)
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
@@ -666,18 +565,18 @@ typedef struct
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 1)? (((__HANDLE__)->Instance->MSR) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__HANDLE__)->Instance->ESR) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))))
+((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 1)? (((__HANDLE__)->Instance->MSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__HANDLE__)->Instance->ESR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))))
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
* @param __HANDLE__: CAN Handle
* @param __INTERRUPT__: specifies the CAN interrupt source to check.
* This parameter can be one of the following values:
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
- * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
+ * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
* @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
@@ -694,8 +593,6 @@ typedef struct
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
-
-
/**
* @brief Release the specified receive FIFO.
* @param __HANDLE__: CAN handle
@@ -703,7 +600,7 @@ typedef struct
* @retval None
*/
#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
+((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
/**
* @brief Cancel a transmit request.
@@ -719,24 +616,40 @@ typedef struct
/**
* @brief Enable or disable the DBG Freeze for CAN.
* @param __HANDLE__: CAN Handle
- * @param __NEWSTATE__: new state of the CAN peripheral.
+ * @param __NEWSTATE__: new state of the CAN peripheral.
* This parameter can be: ENABLE (CAN reception/transmission is frozen
- * during debug. Reception FIFOs can still be accessed/controlled normally)
+ * during debug. Reception FIFOs can still be accessed/controlled normally)
* or DISABLE (CAN is working during debug).
* @retval None
*/
#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
-((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
-
-/* Exported functions --------------------------------------------------------*/
+((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CAN_Exported_Functions
+ * @{
+ */
-/* Initialization/de-initialization functions ***********************************/
+/** @addtogroup CAN_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ***********************************/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+/** @addtogroup CAN_Exported_Functions_Group2
+ * @{
+ */
/* I/O operation functions ******************************************************/
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
@@ -744,15 +657,99 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, u
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
+void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+/**
+ * @}
+ */
+/** @addtogroup CAN_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral State functions ***************************************************/
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CAN_Private_Types CAN Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Variables CAN Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+ * @{
+ */
+#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
+#define CAN_FLAG_MASK ((uint32_t)0x000000FF)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CAN_Private_Macros CAN Private Macros
+ * @{
+ */
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
+ ((MODE) == CAN_MODE_LOOPBACK)|| \
+ ((MODE) == CAN_MODE_SILENT) || \
+ ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
+ ((MODE) == CAN_FILTERMODE_IDLIST))
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
+ ((SCALE) == CAN_FILTERSCALE_32BIT))
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
+ ((FIFO) == CAN_FILTER_FIFO1))
+#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
+ ((IDTYPE) == CAN_ID_EXT))
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Functions CAN Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
-void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_cortex.h b/f2/include/stm32f2xx_hal_cortex.h
index f485cba0305706765962e443d9c8aba86f0245d2..0024f517d0bf7967485035faf51bfb6b6f3c701a 100755
--- a/f2/include/stm32f2xx_hal_cortex.h
+++ b/f2/include/stm32f2xx_hal_cortex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_cortex.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,17 +54,57 @@
* @{
*/
/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types
+ * @{
+ */
-/** @defgroup CORTEX_Exported_Constants
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+ * @brief MPU Region initialization structure
* @{
*/
+typedef struct
+{
+ uint8_t Enable; /*!< Specifies the status of the region.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
+ uint8_t Number; /*!< Specifies the number of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Number */
+ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
+ uint8_t Size; /*!< Specifies the size of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Size */
+ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint8_t TypeExtField; /*!< Specifies the TEX field level.
+ This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
+ uint8_t AccessPermission; /*!< Specifies the region access permission type.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
+ uint8_t DisableExec; /*!< Specifies the instruction access status.
+ This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
+ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
+ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
+ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
+}MPU_Region_InitTypeDef;
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
-/** @defgroup CORTEX_Preemption_Priority_Group
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{
*/
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+ * @{
+ */
#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
@@ -75,33 +115,160 @@
1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
+/**
+ * @}
+ */
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
- ((GROUP) == NVIC_PRIORITYGROUP_1) || \
- ((GROUP) == NVIC_PRIORITYGROUP_2) || \
- ((GROUP) == NVIC_PRIORITYGROUP_3) || \
- ((GROUP) == NVIC_PRIORITYGROUP_4))
+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
+ * @{
+ */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
+#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+/**
+ * @}
+ */
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
+ * @{
+ */
+#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
+#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
+#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
+#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
+/**
+ * @}
+ */
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+ * @{
+ */
+#define MPU_REGION_ENABLE ((uint8_t)0x01)
+#define MPU_REGION_DISABLE ((uint8_t)0x00)
/**
* @}
*/
-/** @defgroup CORTEX_SysTick_clock_source
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
-#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
-#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
- ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
+#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+ * @{
+ */
+#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+ * @{
+ */
+#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+ * @{
+ */
+#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
+ * @{
+ */
+#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
+#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
+#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
/**
* @}
*/
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+ * @{
+ */
+#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
+#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
+#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
+#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
+#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
+#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
+#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+ * @{
+ */
+#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
+#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
+#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
+#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+ * @{
+ */
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
+#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
+#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
+#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+
/* Exported Macros -----------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
+ * @{
+ */
/** @brief Configures the SysTick clock source.
* @param __CLKSRC__: specifies the SysTick clock source.
@@ -119,22 +286,36 @@
else \
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \
} while(0)
-
/**
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/* Initialization and de-initialization functions *******************************/
+/** @addtogroup CORTEX_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+ * @}
+ */
-/* Peripheral Control functions *************************************************/
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+#if (__MPU_PRESENT == 1)
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
@@ -144,6 +325,152 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+ * @{
+ */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+ ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
+ ((TYPE) == MPU_TEX_LEVEL1) || \
+ ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
+ ((TYPE) == MPU_REGION_PRIV_RW) || \
+ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+ ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+ ((TYPE) == MPU_REGION_PRIV_RO) || \
+ ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
+ ((NUMBER) == MPU_REGION_NUMBER1) || \
+ ((NUMBER) == MPU_REGION_NUMBER2) || \
+ ((NUMBER) == MPU_REGION_NUMBER3) || \
+ ((NUMBER) == MPU_REGION_NUMBER4) || \
+ ((NUMBER) == MPU_REGION_NUMBER5) || \
+ ((NUMBER) == MPU_REGION_NUMBER6) || \
+ ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
+ ((SIZE) == MPU_REGION_SIZE_64B) || \
+ ((SIZE) == MPU_REGION_SIZE_128B) || \
+ ((SIZE) == MPU_REGION_SIZE_256B) || \
+ ((SIZE) == MPU_REGION_SIZE_512B) || \
+ ((SIZE) == MPU_REGION_SIZE_1KB) || \
+ ((SIZE) == MPU_REGION_SIZE_2KB) || \
+ ((SIZE) == MPU_REGION_SIZE_4KB) || \
+ ((SIZE) == MPU_REGION_SIZE_8KB) || \
+ ((SIZE) == MPU_REGION_SIZE_16KB) || \
+ ((SIZE) == MPU_REGION_SIZE_32KB) || \
+ ((SIZE) == MPU_REGION_SIZE_64KB) || \
+ ((SIZE) == MPU_REGION_SIZE_128KB) || \
+ ((SIZE) == MPU_REGION_SIZE_256KB) || \
+ ((SIZE) == MPU_REGION_SIZE_512KB) || \
+ ((SIZE) == MPU_REGION_SIZE_1MB) || \
+ ((SIZE) == MPU_REGION_SIZE_2MB) || \
+ ((SIZE) == MPU_REGION_SIZE_4MB) || \
+ ((SIZE) == MPU_REGION_SIZE_8MB) || \
+ ((SIZE) == MPU_REGION_SIZE_16MB) || \
+ ((SIZE) == MPU_REGION_SIZE_32MB) || \
+ ((SIZE) == MPU_REGION_SIZE_64MB) || \
+ ((SIZE) == MPU_REGION_SIZE_128MB) || \
+ ((SIZE) == MPU_REGION_SIZE_256MB) || \
+ ((SIZE) == MPU_REGION_SIZE_512MB) || \
+ ((SIZE) == MPU_REGION_SIZE_1GB) || \
+ ((SIZE) == MPU_REGION_SIZE_2GB) || \
+ ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
+ * @brief CORTEX private functions
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1)
+/**
+ * @brief Disables the MPU
+ * @retval None
+ */
+__STATIC_INLINE void HAL_MPU_Disable(void)
+{
+ /* Disable fault exceptions */
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
+ /* Disable the MPU */
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/**
+ * @brief Enables the MPU
+ * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
+ * NMI, FAULTMASK and privileged access to the default memory
+ * This parameter can be one of the following values:
+ * @arg MPU_HFNMI_PRIVDEF_NONE
+ * @arg MPU_HARDFAULT_NMI
+ * @arg MPU_PRIVILEGED_DEFAULT
+ * @arg MPU_HFNMI_PRIVDEF
+ * @retval None
+ */
+__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+ /* Enable the MPU */
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+ /* Enable fault exceptions */
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+}
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_crc.h b/f2/include/stm32f2xx_hal_crc.h
index ae63dbce1dcf9cf0a83865b26bcccf0f0781936e..206f3064fb9336b3837a8872550bbf59c2a89031 100755
--- a/f2/include/stm32f2xx_hal_crc.h
+++ b/f2/include/stm32f2xx_hal_crc.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_crc.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,15 +50,19 @@
* @{
*/
-/** @addtogroup CRC
+/** @defgroup CRC CRC
+ * @brief CRC HAL module driver
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
+/** @defgroup CRC_Exported_Types CRC Exported Types
+ * @{
+ */
-/**
- * @brief CRC HAL State Structure definition
- */
+/** @defgroup CRC_Exported_Types_Group1 CRC State Structure definition
+ * @{
+ */
typedef enum
{
HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */
@@ -68,9 +72,12 @@ typedef enum
HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */
}HAL_CRC_StateTypeDef;
-
/**
- * @brief CRC handle Structure definition
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Types_Group2 CRC Handle Structure definition
+ * @{
*/
typedef struct
{
@@ -81,9 +88,25 @@ typedef struct
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
}CRC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRC_Exported_Macros CRC Exported Macros
+ * @{
+ */
+
+/** @brief Resets CRC handle state
+ * @param __HANDLE__: CRC handle
+ * @retval None
+ */
+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
/**
* @brief Resets CRC Data Register.
@@ -92,29 +115,131 @@ typedef struct
*/
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
+/**
+ * @brief Stores a 8-bit data in the Independent Data(ID) register.
+ * @param __HANDLE__: CRC handle
+ * @param __VALUE__: 8-bit value to be stored in the ID register
+ * @retval None
+ */
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
+
+/**
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register.
+ * @param __HANDLE__: CRC handle
+ * @retval 8-bit value of the ID register
+ */
+#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+ * @{
+ */
-/* Initialization/de-initialization functions **********************************/
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+/**
+ * @}
+ */
-/* Peripheral Control functions ************************************************/
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+/**
+ * @}
+ */
-/* Peripheral State functions **************************************************/
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+ * @{
+ */
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CRC_Private_Types CRC Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup CRC_Private_Defines CRC Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRC_Private_Variables CRC Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRC_Private_Constants CRC Private Constants
+ * @{
+ */
/**
* @}
*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CRC_Private_Macros CRC Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup CRC_Private_Functions_Prototypes CRC Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CRC_Private_Functions CRC Private Functions
+ * @{
+ */
+
/**
* @}
*/
-
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
diff --git a/f2/include/stm32f2xx_hal_cryp.h b/f2/include/stm32f2xx_hal_cryp.h
index 7cdb2d74be4829111aa68ef3d35259ed2e9ecd64..1a696758eb4751b42d0f91fba218410e15ab0412 100755
--- a/f2/include/stm32f2xx_hal_cryp.h
+++ b/f2/include/stm32f2xx_hal_cryp.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_cryp.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -53,59 +53,74 @@
/** @addtogroup CRYP
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
-/**
- * @brief CRYP Configuration Structure definition
+/** @defgroup CRYP_Exported_Types CRYP Exported Types
+ * @{
+ */
+
+/** @defgroup CRYP_Exported_Types_Group1 CRYP Configuration Structure definition
+ * @{
*/
+
typedef struct
-{
+{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
- This parameter can be a value of @ref CRYP_Data_Type */
-
+ This parameter can be a value of @ref CRYP CRYP_Data_Type */
+
uint32_t KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit key length.
- This parameter can be a value of @ref CRYP_Key_Size */
-
+ This parameter can be a value of @ref CRYP CRYP_Key_Size */
+
uint8_t* pKey; /*!< The key used for encryption/decryption */
-
+
uint8_t* pInitVect; /*!< The initialization vector used also as initialization
counter in CTR mode */
-
+
uint8_t IVSize; /*!< The size of initialization vector.
This parameter (called nonce size in CCM) is used only
in AES-128/192/256 encryption/decryption CCM mode */
-
+
uint8_t TagSize; /*!< The size of returned authentication TAG.
This parameter is used only in AES-128/192/256
encryption/decryption CCM mode */
-
+
uint8_t* Header; /*!< The header used in GCM and CCM modes */
-
- uint16_t HeaderSize; /*!< The size of header buffer in bytes */
-
+
+ uint32_t HeaderSize; /*!< The size of header buffer in bytes */
+
uint8_t* pScratch; /*!< Scratch buffer used to append the header. It's size must be equal to header size + 21 bytes.
This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */
-
}CRYP_InitTypeDef;
/**
- * @brief HAL CRYP State structures definition
- */
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Types_Group2 CRYP State structures definition
+ * @{
+ */
+
+
typedef enum
{
HAL_CRYP_STATE_RESET = 0x00, /*!< CRYP not yet initialized or disabled */
HAL_CRYP_STATE_READY = 0x01, /*!< CRYP initialized and ready for use */
HAL_CRYP_STATE_BUSY = 0x02, /*!< CRYP internal processing is ongoing */
HAL_CRYP_STATE_TIMEOUT = 0x03, /*!< CRYP timeout state */
- HAL_CRYP_STATE_ERROR = 0x04 /*!< CRYP error state */
-
+ HAL_CRYP_STATE_ERROR = 0x04 /*!< CRYP error state */
}HAL_CRYP_STATETypeDef;
/**
- * @brief HAL CRYP phase structures definition
- */
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Types_Group3 CRYP phase structures definition
+ * @{
+ */
+
+
typedef enum
{
HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */
@@ -115,73 +130,77 @@ typedef enum
}HAL_PhaseTypeDef;
/**
- * @brief CRYP handle Structure definition
- */
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Types_Group4 CRYP handle Structure definition
+ * @{
+ */
+
typedef struct
-{
+{
+ CRYP_TypeDef *Instance; /*!< CRYP registers base address */
+
CRYP_InitTypeDef Init; /*!< CRYP required parameters */
-
+
uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
+
uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
- __IO uint16_t CrypInCount; /*!< Counter of inputed data */
-
- __IO uint16_t CrypOutCount; /*!< Counter of outputed data */
-
+
+ __IO uint16_t CrypInCount; /*!< Counter of input data */
+
+ __IO uint16_t CrypOutCount; /*!< Counter of outputted data */
+
HAL_StatusTypeDef Status; /*!< CRYP peripheral status */
-
+
HAL_PhaseTypeDef Phase; /*!< CRYP peripheral phase */
-
+
DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
-
+
DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
-
+
HAL_LockTypeDef Lock; /*!< CRYP locking object */
-
+
__IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
-
}CRYP_HandleTypeDef;
-/* Exported constants --------------------------------------------------------*/
+/**
+ * @}
+ */
-/** @defgroup CRYP_Exported_Constants
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
* @{
*/
-/** @defgroup CRYP_Key_Size
+/** @defgroup CRYP_Exported_Constants_Group1 CRYP CRYP_Key_Size
* @{
- */
+ */
#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000)
#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
-
-#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KEYSIZE_128B) || \
- ((KEYSIZE) == CRYP_KEYSIZE_192B) || \
- ((KEYSIZE) == CRYP_KEYSIZE_256B))
-/**
+/**
* @}
*/
-/** @defgroup CRYP_Data_Type
+/** @defgroup CRYP_Exported_Constants_Group2 CRYP CRYP_Data_Type
* @{
*/
#define CRYP_DATATYPE_32B ((uint32_t)0x00000000)
#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE
-
-#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DATATYPE_32B) || \
- ((DATATYPE) == CRYP_DATATYPE_16B) || \
- ((DATATYPE) == CRYP_DATATYPE_8B) || \
- ((DATATYPE) == CRYP_DATATYPE_1B))
-/**
+/**
* @}
*/
-/** @defgroup CRYP_AlgoModeDirection
+/** @defgroup CRYP_Exported_Constants_Group3 CRYP CRYP_AlgoModeDirection
* @{
- */
+ */
#define CRYP_CR_ALGOMODE_DIRECTION ((uint32_t)0x0008003C)
#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT ((uint32_t)0x00000000)
#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT ((uint32_t)0x00000004)
@@ -201,7 +220,7 @@ typedef struct
* @}
*/
-/** @defgroup CRYP_Interrupt
+/** @defgroup CRYP_Exported_Constants_Group4 CRYP CRYP_Interrupt
* @{
*/
#define CRYP_IT_INI ((uint32_t)CRYP_IMSCR_INIM) /*!< Input FIFO Interrupt */
@@ -210,11 +229,9 @@ typedef struct
* @}
*/
-
-/** @defgroup CRYP_Flags
+/** @defgroup CRYP_Exported_Constants_Group5 CRYP CRYP_Flags
* @{
*/
-
#define CRYP_FLAG_BUSY ((uint32_t)0x00000010) /*!< The CRYP core is currently
processing a block of data
or a key preparation (for
@@ -229,38 +246,48 @@ typedef struct
interrupt status */
/**
* @}
- */
+ */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
+ * @{
+ */
+
+/** @brief Reset CRYP handle state
+ * @param __HANDLE__: specifies the CRYP handle.
+ * @retval None
+ */
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
/**
* @brief Enable/Disable the CRYP peripheral.
- * @param None
+ * @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#define __HAL_CRYP_ENABLE() (CRYP->CR |= CRYP_CR_CRYPEN)
-#define __HAL_CRYP_DISABLE() (CRYP->CR &= ~CRYP_CR_CRYPEN)
+#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
+#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
/**
* @brief Flush the data FIFO.
- * @param None
+ * @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#define __HAL_CRYP_FIFO_FLUSH() (CRYP->CR |= CRYP_CR_FFLUSH)
+#define __HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
/**
- * @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC,...
+ * @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC.
+ * @param __HANDLE__: specifies the CRYP handle.
* @param MODE: The algorithm mode.
* @retval None
*/
-#define __HAL_CRYP_SET_MODE(MODE) CRYP->CR |= (uint32_t)(MODE)
-
+#define __HAL_CRYP_SET_MODE(__HANDLE__, MODE) ((__HANDLE__)->Instance->CR |= (uint32_t)(MODE))
/** @brief Check whether the specified CRYP flag is set or not.
+ * @param __HANDLE__: specifies the CRYP handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
@@ -273,38 +300,62 @@ typedef struct
* @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define CRYP_FLAG_MASK ((uint32_t)0x0000001F)
-#define __HAL_CRYP_GET_FLAG(__FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01)?(((CRYP->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
- (((CRYP->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
+
+#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
+ ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
/** @brief Check whether the specified CRYP interrupt is set or not.
+ * @param __HANDLE__: specifies the CRYP handle.
* @param __INTERRUPT__: specifies the interrupt to check.
* This parameter can be one of the following values:
* @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending
* @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_CRYP_GET_IT(__INTERRUPT__) ((CRYP->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Enable the CRYP interrupt.
+ * @param __HANDLE__: specifies the CRYP handle.
* @param __INTERRUPT__: CRYP Interrupt.
* @retval None
*/
-#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((CRYP->IMSCR) |= (__INTERRUPT__))
+#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
/**
* @brief Disable the CRYP interrupt.
+ * @param __HANDLE__: specifies the CRYP handle.
* @param __INTERRUPT__: CRYP interrupt.
* @retval None
*/
-#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((CRYP->IMSCR) &= ~(__INTERRUPT__))
+#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+
+
/* Exported functions --------------------------------------------------------*/
-/* Initialization/de-initialization functions **********************************/
+/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
+ * @{
+ */
+
+/** @addtogroup CRYP_Exported_Functions_Group1
+ * @{
+ */
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
+/**
+ * @}
+ */
+/** @addtogroup CRYP_Exported_Functions_Group2
+ * @{
+ */
/* AES encryption/decryption using polling ***********************************/
HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
@@ -328,7 +379,13 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+/**
+ * @}
+ */
+/** @addtogroup CRYP_Exported_Functions_Group3
+ * @{
+ */
/* DES encryption/decryption using polling ***********************************/
HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
@@ -343,10 +400,16 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/* DES encryption/decryption using DMA ***************************************/
HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+/**
+ * @}
+ */
+/** @addtogroup CRYP_Exported_Functions_Group4
+ * @{
+ */
/* TDES encryption/decryption using polling **********************************/
HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
@@ -364,22 +427,96 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_
HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+/**
+ * @}
+ */
-/* Processing functions ********************************************************/
+/** @addtogroup CRYP_Exported_Functions_Group5
+ * @{
+ */
+void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
+/**
+ * @}
+ */
+
+/** @addtogroup CRYP_Exported_Functions_Group6
+ * @{
+ */
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
+/**
+ * @}
+ */
-/* Peripheral State functions **************************************************/
+/** @addtogroup CRYP_Exported_Functions_Group7
+ * @{
+ */
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
-/* MSP functions *************************************************************/
-void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CRYP_Private_Types CRYP Private Types
+ * @{
+ */
-/* CallBack functions ********************************************************/
-void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Variables CRYP Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Constants CRYP Private Constants
+ * @{
+ */
+#define CRYP_FLAG_MASK ((uint32_t)0x0000001F)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CRYP_Private_Macros CRYP Private Macros
+ * @{
+ */
+
+#define IS_CRYP_KEYSIZE(__KEYSIZE__) (((__KEYSIZE__) == CRYP_KEYSIZE_128B) || \
+ ((__KEYSIZE__) == CRYP_KEYSIZE_192B) || \
+ ((__KEYSIZE__) == CRYP_KEYSIZE_256B))
+
+
+#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
+ ((__DATATYPE__) == CRYP_DATATYPE_16B) || \
+ ((__DATATYPE__) == CRYP_DATATYPE_8B) || \
+ ((__DATATYPE__) == CRYP_DATATYPE_1B))
+
+
+ /**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Functions CRYP Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
#endif /* STM32F215xx || STM32F217xx */
/**
diff --git a/f2/include/stm32f2xx_hal_dac.h b/f2/include/stm32f2xx_hal_dac.h
index 2ace186c1479234936b48f900038ef50965881eb..b6d6625cf0bb28c4be2f81f67eaa2ae64bab7d82 100755
--- a/f2/include/stm32f2xx_hal_dac.h
+++ b/f2/include/stm32f2xx_hal_dac.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_dac.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,10 +55,13 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup DAC_Exported_Types DAC Exported Types
+ * @{
+ */
/**
- * @brief HAL State structures definition
- */
+ * @brief HAL State structures definition
+ */
typedef enum
{
HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */
@@ -66,55 +69,59 @@ typedef enum
HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */
HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */
HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
-
}HAL_DAC_StateTypeDef;
/**
- * @brief DAC handle Structure definition
- */
+ * @brief DAC handle Structure definition
+ */
typedef struct
{
DAC_TypeDef *Instance; /*!< Register base address */
-
+
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
HAL_LockTypeDef Lock; /*!< DAC locking object */
-
+
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
-
- DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
-
+
+ DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
+
__IO uint32_t ErrorCode; /*!< DAC Error code */
-
+
}DAC_HandleTypeDef;
/**
- * @brief DAC Configuration regular Channel structure definition
- */
+ * @brief DAC Configuration regular Channel structure definition
+ */
typedef struct
{
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection */
-
+
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
-
}DAC_ChannelConfTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
+/** @defgroup DAC_Exported_Constants DAC Exported Constants
+ * @{
+ */
-/** @defgroup DAC_Error_Code
+/** @defgroup DAC_Error_Code DAC Error Code
* @{
*/
#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */
-#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
+#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
/**
* @}
*/
-
-/** @defgroup DAC_trigger_selection
+
+/** @defgroup DAC_trigger_selection DAC Trigger Selection
* @{
*/
@@ -129,143 +136,179 @@ typedef struct
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
- ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
/**
* @}
*/
-/** @defgroup DAC_output_buffer
+/** @defgroup DAC_output_buffer DAC Output Buffer
* @{
*/
#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
-
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
- ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
/**
* @}
*/
-/** @defgroup DAC_Channel_selection
+/** @defgroup DAC_Channel_selection DAC Channel Selection
* @{
*/
#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
-
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
- ((CHANNEL) == DAC_CHANNEL_2))
/**
* @}
*/
-/** @defgroup DAC_data_alignement
+/** @defgroup DAC_data_alignment DAC Data Alignment
* @{
*/
#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
-
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
- ((ALIGN) == DAC_ALIGN_12B_L) || \
- ((ALIGN) == DAC_ALIGN_8B_R))
-/**
- * @}
- */
-
-/** @defgroup DAC_data
- * @{
- */
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
/**
* @}
*/
-/** @defgroup DAC_flags_definition
+/** @defgroup DAC_flags_definition DAC Flags Definition
* @{
*/
#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
-
-#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR1) || \
- ((FLAG) == DAC_FLAG_DMAUDR2))
+#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
/**
* @}
*/
-/** @defgroup DAC_IT_definition
+/** @defgroup DAC_IT_definition DAC IT Definition
* @{
*/
#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
-
-#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR1) || \
- ((IT) == DAC_IT_DMAUDR2))
+#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+/**
+ * @}
+ */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
-/* Enable the DAC peripheral */
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
+/** @defgroup DAC_Exported_Macros DAC Exported Macros
+ * @{
+ */
-/* Disable the DAC peripheral */
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
-
-/* Set DHR12R1 alignment */
-#define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__))
+/** @brief Reset DAC handle state
+ * @param __HANDLE__: specifies the DAC handle.
+ * @retval None
+ */
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
-/* Set DHR12R2 alignment */
-#define __HAL_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__))
+/** @brief Enable the DAC channel
+ * @param __HANDLE__: specifies the DAC handle.
+ * @param __DAC_Channel__: specifies the DAC channel
+ * @retval None
+ */
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
-/* Set DHR12RD alignment */
-#define __HAL_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__))
+/** @brief Disable the DAC channel
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __DAC_Channel__: specifies the DAC channel.
+ * @retval None
+ */
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
-/* Enable the DAC interrupt */
+/** @brief Enable the DAC interrupt
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __INTERRUPT__: specifies the DAC interrupt.
+ * @retval None
+ */
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
-/* Disable the DAC interrupt */
+/** @brief Disable the DAC interrupt
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __INTERRUPT__: specifies the DAC interrupt.
+ * @retval None
+ */
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
-/* Get the selected DAC's flag status */
+/** @brief Checks if the specified DAC interrupt source is enabled or disabled.
+ * @param __HANDLE__: DAC handle
+ * @param __INTERRUPT__: DAC interrupt source to check
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Get the selected DAC's flag status.
+ * @param __HANDLE__: specifies the DAC handle.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
+ * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
+ * @retval None
+ */
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-/* Clear the DAC's flag */
-#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) |= (__FLAG__))
+/** @brief Clear the DAC's flag.
+ * @param __HANDLE__: specifies the DAC handle.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
+ * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
+ * @retval None
+ */
+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
+/**
+ * @}
+ */
/* Include DAC HAL Extension module */
#include "stm32f2xx_hal_dac_ex.h"
-/* Exported functions --------------------------------------------------------*/
-/* Initialization/de-initialization functions ***********************************/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DAC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions *********************************/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
+/**
+ * @}
+ */
-/* I/O operation functions ******************************************************/
+/** @addtogroup DAC_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ****************************************************/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
+/**
+ * @}
+ */
-/* Peripheral Control functions *************************************************/
+/** @addtogroup DAC_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+/**
+ * @}
+ */
-/* Peripheral State functions ***************************************************/
+/** @addtogroup DAC_Exported_Functions_Group4
+ * @{
+ */
+/* Peripheral State functions *************************************************/
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
@@ -274,6 +317,76 @@ void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DAC_Private_Constants DAC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DAC_Private_Macros DAC Private Macros
+ * @{
+ */
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+ ((ALIGN) == DAC_ALIGN_12B_L) || \
+ ((ALIGN) == DAC_ALIGN_8B_R))
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+ ((CHANNEL) == DAC_CHANNEL_2))
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+ ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
+/** @brief Set DHR12R1 alignment
+ * @param __ALIGNMENT__: specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
+
+/** @brief Set DHR12R2 alignment
+ * @param __ALIGNMENT__: specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
+
+/** @brief Set DHR12RD alignment
+ * @param __ALIGNMENT__: specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DAC_Private_Functions DAC Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_dac_ex.h b/f2/include/stm32f2xx_hal_dac_ex.h
index 2a28438be4436d90d797fe9dbe3add577f0b571a..098a68e5255a75ad12e501c840f1ff2c6896673f 100755
--- a/f2/include/stm32f2xx_hal_dac_ex.h
+++ b/f2/include/stm32f2xx_hal_dac_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_dac.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,28 +55,12 @@
*/
/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief HAL State structures definition
- */
-
/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DACEx_wave_generation
+/** @defgroup DACEx_Exported_Constants DAC Exported Constants
* @{
*/
-#define DAC_WAVEGENERATION_NONE ((uint32_t)0x00000000)
-#define DAC_WAVEGENERATION_NOISE ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVEGENERATION_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
-#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WAVEGENERATION_NONE) || \
- ((WAVE) == DAC_WAVEGENERATION_NOISE) || \
- ((WAVE) == DAC_WAVEGENERATION_TRIANGLE))
-/**
- * @}
- */
-
-/** @defgroup DACEx_lfsrunmask_triangleamplitude
+/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude
* @{
*/
#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
@@ -103,7 +87,55 @@
#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DACEx_Exported_Functions
+ * @{
+ */
+/** @addtogroup DACEx_Exported_Functions_Group1
+ * @{
+ */
+/* Extension features functions ***********************************************/
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DACEx_Private_Constants DAC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DACEx_Private_Macros DAC Private Macros
+ * @{
+ */
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
@@ -128,39 +160,21 @@
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
+
/**
* @}
*/
-/** @defgroup DACEx_wave_generation
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DACEx_Private_Functions DAC Private Functions
* @{
*/
-#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
-
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || \
- ((WAVE) == DAC_WAVE_TRIANGLE))
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Extension features functions ***********************************************/
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
-
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_dcmi.h b/f2/include/stm32f2xx_hal_dcmi.h
index fb81ffa825f579a0a29bbd52a9630b6500eecf73..d84d83f3330f70e924f73155db478d418ecbee25 100755
--- a/f2/include/stm32f2xx_hal_dcmi.h
+++ b/f2/include/stm32f2xx_hal_dcmi.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_dcmi.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of DCMI HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -52,24 +52,26 @@
* @{
*/
-/** @addtogroup DCMI
+/** @addtogroup DCMI DCMI
+ * @brief DCMI HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
-
+/** @defgroup DCMI_Exported_Types DCMI Exported Types
+ * @{
+ */
/**
- * @brief DCMI Error source
- */
+ * @brief DCMI Error source
+ */
typedef enum
{
DCMI_ERROR_SYNC = 1, /*!< Synchronisation error */
DCMI_OVERRUN = 2, /*!< DCMI Overrun */
-
-}DCMI_ErrorTypeDef;
+}DCMI_ErrorTypeDef;
/**
- * @brief DCMI Embedded Synchronisation CODE Init structure definition
+ * @brief DCMI Embedded Synchronisation CODE Init structure definition
*/
typedef struct
{
@@ -77,11 +79,10 @@ typedef struct
uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
-
}DCMI_CodesInitTypeDef;
/**
- * @brief DCMI Init structure definition
+ * @brief DCMI Init structure definition
*/
typedef struct
{
@@ -102,17 +103,16 @@ typedef struct
uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
This parameter can be a value of @ref DCMI_Extended_Data_Mode */
-
+
DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the frame start delimiter. */
-
+
uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
- This parameter can be a value of @ref DCMI_MODE_JPEG */
-
-}DCMI_InitTypeDef;
+ This parameter can be a value of @ref DCMI_MODE_JPEG */
+}DCMI_InitTypeDef;
/**
- * @brief HAL DCMI State structures definition
+ * @brief HAL DCMI State structures definition
*/
typedef enum
{
@@ -121,209 +121,176 @@ typedef enum
HAL_DCMI_STATE_BUSY = 0x02, /*!< DCMI internal processing is ongoing */
HAL_DCMI_STATE_TIMEOUT = 0x03, /*!< DCMI timeout state */
HAL_DCMI_STATE_ERROR = 0x04 /*!< DCMI error state */
-
}HAL_DCMI_StateTypeDef;
/**
- * @brief DCMI handle Structure definition
- */
+ * @brief DCMI handle Structure definition
+ */
typedef struct
-{
+{
DCMI_TypeDef *Instance; /*!< DCMI Register base address */
-
+
DCMI_InitTypeDef Init; /*!< DCMI parameters */
-
+
HAL_LockTypeDef Lock; /*!< DCMI locking object */
-
+
__IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */
-
+
__IO uint32_t XferCount; /*!< DMA transfer counter */
-
+
__IO uint32_t XferSize; /*!< DMA transfer size */
-
- uint32_t XferTransferNumber; /*!< DMA transfer number */
- uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */
-
+ uint32_t XferTransferNumber; /*!< DMA transfer number */
+
+ uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */
+
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */
- __IO uint32_t ErrorCode; /*!< DCMI Error code */
-
-}DCMI_HandleTypeDef;
+ __IO uint32_t ErrorCode; /*!< DCMI Error code */
-/* Exported constants --------------------------------------------------------*/
+}DCMI_HandleTypeDef;
+/**
+ * @}
+ */
-/** @defgroup DCMI_Exported_Constants
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DCMI_Exported_Constants DCMI Exported Constants
* @{
*/
-/** @defgroup DCMI_Error_Code
+/** @defgroup DCMI_Error_Code DCMI Error Code
* @{
*/
#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DCMI_ERROR_OVF ((uint32_t)0x00000001) /*!< Overflow error */
-#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002) /*!< Synchronization error */
+#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002) /*!< Synchronization error */
#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
/**
* @}
- */
+ */
-/** @defgroup DCMI_Capture_Mode
+/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
* @{
*/
#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000) /*!< The received data are transferred continuously
into the destination memory through the DMA */
#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
frame and then transfers a single frame through the DMA */
-
-#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
- ((MODE) == DCMI_MODE_SNAPSHOT))
/**
* @}
- */
-
+ */
-/** @defgroup DCMI_Synchronization_Mode
+/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
* @{
*/
#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000) /*!< Hardware synchronization data capture (frame/line start/stop)
is synchronized with the HSYNC/VSYNC signals */
#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
synchronization codes embedded in the data flow */
-
-#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
- ((MODE) == DCMI_SYNCHRO_EMBEDDED))
+
/**
* @}
- */
-
+ */
-/** @defgroup DCMI_PIXCK_Polarity
+/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
* @{
- */
+ */
#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000) /*!< Pixel clock active on Falling edge */
#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
-#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
- ((POLARITY) == DCMI_PCKPOLARITY_RISING))
/**
* @}
- */
-
-
-/** @defgroup DCMI_VSYNC_Polarity
+ */
+
+/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
* @{
- */
+ */
#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Vertical synchronization active Low */
#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
-#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
- ((POLARITY) == DCMI_VSPOLARITY_HIGH))
/**
* @}
- */
-
+ */
-/** @defgroup DCMI_HSYNC_Polarity
+/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
* @{
*/
#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Horizontal synchronization active Low */
#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
-#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
- ((POLARITY) == DCMI_HSPOLARITY_HIGH))
/**
* @}
- */
+ */
-/** @defgroup DCMI_MODE_JPEG
+/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
* @{
- */
+ */
#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000) /*!< Mode JPEG Disabled */
#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */
-#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
- ((JPEG_MODE) == DCMI_JPEG_ENABLE))
/**
* @}
- */
+ */
-/** @defgroup DCMI_Capture_Rate
+/** @defgroup DCMI_Capture_Rate DCMI Capture Rate
* @{
- */
+ */
#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000) /*!< All frames are captured */
#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
-#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \
- ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
- ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
/**
* @}
- */
-
+ */
-/** @defgroup DCMI_Extended_Data_Mode
+/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
* @{
- */
+ */
#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000) /*!< Interface captures 8-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
-#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \
- ((DATA) == DCMI_EXTEND_DATA_10B) || \
- ((DATA) == DCMI_EXTEND_DATA_12B) || \
- ((DATA) == DCMI_EXTEND_DATA_14B))
/**
* @}
- */
+ */
-/** @defgroup DCMI_Window_Coordinate
+/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
* @{
- */
+ */
#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFF) /*!< Window coordinate */
-#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
/**
* @}
*/
-/** @defgroup DCMI_Window_Height
+/** @defgroup DCMI_Window_Height DCMI Window Height
* @{
*/
#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFF) /*!< Window Height */
-#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
/**
* @}
- */
+ */
-/** @defgroup DCMI_interrupt_sources
+/** @defgroup DCMI_interrupt_sources DCMI interrupt sources
* @{
- */
+ */
#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE)
#define DCMI_IT_OVF ((uint32_t)DCMI_IER_OVF_IE)
#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE)
#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE)
#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE)
-
-#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))
-
-#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \
- ((IT) == DCMI_IT_OVF) || \
- ((IT) == DCMI_IT_ERR) || \
- ((IT) == DCMI_IT_VSYNC) || \
- ((IT) == DCMI_IT_LINE))
/**
* @}
- */
+ */
-/** @defgroup DCMI_Flags
+/** @defgroup DCMI_Flags DCMI Flags
* @{
- */
+ */
+
/**
- * @brief DCMI SR register
+ * @brief DCMI SR register
*/
#define DCMI_FLAG_HSYNC ((uint32_t)0x2001)
#define DCMI_FLAG_VSYNC ((uint32_t)0x2002)
@@ -344,21 +311,6 @@ typedef struct
#define DCMI_FLAG_ERRMI ((uint32_t)0x1004)
#define DCMI_FLAG_VSYNCMI ((uint32_t)0x1008)
#define DCMI_FLAG_LINEMI ((uint32_t)0x1010)
-#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \
- ((FLAG) == DCMI_FLAG_VSYNC) || \
- ((FLAG) == DCMI_FLAG_FNE) || \
- ((FLAG) == DCMI_FLAG_FRAMERI) || \
- ((FLAG) == DCMI_FLAG_OVFRI) || \
- ((FLAG) == DCMI_FLAG_ERRRI) || \
- ((FLAG) == DCMI_FLAG_VSYNCRI) || \
- ((FLAG) == DCMI_FLAG_LINERI) || \
- ((FLAG) == DCMI_FLAG_FRAMEMI) || \
- ((FLAG) == DCMI_FLAG_OVFMI) || \
- ((FLAG) == DCMI_FLAG_ERRMI) || \
- ((FLAG) == DCMI_FLAG_VSYNCMI) || \
- ((FLAG) == DCMI_FLAG_LINEMI))
-
-#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))
/**
* @}
*/
@@ -366,8 +318,18 @@ typedef struct
/**
* @}
*/
-
+
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DCMI_Exported_Macros DCMI Exported Macros
+ * @{
+ */
+
+/** @brief Reset DCMI handle state
+ * @param __HANDLE__: specifies the DCMI handle.
+ * @retval None
+ */
+#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
+
/**
* @brief Enable the DCMI.
* @param __HANDLE__: DCMI handle
@@ -411,7 +373,7 @@ typedef struct
* @arg DCMI_FLAG_LINERI: Line flag mask
* @retval None
*/
-#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR |= (__FLAG__))
+#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/**
* @brief Enable the specified DCMI interrupts.
@@ -454,38 +416,128 @@ typedef struct
* @retval The state of INTERRUPT.
*/
#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
-
-/* Exported functions --------------------------------------------------------*/
-/* Initialization and de-initialization functions *******************************/
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DCMI_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DCMI_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
-
-/* IO operation functions *******************************************************/
+/**
+ * @}
+ */
+
+/** @addtogroup DCMI_Exported_Functions_Group2
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
-void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
-
-/* Peripheral Control functions *************************************************/
+void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
+/**
+ * @}
+ */
+
+/** @addtogroup DCMI_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi);
-
-/* Peripheral State functions ***************************************************/
+/**
+ * @}
+ */
+
+/** @addtogroup DCMI_Exported_Functions_Group4
+ * @{
+ */
+/* Peripheral State functions *************************************************/
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
+/**
+ * @}
+ */
-#endif /* STM32F207xx || STM32F217xx */
/**
* @}
- */
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup DCMI_Private_Macros DCMI Private Macros
+ * @{
+ */
+#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
+ ((MODE) == DCMI_MODE_SNAPSHOT))
+
+#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
+ ((MODE) == DCMI_SYNCHRO_EMBEDDED))
+
+#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
+ ((POLARITY) == DCMI_PCKPOLARITY_RISING))
+
+#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
+ ((POLARITY) == DCMI_VSPOLARITY_HIGH))
+
+#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
+ ((POLARITY) == DCMI_HSPOLARITY_HIGH))
+
+#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
+ ((JPEG_MODE) == DCMI_JPEG_ENABLE))
+
+#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \
+ ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
+ ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
+
+#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \
+ ((DATA) == DCMI_EXTEND_DATA_10B) || \
+ ((DATA) == DCMI_EXTEND_DATA_12B) || \
+ ((DATA) == DCMI_EXTEND_DATA_14B))
+
+#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
+
+#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DCMI_Private_Functions DCMI Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F207xx || STM32F217xx */
+
+
+/**
+ * @}
+ */
+
/**
* @}
*/
diff --git a/f2/include/stm32f2xx_hal_def.h b/f2/include/stm32f2xx_hal_def.h
index a20355fbf3a007d8926f97c26304eedfd791c64a..443d9588cd6bbefc654448e66374eff88654a266 100755
--- a/f2/include/stm32f2xx_hal_def.h
+++ b/f2/include/stm32f2xx_hal_def.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f2xx_hal_def.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -46,6 +46,8 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f2xx.h"
+#include "Legacy/stm32_hal_legacy.h"
+#include <stdio.h>
/* Exported types ------------------------------------------------------------*/
@@ -70,10 +72,6 @@ typedef enum
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/
-#ifndef NULL
- #define NULL (void *) 0
-#endif
-
#define HAL_MAX_DELAY 0xFFFFFFFF
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
@@ -85,8 +83,28 @@ typedef enum
(__DMA_HANDLE_).Parent = (__HANDLE__); \
} while(0)
+#define UNUSED(x) ((void)(x))
+
+/** @brief Reset the Handle's State field.
+ * @param __HANDLE__: specifies the Peripheral Handle.
+ * @note This macro can be used for the following purpose:
+ * - When the Handle is declared as local variable; before passing it as parameter
+ * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+ * to set to 0 the Handle's "State" field.
+ * Otherwise, "State" field may have any random value and the first time the function
+ * HAL_PPP_Init() is called, the low level hardware initialization will be missed
+ * (i.e. HAL_PPP_MspInit() will not be executed).
+ * - When there is a need to reconfigure the low level hardware: instead of calling
+ * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+ * In this later function, when the Handle's "State" field is set to 0, it will execute the function
+ * HAL_PPP_MspInit() which will reconfigure the low level hardware.
+ * @retval None
+ */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+
#if (USE_RTOS == 1)
/* Reserved for future use */
+ #error " USE_RTOS should be 0 in the current HAL release "
#else
#define __HAL_LOCK(__HANDLE__) \
do{ \
@@ -133,12 +151,27 @@ typedef enum
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
- #elif defined (__TASKING__) /* TASKING Compiler */
- #define __ALIGN_BEGIN __align(4)
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
+/**
+ * @brief __NOINLINE definition
+ */
+#if defined ( __CC_ARM ) || defined ( __GNUC__ )
+/* ARM & GNUCompiler
+ ----------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
#ifdef __cplusplus
}
#endif
diff --git a/f2/include/stm32f2xx_hal_dma.h b/f2/include/stm32f2xx_hal_dma.h
index 05acb0ba34e6734a987f1b6729a83b41d41e627a..f66fedaa2c681f7ede91ece868fb9ef436987735 100755
--- a/f2/include/stm32f2xx_hal_dma.h
+++ b/f2/include/stm32f2xx_hal_dma.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_dma.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,36 +54,41 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Types DMA Exported Types
+ * @brief DMA Exported Types
+ * @{
+ */
+
/**
- * @brief DMA Configuration Structure definition
+ * @brief DMA Configuration Structure definition
*/
typedef struct
{
uint32_t Channel; /*!< Specifies the channel used for the specified stream.
This parameter can be a value of @ref DMA_Channel_selection */
-
+
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
from memory to memory or from peripheral to memory.
This parameter can be a value of @ref DMA_Data_transfer_direction */
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
- This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
-
+ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
This parameter can be a value of @ref DMA_Memory_incremented_mode */
-
+
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
- This parameter can be a value of @ref DMA_Peripheral_data_size */
+ This parameter can be a value of @ref DMA_Peripheral_data_size */
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_Memory_data_size */
-
+
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
This parameter can be a value of @ref DMA_mode
@note The circular buffer mode cannot be used if the memory-to-memory
- data transfer is configured on the selected Stream */
+ data transfer is configured on the selected Stream */
uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
This parameter can be a value of @ref DMA_Priority_level */
@@ -92,100 +97,107 @@ typedef struct
This parameter can be a value of @ref DMA_FIFO_direct_mode
@note The Direct mode (FIFO mode disabled) cannot be used if the
memory-to-memory data transfer is configured on the selected stream */
-
+
uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
This parameter can be a value of @ref DMA_FIFO_threshold_level */
-
+
uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
- It specifies the amount of data to be transferred in a single non interruptable
- transaction.
+ It specifies the amount of data to be transferred in a single non interruptible
+ transaction.
This parameter can be a value of @ref DMA_Memory_burst
@note The burst mode is possible only if the address Increment mode is enabled. */
-
+
uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
- It specifies the amount of data to be transferred in a single non interruptable
+ It specifies the amount of data to be transferred in a single non interruptible
transaction.
This parameter can be a value of @ref DMA_Peripheral_burst
@note The burst mode is possible only if the address Increment mode is enabled. */
-
}DMA_InitTypeDef;
+
/**
- * @brief HAL DMA State structures definition
- */
+ * @brief HAL DMA State structures definition
+ */
typedef enum
{
- HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
+ HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */
- HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
+ HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */
- HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
+ HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */
- HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
- HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
+ HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
+ HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
-
}HAL_DMA_StateTypeDef;
/**
- * @brief HAL DMA Error Code structure definition
- */
+ * @brief HAL DMA Error Code structure definition
+ */
typedef enum
{
HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
-
}HAL_DMA_LevelCompleteTypeDef;
-
/**
- * @brief DMA handle Structure definition
- */
+ * @brief DMA handle Structure definition
+ */
typedef struct __DMA_HandleTypeDef
-{
+{
DMA_Stream_TypeDef *Instance; /*!< Register base address */
-
+
DMA_InitTypeDef Init; /*!< DMA communication parameters */
-
+
HAL_LockTypeDef Lock; /*!< DMA locking object */
-
+
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
-
+
void *Parent; /*!< Parent object state */
-
+
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
-
+
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
-
+
void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
-
+
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
- __IO uint32_t ErrorCode; /*!< DMA Error code */
-
-}DMA_HandleTypeDef;
+ __IO uint32_t ErrorCode; /*!< DMA Error code */
+
+ uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
+
+ uint32_t StreamIndex; /*!< DMA Stream Index */
+}DMA_HandleTypeDef;
+
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup DMA_Exported_Constants
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+ * @brief DMA Exported constants
* @{
*/
-/** @defgroup DMA_Error_Code
+/** @defgroup DMA_Error_Code DMA Error Code
+ * @brief DMA Error Code
* @{
*/
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
-#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
+#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
/**
* @}
*/
-/** @defgroup DMA_Channel_selection
+/** @defgroup DMA_Channel_selection DMA Channel selection
+ * @brief DMA channel selection
* @{
*/
#define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */
@@ -196,185 +208,134 @@ typedef struct __DMA_HandleTypeDef
#define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */
#define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */
#define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */
-
-#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
- ((CHANNEL) == DMA_CHANNEL_1) || \
- ((CHANNEL) == DMA_CHANNEL_2) || \
- ((CHANNEL) == DMA_CHANNEL_3) || \
- ((CHANNEL) == DMA_CHANNEL_4) || \
- ((CHANNEL) == DMA_CHANNEL_5) || \
- ((CHANNEL) == DMA_CHANNEL_6) || \
- ((CHANNEL) == DMA_CHANNEL_7))
/**
* @}
*/
-/** @defgroup DMA_Data_transfer_direction
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+ * @brief DMA data transfer direction
* @{
*/
#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
-
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
- ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
- ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
-/**
- * @}
- */
-
-/** @defgroup DMA_Data_buffer_size
- * @{
- */
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
/**
* @}
- */
+ */
-/** @defgroup DMA_Peripheral_incremented_mode
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+ * @brief DMA peripheral incremented mode
* @{
*/
#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
- ((STATE) == DMA_PINC_DISABLE))
/**
* @}
*/
-/** @defgroup DMA_Memory_incremented_mode
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+ * @brief DMA memory incremented mode
* @{
*/
#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
- ((STATE) == DMA_MINC_DISABLE))
/**
* @}
*/
-/** @defgroup DMA_Peripheral_data_size
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+ * @brief DMA peripheral data size
* @{
*/
#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
- ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_PDATAALIGN_WORD))
/**
* @}
*/
-
-/** @defgroup DMA_Memory_data_size
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+ * @brief DMA memory data size
* @{
*/
#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
- ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_MDATAALIGN_WORD ))
/**
* @}
*/
-/** @defgroup DMA_mode
+/** @defgroup DMA_mode DMA mode
+ * @brief DMA mode
* @{
*/
#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
- ((MODE) == DMA_CIRCULAR) || \
- ((MODE) == DMA_PFCTRL))
/**
* @}
*/
-/** @defgroup DMA_Priority_level
+/** @defgroup DMA_Priority_level DMA Priority level
+ * @brief DMA priority levels
* @{
*/
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
- ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
- ((PRIORITY) == DMA_PRIORITY_HIGH) || \
- ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
/**
* @}
*/
-/** @defgroup DMA_FIFO_direct_mode
+/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
+ * @brief DMA FIFO direct mode
* @{
*/
#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */
#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
-
-#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
- ((STATE) == DMA_FIFOMODE_ENABLE))
/**
* @}
*/
-/** @defgroup DMA_FIFO_threshold_level
+/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
+ * @brief DMA FIFO level
* @{
*/
#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */
#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
-
-#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
- ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
- ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
- ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
/**
* @}
*/
-/** @defgroup DMA_Memory_burst
+/** @defgroup DMA_Memory_burst DMA Memory burst
+ * @brief DMA memory burst
* @{
*/
#define DMA_MBURST_SINGLE ((uint32_t)0x00000000)
#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
-
-#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
- ((BURST) == DMA_MBURST_INC4) || \
- ((BURST) == DMA_MBURST_INC8) || \
- ((BURST) == DMA_MBURST_INC16))
/**
* @}
*/
-/** @defgroup DMA_Peripheral_burst
+/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
+ * @brief DMA peripheral burst
* @{
*/
#define DMA_PBURST_SINGLE ((uint32_t)0x00000000)
#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
-
-#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
- ((BURST) == DMA_PBURST_INC4) || \
- ((BURST) == DMA_PBURST_INC8) || \
- ((BURST) == DMA_PBURST_INC16))
/**
* @}
*/
-/** @defgroup DMA_interrupt_enable_definitions
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+ * @brief DMA interrupts definition
* @{
*/
#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
@@ -386,7 +347,8 @@ typedef struct __DMA_HandleTypeDef
* @}
*/
-/** @defgroup DMA_flag_definitions
+/** @defgroup DMA_flag_definitions DMA flag definitions
+ * @brief DMA flag definitions
* @{
*/
#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)
@@ -412,12 +374,19 @@ typedef struct __DMA_HandleTypeDef
/**
* @}
*/
-
+
/**
* @}
*/
-
+
/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset DMA handle state
+ * @param __HANDLE__: specifies the DMA handle.
+ * @retval None
+ */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
/**
* @brief Return the current DMA Stream FIFO filled level.
* @param __HANDLE__: DMA handle
@@ -580,9 +549,9 @@ typedef struct __DMA_HandleTypeDef
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR |= (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR |= (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR |= (__FLAG__)) : (DMA1->LIFCR |= (__FLAG__)))
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
/**
* @brief Enable the specified DMA Stream interrupts.
@@ -615,7 +584,7 @@ typedef struct __DMA_HandleTypeDef
((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
/**
- * @brief Check whether the specified DMA Stream interrupt has occurred or not.
+ * @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
* @param __HANDLE__: DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
@@ -662,21 +631,128 @@ typedef struct __DMA_HandleTypeDef
#include "stm32f2xx_hal_dma_ex.h"
/* Exported functions --------------------------------------------------------*/
-
-/* Initialization and de-initialization functions *****************************/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+ * @brief DMA Exported functions
+ * @{
+ */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ * @{
+ */
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
-/* IO operation functions *****************************************************/
+/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
+ * @brief I/O operation functions
+ * @{
+ */
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
-/* Peripheral State and Error functions ***************************************/
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions
+ * @{
+ */
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/* Private Constants -------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+ * @brief DMA private defines and constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+ * @brief DMA private macros
+ * @{
+ */
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
+ ((CHANNEL) == DMA_CHANNEL_1) || \
+ ((CHANNEL) == DMA_CHANNEL_2) || \
+ ((CHANNEL) == DMA_CHANNEL_3) || \
+ ((CHANNEL) == DMA_CHANNEL_4) || \
+ ((CHANNEL) == DMA_CHANNEL_5) || \
+ ((CHANNEL) == DMA_CHANNEL_6) || \
+ ((CHANNEL) == DMA_CHANNEL_7))
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+ ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
+ ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
+ ((MODE) == DMA_CIRCULAR) || \
+ ((MODE) == DMA_PFCTRL))
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
+ ((STATE) == DMA_FIFOMODE_ENABLE))
+
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
+
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
+ ((BURST) == DMA_MBURST_INC4) || \
+ ((BURST) == DMA_MBURST_INC8) || \
+ ((BURST) == DMA_MBURST_INC16))
+
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
+ ((BURST) == DMA_PBURST_INC4) || \
+ ((BURST) == DMA_PBURST_INC8) || \
+ ((BURST) == DMA_PBURST_INC16))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+ * @brief DMA private functions
+ * @{
+ */
+/**
+ * @}
+ */
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_dma_ex.h b/f2/include/stm32f2xx_hal_dma_ex.h
index 1fb515c235bb262ae248a4aded1bf5aa67b04012..5738b894bfe683b7b640d263df00ad2ec529ea67 100755
--- a/f2/include/stm32f2xx_hal_dma_ex.h
+++ b/f2/include/stm32f2xx_hal_dma_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_dma_ex.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,7 +55,11 @@
*/
/* Exported types ------------------------------------------------------------*/
-
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
+ * @brief DMAEx Exported types
+ * @{
+ */
+
/**
* @brief HAL DMA Memory definition
*/
@@ -66,15 +70,42 @@ typedef enum
}HAL_DMA_MemoryTypeDef;
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
+ * @brief DMAEx Exported functions
+ * @{
+ */
+
+/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ * @{
+ */
+
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
+ * @brief DMAEx Private functions
+ * @{
+ */
+/**
+ * @}
+ */
+
/**
* @}
*/
diff --git a/f2/include/stm32f2xx_hal_eth.h b/f2/include/stm32f2xx_hal_eth.h
index 07993fb2618612c01ca98ad9df2194927ff4229f..d8fbe687310181ccca3b8f7cabb7330f16e7d311 100755
--- a/f2/include/stm32f2xx_hal_eth.h
+++ b/f2/include/stm32f2xx_hal_eth.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_eth.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of ETH HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,8 +54,316 @@
/** @addtogroup ETH
* @{
*/
+
+/** @defgroup ETH_Private_Macros ETH Private Macros
+ * @{
+ */
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
+ ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
+ ((SPEED) == ETH_SPEED_100M))
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
+ ((MODE) == ETH_MODE_HALFDUPLEX))
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
+ ((MODE) == ETH_RXINTERRUPT_MODE))
+#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
+ ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
+#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
+ ((MODE) == ETH_MEDIA_INTERFACE_RMII))
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
+ ((CMD) == ETH_WATCHDOG_DISABLE))
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
+ ((CMD) == ETH_JABBER_DISABLE))
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_40BIT))
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
+ ((CMD) == ETH_CARRIERSENCE_DISABLE))
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
+ ((CMD) == ETH_RECEIVEOWN_DISABLE))
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
+ ((CMD) == ETH_LOOPBACKMODE_DISABLE))
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
+ ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
+ ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
+ ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_1))
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
+ ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
+ ((CMD) == ETH_RECEIVEAll_DISABLE))
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
+ ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
+ ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
+ ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
+ ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
+ ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
+ ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
+ ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
+ ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
+ ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
+ ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS1) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS3))
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS3))
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
+ ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
+ ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
+ ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
+ ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
+ ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
+ ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
+ ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
+ ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
+ ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
+ ((CMD) == ETH_FIXEDBURST_DISABLE))
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
+#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
+ ((FLAG) == ETH_DMATXDESC_IC) || \
+ ((FLAG) == ETH_DMATXDESC_LS) || \
+ ((FLAG) == ETH_DMATXDESC_FS) || \
+ ((FLAG) == ETH_DMATXDESC_DC) || \
+ ((FLAG) == ETH_DMATXDESC_DP) || \
+ ((FLAG) == ETH_DMATXDESC_TTSE) || \
+ ((FLAG) == ETH_DMATXDESC_TER) || \
+ ((FLAG) == ETH_DMATXDESC_TCH) || \
+ ((FLAG) == ETH_DMATXDESC_TTSS) || \
+ ((FLAG) == ETH_DMATXDESC_IHE) || \
+ ((FLAG) == ETH_DMATXDESC_ES) || \
+ ((FLAG) == ETH_DMATXDESC_JT) || \
+ ((FLAG) == ETH_DMATXDESC_FF) || \
+ ((FLAG) == ETH_DMATXDESC_PCE) || \
+ ((FLAG) == ETH_DMATXDESC_LCA) || \
+ ((FLAG) == ETH_DMATXDESC_NC) || \
+ ((FLAG) == ETH_DMATXDESC_LCO) || \
+ ((FLAG) == ETH_DMATXDESC_EC) || \
+ ((FLAG) == ETH_DMATXDESC_VF) || \
+ ((FLAG) == ETH_DMATXDESC_CC) || \
+ ((FLAG) == ETH_DMATXDESC_ED) || \
+ ((FLAG) == ETH_DMATXDESC_UF) || \
+ ((FLAG) == ETH_DMATXDESC_DB))
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
+ ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
+#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
+#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
+ ((FLAG) == ETH_DMARXDESC_AFM) || \
+ ((FLAG) == ETH_DMARXDESC_ES) || \
+ ((FLAG) == ETH_DMARXDESC_DE) || \
+ ((FLAG) == ETH_DMARXDESC_SAF) || \
+ ((FLAG) == ETH_DMARXDESC_LE) || \
+ ((FLAG) == ETH_DMARXDESC_OE) || \
+ ((FLAG) == ETH_DMARXDESC_VLAN) || \
+ ((FLAG) == ETH_DMARXDESC_FS) || \
+ ((FLAG) == ETH_DMARXDESC_LS) || \
+ ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
+ ((FLAG) == ETH_DMARXDESC_LC) || \
+ ((FLAG) == ETH_DMARXDESC_FT) || \
+ ((FLAG) == ETH_DMARXDESC_RWT) || \
+ ((FLAG) == ETH_DMARXDESC_RE) || \
+ ((FLAG) == ETH_DMARXDESC_DBE) || \
+ ((FLAG) == ETH_DMARXDESC_CE) || \
+ ((FLAG) == ETH_DMARXDESC_MAMPCE))
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
+ ((BUFFER) == ETH_DMARXDESC_BUFFER2))
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
+ ((FLAG) == ETH_PMT_FLAG_MPR))
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
+ ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
+ ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
+ ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
+ ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
+ ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
+ ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
+ ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
+ ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
+ ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
+ ((FLAG) == ETH_DMA_FLAG_T))
+#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFD87) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
+ ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
+ ((IT) == ETH_MAC_IT_PMT))
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
+ ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
+ ((FLAG) == ETH_MAC_FLAG_PMT))
+#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
+ ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
+ ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
+ ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
+ ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
+ ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
+ ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
+ ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
+ ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
+ ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
+#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
+ ((IT) != 0x00))
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
+ ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
+ ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
+#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
+ ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Private_Defines ETH Private Defines
+ * @{
+ */
+/* Delay to wait when writing to some Ethernet registers */
+#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
+
+/* ETHERNET Errors */
+#define ETH_SUCCESS ((uint32_t)0)
+#define ETH_ERROR ((uint32_t)1)
+
+/* ETHERNET DMA Tx descriptors Collision Count Shift */
+#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
+
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
+#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
+
+/* ETHERNET DMA Rx descriptors Frame Length Shift */
+#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
+
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
+#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
+
+/* ETHERNET DMA Rx descriptors Frame length Shift */
+#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
+
+/* ETHERNET MAC address offsets */
+#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
+#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
+
+/* ETHERNET MACMIIAR register Mask */
+#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
+
+/* ETHERNET MACCR register Mask */
+#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
+
+/* ETHERNET MACFCR register Mask */
+#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
+
+/* ETHERNET DMAOMR register Mask */
+#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
+
+/* ETHERNET Remote Wake-up frame register length */
+#define ETH_WAKEUP_REGISTER_LENGTH 8
+
+/* ETHERNET Missed frames counter Shift */
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
+ /**
+ * @}
+ */
/* Exported types ------------------------------------------------------------*/
+/** @defgroup ETH_Exported_Types ETH Exported Types
+ * @{
+ */
/**
* @brief HAL State structures definition
@@ -85,24 +393,24 @@ typedef struct
and the mode (half/full-duplex).
This parameter can be a value of @ref ETH_AutoNegotiation */
- uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps
+ uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
This parameter can be a value of @ref ETH_Speed */
uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
This parameter can be a value of @ref ETH_Duplex_Mode */
- uint16_t PhyAddress; /*!< Ethernet PHY address
+ uint16_t PhyAddress; /*!< Ethernet PHY address.
This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
- uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode
+ uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
This parameter can be a value of @ref ETH_Rx_Mode */
- uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software
+ uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
This parameter can be a value of @ref ETH_Checksum_Mode */
- uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface
+ uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
This parameter can be a value of @ref ETH_Media_Interface */
} ETH_InitTypeDef;
@@ -117,85 +425,85 @@ typedef struct
uint32_t Watchdog; /*!< Selects or not the Watchdog timer
When enabled, the MAC allows no more then 2048 bytes to be received.
When disabled, the MAC can receive up to 16384 bytes.
- This parameter can be a value of @ref ETH_watchdog */
+ This parameter can be a value of @ref ETH_Watchdog */
uint32_t Jabber; /*!< Selects or not Jabber timer
When enabled, the MAC allows no more then 2048 bytes to be sent.
When disabled, the MAC can send up to 16384 bytes.
This parameter can be a value of @ref ETH_Jabber */
- uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission
+ uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
This parameter can be a value of @ref ETH_Inter_Frame_Gap */
- uint32_t CarrierSense; /*!< Selects or not the Carrier Sense
+ uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
This parameter can be a value of @ref ETH_Carrier_Sense */
- uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn
+ uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
- in Half-Duplex mode
+ in Half-Duplex mode.
This parameter can be a value of @ref ETH_Receive_Own */
- uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode
+ uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
This parameter can be a value of @ref ETH_Loop_Back_Mode */
uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
This parameter can be a value of @ref ETH_Checksum_Offload */
uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
- when a collision occurs (Half-Duplex mode)
+ when a collision occurs (Half-Duplex mode).
This parameter can be a value of @ref ETH_Retry_Transmission */
- uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping
+ uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
- uint32_t BackOffLimit; /*!< Selects the BackOff limit value
+ uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
This parameter can be a value of @ref ETH_Back_Off_Limit */
- uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode)
+ uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
This parameter can be a value of @ref ETH_Deferral_Check */
- uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering)
+ uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
This parameter can be a value of @ref ETH_Receive_All */
- uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode
+ uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
This parameter can be a value of @ref ETH_Source_Addr_Filter */
uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
This parameter can be a value of @ref ETH_Pass_Control_Frames */
- uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames
+ uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
- uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames
+ uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
This parameter can be a value of @ref ETH_Destination_Addr_Filter */
uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
This parameter can be a value of @ref ETH_Promiscuous_Mode */
- uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
+ uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
- uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
+ uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
- uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table
+ uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
- uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table
+ uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
- uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame
+ uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
- uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames
+ uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
- automatic retransmission of PAUSE Frame
+ automatic retransmission of PAUSE Frame.
This parameter can be a value of @ref ETH_Pause_Low_Threshold */
uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
- unicast address and unique multicast address)
+ unicast address and unique multicast address).
This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
@@ -207,7 +515,7 @@ typedef struct
This parameter can be a value of @ref ETH_Transmit_Flow_Control */
uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
- comparison and filtering
+ comparison and filtering.
This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
@@ -221,54 +529,54 @@ typedef struct
typedef struct
{
- uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames
+ uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
- uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode
+ uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
This parameter can be a value of @ref ETH_Receive_Store_Forward */
- uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames
+ uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
This parameter can be a value of @ref ETH_Flush_Received_Frame */
- uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode
+ uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
This parameter can be a value of @ref ETH_Transmit_Store_Forward */
- uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control
+ uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
- uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames
+ uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
This parameter can be a value of @ref ETH_Forward_Error_Frames */
uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
and length less than 64 bytes) including pad-bytes and CRC)
This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
- uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO
+ uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
This parameter can be a value of @ref ETH_Receive_Threshold_Control */
uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
frame of Transmit data even before obtaining the status for the first frame.
This parameter can be a value of @ref ETH_Second_Frame_Operate */
- uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats
+ uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
This parameter can be a value of @ref ETH_Address_Aligned_Beats */
- uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers
+ uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
This parameter can be a value of @ref ETH_Fixed_Burst */
- uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction
+ uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
- uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction
+ uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
- uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format
+ uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
- uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration
+ uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
This parameter can be a value of @ref ETH_DMA_Arbitration */
} ETH_DMAInitTypeDef;
@@ -341,29 +649,26 @@ typedef struct
} ETH_HandleTypeDef;
-/* Exported constants --------------------------------------------------------*/
-
-#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
-
-/* Delay to wait when writing to some Ethernet registers */
-#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
-
+ /**
+ * @}
+ */
-/* ETHERNET Errors */
-#define ETH_SUCCESS ((uint32_t)0)
-#define ETH_ERROR ((uint32_t)1)
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ETH_Exported_Constants ETH Exported Constants
+ * @{
+ */
-/** @defgroup ETH_Buffers_setting
+/** @defgroup ETH_Buffers_setting ETH Buffers setting
* @{
*/
-#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
#define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
#define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */
#define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */
-#define VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
-#define MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
-#define MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
-#define JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
+#define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
+#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
+#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
/* Ethernet driver receive buffers are organized in a chained linked-list, when
an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
@@ -418,9 +723,16 @@ typedef struct
#define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
#endif
+ /**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
+ * @{
+ */
/*
- DMA Tx Desciptor
+ DMA Tx Descriptor
-----------------------------------------------------------------------------------------------
TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
-----------------------------------------------------------------------------------------------
@@ -495,10 +807,8 @@ typedef struct
/**
* @}
- */
-
-
-/** @defgroup ETH_DMA_Rx_descriptor
+ */
+/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
* @{
*/
@@ -593,97 +903,81 @@ typedef struct
/* Bit definition of RDES7 register */
#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
-
-
- /** @defgroup ETH_AutoNegotiation
+/**
+ * @}
+ */
+ /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
* @{
*/
#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
- ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
+
/**
* @}
*/
-/** @defgroup ETH_Speed
+/** @defgroup ETH_Speed ETH Speed
* @{
*/
#define ETH_SPEED_10M ((uint32_t)0x00000000)
#define ETH_SPEED_100M ((uint32_t)0x00004000)
-#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
- ((SPEED) == ETH_SPEED_100M))
+
/**
* @}
*/
-/** @defgroup ETH_Duplex_Mode
+/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
* @{
*/
#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
-#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
- ((MODE) == ETH_MODE_HALFDUPLEX))
/**
* @}
*/
-/** @defgroup ETH_Rx_Mode
+/** @defgroup ETH_Rx_Mode ETH Rx Mode
* @{
*/
#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
-#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
- ((MODE) == ETH_RXINTERRUPT_MODE))
/**
* @}
*/
-/** @defgroup ETH_Checksum_Mode
+/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
* @{
*/
#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
-#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
- ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
/**
* @}
*/
-/** @defgroup ETH_Media_Interface
+/** @defgroup ETH_Media_Interface ETH Media Interface
* @{
*/
#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
-#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
- ((MODE) == ETH_MEDIA_INTERFACE_RMII))
-
/**
* @}
*/
-/** @defgroup ETH_watchdog
+/** @defgroup ETH_Watchdog ETH Watchdog
* @{
*/
#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
-#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
- ((CMD) == ETH_WATCHDOG_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Jabber
+/** @defgroup ETH_Jabber ETH Jabber
* @{
*/
#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
-#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
- ((CMD) == ETH_JABBER_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Inter_Frame_Gap
+/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
* @{
*/
#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
@@ -694,334 +988,238 @@ typedef struct
#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
-#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_40BIT))
-
/**
* @}
*/
-/** @defgroup ETH_Carrier_Sense
+/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
* @{
*/
#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
-#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
-#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
- ((CMD) == ETH_CARRIERSENCE_DISABLE))
-
+#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
/**
* @}
*/
-/** @defgroup ETH_Receive_Own
+/** @defgroup ETH_Receive_Own ETH Receive Own
* @{
*/
#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
-#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
-#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
- ((CMD) == ETH_RECEIVEOWN_DISABLE))
-
+#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
/**
* @}
*/
-/** @defgroup ETH_Loop_Back_Mode
+/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
* @{
*/
#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
- ((CMD) == ETH_LOOPBACKMODE_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Checksum_Offload
+/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
* @{
*/
#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
- ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Retry_Transmission
+/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
* @{
*/
#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
-#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
- ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Automatic_Pad_CRC_Strip
+/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
* @{
*/
#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
- ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Back_Off_Limit
+/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
* @{
*/
#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
-#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
- ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
- ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
- ((LIMIT) == ETH_BACKOFFLIMIT_1))
-
/**
* @}
*/
-/** @defgroup ETH_Deferral_Check
+/** @defgroup ETH_Deferral_Check ETH Deferral Check
* @{
*/
#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
- ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Receive_All
+/** @defgroup ETH_Receive_All ETH Receive All
* @{
*/
#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
- ((CMD) == ETH_RECEIVEAll_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Source_Addr_Filter
+/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
* @{
*/
#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
- ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
- ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Pass_Control_Frames
+/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
* @{
*/
#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
-#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
- ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
- ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
-
/**
* @}
*/
-/** @defgroup ETH_Broadcast_Frames_Reception
+/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
* @{
*/
#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
-#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
- ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Destination_Addr_Filter
+/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
* @{
*/
#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
-#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
- ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
-
/**
* @}
*/
-/** @defgroup ETH_Promiscuous_Mode
+/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
* @{
*/
-#define ETH_PROMISCIOUSMODE_ENABLE ((uint32_t)0x00000001)
-#define ETH_PROMISCIOUSMODE_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_PROMISCIOUS_MODE(CMD) (((CMD) == ETH_PROMISCIOUSMODE_ENABLE) || \
- ((CMD) == ETH_PROMISCIOUSMODE_DISABLE))
-
+#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
+#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
/**
* @}
*/
-/** @defgroup ETH_Multicast_Frames_Filter
+/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
* @{
*/
#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
-#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
- ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
- ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
- ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
/**
* @}
*/
-/** @defgroup ETH_Unicast_Frames_Filter
+/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
* @{
*/
#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
-#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
- ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
- ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
-/**
- * @}
- */
-
-/** @defgroup ETH_Pause_Time
- * @{
- */
-#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
-
/**
* @}
*/
-/** @defgroup ETH_Zero_Quanta_Pause
+/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
* @{
*/
#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
-#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
- ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
/**
* @}
*/
-/** @defgroup ETH_Pause_Low_Threshold
+/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
* @{
*/
#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
-#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
- ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
- ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
- ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
/**
* @}
*/
-/** @defgroup ETH_Unicast_Pause_Frame_Detect
+/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
* @{
*/
#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
- ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
/**
* @}
*/
-/** @defgroup ETH_Receive_Flow_Control
+/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
* @{
*/
#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
- ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
/**
* @}
*/
-/** @defgroup ETH_Transmit_Flow_Control
+/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
* @{
*/
#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
- ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
/**
* @}
*/
-/** @defgroup ETH_VLAN_Tag_Comparison
+/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
* @{
*/
#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
-#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
- ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
-#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
-
/**
* @}
*/
-/** @defgroup ETH_MAC_addresses
+/** @defgroup ETH_MAC_addresses ETH MAC addresses
* @{
*/
#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
-#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
- ((ADDRESS) == ETH_MAC_ADDRESS1) || \
- ((ADDRESS) == ETH_MAC_ADDRESS2) || \
- ((ADDRESS) == ETH_MAC_ADDRESS3))
-#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
- ((ADDRESS) == ETH_MAC_ADDRESS2) || \
- ((ADDRESS) == ETH_MAC_ADDRESS3))
/**
* @}
*/
-/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames
+/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
* @{
*/
#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
-#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
- ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
/**
* @}
*/
-/** @defgroup ETH_MAC_addresses_filter_Mask_bytes
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
* @{
*/
#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
@@ -1030,108 +1228,81 @@ typedef struct
#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
-#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
-
/**
* @}
*/
-/** @defgroup ETH_MAC_Debug_flags
+/** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags
* @{
*/
#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
-
#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
-
#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
-
#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-
#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
-
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
-
#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
-
#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
-
-#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
-
+#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
-
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
-
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_AVTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
-
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
/**
* @}
*/
-/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
* @{
*/
#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
-#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
- ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
/**
* @}
*/
-/** @defgroup ETH_Receive_Store_Forward
+/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
* @{
*/
#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
- ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
/**
* @}
*/
-/** @defgroup ETH_Flush_Received_Frame
+/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
* @{
*/
#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
-#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
- ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
/**
* @}
*/
-/** @defgroup ETH_Transmit_Store_Forward
+/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
* @{
*/
#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
- ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
/**
* @}
*/
-/** @defgroup ETH_Transmit_Threshold_Control
+/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
* @{
*/
#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
@@ -1142,93 +1313,67 @@ typedef struct
#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
/**
* @}
*/
-/** @defgroup ETH_Forward_Error_Frames
+/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
* @{
*/
#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
- ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
/**
* @}
*/
-/** @defgroup ETH_Forward_Undersized_Good_Frames
+/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
* @{
*/
#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
- ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Receive_Threshold_Control
+/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
* @{
*/
#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
-#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
- ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
- ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
- ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
/**
* @}
*/
-/** @defgroup ETH_Second_Frame_Operate
+/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
* @{
*/
#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
- ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Address_Aligned_Beats
+/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
* @{
*/
#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
- ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Fixed_Burst
+/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
* @{
*/
#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
-#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
- ((CMD) == ETH_FIXEDBURST_DISABLE))
-
/**
* @}
*/
-/** @defgroup ETH_Rx_DMA_Burst_Length
+/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
* @{
*/
#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
@@ -1243,25 +1388,11 @@ typedef struct
#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
-
-#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
-
/**
* @}
*/
-/** @defgroup ETH_Tx_DMA_Burst_Length
+/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
* @{
*/
#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
@@ -1276,252 +1407,91 @@ typedef struct
#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-
-#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
-
-/**
- * @brief ETH_DMA_Enhanced_descriptor_format
- */
-#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
-#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
-
-#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
- ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
-
-/**
- * @}
- */
-
-/**
- * @brief ETH DMA Descriptor SkipLength
- */
-#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
-
-
-/** @defgroup ETH_DMA_Arbitration
- * @{
- */
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
-#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
-#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
- ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
- ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
- ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
- ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
/**
* @}
*/
-/** @defgroup ETH_DMA_Tx_descriptor_flags
- * @{
- */
-#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
- ((FLAG) == ETH_DMATXDESC_IC) || \
- ((FLAG) == ETH_DMATXDESC_LS) || \
- ((FLAG) == ETH_DMATXDESC_FS) || \
- ((FLAG) == ETH_DMATXDESC_DC) || \
- ((FLAG) == ETH_DMATXDESC_DP) || \
- ((FLAG) == ETH_DMATXDESC_TTSE) || \
- ((FLAG) == ETH_DMATXDESC_TER) || \
- ((FLAG) == ETH_DMATXDESC_TCH) || \
- ((FLAG) == ETH_DMATXDESC_TTSS) || \
- ((FLAG) == ETH_DMATXDESC_IHE) || \
- ((FLAG) == ETH_DMATXDESC_ES) || \
- ((FLAG) == ETH_DMATXDESC_JT) || \
- ((FLAG) == ETH_DMATXDESC_FF) || \
- ((FLAG) == ETH_DMATXDESC_PCE) || \
- ((FLAG) == ETH_DMATXDESC_LCA) || \
- ((FLAG) == ETH_DMATXDESC_NC) || \
- ((FLAG) == ETH_DMATXDESC_LCO) || \
- ((FLAG) == ETH_DMATXDESC_EC) || \
- ((FLAG) == ETH_DMATXDESC_VF) || \
- ((FLAG) == ETH_DMATXDESC_CC) || \
- ((FLAG) == ETH_DMATXDESC_ED) || \
- ((FLAG) == ETH_DMATXDESC_UF) || \
- ((FLAG) == ETH_DMATXDESC_DB))
+/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
+ * @{
+ */
+#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
+#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
+ * @{
+ */
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
+#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
/**
* @}
*/
-/** @defgroup ETH_DMA_Tx_descriptor_segment
+/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
* @{
*/
#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */
#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */
-#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
- ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
-
/**
* @}
*/
-/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
* @{
*/
#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */
#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
-#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
- ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
- ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
- ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
-/**
- * @brief ETH DMA Tx Desciptor buffer size
- */
-#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Rx_descriptor_flags
- * @{
- */
-#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
- ((FLAG) == ETH_DMARXDESC_AFM) || \
- ((FLAG) == ETH_DMARXDESC_ES) || \
- ((FLAG) == ETH_DMARXDESC_DE) || \
- ((FLAG) == ETH_DMARXDESC_SAF) || \
- ((FLAG) == ETH_DMARXDESC_LE) || \
- ((FLAG) == ETH_DMARXDESC_OE) || \
- ((FLAG) == ETH_DMARXDESC_VLAN) || \
- ((FLAG) == ETH_DMARXDESC_FS) || \
- ((FLAG) == ETH_DMARXDESC_LS) || \
- ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
- ((FLAG) == ETH_DMARXDESC_LC) || \
- ((FLAG) == ETH_DMARXDESC_FT) || \
- ((FLAG) == ETH_DMARXDESC_RWT) || \
- ((FLAG) == ETH_DMARXDESC_RE) || \
- ((FLAG) == ETH_DMARXDESC_DBE) || \
- ((FLAG) == ETH_DMARXDESC_CE) || \
- ((FLAG) == ETH_DMARXDESC_MAMPCE))
-
-/* ETHERNET DMA PTP Rx descriptor extended flags --------------------------------*/
-#define IS_ETH_DMAPTPRXDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRXDESC_PTPV) || \
- ((FLAG) == ETH_DMAPTPRXDESC_PTPFT) || \
- ((FLAG) == ETH_DMAPTPRXDESC_PTPMT) || \
- ((FLAG) == ETH_DMAPTPRXDESC_IPV6PR) || \
- ((FLAG) == ETH_DMAPTPRXDESC_IPV4PR) || \
- ((FLAG) == ETH_DMAPTPRXDESC_IPCB) || \
- ((FLAG) == ETH_DMAPTPRXDESC_IPPE) || \
- ((FLAG) == ETH_DMAPTPRXDESC_IPHE) || \
- ((FLAG) == ETH_DMAPTPRXDESC_IPPT))
-
/**
* @}
*/
-/** @defgroup ETH_DMA_Rx_descriptor_buffers_
+/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
* @{
*/
#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
-#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
- ((BUFFER) == ETH_DMARXDESC_BUFFER2))
-
-
-/* ETHERNET DMA Tx descriptors Collision Count Shift */
-#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
-
-/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
-#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
-
-/* ETHERNET DMA Rx descriptors Frame Length Shift */
-#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
-
-/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
-#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
-
-/* ETHERNET DMA Rx descriptors Frame length Shift */
-#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
-
/**
* @}
*/
-/** @defgroup ETH_PMT_Flags
+/** @defgroup ETH_PMT_Flags ETH PMT Flags
* @{
*/
#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
-#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
- ((FLAG) == ETH_PMT_FLAG_MPR))
/**
* @}
*/
-/** @defgroup ETH_MMC_Tx_Interrupts
+/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
* @{
*/
#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
-
/**
* @}
*/
-/** @defgroup ETH_MMC_Rx_Interrupts
+/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
* @{
*/
#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
-#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
- ((IT) != 0x00))
-#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
- ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
- ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
-/**
- * @}
- */
-
-/** @defgroup ETH_MMC_Registers
- * @{
- */
-#define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */
-#define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */
-#define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */
-#define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */
-#define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */
-#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */
-#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */
-#define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */
-#define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */
-#define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */
-#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */
-
-/**
- * @brief ETH MMC registers
- */
-#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \
- ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \
- ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \
- ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \
- ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \
- ((REG) == ETH_MMCRGUFCR))
/**
* @}
*/
-/** @defgroup ETH_MAC_Flags
+/** @defgroup ETH_MAC_Flags ETH MAC Flags
* @{
*/
#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
@@ -1529,21 +1499,18 @@ typedef struct
#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
-#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
- ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
- ((FLAG) == ETH_MAC_FLAG_PMT))
/**
* @}
*/
-/** @defgroup ETH_DMA_Flags
+/** @defgroup ETH_DMA_Flags ETH DMA Flags
* @{
*/
#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write transfer, 1-read transfer */
#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
@@ -1560,24 +1527,11 @@ typedef struct
#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
-
-#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
-#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
- ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
- ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
- ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
- ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
- ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
- ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
- ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
- ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
- ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
- ((FLAG) == ETH_DMA_FLAG_T))
/**
* @}
*/
-/** @defgroup ETH_MAC_Interrupts
+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
* @{
*/
#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
@@ -1585,15 +1539,11 @@ typedef struct
#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
-#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
-#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
- ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
- ((IT) == ETH_MAC_IT_PMT))
/**
* @}
*/
-/** @defgroup ETH_DMA_Interrupts
+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
* @{
*/
#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
@@ -1614,23 +1564,11 @@ typedef struct
#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
-
-#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
-#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
- ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
- ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
- ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
- ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
- ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
- ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
- ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
- ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
-
/**
* @}
*/
-/** @defgroup ETH_DMA_transmit_process_state_
+/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
* @{
*/
#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
@@ -1645,7 +1583,7 @@ typedef struct
*/
-/** @defgroup ETH_DMA_receive_process_state_
+/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
* @{
*/
#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
@@ -1659,51 +1597,44 @@ typedef struct
* @}
*/
-/** @defgroup ETH_DMA_overflow_
+/** @defgroup ETH_DMA_overflow ETH DMA overflow
* @{
*/
#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
-#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
- ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
/**
* @}
*/
-/* ETHERNET MAC address offsets */
-#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
-#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
-
-/* ETHERNET MACMIIAR register Mask */
-#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
-
-/* ETHERNET MACCR register Mask */
-#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
-
-/* ETHERNET MACFCR register Mask */
-#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
-
-
-/* ETHERNET DMAOMR register Mask */
-#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
-
-
-/* ETHERNET Remote Wake-up frame register length */
-#define ETH_WAKEUP_REGISTER_LENGTH 8
+/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
+ * @{
+ */
+#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */
-/* ETHERNET Missed frames counter Shift */
-#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
+/**
+ * @}
+ */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ETH_Exported_Macros ETH Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+
+/** @brief Reset ETH handle state
+ * @param __HANDLE__: specifies the ETH handle.
+ * @retval None
+ */
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
/**
* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
* @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__: specifies the flag of TDES0 to check.
* @retval the ETH_DMATxDescFlag (SET or RESET).
*/
#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
@@ -1711,7 +1642,7 @@ typedef struct
/**
* @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
* @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__: specifies the flag of RDES0 to check.
* @retval the ETH_DMATxDescFlag (SET or RESET).
*/
#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
@@ -1872,25 +1803,11 @@ typedef struct
*/
#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
-/**
- * @brief Clears the specified ETHERNET MAC flag.
- * @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
- * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
- * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
- * @arg ETH_MAC_FLAG_MMC : MMC flag
- * @arg ETH_MAC_FLAG_PMT : PMT flag
- * @retval None.
- */
-#define __HAL_ETH_MAC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->MACSR &= ~(__FLAG__))
-
/**
* @brief Enables the specified ETHERNET DMA interrupts.
* @param __HANDLE__ : ETH Handle
* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
- * enabled @defgroup ETH_DMA_Interrupts
+ * enabled @ref ETH_DMA_Interrupts
* @retval None
*/
#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
@@ -1899,7 +1816,7 @@ typedef struct
* @brief Disables the specified ETHERNET DMA interrupts.
* @param __HANDLE__ : ETH Handle
* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
- * disabled. @defgroup ETH_DMA_Interrupts
+ * disabled. @ref ETH_DMA_Interrupts
* @retval None
*/
#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
@@ -1907,7 +1824,7 @@ typedef struct
/**
* @brief Clears the ETHERNET DMA IT pending bit.
* @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @defgroup ETH_DMA_Interrupts
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
* @retval None
*/
#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
@@ -1915,7 +1832,7 @@ typedef struct
/**
* @brief Checks whether the specified ETHERNET DMA flag is set or not.
* @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
* @retval The new state of ETH_DMA_FLAG (SET or RESET).
*/
#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
@@ -1923,10 +1840,10 @@ typedef struct
/**
* @brief Checks whether the specified ETHERNET DMA flag is set or not.
* @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to clear.
+ * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
* @retval The new state of ETH_DMA_FLAG (SET or RESET).
*/
-#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR &= ~(__FLAG__))
+#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
/**
* @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
@@ -2125,13 +2042,102 @@ typedef struct
* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
* @retval None
*/
-#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
+#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
+
+/**
+ * @brief Enables the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Disables the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Enable event on ETH External event line.
+ * @retval None.
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Disable event on ETH External event line
+ * @retval None.
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Get flag of the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Clear flag of the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Enables rising edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
+
+/**
+ * @brief Disables the rising edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Enables falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Disables falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
+ EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
+/**
+ * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
+ EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @retval None.
+ */
+#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ETH_Exported_Functions
+ * @{
+ */
+
/* Initialization and de-initialization functions ****************************/
+
+/** @addtogroup ETH_Exported_Functions_Group1
+ * @{
+ */
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
@@ -2139,41 +2145,67 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
+/**
+ * @}
+ */
/* IO operation functions ****************************************************/
+
+/** @addtogroup ETH_Exported_Functions_Group2
+ * @{
+ */
HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
-
- /* Non-Blocking mode: Interrupt */
+/* Communication with PHY functions*/
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
+/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
-
- /* Callback in non blocking modes (Interrupt) */
+/* Callback in non blocking modes (Interrupt) */
void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
-
-/* Cmmunication with PHY functions*/
-HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
-HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
+/**
+ * @}
+ */
/* Peripheral Control functions **********************************************/
+
+/** @addtogroup ETH_Exported_Functions_Group3
+ * @{
+ */
+
HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
-
HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
+/**
+ * @}
+ */
/* Peripheral State functions ************************************************/
+
+/** @addtogroup ETH_Exported_Functions_Group4
+ * @{
+ */
HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
+/**
+ * @}
+ */
#endif /* STM32F207xx || STM32F217xx */
/**
* @}
- */
+ */
/**
* @}
- */
+ */
+
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
diff --git a/f2/include/stm32f2xx_hal_flash.h b/f2/include/stm32f2xx_hal_flash.h
index aadea5d59b45d437b9a12a7e899fe1505e0bf740..bad64a357d613f83a8462c7974e0eac6667c87a6 100755
--- a/f2/include/stm32f2xx_hal_flash.h
+++ b/f2/include/stm32f2xx_hal_flash.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_flash.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,20 +54,11 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
-/**
- * @brief FLASH Error structure definition
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+ * @{
*/
-typedef enum
-{
- FLASH_ERROR_RD = 0x01,
- FLASH_ERROR_PGS = 0x02,
- FLASH_ERROR_PGP = 0x04,
- FLASH_ERROR_PGA = 0x08,
- FLASH_ERROR_WRP = 0x10,
- FLASH_ERROR_OPERATION = 0x20
-}FLASH_ErrorTypeDef;
-
+
/**
* @brief FLASH Procedure structure definition
*/
@@ -79,7 +70,6 @@ typedef enum
FLASH_PROC_PROGRAM
} FLASH_ProcedureTypeDef;
-
/**
* @brief FLASH handle Structure definition
*/
@@ -89,42 +79,49 @@ typedef struct
__IO uint32_t NbSectorsToErase; /*Internal variable to save the remaining sectors to erase in IT context*/
- __IO uint8_t VoltageForErase; /*Internal variable to provide voltange range selected by user in IT context*/
+ __IO uint8_t VoltageForErase; /*Internal variable to provide voltage range selected by user in IT context*/
__IO uint32_t Sector; /*Internal variable to define the current sector which is erasing*/
+ __IO uint32_t Bank; /*Internal variable to save current bank selected during mass erase*/
+
__IO uint32_t Address; /*Internal variable to save address selected for program*/
HAL_LockTypeDef Lock; /* FLASH locking object */
- __IO FLASH_ErrorTypeDef ErrorCode; /* FLASH error code */
+ __IO uint32_t ErrorCode; /* FLASH error code */
}FLASH_ProcessTypeDef;
-/**
- * @brief FLASH Error source
- */
-/* Exported constants --------------------------------------------------------*/
+/**
+ * @}
+ */
+/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
* @{
*/
-
-
-
+/** @defgroup FLASH_Error_Code FLASH Error Code
+ * @brief FLASH Error Code
+ * @{
+ */
+#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000001) /*!< Programming Sequence error */
+#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000002) /*!< Programming Parallelism error */
+#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000004) /*!< Programming Alignment error */
+#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000008) /*!< Write protection error */
+#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000010) /*!< Operation Error */
+/**
+ * @}
+ */
+
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
-#define TYPEPROGRAM_BYTE ((uint32_t)0x00) /*!< Program byte (8-bit) at a specified address */
-#define TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!< Program a half-word (16-bit) at a specified address */
-#define TYPEPROGRAM_WORD ((uint32_t)0x02) /*!< Program a word (32-bit) at a specified address */
-#define TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!< Program a double word (64-bit) at a specified address */
-
-#define IS_TYPEPROGRAM(VALUE)(((VALUE) == TYPEPROGRAM_BYTE) || \
- ((VALUE) == TYPEPROGRAM_HALFWORD) || \
- ((VALUE) == TYPEPROGRAM_WORD) || \
- ((VALUE) == TYPEPROGRAM_DOUBLEWORD))
-
+#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00) /*!< Program byte (8-bit) at a specified address */
+#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!< Program a half-word (16-bit) at a specified address */
+#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02) /*!< Program a word (32-bit) at a specified address */
+#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!< Program a double word (64-bit) at a specified address */
/**
* @}
*/
@@ -139,9 +136,7 @@ typedef struct
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */
#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming Sequence error flag */
-#define FLASH_FLAG_RDERR ((uint32_t)0x00000100) /*!< Read Protection error flag (PCROP) */
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
-
/**
* @}
*/
@@ -152,7 +147,6 @@ typedef struct
*/
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */
-
/**
* @}
*/
@@ -181,33 +175,14 @@ typedef struct
* @}
*/
-/**
- * @brief ACR register byte 0 (Bits[7:0]) base address
- */
-#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
-/**
- * @brief OPTCR register byte 0 (Bits[7:0]) base address
- */
-#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14)
-/**
- * @brief OPTCR register byte 1 (Bits[15:8]) base address
- */
-#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
-/**
- * @brief OPTCR register byte 2 (Bits[23:16]) base address
- */
-#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16)
-/**
- * @brief OPTCR register byte 3 (Bits[31:24]) base address
- */
-#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17)
-
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
-
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+ * @{
+ */
/**
* @brief Set the FLASH Latency.
* @param __LATENCY__: FLASH Latency
@@ -216,6 +191,13 @@ typedef struct
*/
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))
+/**
+ * @brief Get the FLASH Latency.
+ * @retval FLASH Latency
+ * The value of this parameter depend on device used within the same series
+ */
+#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
/**
* @brief Enable the FLASH prefetch buffer.
* @retval none
@@ -257,15 +239,18 @@ typedef struct
* @note This function must be used only when the Instruction Cache is disabled.
* @retval None
*/
-#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() (FLASH->ACR |= FLASH_ACR_ICRST)
+#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST; \
+ FLASH->ACR &= ~FLASH_ACR_ICRST; \
+ }while(0)
/**
* @brief Resets the FLASH data Cache.
* @note This function must be used only when the data Cache is disabled.
* @retval None
*/
-#define __HAL_FLASH_DATA_CACHE_RESET() (FLASH->ACR |= FLASH_ACR_DCRST)
-
+#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST; \
+ FLASH->ACR &= ~FLASH_ACR_DCRST; \
+ }while(0)
/**
* @brief Enable the specified FLASH interrupt.
* @param __INTERRUPT__ : FLASH interrupt
@@ -296,11 +281,10 @@ typedef struct
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
* @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
- * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP)
* @arg FLASH_FLAG_BSY : FLASH Busy flag
* @retval The new state of __FLAG__ (SET or RESET).
*/
-#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)))
+#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)) == (__FLAG__))
/**
* @brief Clear the specified FLASH flag.
@@ -311,37 +295,130 @@ typedef struct
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
- * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
- * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP)
+ * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
* @retval none
*/
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
+/**
+ * @}
+ */
/* Include FLASH HAL Extension module */
#include "stm32f2xx_hal_flash_ex.h"
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+ * @{
+ */
+/** @addtogroup FLASH_Exported_Functions_Group1
+ * @{
+ */
/* Program operation functions ***********************************************/
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
/* FLASH IRQ handler method */
-void HAL_FLASH_IRQHandler(void);
+void HAL_FLASH_IRQHandler(void);
/* Callbacks in non blocking modes */
-void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
-void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+/**
+ * @}
+ */
+/** @addtogroup FLASH_Exported_Functions_Group2
+ * @{
+ */
/* Peripheral Control functions **********************************************/
-HAL_StatusTypeDef HAL_FLASH_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_Lock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
/* Option bytes control */
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+/**
+ * @}
+ */
+/** @addtogroup FLASH_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral State functions ************************************************/
-FLASH_ErrorTypeDef HAL_FLASH_GetError(void);
-
+uint32_t HAL_FLASH_GetError(void);
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+ * @{
+ */
+
+/**
+ * @brief ACR register byte 0 (Bits[7:0]) base address
+ */
+#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
+/**
+ * @brief OPTCR register byte 0 (Bits[7:0]) base address
+ */
+#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14)
+/**
+ * @brief OPTCR register byte 1 (Bits[15:8]) base address
+ */
+#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
+/**
+ * @brief OPTCR register byte 2 (Bits[23:16]) base address
+ */
+#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16)
+/**
+ * @brief OPTCR register byte 3 (Bits[31:24]) base address
+ */
+#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+ * @{
+ */
+
+/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters
+ * @{
+ */
+#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_flash_ex.h b/f2/include/stm32f2xx_hal_flash_ex.h
index 1949bfd802bc404104c5681f1a29a1308a8056ce..e1157ad1ee7ec0f8edfc3d2f13e4d784b4dc0761 100755
--- a/f2/include/stm32f2xx_hal_flash_ex.h
+++ b/f2/include/stm32f2xx_hal_flash_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_flash_ex.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of FLASH HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,22 +55,28 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
+ * @{
+ */
/**
* @brief FLASH Erase structure definition
*/
typedef struct
{
- uint32_t TypeErase; /*!< TypeErase: Mass erase or sector Erase.
+ uint32_t TypeErase; /*!< Mass erase or sector Erase.
This parameter can be a value of @ref FLASHEx_Type_Erase */
- uint32_t Sector; /*!< Sector: Initial FLASH sector to erase when Mass erase is disabled
+ uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
+ This parameter must be a value of @ref FLASHEx_Banks */
+
+ uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled
This parameter must be a value of @ref FLASHEx_Sectors */
- uint32_t NbSectors; /*!< NbSectors: Number of sectors to be erased.
+ uint32_t NbSectors; /*!< Number of sectors to be erased.
This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
- uint32_t VoltageRange;/*!< VoltageRange: The device voltage range which defines the erase parallelism
+ uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
This parameter must be a value of @ref FLASHEx_Voltage_Range */
} FLASH_EraseInitTypeDef;
@@ -80,41 +86,39 @@ typedef struct
*/
typedef struct
{
- uint32_t OptionType; /*!< OptionType: Option byte to be configured.
+ uint32_t OptionType; /*!< Option byte to be configured.
This parameter can be a value of @ref FLASHEx_Option_Type */
- uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
+ uint32_t WRPState; /*!< Write protection activation or deactivation.
This parameter can be a value of @ref FLASHEx_WRP_State */
- uint32_t WRPSector; /*!< WRPSector: specifies the sector(s) to be write protected
+ uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
The value of this parameter depend on device used within the same series */
- uint32_t RDPLevel; /*!< RDPLevel: Set the read protection level..
+ uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
+ This parameter must be a value of @ref FLASHEx_Banks */
+
+ uint32_t RDPLevel; /*!< Set the read protection level.
This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
- uint32_t BORLevel; /*!< BORLevel: Set the BOR Level.
+ uint32_t BORLevel; /*!< Set the BOR Level.
This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
- uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
- This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog, @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/
+ uint8_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */
} FLASH_OBProgramInitTypeDef;
/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
* @{
*/
/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
* @{
*/
-#define TYPEERASE_SECTORS ((uint32_t)0x00) /*!< Sectors erase only */
-#define TYPEERASE_MASSERASE ((uint32_t)0x01) /*!< Flash Mass erase activation */
-
-#define IS_TYPEERASE(VALUE)(((VALUE) == TYPEERASE_SECTORS) || \
- ((VALUE) == TYPEERASE_MASSERASE))
-
+#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00) /*!< Sectors erase only */
+#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /*!< Flash Mass erase activation */
/**
* @}
*/
@@ -122,16 +126,10 @@ typedef struct
/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
* @{
*/
-#define VOLTAGE_RANGE_1 ((uint32_t)0x00) /*!< Device operating range: 1.8V to 2.1V */
-#define VOLTAGE_RANGE_2 ((uint32_t)0x01) /*!< Device operating range: 2.1V to 2.7V */
-#define VOLTAGE_RANGE_3 ((uint32_t)0x02) /*!< Device operating range: 2.7V to 3.6V */
-#define VOLTAGE_RANGE_4 ((uint32_t)0x03) /*!< Device operating range: 2.7V to 3.6V + External Vpp */
-
-#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VOLTAGE_RANGE_1) || \
- ((RANGE) == VOLTAGE_RANGE_2) || \
- ((RANGE) == VOLTAGE_RANGE_3) || \
- ((RANGE) == VOLTAGE_RANGE_4))
-
+#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00) /*!< Device operating range: 1.8V to 2.1V */
+#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01) /*!< Device operating range: 2.1V to 2.7V */
+#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02) /*!< Device operating range: 2.7V to 3.6V */
+#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03) /*!< Device operating range: 2.7V to 3.6V + External Vpp */
/**
* @}
*/
@@ -139,12 +137,8 @@ typedef struct
/** @defgroup FLASHEx_WRP_State FLASH WRP State
* @{
*/
-#define WRPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable the write protection of the desired bank 1 sectors */
-#define WRPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable the write protection of the desired bank 1 sectors */
-
-#define IS_WRPSTATE(VALUE)(((VALUE) == WRPSTATE_DISABLE) || \
- ((VALUE) == WRPSTATE_ENABLE))
-
+#define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable the write protection of the desired bank 1 sectors */
+#define OB_WRPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable the write protection of the desired bank 1 sectors */
/**
* @}
*/
@@ -156,9 +150,6 @@ typedef struct
#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */
#define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */
#define OPTIONBYTE_BOR ((uint32_t)0x08) /*!< BOR option byte configuration */
-
-#define IS_OPTIONBYTE(VALUE)(((VALUE) < (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
-
/**
* @}
*/
@@ -168,11 +159,8 @@ typedef struct
*/
#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
#define OB_RDP_LEVEL_1 ((uint8_t)0x55)
-/*#define OB_RDP_LEVEL_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2
- it s no more possible to go back to level 1 or 0 */
-#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
- ((LEVEL) == OB_RDP_LEVEL_1))/*||\
- ((LEVEL) == OB_RDP_LEVEL_2))*/
+#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2
+ it s no more possible to go back to level 1 or 0 */
/**
* @}
*/
@@ -182,7 +170,6 @@ typedef struct
*/
#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
/**
* @}
*/
@@ -192,7 +179,6 @@ typedef struct
*/
#define OB_STOP_NO_RST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
/**
* @}
*/
@@ -203,7 +189,6 @@ typedef struct
*/
#define OB_STDBY_NO_RST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
/**
* @}
*/
@@ -215,8 +200,11 @@ typedef struct
#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */
#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */
#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */
-#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
- ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
+/**
+ * @}
+ */
+
+
/**
* @}
*/
@@ -233,18 +221,27 @@ typedef struct
#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
- ((LATENCY) == FLASH_LATENCY_1) || \
- ((LATENCY) == FLASH_LATENCY_2) || \
- ((LATENCY) == FLASH_LATENCY_3) || \
- ((LATENCY) == FLASH_LATENCY_4) || \
- ((LATENCY) == FLASH_LATENCY_5) || \
- ((LATENCY) == FLASH_LATENCY_6) || \
- ((LATENCY) == FLASH_LATENCY_7))
/**
* @}
*/
+
+/** @defgroup FLASHEx_Banks FLASH Banks
+ * @{
+ */
+#define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
+ * @{
+ */
+#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER Bit */
+/**
+ * @}
+ */
+
/** @defgroup FLASHEx_Sectors FLASH Sectors
* @{
*/
@@ -261,19 +258,7 @@ typedef struct
#define FLASH_SECTOR_10 ((uint32_t)10) /*!< Sector Number 10 */
#define FLASH_SECTOR_11 ((uint32_t)11) /*!< Sector Number 11 */
-#define FLASH_SECTOR_TOTAL 12
-
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
- ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
- ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
- ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
- ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
- ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11))
-
-#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\
- (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
-#define IS_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
/**
* @}
@@ -296,34 +281,135 @@ typedef struct
#define OB_WRP_SECTOR_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
-#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+
/**
* @}
- */
+ */
+/**
+ * @}
+ */
+
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+ * @{
+ */
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+ * @{
+ */
/* Extension Program operation functions *************************************/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
-void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
+/**
+ * @}
+ */
/**
* @}
- */
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Constants FLASH Private Constants
+ * @{
+ */
+
+#define FLASH_SECTOR_TOTAL 12
/**
* @}
*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
+ * @{
+ */
+
+/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters
+ * @{
+ */
+
+#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
+ ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+
+#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
+ ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
+ ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
+ ((RANGE) == FLASH_VOLTAGE_RANGE_4))
+
+#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
+ ((VALUE) == OB_WRPSTATE_ENABLE))
+
+#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
+
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
+ ((LEVEL) == OB_RDP_LEVEL_1) ||\
+ ((LEVEL) == OB_RDP_LEVEL_2))
+
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+
+#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
+ ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
+
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
+ ((LATENCY) == FLASH_LATENCY_1) || \
+ ((LATENCY) == FLASH_LATENCY_2) || \
+ ((LATENCY) == FLASH_LATENCY_3) || \
+ ((LATENCY) == FLASH_LATENCY_4) || \
+ ((LATENCY) == FLASH_LATENCY_5) || \
+ ((LATENCY) == FLASH_LATENCY_6) || \
+ ((LATENCY) == FLASH_LATENCY_7))
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
+ ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
+ ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11))
+
+
+
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
+#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+
/**
* @}
- */
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASH Private Functions
+ * @{
+ */
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
+void FLASH_FlushCaches(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
diff --git a/f2/include/stm32f2xx_hal_gpio.h b/f2/include/stm32f2xx_hal_gpio.h
index 3e8228c275bf51962a39ff545dc01c96345749da..7c4edd56166d2c0eacda41d20ea116f9e5dbe1f9 100755
--- a/f2/include/stm32f2xx_hal_gpio.h
+++ b/f2/include/stm32f2xx_hal_gpio.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_gpio.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,9 +55,12 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+ * @{
+ */
/**
- * @brief GPIO Init structure definition
+ * @brief GPIO Init structure definition
*/
typedef struct
{
@@ -73,8 +76,8 @@ typedef struct
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed_define */
- uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
- This parameter can be a value of @ref GPIO_Alternat_function_selection */
+ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
+ This parameter can be a value of @ref GPIO_Alternate_function_selection */
}GPIO_InitTypeDef;
/**
@@ -85,15 +88,17 @@ typedef enum
GPIO_PIN_RESET = 0,
GPIO_PIN_SET
}GPIO_PinState;
-#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Constants
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{
- */
+ */
-/** @defgroup GPIO_pins_define
+/** @defgroup GPIO_pins_define GPIO pins define
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
@@ -114,28 +119,12 @@ typedef enum
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
-#define IS_GPIO_PIN(PIN) ((((PIN) & (uint32_t)0x00) == 0x00) && ((PIN) != (uint32_t)0x00))
-#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_PIN_0) || \
- ((PIN) == GPIO_PIN_1) || \
- ((PIN) == GPIO_PIN_2) || \
- ((PIN) == GPIO_PIN_3) || \
- ((PIN) == GPIO_PIN_4) || \
- ((PIN) == GPIO_PIN_5) || \
- ((PIN) == GPIO_PIN_6) || \
- ((PIN) == GPIO_PIN_7) || \
- ((PIN) == GPIO_PIN_8) || \
- ((PIN) == GPIO_PIN_9) || \
- ((PIN) == GPIO_PIN_10) || \
- ((PIN) == GPIO_PIN_11) || \
- ((PIN) == GPIO_PIN_12) || \
- ((PIN) == GPIO_PIN_13) || \
- ((PIN) == GPIO_PIN_14) || \
- ((PIN) == GPIO_PIN_15))
+#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
/**
* @}
*/
-/** @defgroup GPIO_mode_define
+/** @defgroup GPIO_mode_define GPIO mode define
* @brief GPIO Configuration Mode
* Elements values convention: 0xX0yz00YZ
* - X : GPIO mode or EXTI Mode
@@ -160,48 +149,29 @@ typedef enum
#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */
-
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
- ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
- ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
- ((MODE) == GPIO_MODE_AF_PP) ||\
- ((MODE) == GPIO_MODE_AF_OD) ||\
- ((MODE) == GPIO_MODE_IT_RISING) ||\
- ((MODE) == GPIO_MODE_IT_FALLING) ||\
- ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
- ((MODE) == GPIO_MODE_EVT_RISING) ||\
- ((MODE) == GPIO_MODE_EVT_FALLING) ||\
- ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
- ((MODE) == GPIO_MODE_ANALOG))
-
/**
* @}
*/
-/** @defgroup GPIO_speed_define
+
+/** @defgroup GPIO_speed_define GPIO speed define
* @brief GPIO Output Maximum frequency
* @{
*/
-#define GPIO_SPEED_LOW ((uint32_t)0x00000000) /*!< Low speed */
-#define GPIO_SPEED_MEDIUM ((uint32_t)0x00000001) /*!< Medium speed */
-#define GPIO_SPEED_FAST ((uint32_t)0x00000002) /*!< Fast speed */
-#define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */
-
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \
- ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH))
+#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000) /*!< IO works at 2 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001) /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002) /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003) /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */
/**
* @}
*/
- /** @defgroup GPIO_pull_define
+ /** @defgroup GPIO_pull_define GPIO pull define
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */
#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */
-
-#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
- ((PULL) == GPIO_PULLDOWN))
/**
* @}
*/
@@ -211,6 +181,9 @@ typedef enum
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+ * @{
+ */
/**
* @brief Checks whether the specified EXTI line flag is set or not.
@@ -244,20 +217,45 @@ typedef enum
*/
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+/**
+ * @brief Generates a Software interrupt on selected EXTI line.
+ * @param __EXTI_LINE__: specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
+/**
+ * @}
+ */
+
/* Include GPIO HAL Extension module */
#include "stm32f2xx_hal_gpio_ex.h"
-/* Exported functions --------------------------------------------------------*/
-/* Initialization and de-initialization functions *******************************/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+/**
+ * @}
+ */
-/* IO operation functions *******************************************************/
+/** @addtogroup GPIO_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/**
* @}
@@ -266,6 +264,59 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/**
* @}
*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+ * @{
+ */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
+ ((MODE) == GPIO_MODE_AF_PP) ||\
+ ((MODE) == GPIO_MODE_AF_OD) ||\
+ ((MODE) == GPIO_MODE_IT_RISING) ||\
+ ((MODE) == GPIO_MODE_IT_FALLING) ||\
+ ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING) ||\
+ ((MODE) == GPIO_MODE_EVT_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_ANALOG))
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
+ ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
+ ((PULL) == GPIO_PULLDOWN))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Functions GPIO Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
#ifdef __cplusplus
}
diff --git a/f2/include/stm32f2xx_hal_gpio_ex.h b/f2/include/stm32f2xx_hal_gpio_ex.h
index 67e455eb5ecb3570fc1d66766133ebd13c0f8dfc..88f5c7706433174440198e39452309b86ef1b851 100755
--- a/f2/include/stm32f2xx_hal_gpio_ex.h
+++ b/f2/include/stm32f2xx_hal_gpio_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_gpio_ex.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
- * @attention
+ * @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,19 +50,19 @@
* @{
*/
-/** @addtogroup GPIO
+/** @defgroup GPIOEx GPIOEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
-
+/* Exported constants --------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Constants
+/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
* @{
*/
-/** @defgroup GPIO_Alternat_function_selection
+/** @defgroup GPIO_Alternate_function_selection GPIO Alternate function selection
* @{
*/
@@ -168,7 +168,65 @@
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
+ * @{
+ */
+/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
+ * @{
+ */
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U :\
+ ((__GPIOx__) == (GPIOF))? 5U :\
+ ((__GPIOx__) == (GPIOG))? 6U :\
+ ((__GPIOx__) == (GPIOH))? 7U :\
+ ((__GPIOx__) == (GPIOI))? 8U : 9U)
+/**
+ * @}
+ */
+
+/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
+ * @{
+ */
#if defined(STM32F207xx) || defined(STM32F217xx)
+
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
@@ -215,9 +273,14 @@
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_hash.h b/f2/include/stm32f2xx_hal_hash.h
index 2433d3a9d613f611998337cbfd2d5841e3bc4b83..1279ec66270ae32cf53b212ec752c084ef140da4 100755
--- a/f2/include/stm32f2xx_hal_hash.h
+++ b/f2/include/stm32f2xx_hal_hash.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_hash.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F2xx_HAL_HASH_H
@@ -52,139 +52,150 @@
* @{
*/
-/** @addtogroup HASH
- * @{
+/** @addtogroup HASH
+ * @brief HASH HAL module driver
+ * @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HASH_Exported_Types HASH Exported Types
+ * @{
+ */
-/**
- * @brief HASH Configuration Structure definition
+/** @defgroup HASH_Exported_Types_Group1 HASH Configuration Structure definition
+ * @{
*/
+
typedef struct
-{
+{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
This parameter can be a value of @ref HASH_Data_Type */
-
+
uint32_t KeySize; /*!< The key size is used only in HMAC operation */
-
+
uint8_t* pKey; /*!< The key is used only in HMAC operation */
-
}HASH_InitTypeDef;
/**
- * @brief HAL State structures definition
- */
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Types_Group2 HASH State structures definition
+ * @{
+ */
+
typedef enum
{
HAL_HASH_STATE_RESET = 0x00, /*!< HASH not yet initialized or disabled */
- HAL_HASH_STATE_READY = 0x01, /*!< HASH initialized and ready for use */
- HAL_HASH_STATE_BUSY = 0x02, /*!< HASH internal process is ongoing */
+ HAL_HASH_STATE_READY = 0x01, /*!< HASH initialized and ready for use */
+ HAL_HASH_STATE_BUSY = 0x02, /*!< HASH internal process is ongoing */
HAL_HASH_STATE_TIMEOUT = 0x03, /*!< HASH timeout state */
HAL_HASH_STATE_ERROR = 0x04 /*!< HASH error state */
-
}HAL_HASH_STATETypeDef;
/**
- * @brief HAL phase structures definition
- */
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Types_Group3 HASH phase structures definition
+ * @{
+ */
+
typedef enum
{
HAL_HASH_PHASE_READY = 0x01, /*!< HASH peripheral is ready for initialization */
HAL_HASH_PHASE_PROCESS = 0x02, /*!< HASH peripheral is in processing phase */
-
}HAL_HASHPhaseTypeDef;
/**
- * @brief HASH Handle Structure definition
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Types_Group4 HASH Handle structures definition
+ * @{
*/
+
typedef struct
-{
+{
HASH_InitTypeDef Init; /*!< HASH required parameters */
-
+
uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
-
+
uint8_t *pHashOutBuffPtr; /*!< Pointer to input buffer */
-
+
__IO uint32_t HashBuffSize; /*!< Size of buffer to be processed */
-
- __IO uint32_t HashInCount; /*!< Counter of inputed data */
-
+
+ __IO uint32_t HashInCount; /*!< Counter of input data */
+
__IO uint32_t HashITCounter; /*!< Counter of issued interrupts */
-
+
HAL_StatusTypeDef Status; /*!< HASH peripheral status */
-
+
HAL_HASHPhaseTypeDef Phase; /*!< HASH peripheral phase */
-
+
DMA_HandleTypeDef *hdmain; /*!< HASH In DMA handle parameters */
-
+
HAL_LockTypeDef Lock; /*!< HASH locking object */
-
+
__IO HAL_HASH_STATETypeDef State; /*!< HASH peripheral state */
-
} HASH_HandleTypeDef;
-/* Exported constants --------------------------------------------------------*/
+/**
+ * @}
+ */
+
-/** @defgroup HASH_Exported_Constants
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HASH_Exported_Constants HASH Exported Constants
* @{
*/
-/** @defgroup HASH_Algo_Selection
+/** @defgroup HASH_Exported_Constants_Group1 HASH Algorithm Selection
* @{
- */
-#define HASH_AlgoSelection_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */
-#define HASH_AlgoSelection_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
-
-#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \
- ((ALGOSELECTION) == HASH_AlgoSelection_MD5))
+ */
+#define HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */
+#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
/**
* @}
*/
-/** @defgroup HASH_Algorithm_Mode
+/** @defgroup HASH_Exported_Constants_Group2 HASH Algorithm Mode
* @{
- */
-#define HASH_AlgoMode_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */
-#define HASH_AlgoMode_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
-
-#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \
- ((ALGOMODE) == HASH_AlgoMode_HMAC))
+ */
+#define HASH_ALGOMODE_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */
+#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
/**
* @}
*/
-/** @defgroup HASH_Data_Type
+/** @defgroup HASH_Data_Type HASH Data Type
* @{
- */
+ */
#define HASH_DATATYPE_32B ((uint32_t)0x0000) /*!< 32-bit data. No swapping */
#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
-
-#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DATATYPE_32B)|| \
- ((DATATYPE) == HASH_DATATYPE_16B)|| \
- ((DATATYPE) == HASH_DATATYPE_8B) || \
- ((DATATYPE) == HASH_DATATYPE_1B))
/**
* @}
*/
-/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode
+/** @defgroup HASH_Exported_Constants_Group4 HASH HMAC Long key
+ * @brief HASH HMAC Long key used only for HMAC mode
* @{
- */
-#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
-#define HASH_HMACKeyType_LongKey HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */
-
-#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \
- ((KEYTYPE) == HASH_HMACKeyType_LongKey))
+ */
+#define HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
+#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */
/**
* @}
*/
-/** @defgroup HASH_flags_definition
+/** @defgroup HASH_Exported_Constants_Group5 HASH Flags definition
* @{
- */
+ */
#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
@@ -192,13 +203,13 @@ typedef struct
#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */
/**
* @}
- */
+ */
-/** @defgroup HASH_interrupts_definition
+/** @defgroup HASH_Exported_Constants_Group6 HASH Interrupts definition
* @{
- */
-#define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */
-#define HASH_IT_DCI HASH_IMR_DCIM /*!< Digest calculation complete */
+ */
+#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
+#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
/**
* @}
*/
@@ -208,6 +219,15 @@ typedef struct
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HASH_Exported_Macros HASH Exported Macros
+ * @{
+ */
+
+/** @brief Reset HASH handle state
+ * @param __HANDLE__: specifies the HASH handle.
+ * @retval None
+ */
+#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
/** @brief Check whether the specified HASH flag is set or not.
* @param __FLAG__: specifies the flag to check.
@@ -219,19 +239,10 @@ typedef struct
* @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_HASH_GET_FLAG(__FLAG__) ((HASH->SR & (__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Macros for HMAC finish.
- * @param None
- * @retval None
- */
-#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
-#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
-
+#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
+ ((HASH->SR & (__FLAG__)) == (__FLAG__)))
/**
* @brief Start the digest computation
- * @param None
* @retval None
*/
#define __HAL_HASH_START_DIGEST() HASH->STR |= HASH_STR_DCAL
@@ -241,51 +252,167 @@ typedef struct
* @param SIZE: size in byte of last data written in Data register.
* @retval None
*/
-#define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBW);\
+#define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBLW);\
HASH->STR |= 8 * ((SIZE) % 4);\
}while(0)
+/**
+ * @}
+ */
+
+
/* Exported functions --------------------------------------------------------*/
-/* Initialization and de-initialization functions **********************************/
+/** @defgroup HASH_Exported_Functions HASH Exported Functions
+ * @{
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group1
+ * @{
+ */
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
+/**
+ * @}
+ */
-/* HASH processing using polling *********************************************/
+/** @addtogroup HASH_Exported_Functions_Group2
+ * @{
+ */
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-
-/* HASH-MAC processing using polling *****************************************/
+/**
+ * @}
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group3
+ * @{
+ */
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+/**
+ * @}
+ */
-/* HASH processing using interrupt *******************************************/
+/** @addtogroup HASH_Exported_Functions_Group4
+ * @{
+ */
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+/**
+ * @}
+ */
-/* HASH processing using DMA *************************************************/
+/** @addtogroup HASH_Exported_Functions_Group5
+ * @{
+ */
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+/**
+ * @}
+ */
-/* HASH-HMAC processing using DMA ********************************************/
+/** @addtogroup HASH_Exported_Functions_Group6
+ * @{
+ */
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+/**
+ * @}
+ */
-/* Processing functions ******************************************************/
+/** @addtogroup HASH_Exported_Functions_Group7
+ * @{
+ */
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
+/**
+ * @}
+ */
-/* Peripheral State functions ************************************************/
+/** @addtogroup HASH_Exported_Functions_Group8
+ * @{
+ */
HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+ /* Private types -------------------------------------------------------------*/
+/** @defgroup HASH_Private_Types HASH Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HASH_Private_Variables HASH Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HASH_Private_Constants HASH Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HASH_Private_Macros HASH Private Macros
+ * @{
+ */
+#define IS_HASH_ALGOSELECTION(__ALGOSELECTION__) (((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA1) || \
+ ((__ALGOSELECTION__) == HASH_ALGOSELECTION_MD5))
+
+
+#define IS_HASH_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == HASH_ALGOMODE_HASH) || \
+ ((__ALGOMODE__) == HASH_ALGOMODE_HMAC))
+
+
+#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
+ ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
+ ((__DATATYPE__) == HASH_DATATYPE_8B) || \
+ ((__DATATYPE__) == HASH_DATATYPE_1B))
+
+
+#define IS_HASH_HMAC_KEYTYPE(__KEYTYPE__) (((__KEYTYPE__) == HASH_HMAC_KEYTYPE_SHORTKEY) || \
+ ((__KEYTYPE__) == HASH_HMAC_KEYTYPE_LONGKEY))
+
+#define IS_HASH_SHA1_BUFFER_SIZE(__SIZE__) ((((__SIZE__)%4) != 0)? 0U: 1U)
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup HASH_Private_Functions HASH Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
#endif /* STM32F215xx || STM32F217xx */
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_hcd.h b/f2/include/stm32f2xx_hal_hcd.h
index 32433c782922326c300f1cc20757ad1fe97af033..051004c88b7f8299a0aebb15d639687e7e038015 100755
--- a/f2/include/stm32f2xx_hal_hcd.h
+++ b/f2/include/stm32f2xx_hal_hcd.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_hcd.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of HCD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -52,19 +52,23 @@
/** @addtogroup HCD
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
+/** @defgroup HCD_Exported_Types HCD Exported Types
+ * @{
+ */
- /**
- * @brief HCD Status structures structure definition
- */
+/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
+ * @{
+ */
typedef enum
{
- HCD_READY = 0x00,
- HCD_ERROR = 0x01,
- HCD_BUSY = 0x02,
- HCD_TIMEOUT = 0x03
+ HAL_HCD_STATE_RESET = 0x00,
+ HAL_HCD_STATE_READY = 0x01,
+ HAL_HCD_STATE_ERROR = 0x02,
+ HAL_HCD_STATE_BUSY = 0x03,
+ HAL_HCD_STATE_TIMEOUT = 0x04
} HCD_StateTypeDef;
typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
@@ -72,53 +76,46 @@ typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
typedef USB_OTG_HCTypeDef HCD_HCTypeDef ;
typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef ;
+/**
+ * @}
+ */
-/**
- * @brief HCD Handle Structure definition
+/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
+ * @{
*/
typedef struct
{
- HCD_TypeDef *Instance; /*!< Register base address */
+ HCD_TypeDef *Instance; /*!< Register base address */
HCD_InitTypeDef Init; /*!< HCD required parameters */
HCD_HCTypeDef hc[15]; /*!< Host channels parameters */
HAL_LockTypeDef Lock; /*!< HCD peripheral status */
__IO HCD_StateTypeDef State; /*!< HCD communication state */
- void *pData; /*!< Pointer Stack Handler */
-
+ void *pData; /*!< Pointer Stack Handler */
} HCD_HandleTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup HCD_Exported_Constants
- * @{
+/**
+ * @}
*/
-/** @defgroup HCD_Instance_definition
- * @{
- */
-
-#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) |= (__INTERRUPT__))
-#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
-
-
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
- ((INSTANCE) == USB_OTG_HS))
/**
* @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Constants HCD Exported Constants
+ * @{
*/
-/** @defgroup HCD_Speed
+/** @defgroup HCD_Speed HCD Speed
* @{
*/
#define HCD_SPEED_HIGH 0
#define HCD_SPEED_LOW 2
#define HCD_SPEED_FULL 3
-
/**
* @}
*/
-
- /** @defgroup HCD_PHY_Module
+
+/** @defgroup HCD_PHY_Module HCD PHY Module
* @{
*/
#define HCD_PHY_ULPI 1
@@ -126,93 +123,138 @@ typedef struct
/**
* @}
*/
+
/**
* @}
*/
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup HCD_Interrupt_Clock
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HCD_Exported_Macros HCD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
-#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
-
-#define __HAL_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) |= (__INTERRUPT__))
-#define __HAL_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
-
+#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
+#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
+
#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
-
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HCD_Exported_Functions HCD Exported Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+/** @addtogroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
+ uint8_t ch_num,
+ uint8_t epnum,
+ uint8_t dev_address,
+ uint8_t speed,
+ uint8_t ep_type,
+ uint16_t mps);
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
-
-HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num);
-
-void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
-
-/* I/O operation functions *****************************************************/
-HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
- uint8_t pipe,
- uint8_t direction ,
- uint8_t ep_type,
- uint8_t token,
- uint8_t* pbuff,
- uint16_t length,
- uint8_t do_ping);
-
- /* Non-Blocking mode: Interrupt */
-void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
- uint8_t chnum,
- HCD_URBStateTypeDef urb_state);
-
-/* Peripheral Control functions ************************************************/
-HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
-
-/* Peripheral State functions **************************************************/
-HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
-HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
-uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
+void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
/**
* @}
- */
+ */
+
+/* I/O operation functions ***************************************************/
+/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
+ uint8_t pipe,
+ uint8_t direction,
+ uint8_t ep_type,
+ uint8_t token,
+ uint8_t* pbuff,
+ uint16_t length,
+ uint8_t do_ping);
+/* Non-Blocking mode: Interrupt */
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
+ uint8_t chnum,
+ HCD_URBStateTypeDef urb_state);
/**
* @}
*/
-
+
+/* Peripheral Control functions **********************************************/
+/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+/**
+ * @}
+ */
+
+/* Peripheral State functions ************************************************/
+/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
+uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HCD_Private_Macros HCD Private Macros
+ * @{
+ */
+/** @defgroup HCD_Instance_definition HCD Instance definition
+ * @{
+ */
+ #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
diff --git a/f2/include/stm32f2xx_hal_i2c.h b/f2/include/stm32f2xx_hal_i2c.h
index f5cf6e541b4b80bd346e7089bdee9a0dca865a8d..d2333ff71aee5accda62e7302c2ba26aff6d863a 100755
--- a/f2/include/stm32f2xx_hal_i2c.h
+++ b/f2/include/stm32f2xx_hal_i2c.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_i2c.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,7 +55,10 @@
*/
/* Exported types ------------------------------------------------------------*/
-
+/** @defgroup I2C_Exported_Types I2C Exported Types
+ * @{
+ */
+
/**
* @brief I2C Configuration Structure definition
*/
@@ -80,7 +83,7 @@ typedef struct
This parameter can be a 7-bit address. */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
- This parameter can be a value of @ref I2C_general_call_addressing_mode. */
+ This parameter can be a value of @ref I2C_general_call_addressing_mode */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_nostretch_mode */
@@ -104,21 +107,6 @@ typedef enum
}HAL_I2C_StateTypeDef;
-/**
- * @brief HAL I2C Error Code structure definition
- */
-typedef enum
-{
- HAL_I2C_ERROR_NONE = 0x00, /*!< No error */
- HAL_I2C_ERROR_BERR = 0x01, /*!< BERR error */
- HAL_I2C_ERROR_ARLO = 0x02, /*!< ARLO error */
- HAL_I2C_ERROR_AF = 0x04, /*!< AF error */
- HAL_I2C_ERROR_OVR = 0x08, /*!< OVR error */
- HAL_I2C_ERROR_DMA = 0x10, /*!< DMA transfer error */
- HAL_I2C_ERROR_TIMEOUT = 0x20 /*!< Timeout error */
-
-}HAL_I2C_ErrorTypeDef;
-
/**
* @brief I2C handle Structure definition
*/
@@ -142,89 +130,88 @@ typedef struct
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
- __IO HAL_I2C_ErrorTypeDef ErrorCode; /* I2C Error code */
+ __IO uint32_t ErrorCode; /*!< I2C Error code */
}I2C_HandleTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+ * @{
+ */
-/** @defgroup I2C_Exported_Constants
+/** @defgroup I2C_Error_Code I2C Error Code
+ * @brief I2C Error Code
* @{
+ */
+#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */
+#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */
+#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004) /*!< AF error */
+#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */
+#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout Error */
+/**
+ * @}
*/
-/** @defgroup I2C_duty_cycle_in_fast_mode
+/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
* @{
*/
#define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000)
#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
-
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
- ((CYCLE) == I2C_DUTYCYCLE_16_9))
/**
* @}
*/
-/** @defgroup I2C_addressing_mode
+/** @defgroup I2C_addressing_mode I2C addressing mode
* @{
*/
#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000)
#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000))
-
-#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
- ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
/**
* @}
*/
-/** @defgroup I2C_dual_addressing_mode
+/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
* @{
*/
-#define I2C_DUALADDRESS_DISABLED ((uint32_t)0x00000000)
-#define I2C_DUALADDRESS_ENABLED I2C_OAR2_ENDUAL
-
-#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLED) || \
- ((ADDRESS) == I2C_DUALADDRESS_ENABLED))
+#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
+#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
/**
* @}
*/
-/** @defgroup I2C_general_call_addressing_mode
+/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
* @{
*/
-#define I2C_GENERALCALL_DISABLED ((uint32_t)0x00000000)
-#define I2C_GENERALCALL_ENABLED I2C_CR1_ENGC
-
-#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLED) || \
- ((CALL) == I2C_GENERALCALL_ENABLED))
+#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000)
+#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
/**
* @}
*/
-/** @defgroup I2C_nostretch_mode
+/** @defgroup I2C_nostretch_mode I2C nostretch mode
* @{
*/
-#define I2C_NOSTRETCH_DISABLED ((uint32_t)0x00000000)
-#define I2C_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH
-
-#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLED) || \
- ((STRETCH) == I2C_NOSTRETCH_ENABLED))
+#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
+#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
-/** @defgroup I2C_Memory_Address_Size
+/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
* @{
*/
#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010)
-
-#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
- ((SIZE) == I2C_MEMADD_SIZE_16BIT))
/**
* @}
*/
-/** @defgroup I2C_Interrupt_configuration_definition
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
* @{
*/
#define I2C_IT_BUF I2C_CR2_ITBUFEN
@@ -234,7 +221,7 @@ typedef struct
* @}
*/
-/** @defgroup I2C_Flag_definition
+/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
#define I2C_FLAG_SMBALERT ((uint32_t)0x00018000)
@@ -267,6 +254,16 @@ typedef struct
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+ * @{
+ */
+
+/** @brief Reset I2C handle state
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @retval None
+ */
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
/** @brief Enable or disable the specified I2C interrupts.
* @param __HANDLE__: specifies the I2C Handle.
@@ -278,7 +275,6 @@ typedef struct
* @arg I2C_IT_ERR: Error interrupt enable
* @retval None
*/
-
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
@@ -323,7 +319,6 @@ typedef struct
* @arg I2C_FLAG_MSL: Master/Slave flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define I2C_FLAG_MASK ((uint32_t)0x0000FFFF)
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16)) == 0x01)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
@@ -341,57 +336,61 @@ typedef struct
* @arg I2C_FLAG_BERR: Bus error flag
* @retval None
*/
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 &= ~((__FLAG__) & I2C_FLAG_MASK))
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
/** @brief Clears the I2C ADDR pending flag.
* @param __HANDLE__: specifies the I2C Handle.
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
* @retval None
*/
-
-#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\
- (__HANDLE__)->Instance->SR2;}while(0)
+#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR1; \
+ tmpreg = (__HANDLE__)->Instance->SR2; \
+ UNUSED(tmpreg); \
+ } while(0)
/** @brief Clears the I2C STOPF pending flag.
* @param __HANDLE__: specifies the I2C Handle.
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
* @retval None
*/
-#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\
- (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE;}while(0)
-
+#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR1; \
+ (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \
+ UNUSED(tmpreg); \
+ } while(0)
+
#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
-#define __HAL_I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000)
-#define __HAL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1))
-#define __HAL_I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1)))
-#define __HAL_I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9))
-#define __HAL_I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000)? (__HAL_I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
- ((__HAL_I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \
- ((__HAL_I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
-
-#define __HAL_I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
-#define __HAL_I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
-
-#define __HAL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
-#define __HAL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
-#define __HAL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
-
-#define __HAL_I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
-#define __HAL_I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
-
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000))
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0)
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+/** @addtogroup I2C_Exported_Functions_Group2
+ * @{
+ */
/* I/O operation functions *****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -428,10 +427,92 @@ void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+/** @addtogroup I2C_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral Control and State functions **************************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+ * @{
+ */
+#define I2C_FLAG_MASK ((uint32_t)0x0000FFFF)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macros I2C Private Macros
+ * @{
+ */
+
+#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000)
+#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1))
+#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1)))
+#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9))
+#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
+ ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \
+ ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
+
+#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
+#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
+
+#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
+#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+
+/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
+ * @{
+ */
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
+ ((CYCLE) == I2C_DUTYCYCLE_16_9))
+#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
+ ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
+ ((CALL) == I2C_GENERALCALL_ENABLE))
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+ ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000))
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_i2s.h b/f2/include/stm32f2xx_hal_i2s.h
index 0dc79fd974ed598383151f12586a60d074b1962f..49b7fe99b8c541dd1f0ec862a4ef7087f1c3e8e4 100755
--- a/f2/include/stm32f2xx_hal_i2s.h
+++ b/f2/include/stm32f2xx_hal_i2s.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_i2s.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,7 +54,11 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2S_Exported_Types I2S Exported Types
+ * @{
+ */
+
/**
* @brief I2S Init structure definition
*/
@@ -99,18 +103,6 @@ typedef enum
}HAL_I2S_StateTypeDef;
-/**
- * @brief HAL I2S Error Code structure definition
- */
-typedef enum
-{
- HAL_I2S_ERROR_NONE = 0x00, /*!< No error */
- HAL_I2S_ERROR_UDR = 0x01, /*!< I2S Underrun error */
- HAL_I2S_ERROR_OVR = 0x02, /*!< I2S Overrun error */
- HAL_I2S_ERROR_FRE = 0x10, /*!< I2S Frame format error */
- HAL_I2S_ERROR_DMA = 0x20 /*!< DMA transfer error */
-}HAL_I2S_ErrorTypeDef;
-
/**
* @brief I2S handle Structure definition
*/
@@ -140,41 +132,54 @@ typedef struct
__IO HAL_I2S_StateTypeDef State; /* I2S communication state */
- __IO HAL_I2S_ErrorTypeDef ErrorCode; /* I2S Error code */
-
+ __IO uint32_t ErrorCode; /* I2S Error code */
+
}I2S_HandleTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_Exported_Constants I2S Exported Constants
+ * @{
+ */
-/** @defgroup I2S_Clock_Source
+/** @defgroup I2S_Error_Code I2S Error Code
+ * @brief I2S Error Code
+ * @{
+ */
+#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000001) /*!< I2S Underrun error */
+#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002) /*!< I2S Overrun error */
+#define HAL_I2SEX_ERROR_UDR ((uint32_t)0x00000004) /*!< I2S extended Underrun error */
+#define HAL_I2SEX_ERROR_OVR ((uint32_t)0x00000008) /*!< I2S extended Overrun error */
+#define HAL_I2S_ERROR_FRE ((uint32_t)0x00000010) /*!< I2S Frame format error */
+#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000020) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Clock_Source I2S Clock Source
* @{
*/
#define I2S_CLOCK_PLL ((uint32_t)0x00000000)
#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)
-
-#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
- ((CLOCK) == I2S_CLOCK_PLL))
/**
* @}
*/
-/** @defgroup I2S_Mode
+/** @defgroup I2S_Mode I2S Mode
* @{
*/
#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)
#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)
#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200)
#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300)
-
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
- ((MODE) == I2S_MODE_SLAVE_RX) || \
- ((MODE) == I2S_MODE_MASTER_TX) || \
- ((MODE) == I2S_MODE_MASTER_RX))
/**
* @}
*/
-/** @defgroup I2S_Standard
+/** @defgroup I2S_Standard I2S Standard
* @{
*/
#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)
@@ -182,53 +187,31 @@ typedef struct
#define I2S_STANDARD_LSB ((uint32_t)0x00000020)
#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)
#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)
-
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
- ((STANDARD) == I2S_STANDARD_MSB) || \
- ((STANDARD) == I2S_STANDARD_LSB) || \
- ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
- ((STANDARD) == I2S_STANDARD_PCM_LONG))
-/** @defgroup I2S_Legacy
- * @{
- */
-#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
-/**
- * @}
- */
-
/**
* @}
*/
-/** @defgroup I2S_Data_Format
+/** @defgroup I2S_Data_Format I2S Data Format
* @{
*/
#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000)
#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001)
#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003)
#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005)
-
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
- ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
- ((FORMAT) == I2S_DATAFORMAT_24B) || \
- ((FORMAT) == I2S_DATAFORMAT_32B))
/**
* @}
*/
-/** @defgroup I2S_MCLK_Output
+/** @defgroup I2S_MCLK_Output I2S Mclk Output
* @{
*/
#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
-
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
- ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
/**
* @}
*/
-/** @defgroup I2S_Audio_Frequency
+/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
* @{
*/
#define I2S_AUDIOFREQ_192K ((uint32_t)192000)
@@ -241,27 +224,20 @@ typedef struct
#define I2S_AUDIOFREQ_11K ((uint32_t)11025)
#define I2S_AUDIOFREQ_8K ((uint32_t)8000)
#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
-
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
- ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
- ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
/**
* @}
*/
-
-/** @defgroup I2S_Clock_Polarity
+
+/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
* @{
*/
#define I2S_CPOL_LOW ((uint32_t)0x00000000)
#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
-
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
- ((CPOL) == I2S_CPOL_HIGH))
/**
* @}
*/
-/** @defgroup I2S_Interrupt_configuration_definition
+/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
* @{
*/
#define I2S_IT_TXE SPI_CR2_TXEIE
@@ -271,7 +247,7 @@ typedef struct
* @}
*/
-/** @defgroup I2S_Flag_definition
+/** @defgroup I2S_Flags_Definition I2S Flags Definition
* @{
*/
#define I2S_FLAG_TXE SPI_SR_TXE
@@ -287,8 +263,20 @@ typedef struct
* @}
*/
+/**
+ * @}
+ */
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2S_Exported_Macros I2S Exported Macros
+ * @{
+ */
+
+/** @brief Reset I2S handle state
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
/** @brief Enable or disable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__: specifies the I2S Handle.
@@ -340,25 +328,50 @@ typedef struct
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
*/
-#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
- (__HANDLE__)->Instance->SR;}while(0)
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ } while(0)
+
/** @brief Clears the I2S UDR pending flag.
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
*/
-#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
-
-
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ } while(0)
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_Exported_Functions
+ * @{
+ */
+/** @addtogroup I2S_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+/** @addtogroup I2S_Exported_Functions_Group2
+ * @{
+ */
/* I/O operation functions *****************************************************/
- /* Blocking mode: Polling */
+/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
@@ -377,7 +390,7 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
/* Peripheral Control and State functions **************************************/
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
-HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
@@ -385,22 +398,78 @@ void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
-void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
-void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
-void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-void I2S_DMAError(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2S_Private_Constants I2S Private Constants
+ * @{
+ */
/**
* @}
- */
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_Private_Macros I2S Private Macros
+ * @{
+ */
+#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
+ ((CLOCK) == I2S_CLOCK_PLL))
+
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
+ ((MODE) == I2S_MODE_SLAVE_RX) || \
+ ((MODE) == I2S_MODE_MASTER_TX) || \
+ ((MODE) == I2S_MODE_MASTER_RX))
+
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
+ ((STANDARD) == I2S_STANDARD_MSB) || \
+ ((STANDARD) == I2S_STANDARD_LSB) || \
+ ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
+ ((STANDARD) == I2S_STANDARD_PCM_LONG))
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
+ ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
+ ((FORMAT) == I2S_DATAFORMAT_24B) || \
+ ((FORMAT) == I2S_DATAFORMAT_32B))
+
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
+ ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
+ ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
+ ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
+
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
+ ((CPOL) == I2S_CPOL_HIGH))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup I2S_Private_Functions I2S Private Functions
+ * @{
+ */
/**
* @}
*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
diff --git a/f2/include/stm32f2xx_hal_irda.h b/f2/include/stm32f2xx_hal_irda.h
index 27b4efe96e5b035fbffd8ae48fdfd03993b86536..2276b2771086744862e5a82669e69e78e7871a35 100755
--- a/f2/include/stm32f2xx_hal_irda.h
+++ b/f2/include/stm32f2xx_hal_irda.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_irda.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,7 +55,9 @@
*/
/* Exported types ------------------------------------------------------------*/
-
+/** @defgroup IRDA_Exported_Types IRDA Exported Types
+ * @{
+ */
/**
* @brief IRDA Init Structure definition
*/
@@ -83,7 +85,7 @@ typedef struct
uint8_t Prescaler; /*!< Specifies the Prescaler */
uint32_t IrDAMode; /*!< Specifies the IrDA mode
- This parameter can be a value of @ref IrDA_Low_Power */
+ This parameter can be a value of @ref IRDA_Low_Power */
}IRDA_InitTypeDef;
/**
@@ -93,7 +95,7 @@ typedef enum
{
HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_IRDA_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
@@ -102,20 +104,7 @@ typedef enum
}HAL_IRDA_StateTypeDef;
/**
- * @brief HAL IRDA Error Code structure definition
- */
-typedef enum
-{
- HAL_IRDA_ERROR_NONE = 0x00, /*!< No error */
- HAL_IRDA_ERROR_PE = 0x01, /*!< Parity error */
- HAL_IRDA_ERROR_NE = 0x02, /*!< Noise error */
- HAL_IRDA_ERROR_FE = 0x04, /*!< frame error */
- HAL_IRDA_ERROR_ORE = 0x08, /*!< Overrun error */
- HAL_IRDA_ERROR_DMA = 0x10 /*!< DMA transfer error */
-}HAL_IRDA_ErrorTypeDef;
-
-/**
- * @brief IRDA handle Structure definition
+ * @brief IRDA handle Structure definition
*/
typedef struct
{
@@ -139,68 +128,74 @@ typedef struct
DMA_HandleTypeDef *hdmarx; /* IRDA Rx DMA Handle parameters */
- HAL_LockTypeDef Lock; /* Locking object */
-
- __IO HAL_IRDA_StateTypeDef State; /* IRDA communication state */
+ HAL_LockTypeDef Lock; /* Locking object */
- __IO HAL_IRDA_ErrorTypeDef ErrorCode; /* IRDA Error code */
+ __IO HAL_IRDA_StateTypeDef State; /* IRDA communication state */
+ __IO uint32_t ErrorCode; /* IRDA Error code */
+
}IRDA_HandleTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Constants
+/** @defgroup IRDA_Exported_Constants IRDA Exported constants
* @{
*/
+/** @defgroup IRDA_Error_Code IRDA Error Code
+ * @brief IRDA Error Code
+ * @{
+ */
+#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004) /*!< Frame error */
+#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+/**
+ * @}
+ */
-/** @defgroup IRDA_Word_Length
+/** @defgroup IRDA_Word_Length IRDA Word Length
* @{
*/
#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
- ((LENGTH) == IRDA_WORDLENGTH_9B))
/**
* @}
*/
-
-/** @defgroup IRDA_Parity
+/** @defgroup IRDA_Parity IRDA Parity
* @{
*/
#define IRDA_PARITY_NONE ((uint32_t)0x00000000)
#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
- ((PARITY) == IRDA_PARITY_EVEN) || \
- ((PARITY) == IRDA_PARITY_ODD))
/**
* @}
*/
-
-/** @defgroup IRDA_Mode
+/** @defgroup IRDA_Mode IRDA Transfer Mode
* @{
*/
#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-#define IS_IRDA_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
/**
* @}
*/
-/** @defgroup IrDA_Low_Power
+/** @defgroup IRDA_Low_Power IRDA Low Power
* @{
*/
#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000)
-#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
- ((MODE) == IRDA_POWERMODE_NORMAL))
/**
* @}
*/
-/** @defgroup IRDA_Flags
+/** @defgroup IRDA_Flags IRDA Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the SR register
* @{
@@ -217,37 +212,52 @@ typedef struct
* @}
*/
-/** @defgroup IRDA_Interrupt_definition
+/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
* Elements values convention: 0xY000XXXX
* - XXXX : Interrupt mask in the XX register
* - Y : Interrupt source register (2bits)
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
- *
* @{
*/
-
-#define IRDA_IT_PE ((uint32_t)0x10000100)
-#define IRDA_IT_TXE ((uint32_t)0x10000080)
-#define IRDA_IT_TC ((uint32_t)0x10000040)
-#define IRDA_IT_RXNE ((uint32_t)0x10000020)
-#define IRDA_IT_IDLE ((uint32_t)0x10000010)
-
-#define IRDA_IT_LBD ((uint32_t)0x20000040)
+#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
+#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
+#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
+#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
+#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
-#define IRDA_IT_CTS ((uint32_t)0x30000400)
-#define IRDA_IT_ERR ((uint32_t)0x30000001)
+#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
+#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
+#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28 | USART_CR3_EIE))
/**
* @}
*/
-
+
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
+ * @{
+ */
+
+/** @brief Reset IRDA handle state
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
+
+/** @brief Flushes the IRDA DR register
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ */
+#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
/** @brief Checks whether the specified IRDA flag is set or not.
* @param __HANDLE__: specifies the USART Handle.
@@ -287,8 +297,52 @@ typedef struct
*
* @retval None
*/
-#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+/** @brief Clear the IRDA PE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ } while(0)
+
+/** @brief Clear the IRDA FE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the IRDA NE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the IRDA ORE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the IRDA IDLE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
/** @brief Enables or disables the specified IRDA interrupt.
* @param __HANDLE__: specifies the USART Handle.
@@ -302,17 +356,14 @@ typedef struct
* @arg IRDA_IT_IDLE: Idle line detection interrupt
* @arg IRDA_IT_PE: Parity Error interrupt
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @param NewState: new state of the specified IRDA interrupt.
- * This parameter can be: ENABLE or DISABLE.
* @retval None
*/
-#define IRDA_IT_MASK ((uint32_t)0x0000FFFF)
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
- (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
- (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
/** @brief Checks whether the specified IRDA interrupt has occurred or not.
* @param __HANDLE__: specifies the USART Handle.
@@ -331,26 +382,58 @@ typedef struct
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
+/** @brief Macro to enable the IRDA's one bit sample method
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+/** @brief Macro to disable the IRDA's one bit sample method
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
-#define __IRDA_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-#define __IRDA_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
-#define __DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
-#define __DIVMANT(_PCLK_, _BAUD_) (__DIV((_PCLK_), (_BAUD_))/100)
-#define __DIVFRAQ(_PCLK_, _BAUD_) (((__DIV((_PCLK_), (_BAUD_)) - (__DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-#define __IRDA_BRR(_PCLK_, _BAUD_) ((__DIVMANT((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+/** @brief Enable UART/USART associated to IRDA Handle
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201)
-
+/** @brief Disable UART/USART associated to IRDA Handle
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup IRDA_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup IRDA_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
+/**
+ * @}
+ */
+/** @addtogroup IRDA_Exported_Functions_Group2
+ * @{
+ */
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -358,14 +441,84 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
+/**
+ * @}
+ */
+/** @addtogroup IRDA_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral State functions **************************************************/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IRDA_Private_Constants IRDA Private Constants
+ * @{
+ */
+
+/** @brief IRDA interruptions flag mask
+ *
+ */
+#define IRDA_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
+ USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
+
+#define IRDA_CR1_REG_INDEX 1
+#define IRDA_CR2_REG_INDEX 2
+#define IRDA_CR3_REG_INDEX 3
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup IRDA_Private_Macros IRDA Private Macros
+ * @{
+ */
+#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
+ ((LENGTH) == IRDA_WORDLENGTH_9B))
+#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
+ ((PARITY) == IRDA_PARITY_EVEN) || \
+ ((PARITY) == IRDA_PARITY_ODD))
+#define IS_IRDA_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
+#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
+ ((MODE) == IRDA_POWERMODE_NORMAL))
+#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201)
+
+#define IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
+#define IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100)
+#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define IRDA_BRR(_PCLK_, _BAUD_) ((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4)|(IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup IRDA_Private_Functions IRDA Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_iwdg.h b/f2/include/stm32f2xx_hal_iwdg.h
index 6c0d5ae052ae425207f69b498aaa6b6ee8723f45..40c15f90bebae768e7985e2996d9030696236ae3 100755
--- a/f2/include/stm32f2xx_hal_iwdg.h
+++ b/f2/include/stm32f2xx_hal_iwdg.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_iwdg.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,8 +54,11 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
-
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Types IWDG Exported Types
+ * @{
+ */
+
/**
* @brief IWDG HAL State Structure definition
*/
@@ -63,10 +66,9 @@ typedef enum
{
HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */
HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */
- HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
+ HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */
HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */
-
}HAL_IWDG_StateTypeDef;
/**
@@ -78,12 +80,11 @@ typedef struct
This parameter can be a value of @ref IWDG_Prescaler */
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
-
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
}IWDG_InitTypeDef;
/**
- * @brief IWDG handle Structure definition
+ * @brief IWDG Handle Structure definition
*/
typedef struct
{
@@ -91,72 +92,53 @@ typedef struct
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
- HAL_LockTypeDef Lock; /*!< IWDG locking object */
+ HAL_LockTypeDef Lock; /*!< IWDG Locking object */
__IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
-
}IWDG_HandleTypeDef;
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Constants
+/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
* @{
*/
-/** @defgroup IWDG_Registers_BitMask
+/** @defgroup IWDG_Registers_BitMask IWDG Registers BitMask
+ * @brief IWDG registers bit mask
* @{
*/
/* --- KR Register ---*/
/* KR register bit mask */
-#define KR_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG reload counter enable */
-#define KR_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG peripheral enable */
-#define KR_KEY_EWA ((uint32_t)0x5555) /*!< IWDG KR write Access enable */
-#define KR_KEY_DWA ((uint32_t)0x0000) /*!< IWDG KR write Access disable */
-
+#define IWDG_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG Reload Counter Enable */
+#define IWDG_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG Peripheral Enable */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x5555) /*!< IWDG KR Write Access Enable */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x0000) /*!< IWDG KR Write Access Disable */
/**
* @}
*/
-/** @defgroup IWDG_Flag_definition
+/** @defgroup IWDG_Flag_definition IWDG Flag definition
* @{
*/
-#define IWDG_FLAG_PVU ((uint32_t)0x0001) /*!< Watchdog counter prescaler value update flag */
-#define IWDG_FLAG_RVU ((uint32_t)0x0002) /*!< Watchdog counter reload value update flag */
-
-#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || \
- ((FLAG) == IWDG_FLAG_RVU))
-
+#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update Flag */
+#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update Flag */
/**
* @}
*/
-/** @defgroup IWDG_Prescaler
+/** @defgroup IWDG_Prescaler IWDG Prescaler
* @{
*/
#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */
-#define IWDG_PRESCALER_8 ((uint8_t)0x01) /*!< IWDG prescaler set to 8 */
-#define IWDG_PRESCALER_16 ((uint8_t)0x02) /*!< IWDG prescaler set to 16 */
-#define IWDG_PRESCALER_32 ((uint8_t)0x03) /*!< IWDG prescaler set to 32 */
-#define IWDG_PRESCALER_64 ((uint8_t)0x04) /*!< IWDG prescaler set to 64 */
-#define IWDG_PRESCALER_128 ((uint8_t)0x05) /*!< IWDG prescaler set to 128 */
-#define IWDG_PRESCALER_256 ((uint8_t)0x06) /*!< IWDG prescaler set to 256 */
-
-#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_PRESCALER_4) || \
- ((PRESCALER) == IWDG_PRESCALER_8) || \
- ((PRESCALER) == IWDG_PRESCALER_16) || \
- ((PRESCALER) == IWDG_PRESCALER_32) || \
- ((PRESCALER) == IWDG_PRESCALER_64) || \
- ((PRESCALER) == IWDG_PRESCALER_128)|| \
- ((PRESCALER) == IWDG_PRESCALER_256))
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Reload_Value
- * @{
- */
-#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
-
+#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */
+#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */
+#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */
+#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */
+#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */
/**
* @}
*/
@@ -165,36 +147,31 @@ typedef struct
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
-
-/**
- * @brief Enables the IWDG peripheral.
- * @param __HANDLE__: IWDG handle
- * @retval None
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
+ * @{
*/
-#define __HAL_IWDG_START(__HANDLE__) ((__HANDLE__)->Instance->KR |= KR_KEY_ENABLE)
-/**
- * @brief Reloads IWDG counter with value defined in the reload register
- * (write access to IWDG_PR and IWDG_RLR registers disabled).
- * @param __HANDLE__: IWDG handle
+/** @brief Reset IWDG handle state
+ * @param __HANDLE__: IWDG handle.
* @retval None
*/
-#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) (((__HANDLE__)->Instance->KR) |= KR_KEY_RELOAD)
+#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
/**
- * @brief Enables write access to IWDG_PR and IWDG_RLR registers.
+ * @brief Enables the IWDG peripheral.
* @param __HANDLE__: IWDG handle
* @retval None
*/
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) (((__HANDLE__)->Instance->KR) |= KR_KEY_EWA)
+#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
/**
- * @brief Disables write access to IWDG_PR and IWDG_RLR registers.
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).
* @param __HANDLE__: IWDG handle
* @retval None
*/
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) (((__HANDLE__)->Instance->KR) |= KR_KEY_DWA)
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
/**
* @brief Gets the selected IWDG's flag status.
@@ -208,30 +185,92 @@ typedef struct
#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/**
- * @brief Clears the IWDG's pending flags.
- * @param __HANDLE__: IWDG handle
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
- * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
- * @retval None
- */
-#define __HAL_IWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
-
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup IWDG_Exported_Functions
+ * @{
+ */
+/** @addtogroup IWDG_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+/** @addtogroup IWDG_Exported_Functions_Group2
+ * @{
+ */
/* I/O operation functions ****************************************************/
HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+/** @addtogroup IWDG_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral State functions ************************************************/
HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Macros IWDG Private Macros
+ * @{
+ */
+
+/**
+ * @brief Enables write access to IWDG_PR and IWDG_RLR registers.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+
+/**
+ * @brief Disables write access to IWDG_PR and IWDG_RLR registers.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
+
+
+#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_8) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_32) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_64) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
+ ((__PRESCALER__) == IWDG_PRESCALER_256))
+
+
+#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/* Private define ------------------------------------------------------------*/
+ /** @defgroup IWDG_Private_Constants IWDG Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/**
* @}
*/
diff --git a/f2/include/stm32f2xx_hal_nand.h b/f2/include/stm32f2xx_hal_nand.h
index 816545718b28a154b0e8af0704f4b9e063d9bc42..b04b1aa3daa768ee7a6a2f0352ed31f9278904a0 100755
--- a/f2/include/stm32f2xx_hal_nand.h
+++ b/f2/include/stm32f2xx_hal_nand.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_nand.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F2xx_HAL_NAND_H
@@ -43,7 +43,9 @@
extern "C" {
#endif
-#include "stm32f2xx_ll_fsmc.h"
+/* Includes ------------------------------------------------------------------*/
+ #include "stm32f2xx_ll_fsmc.h"
+
/** @addtogroup STM32F2xx_HAL_Driver
* @{
@@ -53,90 +55,176 @@
* @{
*/
-/* Exported typedef ----------------------------------------------------------*/
+/* Exported typedef ----------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Types NAND Exported Types
+ * @{
+ */
/**
- * @brief HAL NAND State structures definition
- */
+ * @brief HAL NAND State structures definition
+ */
typedef enum
{
HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
-
}HAL_NAND_StateTypeDef;
/**
- * @brief NAND Memory electronic signature Structure definition
+ * @brief NAND Memory electronic signature Structure definition
*/
typedef struct
{
- /*<! NAND memory electronic signature maker and device IDs */
-
+ /*<! NAND memory electronic signature maker and device IDs */
+
uint8_t Maker_Id;
-
+
uint8_t Device_Id;
-
+
uint8_t Third_Id;
-
+
uint8_t Fourth_Id;
-
}NAND_IDTypeDef;
/**
- * @brief NAND Memory address Structure definition
+ * @brief NAND Memory address Structure definition
*/
typedef struct
{
- uint16_t Page; /*!< NAND memory Page address */
-
- uint16_t Zone; /*!< NAND memory Zone address */
-
+ uint16_t Page; /*!< NAND memory Page address */
+
+ uint16_t Zone; /*!< NAND memory Zone address */
+
uint16_t Block; /*!< NAND memory Block address */
-
-}NAND_AddressTypedef;
+
+}NAND_AddressTypeDef;
/**
- * @brief NAND Memory info Structure definition
+ * @brief NAND Memory info Structure definition
*/
typedef struct
{
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
-
- uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
-
- uint32_t BlockSize; /*!< NAND memory block size number of pages */
-
+
+ uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
+
+ uint32_t BlockSize; /*!< NAND memory block size number of pages */
+
uint32_t BlockNbr; /*!< NAND memory number of blocks */
-
+
uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
-
}NAND_InfoTypeDef;
/**
- * @brief NAND handle Structure definition
+ * @brief NAND handle Structure definition
*/
typedef struct
{
- FMC_NAND_TypeDef *Instance; /*!< Register base address */
+ FSMC_NAND_TypeDef *Instance; /*!< Register base address */
- FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
+ FSMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
- HAL_LockTypeDef Lock; /*!< NAND locking object */
+ HAL_LockTypeDef Lock; /*!< NAND locking object */
- __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
-
- NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
-
-}NAND_HandleTypeDef;
+ __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
+ NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
+}NAND_HandleTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup NAND_Exported_Constants
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Macros NAND Exported Macros
* @{
*/
+
+/** @brief Reset NAND handle state
+ * @param __HANDLE__: specifies the NAND handle.
+ * @retval None
+ */
+#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NAND_Exported_Functions NAND Exported Functions
+ * @{
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
+void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
+ * @{
+ */
+
+/* IO operation functions ****************************************************/
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* NAND Control functions ****************************************************/
+HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+/* NAND State functions *******************************************************/
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup NAND_Private_Constants NAND Private Constants
+ * @{
+ */
#define NAND_DEVICE1 ((uint32_t)0x70000000)
#define NAND_DEVICE2 ((uint32_t)0x80000000)
#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000)
@@ -144,9 +232,19 @@ typedef struct
#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
-#define NAND_CMD_AREA_A ((uint8_t)0x00)
-#define NAND_CMD_AREA_B ((uint8_t)0x01)
+#define NAND_CMD_AREA_A ((uint8_t)0x00)
+#define NAND_CMD_AREA_B ((uint8_t)0x01)
#define NAND_CMD_AREA_C ((uint8_t)0x50)
+#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
+
+#define NAND_CMD_WRITE0 ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
+#define NAND_CMD_ERASE0 ((uint8_t)0x60)
+#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
+#define NAND_CMD_READID ((uint8_t)0x90)
+#define NAND_CMD_STATUS ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
+#define NAND_CMD_RESET ((uint8_t)0xFF)
/* NAND memory status */
#define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
@@ -155,60 +253,41 @@ typedef struct
#define NAND_BUSY ((uint32_t)0x00000000)
#define NAND_ERROR ((uint32_t)0x00000001)
#define NAND_READY ((uint32_t)0x00000040)
-
/**
* @}
*/
-
-/* Exported macro ------------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup NAND_Private_Macros NAND Private Macros
+ * @{
+ */
+
/**
* @brief NAND memory address computation.
- * @param __ADDRESS__: NAND memory address.
+ * @param __ADDRESS__: NAND memory address.
* @param __HANDLE__ : NAND handle.
* @retval NAND Raw address value
*/
-#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.BlockSize)))* ((__HANDLE__)->Info.ZoneSize)))
+#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
+ (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
/**
* @brief NAND memory address cycling.
- * @param __ADDRESS__: NAND memory address.
+ * @param __ADDRESS__: NAND memory address.
* @retval NAND address cycling value.
*/
-#define ADDR_1st_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__)& 0xFF) /* 1st addressing cycle */
-#define ADDR_2nd_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF00) >> 8) /* 2nd addressing cycle */
-#define ADDR_3rd_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF0000) >> 16) /* 3rd addressing cycle */
-#define ADDR_4th_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF000000) >> 24) /* 4th addressing cycle */
-
-/* Exported functions --------------------------------------------------------*/
-
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
-HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
-void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
-void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
-void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
-void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
-HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
-
-/* NAND Control functions ******************************************************/
-HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
-
-/* NAND State functions *********************************************************/
-HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
+#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
+#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
+#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/**
* @}
*/
diff --git a/f2/include/stm32f2xx_hal_nor.h b/f2/include/stm32f2xx_hal_nor.h
index e4518ff806a5c69b6fca46df6c4b6388e0d380c2..d6a4d31238dcc03f379f15c63c0f7ea25a30f143 100755
--- a/f2/include/stm32f2xx_hal_nor.h
+++ b/f2/include/stm32f2xx_hal_nor.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_nor.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -44,7 +44,8 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_ll_fsmc.h"
+ #include "stm32f2xx_ll_fsmc.h"
+
/** @addtogroup STM32F2xx_HAL_Driver
* @{
@@ -54,7 +55,11 @@
* @{
*/
-/* Exported typedef ----------------------------------------------------------*/
+/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup NOR_Exported_Types NOR Exported Types
+ * @{
+ */
+
/**
* @brief HAL SRAM State structures definition
*/
@@ -63,80 +68,155 @@ typedef enum
HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */
HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */
HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */
- HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */
- HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
-
-}HAL_NOR_StateTypeDef;
+ HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */
+ HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
+}HAL_NOR_StateTypeDef;
/**
- * @brief FMC NOR Status typedef
+ * @brief FSMC NOR Status typedef
*/
typedef enum
{
- NOR_SUCCESS = 0,
- NOR_ONGOING,
- NOR_ERROR,
- NOR_TIMEOUT
-
-}NOR_StatusTypedef;
+ HAL_NOR_STATUS_SUCCESS = 0,
+ HAL_NOR_STATUS_ONGOING,
+ HAL_NOR_STATUS_ERROR,
+ HAL_NOR_STATUS_TIMEOUT
+}HAL_NOR_StatusTypeDef;
/**
- * @brief FMC NOR ID typedef
+ * @brief FSMC NOR ID typedef
*/
typedef struct
{
uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
-
- uint16_t Device_Code1;
-
- uint16_t Device_Code2;
-
+
+ uint16_t Device_Code1;
+
+ uint16_t Device_Code2;
+
uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
These codes can be accessed by performing read operations with specific
control signals and addresses set.They can also be accessed by issuing
- an Auto Select command */
-
+ an Auto Select command */
}NOR_IDTypeDef;
-
/**
- * @brief FMC NOR CFI typedef
+ * @brief FSMC NOR CFI typedef
*/
typedef struct
{
/*!< Defines the information stored in the memory's Common flash interface
which contains a description of various electrical and timing parameters,
density information and functions supported by the memory */
-
- uint16_t CFI_1;
-
- uint16_t CFI_2;
-
- uint16_t CFI_3;
-
- uint16_t CFI_4;
-
+
+ uint16_t CFI_1;
+
+ uint16_t CFI_2;
+
+ uint16_t CFI_3;
+
+ uint16_t CFI_4;
}NOR_CFITypeDef;
/**
- * @brief NOR handle Structure definition
+ * @brief NOR handle Structure definition
*/
typedef struct
{
- FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
-
- FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
-
- FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
+ FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
+
+ FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
+
+ FSMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< NOR locking object */
- HAL_LockTypeDef Lock; /*!< NOR locking object */
-
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
-
-}NOR_HandleTypeDef;
+}NOR_HandleTypeDef;
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup NOR_Exported_Constants
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup NOR_Exported_Macros NOR Exported Macros
+ * @{
+ */
+/** @brief Reset NOR handle state
+ * @param __HANDLE__: specifies the NOR handle.
+ * @retval None
+ */
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NOR_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group3
+ * @{
+ */
+/* NOR Control functions *****************************************************/
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group4
+ * @{
+ */
+/* NOR State functions ********************************************************/
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup NOR_Private_Constants NOR Private Constants
* @{
*/
/* NOR device IDs addresses */
@@ -154,65 +234,44 @@ typedef struct
/* NOR operation wait timeout */
#define NOR_TMEOUT ((uint16_t)0xFFFF)
-/* #define NOR_MEMORY_16B */
-#define NOR_MEMORY_8B
+/* NOR memory data width */
+#define NOR_MEMORY_8B ((uint8_t)0x0)
+#define NOR_MEMORY_16B ((uint8_t)0x1)
/* NOR memory device read/write start address */
-#define NOR_MEMORY_ADRESS ((uint32_t)0x60000000)
-
+#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000)
+#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000)
+#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000)
+#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000)
/**
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup NOR_Private_Macros NOR Private Macros
+ * @{
+ */
/**
* @brief NOR memory address shifting.
- * @param __ADDRESS__: NOR memory address
+ * @param __NOR_ADDRESS__: NOR base address
+ * @param NOR_MEMORY_WIDTH: NOR memory width
+ * @param ADDRESS: NOR memory address
* @retval NOR shifted address value
*/
-#ifdef NOR_MEMORY_8B
- #define __NOR_ADDR_SHIFT(__ADDRESS__) (uint32_t)(NOR_MEMORY_ADRESS + (2 * (__ADDRESS__)))
-#else /* NOR_MEMORY_16B */
- #define __NOR_ADDR_SHIFT(__ADDRESS__) (uint32_t)(NOR_MEMORY_ADRESS + (__ADDRESS__))
-#endif /* NOR_MEMORY_8B */
+#define NOR_ADDR_SHIFT(__NOR_ADDRESS__, NOR_MEMORY_WIDTH, ADDRESS) (uint32_t)(((NOR_MEMORY_WIDTH) == NOR_MEMORY_8B)? ((uint32_t)((__NOR_ADDRESS__) + (2 * (ADDRESS)))):\
+ ((uint32_t)((__NOR_ADDRESS__) + (ADDRESS))))
/**
* @brief NOR memory write data to specified address.
- * @param __ADDRESS__: NOR memory address
- * @param __DATA__: Data to write
+ * @param ADDRESS: NOR memory address
+ * @param DATA: Data to write
* @retval None
*/
-#define __NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
-
-/* Exported functions --------------------------------------------------------*/
-
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
-HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
-
-/* I/O operation functions *****************************************************/
-HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
-HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
-HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+#define NOR_WRITE(ADDRESS, DATA) (*(__IO uint16_t *)((uint32_t)(ADDRESS)) = (DATA))
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
-
-HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
-HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
-HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
-
-/* NOR Control functions *******************************************************/
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
-
-/* NOR State functions **********************************************************/
-HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
-NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
+/**
+ * @}
+ */
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_pccard.h b/f2/include/stm32f2xx_hal_pccard.h
index 8f4bc7babe43a87fa6c37de7bb64514315641166..5a15936618482f336b0e5345a763d2a784bce566 100755
--- a/f2/include/stm32f2xx_hal_pccard.h
+++ b/f2/include/stm32f2xx_hal_pccard.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_pccard.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of PCCARD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,20 +43,25 @@
extern "C" {
#endif
+/* Includes ------------------------------------------------------------------*/
#include "stm32f2xx_ll_fsmc.h"
/** @addtogroup STM32F2xx_HAL_Driver
* @{
*/
+
/** @addtogroup PCCARD
* @{
*/
/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup PCCARD_Exported_Types PCCARD Exported Types
+ * @{
+ */
/**
- * @brief HAL SRAM State structures definition
+ * @brief HAL PCCARD State structures definition
*/
typedef enum
{
@@ -65,95 +70,179 @@ typedef enum
HAL_PCCARD_STATE_BUSY = 0x02, /*!< PCCARD peripheral busy */
HAL_PCCARD_STATE_ERROR = 0x04 /*!< PCCARD peripheral error */
}HAL_PCCARD_StateTypeDef;
-
+
typedef enum
{
- CF_SUCCESS = 0,
- CF_ONGOING,
- CF_ERROR,
- CF_TIMEOUT
-}CF_StatusTypedef;
+ HAL_PCCARD_STATUS_SUCCESS = 0,
+ HAL_PCCARD_STATUS_ONGOING,
+ HAL_PCCARD_STATUS_ERROR,
+ HAL_PCCARD_STATUS_TIMEOUT
+}HAL_PCCARD_StatusTypeDef;
/**
- * @brief FMC_PCCARD handle Structure definition
+ * @brief FSMC_PCCARD handle Structure definition
*/
typedef struct
{
- FMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
+ FSMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
- FMC_PCCARD_InitTypeDef Init; /*!< PCCARD device control configuration parameters */
+ FSMC_PCCARD_InitTypeDef Init; /*!< PCCARD device control configuration parameters */
__IO HAL_PCCARD_StateTypeDef State; /*!< PCCARD device access state */
HAL_LockTypeDef Lock; /*!< PCCARD Lock */
}PCCARD_HandleTypeDef;
-
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup PCCARD_Exported_Constants
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
* @{
*/
-
-#define CF_DEVICE_ADDRESS ((uint32_t)0x90000000)
-#define CF_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)0x98000000) /* Attribute space size to @0x9BFF FFFF */
-#define CF_COMMON_SPACE_ADDRESS CF_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
-#define CF_IO_SPACE_ADDRESS ((uint32_t)0x9C000000) /* IO space size to @0x9FFF FFFF */
-#define CF_IO_SPACE_PRIMARY_ADDR ((uint32_t)0x9C0001F0) /* IO space size to @0x9FFF FFFF */
-
-/* Compact Flash-ATA registers description */
-#define CF_DATA ((uint8_t)0x00) /* Data register */
-#define CF_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */
-#define CF_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */
-#define CF_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */
-#define CF_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */
-#define CF_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */
-#define CF_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */
-#define CF_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */
-#define CF_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
-
-/* Compact Flash-ATA commands */
-#define CF_READ_SECTOR_CMD ((uint8_t)0x20)
-#define CF_WRITE_SECTOR_CMD ((uint8_t)0x30)
-#define CF_ERASE_SECTOR_CMD ((uint8_t)0xC0)
-#define CF_IDENTIFY_CMD ((uint8_t)0xEC)
-
-/* Compact Flash status */
-#define CF_TIMEOUT_ERROR ((uint8_t)0x60)
-#define CF_BUSY ((uint8_t)0x80)
-#define CF_PROGR ((uint8_t)0x01)
-#define CF_READY ((uint8_t)0x40)
-
-#define CF_SECTOR_SIZE ((uint32_t)255) /* In half words */
-
+/** @brief Reset PCCARD handle state
+ * @param __HANDLE__: specifies the PCCARD handle.
+ * @retval None
+ */
+#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCCARD_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup PCCARD_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
-HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
+HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
+HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
+/**
+ * @}
+ */
+/** @addtogroup PCCARD_Exported_Functions_Group2
+ * @{
+ */
/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_CF_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
-HAL_StatusTypeDef HAL_CF_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
-HAL_StatusTypeDef HAL_CF_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
-HAL_StatusTypeDef HAL_CF_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
-HAL_StatusTypeDef HAL_CF_Reset(PCCARD_HandleTypeDef *hpccard);
+HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
-void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
+
+/**
+ * @}
+ */
+/** @addtogroup PCCARD_Exported_Functions_Group3
+ * @{
+ */
/* PCCARD State functions *******************************************************/
-HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
-CF_StatusTypedef HAL_CF_GetStatus(PCCARD_HandleTypeDef *hpccard);
-CF_StatusTypedef HAL_CF_ReadStatus(PCCARD_HandleTypeDef *hpccard);
+HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard);
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
+/**
+ * @}
+ */
/**
* @}
- */
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PCCARD_Private_Constants PCCARD Private Constants
+ * @{
+ */
+#define PCCARD_DEVICE_ADDRESS ((uint32_t)0x90000000)
+#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)0x98000000) /* Attribute space size to @0x9BFF FFFF */
+#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
+#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)0x9C000000) /* IO space size to @0x9FFF FFFF */
+#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)0x9C0001F0) /* IO space size to @0x9FFF FFFF */
+
+/* Flash-ATA registers description */
+#define ATA_DATA ((uint8_t)0x00) /* Data register */
+#define ATA_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */
+#define ATA_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */
+#define ATA_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */
+#define ATA_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */
+#define ATA_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */
+#define ATA_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */
+#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */
+#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
+#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202) /* Card Configuration and Status Register */
+
+/* Flash-ATA commands */
+#define ATA_READ_SECTOR_CMD ((uint8_t)0x20)
+#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30)
+#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0)
+#define ATA_IDENTIFY_CMD ((uint8_t)0xEC)
+
+/* PC Card/Compact Flash status */
+#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60)
+#define PCCARD_BUSY ((uint8_t)0x80)
+#define PCCARD_PROGR ((uint8_t)0x01)
+#define PCCARD_READY ((uint8_t)0x40)
+
+#define PCCARD_SECTOR_SIZE ((uint32_t)255) /* In half words */
+
+/**
+ * @}
+ */
+/* Compact Flash redefinition */
+#define HAL_CF_Init HAL_PCCARD_Init
+#define HAL_CF_DeInit HAL_PCCARD_DeInit
+#define HAL_CF_MspInit HAL_PCCARD_MspInit
+#define HAL_CF_MspDeInit HAL_PCCARD_MspDeInit
+
+#define HAL_CF_Read_ID HAL_PCCARD_Read_ID
+#define HAL_CF_Write_Sector HAL_PCCARD_Write_Sector
+#define HAL_CF_Read_Sector HAL_PCCARD_Read_Sector
+#define HAL_CF_Erase_Sector HAL_PCCARD_Erase_Sector
+#define HAL_CF_Reset HAL_PCCARD_Reset
+#define HAL_CF_IRQHandler HAL_PCCARD_IRQHandler
+#define HAL_CF_ITCallback HAL_PCCARD_ITCallback
+
+#define HAL_CF_GetState HAL_PCCARD_GetState
+#define HAL_CF_GetStatus HAL_PCCARD_GetStatus
+#define HAL_CF_ReadStatus HAL_PCCARD_ReadStatus
+
+#define HAL_CF_STATUS_SUCCESS HAL_PCCARD_STATUS_SUCCESS
+#define HAL_CF_STATUS_ONGOING HAL_PCCARD_STATUS_ONGOING
+#define HAL_CF_STATUS_ERROR HAL_PCCARD_STATUS_ERROR
+#define HAL_CF_STATUS_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
+#define HAL_CF_StatusTypeDef HAL_PCCARD_StatusTypeDef
+
+
+#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS
+#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS
+#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS
+#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS
+#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR
+
+#define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR
+#define CF_BUSY PCCARD_BUSY
+#define CF_PROGR PCCARD_PROGR
+#define CF_READY PCCARD_READY
+
+#define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE
+
+/* Private macros ------------------------------------------------------------*/
+/**
+ * @}
+ */
+
+
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_pcd.h b/f2/include/stm32f2xx_hal_pcd.h
index d0af8fa94b293a81fee2d415e2d9b295d1336e13..ba337f076348ba2aa234b8ce72da9386a3e7a764 100755
--- a/f2/include/stm32f2xx_hal_pcd.h
+++ b/f2/include/stm32f2xx_hal_pcd.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_pcd.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,45 +55,54 @@
*/
/* Exported types ------------------------------------------------------------*/
-
- /**
- * @brief PCD State structures definition
- */
+/** @defgroup PCD_Exported_Types PCD Exported Types
+ * @{
+ */
+
+/**
+ * @brief PCD State structure definition
+ */
typedef enum
{
- PCD_READY = 0x00,
- PCD_ERROR = 0x01,
- PCD_BUSY = 0x02,
- PCD_TIMEOUT = 0x03
+ HAL_PCD_STATE_RESET = 0x00,
+ HAL_PCD_STATE_READY = 0x01,
+ HAL_PCD_STATE_ERROR = 0x02,
+ HAL_PCD_STATE_BUSY = 0x03,
+ HAL_PCD_STATE_TIMEOUT = 0x04
} PCD_StateTypeDef;
-
typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
-typedef USB_OTG_EPTypeDef PCD_EPTypeDef ;
+typedef USB_OTG_EPTypeDef PCD_EPTypeDef ;
/**
* @brief PCD Handle Structure definition
*/
typedef struct
{
- PCD_TypeDef *Instance; /*!< Register base address */
- PCD_InitTypeDef Init; /*!< PCD required parameters */
- PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
- HAL_LockTypeDef Lock; /*!< PCD peripheral status */
- __IO PCD_StateTypeDef State; /*!< PCD communication state */
- uint32_t Setup[12]; /*!< Setup packet buffer */
- void *pData; /*!< Pointer to upper stack Handler */
-
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+ void *pData; /*!< Pointer to upper stack Handler */
} PCD_HandleTypeDef;
-
+
+/**
+ * @}
+ */
+
+/* Include PCD HAL Extension module */
+#include "stm32f2xx_hal_pcd_ex.h"
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Constants
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
-/** @defgroup PCD_Speed
+/** @defgroup PCD_Speed PCD Speed
* @{
*/
#define PCD_SPEED_HIGH 0
@@ -103,7 +112,7 @@ typedef struct
* @}
*/
- /** @defgroup PCD_PHY_Module
+/** @defgroup PCD_PHY_Module PCD PHY Module
* @{
*/
#define PCD_PHY_ULPI 1
@@ -111,107 +120,118 @@ typedef struct
/**
* @}
*/
-
-/** @defgroup PCD_Instance_definition
+
+/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
* @{
- */
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
- ((INSTANCE) == USB_OTG_HS))
+ */
+#ifndef USBD_HS_TRDT_VALUE
+ #define USBD_HS_TRDT_VALUE 9
+#endif /* USBD_HS_TRDT_VALUE */
+#ifndef USBD_FS_TRDT_VALUE
+ #define USBD_FS_TRDT_VALUE 5
+#endif /* USBD_FS_TRDT_VALUE */
/**
* @}
*/
/**
* @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
+ */
-/** @defgroup PCD_Interrupt_Clock
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PCD_Exported_Macros PCD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) |= (__INTERRUPT__))
-#define __HAL_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
+#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
- ~(USB_OTG_PCGCCTL_STOPCLK)
-
+ ~(USB_OTG_PCGCCTL_STOPCLK)
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
-#define USB_FS_EXTI_TRIGGER_RISING_EDGE ((uint32_t)0x08)
-#define USB_FS_EXTI_TRIGGER_FALLING_EDGE ((uint32_t)0x0C)
-#define USB_FS_EXTI_TRIGGER_BOTH_EDGE ((uint32_t)0x10)
-
-#define USB_HS_EXTI_TRIGGER_RISING_EDGE ((uint32_t)0x08)
-#define USB_HS_EXTI_TRIGGER_FALLING_EDGE ((uint32_t)0x0C)
-#define USB_HS_EXTI_TRIGGER_BOTH_EDGE ((uint32_t)0x10)
-
-
-#define USB_HS_EXTI_LINE_WAKEUP ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
-#define USB_FS_EXTI_LINE_WAKEUP ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
+#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
+#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
+#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
+#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
+#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
+#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
-#define __HAL_USB_HS_EXTI_ENABLE_IT() EXTI->IMR |= (USB_HS_EXTI_LINE_WAKEUP)
-#define __HAL_USB_HS_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_HS_EXTI_LINE_WAKEUP)
-#define __HAL_USB_HS_EXTI_GET_FLAG() EXTI->PR & (USB_HS_EXTI_LINE_WAKEUP)
-#define __HAL_USB_HS_EXTI_CLEAR_FLAG() EXTI->PR = (USB_HS_EXTI_LINE_WAKEUP)
-
-#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER() EXTI->FTSR &= ~(USB_HS_EXTI_LINE_WAKEUP);\
- EXTI->RTSR |= USB_HS_EXTI_LINE_WAKEUP
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE
-#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (USB_HS_EXTI_LINE_WAKEUP);\
- EXTI->RTSR &= ~(USB_HS_EXTI_LINE_WAKEUP)
-
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(USB_HS_EXTI_LINE_WAKEUP);\
- EXTI->FTSR &= ~(USB_HS_EXTI_LINE_WAKEUP;)\
- EXTI->RTSR |= USB_HS_EXTI_LINE_WAKEUP;\
- EXTI->FTSR |= USB_HS_EXTI_LINE_WAKEUP
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
+ EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE;)\
+ EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
+ EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_FS_EXTI_ENABLE_IT() EXTI->IMR |= USB_FS_EXTI_LINE_WAKEUP
-#define __HAL_USB_FS_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_FS_EXTI_LINE_WAKEUP)
-#define __HAL_USB_FS_EXTI_GET_FLAG() EXTI->PR & (USB_FS_EXTI_LINE_WAKEUP)
-#define __HAL_USB_FS_EXTI_CLEAR_FLAG() EXTI->PR = USB_FS_EXTI_LINE_WAKEUP
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
-#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER() EXTI->FTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\
- EXTI->RTSR |= USB_FS_EXTI_LINE_WAKEUP
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
-#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (USB_FS_EXTI_LINE_WAKEUP);\
- EXTI->RTSR &= ~(USB_FS_EXTI_LINE_WAKEUP)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
+ EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
-#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\
- EXTI->FTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\
- EXTI->RTSR |= USB_FS_EXTI_LINE_WAKEUP;\
- EXTI->FTSR |= USB_FS_EXTI_LINE_WAKEUP
-
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCD_Exported_Functions PCD Exported Functions
+ * @{
+ */
-/* Initialization/de-initialization functions **********************************/
+/* Initialization/de-initialization functions ********************************/
+/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
-/* I/O operation functions *****************************************************/
- /* Non-Blocking mode: Interrupt */
+/* I/O operation functions ***************************************************/
+/* Non-Blocking mode: Interrupt */
+/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
@@ -227,10 +247,14 @@ void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
-
-
-/* Peripheral Control functions ************************************************/
+/* Peripheral Control functions **********************************************/
+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
@@ -242,12 +266,40 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
-HAL_StatusTypeDef HAL_PCD_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
-HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
-/* Peripheral State functions **************************************************/
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/* Peripheral State functions ************************************************/
+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
+/** @defgroup PCD_Instance_definition PCD Instance definition
+ * @{
+ */
+ #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+/**
+ * @}
+ */
+/**
+ * @}
+ */
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_pwr.h b/f2/include/stm32f2xx_hal_pwr.h
index 8063fb26080f52e447ad8143020a2c46adc9c009..140ee94fec0bcf7545905022cf68c11a8bbd7d2b 100755
--- a/f2/include/stm32f2xx_hal_pwr.h
+++ b/f2/include/stm32f2xx_hal_pwr.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_pwr.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,65 +55,41 @@
*/
/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+ * @{
+ */
+
/**
* @brief PWR PVD configuration structure definition
*/
typedef struct
{
- uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level
+ uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
This parameter can be a value of @ref PWR_PVD_detection_level */
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWR_PVD_Mode */
}PWR_PVDTypeDef;
-/* Exported constants --------------------------------------------------------*/
-/* ------------- PWR registers bit address in the alias region ---------------*/
-#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
-
-/* --- CR Register ---*/
-/* Alias word address of DBP bit */
-#define CR_OFFSET (PWR_OFFSET + 0x00)
-#define DBP_BitNumber 0x08
-#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
-
-/* Alias word address of PVDE bit */
-#define PVDE_BitNumber 0x04
-#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
-
-/* Alias word address of FPDS bit */
-#define FPDS_BitNumber 0x09
-#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
-
-/* Alias word address of PMODE bit */
-#define PMODE_BitNumber 0x0E
-#define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
-
-/* --- CSR Register ---*/
-/* Alias word address of EWUP bit */
-#define CSR_OFFSET (PWR_OFFSET + 0x04)
-#define EWUP_BitNumber 0x08
-#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
+/**
+ * @}
+ */
-/* Alias word address of BRE bit */
-#define BRE_BitNumber 0x09
-#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
-
-/** @defgroup PWR_Exported_Constants
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
* @{
*/
-
-/** @defgroup PWR_WakeUp_Pins
+
+/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
* @{
*/
-
-#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
-#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
+#define PWR_WAKEUP_PIN1 ((uint32_t)0x00000100)
/**
* @}
*/
-/** @defgroup PWR_PVD_detection_level
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level
* @{
*/
#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
@@ -123,68 +99,61 @@ typedef struct
#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
-#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
- ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
- ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
- ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage
+ (Compare internally to VREFINT) */
/**
* @}
*/
-/** @defgroup PWR_PVD_Mode
+/** @defgroup PWR_PVD_Mode PWR PVD Mode
* @{
*/
-#define PWR_MODE_EVT ((uint32_t)0x00000000) /*!< No Interrupt */
-#define PWR_MODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_MODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_MODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_MODE_EVT) || ((MODE) == PWR_MODE_IT_RISING)|| \
- ((MODE) == PWR_MODE_IT_FALLING) || ((MODE) == PWR_MODE_IT_RISING_FALLING))
+#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
+#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
- */
+ */
+
-/** @defgroup PWR_Regulator_state_in_STOP_mode
+/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
* @{
*/
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
-
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
- ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
/**
* @}
*/
-/** @defgroup PWR_SLEEP_mode_entry
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{
*/
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
/**
* @}
*/
-/** @defgroup PWR_STOP_mode_entry
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
* @{
*/
#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
/**
* @}
*/
-/** @defgroup PWR_Flag
+/** @defgroup PWR_Flag PWR Flag
* @{
*/
#define PWR_FLAG_WU PWR_CSR_WUF
#define PWR_FLAG_SB PWR_CSR_SBF
#define PWR_FLAG_PVDO PWR_CSR_PVDO
#define PWR_FLAG_BRR PWR_CSR_BRR
-
/**
* @}
*/
@@ -194,10 +163,10 @@ typedef struct
*/
/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_Exported_Macro
+/** @defgroup PWR_Exported_Macro PWR Exported Macro
* @{
*/
-
+
/** @brief Check PWR flag is set or not.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
@@ -227,71 +196,230 @@ typedef struct
*/
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2)
-#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
/**
- * @brief Enable the PVD Exti Line.
- * @param __EXTILINE__: specifies the PVD Exti sources to be enabled.
- * This parameter can be:
- * @arg PWR_EXTI_LINE_PVD
+ * @brief Enable the PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Disable the PVD EXTI Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Enable event on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Disable event on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Enable the PVD Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Enable the PVD Extended Interrupt Falling Trigger.
* @retval None.
*/
-#define __HAL_PVD_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__))
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
/**
- * @brief Disable the PVD EXTI Line.
- * @param __EXTILINE__: specifies the PVD EXTI sources to be disabled.
+ * @brief Disable the PVD Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+
+/**
+ * @brief PVD EXTI line configuration: set rising & falling edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
* This parameter can be:
- * @arg PWR_EXTI_LINE_PVD
* @retval None.
*/
-#define __HAL_PVD_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__))
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
/**
* @brief checks whether the specified PVD Exti interrupt flag is set or not.
- * @param __EXTILINE__: specifies the PVD Exti sources to be cleared.
- * This parameter can be:
- * @arg PWR_EXTI_LINE_PVD
* @retval EXTI PVD Line Status.
*/
-#define __HAL_PVD_EXTI_GET_FLAG(__EXTILINE__) (EXTI->PR & (__EXTILINE__))
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
/**
* @brief Clear the PVD Exti flag.
- * @param __EXTILINE__: specifies the PVD Exti sources to be cleared.
- * This parameter can be:
- * @arg PWR_EXTI_LINE_PVD
* @retval None.
*/
-#define __HAL_PVD_EXTI_CLEAR_FLAG(__EXTILINE__) (EXTI->PR = (__EXTILINE__))
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Generates a Software interrupt on PVD EXTI line.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
/**
* @}
- */
+ */
/* Include PWR HAL Extension module */
#include "stm32f2xx_hal_pwr_ex.h"
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+/**
+ * @}
+ */
-/* Initialization and de-initialization functions *******************************/
-void HAL_PWR_DeInit(void);
-void HAL_PWR_EnableBkUpAccess(void);
-void HAL_PWR_DisableBkUpAccess(void);
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions **********************************************/
+/* PVD configuration */
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+/* WakeUp pins configuration */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes entry */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+/* Power PVD IRQ Handler */
+void HAL_PWR_PVD_IRQHandler(void);
+void HAL_PWR_PVDCallback(void);
+
+/* Cortex System Control functions *******************************************/
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+/**
+ * @}
+ */
-/* Peripheral Control functions ************************************************/
-void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD);
-void HAL_PWR_EnablePVD(void);
-void HAL_PWR_DisablePVD(void);
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+/**
+ * @}
+ */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
-void HAL_PWR_EnterSTANDBYMode(void);
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PWR_Private_Constants PWR Private Constants
+ * @{
+ */
-void HAL_PWR_PVD_IRQHandler(void);
-void HAL_PWR_PVDCallback(void);
+/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
+ * @{
+ */
+#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+/**
+ * @}
+ */
+/** @defgroup PWR_register_alias_address PWR Register alias address
+ * @{
+ */
+/* ------------- PWR registers bit address in the alias region ---------------*/
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
+#define PWR_CR_OFFSET 0x00
+#define PWR_CSR_OFFSET 0x04
+#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
+#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_CR_register_alias PWR CR Register alias address
+ * @{
+ */
+/* --- CR Register ---*/
+/* Alias word address of DBP bit */
+#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
+#define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
+#define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
+ * @{
+ */
+/* --- CSR Register ---*/
+/* Alias word address of EWUP bit */
+#define EWUP_BIT_NUMBER POSITION_VAL(PWR_CSR_EWUP)
+#define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (EWUP_BIT_NUMBER * 4))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWR_Private_Macros PWR Private Macros
+ * @{
+ */
+
+/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
+ * @{
+ */
+#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
+ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
+ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
+ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
+ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
+ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
+ ((MODE) == PWR_PVD_MODE_NORMAL))
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_pwr_ex.h b/f2/include/stm32f2xx_hal_pwr_ex.h
index f0ff2f8207fe69626423ea51f1784360e1a86947..d222d9aaab29d04cac5652e61110d6f781b5555a 100755
--- a/f2/include/stm32f2xx_hal_pwr_ex.h
+++ b/f2/include/stm32f2xx_hal_pwr_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_pwr_ex.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -56,12 +56,92 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
-void HAL_PWREx_EnableFlashPowerDown(void);
-void HAL_PWREx_DisableFlashPowerDown(void);
+/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWREx_Exported_Functions_Group1
+ * @{
+ */
+void HAL_PWREx_EnableFlashPowerDown(void);
+void HAL_PWREx_DisableFlashPowerDown(void);
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PWREx_Private_Constants PWREx Private Constants
+ * @{
+ */
+
+/** @defgroup PWREx_register_alias_address PWREx Register alias address
+ * @{
+ */
+/* ------------- PWR registers bit address in the alias region ---------------*/
+/* --- CR Register ---*/
+/* Alias word address of FPDS bit */
+#define FPDS_BIT_NUMBER POSITION_VAL(PWR_CR_FPDS)
+#define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FPDS_BIT_NUMBER * 4))
+
+ /**
+ * @}
+ */
+
+/** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address
+ * @{
+ */
+/* --- CSR Register ---*/
+/* Alias word address of BRE bit */
+#define BRE_BIT_NUMBER POSITION_VAL(PWR_CSR_BRE)
+#define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (BRE_BIT_NUMBER * 4))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWREx_Private_Macros PWREx Private Macros
+ * @{
+ */
+
+/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_rcc.h b/f2/include/stm32f2xx_hal_rcc.h
index 8669e49b08e3a077d90913f6c767582d26cb2b05..b8926be0e05caedaafcdfa7a7d7b2f7a8e284b50 100755
--- a/f2/include/stm32f2xx_hal_rcc.h
+++ b/f2/include/stm32f2xx_hal_rcc.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_rcc.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,11 +50,14 @@
* @{
*/
-/** @addtogroup RCC
+/** @addtogroup RCC
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCC_Exported_Types RCC Exported Types
+ * @{
+ */
/**
* @brief RCC PLL configuration structure definition
@@ -65,18 +68,18 @@ typedef struct
This parameter can be a value of @ref RCC_PLL_Config */
uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
- This parameter must be a value of @ref RCC_PLL_Clock_Source */
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */
- uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock
- This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
+ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
- uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock
+ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
- uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK)
- This parameter must be a value of @ref RCC_PLLP_Clock_Divider. */
+ uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
+ This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
- uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks
+ uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
}RCC_PLLInitTypeDef;
@@ -104,7 +107,7 @@ typedef struct
uint32_t LSIState; /*!< The new state of the LSI.
This parameter can be a value of @ref RCC_LSI_Config */
- RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
+ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
}RCC_OscInitTypeDef;
@@ -130,72 +133,16 @@ typedef struct
}RCC_ClkInitTypeDef;
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_Exported_Constants
- * @{
+/**
+ * @}
*/
-/** @defgroup RCC_BitAddress_AliasRegion
- * @brief RCC registers bit address in the alias region
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
* @{
*/
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-/* --- CR Register ---*/
-/* Alias word address of HSION bit */
-#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
-#define HSION_BitNumber 0x00
-#define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4))
-/* Alias word address of CSSON bit */
-#define CSSON_BitNumber 0x13
-#define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4))
-/* Alias word address of PLLON bit */
-#define PLLON_BitNumber 0x18
-#define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4))
-/* Alias word address of PLLI2SON bit */
-#define PLLI2SON_BitNumber 0x1A
-#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
-
-/* --- CFGR Register ---*/
-/* Alias word address of I2SSRC bit */
-#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
-#define I2SSRC_BitNumber 0x17
-#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
-
-/* --- BDCR Register ---*/
-/* Alias word address of RTCEN bit */
-#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
-#define RTCEN_BitNumber 0x0F
-#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
-/* Alias word address of BDRST bit */
-#define BDRST_BitNumber 0x10
-#define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
-
-/* --- CSR Register ---*/
-/* Alias word address of LSION bit */
-#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
-#define LSION_BitNumber 0x00
-#define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4))
-
-/* CR register byte 3 (Bits[23:16]) base address */
-#define CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
-/* CIR register byte 2 (Bits[15:8]) base address */
-#define CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
-
-/* CIR register byte 3 (Bits[23:16]) base address */
-#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
-
-/* BDCR register base address */
-#define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
-
-
-#define DBP_TIMEOUT_VALUE ((uint32_t)100)
-#define LSE_TIMEOUT_VALUE ((uint32_t)5000)
-/**
- * @}
- */
-
-/** @defgroup RCC_Oscillator_Type
+/** @defgroup RCC_Oscillator_Type Oscillator Type
* @{
*/
#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
@@ -203,73 +150,59 @@ typedef struct
#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
-
-#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
/**
* @}
*/
-/** @defgroup RCC_HSE_Config
+/** @defgroup RCC_HSE_Config HSE Config
* @{
*/
#define RCC_HSE_OFF ((uint8_t)0x00)
#define RCC_HSE_ON ((uint8_t)0x01)
#define RCC_HSE_BYPASS ((uint8_t)0x05)
-
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
- ((HSE) == RCC_HSE_BYPASS))
/**
* @}
*/
-/** @defgroup RCC_LSE_Config
+/** @defgroup RCC_LSE_Config LSE Config
* @{
*/
#define RCC_LSE_OFF ((uint8_t)0x00)
#define RCC_LSE_ON ((uint8_t)0x01)
#define RCC_LSE_BYPASS ((uint8_t)0x05)
-
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
- ((LSE) == RCC_LSE_BYPASS))
/**
* @}
*/
-/** @defgroup RCC_HSI_Config
+/** @defgroup RCC_HSI_Config HSI Config
* @{
*/
#define RCC_HSI_OFF ((uint8_t)0x00)
#define RCC_HSI_ON ((uint8_t)0x01)
-
-#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
/**
* @}
*/
-/** @defgroup RCC_LSI_Config
+/** @defgroup RCC_LSI_Config LSI Config
* @{
*/
#define RCC_LSI_OFF ((uint8_t)0x00)
#define RCC_LSI_ON ((uint8_t)0x01)
-
-#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
/**
* @}
*/
-/** @defgroup RCC_PLL_Config
+/** @defgroup RCC_PLL_Config PLL Config
* @{
*/
#define RCC_PLL_NONE ((uint8_t)0x00)
#define RCC_PLL_OFF ((uint8_t)0x01)
#define RCC_PLL_ON ((uint8_t)0x02)
-
-#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
/**
* @}
*/
-/** @defgroup RCC_PLLP_Clock_Divider
+/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
* @{
*/
#define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
@@ -280,54 +213,47 @@ typedef struct
* @}
*/
-/** @defgroup RCC_PLL_Clock_Source
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
* @{
*/
#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
-
-#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
- ((SOURCE) == RCC_PLLSOURCE_HSE))
-#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
-#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
-#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
-
-#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
-
/**
* @}
*/
-/** @defgroup RCC_System_Clock_Type
+/** @defgroup RCC_System_Clock_Type System Clock Type
* @{
*/
#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
-
-#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
/**
* @}
*/
-/** @defgroup RCC_System_Clock_Source
+/** @defgroup RCC_System_Clock_Source System Clock Source
* @{
*/
#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
+/**
+ * @}
+ */
-#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
/**
* @}
- */
+ */
-/** @defgroup RCC_AHB_Clock_Source
+/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
* @{
*/
#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
@@ -339,17 +265,11 @@ typedef struct
#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
-
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
- ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
- ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
- ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
- ((HCLK) == RCC_SYSCLK_DIV512))
/**
* @}
*/
-/** @defgroup RCC_APB1_APB2_Clock_Source
+/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
* @{
*/
#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
@@ -357,15 +277,11 @@ typedef struct
#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
-
-#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
- ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
- ((PCLK) == RCC_HCLK_DIV16))
/**
* @}
*/
-/** @defgroup RCC_RTC_Clock_Source
+/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
* @{
*/
#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
@@ -404,7 +320,7 @@ typedef struct
* @}
*/
-/** @defgroup RCC_I2S_Clock_Source
+/** @defgroup RCC_I2S_Clock_Source I2S Clock Source
* @{
*/
#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
@@ -413,46 +329,38 @@ typedef struct
* @}
*/
-/** @defgroup RCC_MCO_Index
+/** @defgroup RCC_MCO_Index MCO Index
* @{
*/
#define RCC_MCO1 ((uint32_t)0x00000000)
#define RCC_MCO2 ((uint32_t)0x00000001)
-
-#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
/**
* @}
*/
-/** @defgroup RCC_MCO1_Clock_Source
+/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
* @{
*/
#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
-
-#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
- ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
/**
* @}
*/
-/** @defgroup RCC_MCO2_Clock_Source
+/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
* @{
*/
#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
-
-#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
- ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
/**
* @}
*/
-/** @defgroup RCC_MCOx_Clock_Prescaler
+/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
* @{
*/
#define RCC_MCODIV_1 ((uint32_t)0x00000000)
@@ -460,15 +368,11 @@ typedef struct
#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
-
-#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
- ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
- ((DIV) == RCC_MCODIV_5))
/**
* @}
*/
-/** @defgroup RCC_Interrupt
+/** @defgroup RCC_Interrupt Interrupts
* @{
*/
#define RCC_IT_LSIRDY ((uint8_t)0x01)
@@ -482,7 +386,7 @@ typedef struct
* @}
*/
-/** @defgroup RCC_Flag
+/** @defgroup RCC_Flag Flags
* Elements values convention: 0XXYYYYYb
* - YYYYY : Flag position in the register
* - 0XX : Register index
@@ -509,483 +413,846 @@ typedef struct
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
-
-#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
/**
* @}
- */
-
-/** @defgroup RCC_PLLI2S_DIVQ
- * @{
*/
-#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
/**
* @}
*/
-/** @defgroup RCC_TIM_PRescaler_Selection
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
* @{
*/
-#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
-#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
-/**
- * @}
- */
-
-
-
-/**
- * @}
- */
-/* Exported macro ------------------------------------------------------------*/
-/** @brief Enable or disable the AHB1 peripheral clock.
+/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
+ */
+#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
+#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
+#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
+#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
+#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+/**
+ * @}
*/
-#define __GPIOA_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOAEN))
-#define __GPIOB_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOBEN))
-#define __GPIOC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOCEN))
-#define __GPIOD_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIODEN))
-#define __GPIOE_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOEEN))
-#define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
-#define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
-#define __GPIOH_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOHEN))
-#define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
-#define __CRC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_CRCEN))
-#define __BKPSRAM_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_BKPSRAMEN))
-#define __DMA1_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA1EN))
-#define __DMA2_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2EN))
-#define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
-#define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
-
-#define __GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
-#define __GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
-#define __GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
-#define __GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
-#define __GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
-#define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
-#define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
-#define __GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
-#define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
-#define __CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
-#define __BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
-#define __DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
-#define __DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
-#define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
-#define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
-
-/** @brief Enable or disable the AHB2 peripheral clock.
+
+/** @defgroup RCC_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
*/
-#define __USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
- __SYSCFG_CLK_ENABLE();\
- }while(0)
-
-
-#define __USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
- __SYSCFG_CLK_DISABLE();\
- }while(0)
-/** @brief Enables or disables the RNG peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\
+ }while(0)
+#define __HAL_RCC_RNG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+/**
+ * @}
*/
-#define __RNG_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_RNGEN))
-#define __RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
-/** @brief Enables or disables the AHB3 peripheral clock.
+/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB3 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
+ */
+#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
+/**
+ * @}
*/
-#define __FSMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FSMCEN))
-#define __FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
-/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
+ */
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_PWR_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
+#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+/**
+ * @}
*/
-#define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
-#define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
-#define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN))
-#define __TIM5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN))
-#define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
-#define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
-#define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
-#define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
-#define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
-#define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
-#define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
-#define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
-#define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
-#define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
-#define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
-#define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
-#define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
-#define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
-#define __I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
-#define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
-#define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
-#define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
-#define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
-
-#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
-#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
-#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
-#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
-#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
-#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
-#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
-#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
-#define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
-#define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
-#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-
-
-/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
*/
-#define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
-#define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
-#define __USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN))
-#define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
-#define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
-#define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
-#define __SDIO_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDIOEN))
-#define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
-#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
-#define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
-#define __TIM9_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM9EN))
-#define __TIM10_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM10EN))
-#define __TIM11_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM11EN))
-
-#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
-#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
-#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
-#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
-#define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
-#define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
-#define __SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
-#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
-#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
-#define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#define __TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
-#define __TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-#define __TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
-
-/** @brief Force or release AHB1 peripheral reset.
- */
-#define __AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
-#define __GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
-#define __GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
-#define __GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
-#define __GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
-#define __GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
-#define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
-#define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
-#define __GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
-#define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
-#define __CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
-#define __DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
-#define __DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
-#define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
-#define __OTGHSULPI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHSULPIRST))
-
-#define __AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
-#define __GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
-#define __GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
-#define __GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
-#define __GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
-#define __GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
-#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
-#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
-#define __GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
-#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
-#define __CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
-#define __DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
-#define __DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
-#define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
-#define __OTGHSULPI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHSULPIRST))
-
-/** @brief Force or release AHB2 peripheral reset.
- */
-#define __AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
-#define __OTGFS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
-
-#define __AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
-#define __OTGFS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
-
-#define __RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
-#define __RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
-
-/** @brief Force or release APB1 peripheral reset.
- */
-#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
-#define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
-#define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-#define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
-#define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-#define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-#define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-#define __I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
-#define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
-#define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
-#define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
-#define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-
-#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
-#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
-#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
-#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
-#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
-#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
-#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
-#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
-#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
-#define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
-#define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
-#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-
-/** @brief Force or release APB2 peripheral reset.
- */
-#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
-#define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
-#define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
-#define __USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
-#define __ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
-#define __SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
-#define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
-#define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
-#define __TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
-#define __TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-#define __TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
-
-#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
-#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
-#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
-#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
-#define __ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
-#define __SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
-#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
-#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
-#define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
-#define __TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
-#define __TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-#define __TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
-
-/** @brief Force or release AHB3 peripheral reset.
+#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
+#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
+#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
+#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
+#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
+ * @brief Force or release AHB1 peripheral reset.
+ * @{
*/
-#define __AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
-#define __FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
+#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
+#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
+#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_OTGHSULPI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHSULPIRST))
+
+#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
+#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
+#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
+#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_OTGHSULPI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHSULPIRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Force Release Reset
+ * @brief Force or release AHB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+
+#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
+#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+
+#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
+#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
+#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
+#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
+
+#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
+#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
+#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
+#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
+/**
+ * @}
+ */
-#define __AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
-#define __FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
+/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Force Release Reset
+ * @brief Force or release AHB3 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
-/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
+#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
*/
-#define __GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
-#define __GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
-#define __GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
-#define __GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
-#define __GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
-#define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
-#define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
-#define __GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
-#define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
-#define __CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
-#define __FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
-#define __SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
-#define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
-#define __BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
-#define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
-#define __DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
-#define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
-#define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
-
-#define __GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
-#define __GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
-#define __GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
-#define __GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
-#define __GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
-#define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
-#define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
-#define __GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
-#define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
-#define __CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
-#define __FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
-#define __SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
-#define __SRAM2_CLK_SLEEP_DISABLE() RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
-#define __BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
-#define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
-#define __DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
-#define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
-#define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
-
-/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
*/
-#define __OTGFS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
-
-#define __OTGFS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
-#define __RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
-#define __RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+/**
+ * @}
+ */
-/** @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
+/** @defgroup RCC_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
+ * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
*/
-#define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
-#define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
-
+#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
+#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
+/**
+ * @}
+ */
-/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
*/
-#define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
-#define __TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
-#define __TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
-#define __TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
-#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
-#define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
-#define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
-#define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
-#define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
-#define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
-#define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
-#define __SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
-#define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
-#define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
-#define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
-#define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
-#define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
-#define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
-#define __I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
-#define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
-#define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
-#define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
-#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
-
-#define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
-#define __TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
-#define __TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
-#define __TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
-#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
-#define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
-#define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
-#define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
-#define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
-#define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
-#define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
-#define __SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
-#define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
-#define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
-#define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
-#define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
-#define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
-#define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
-#define __I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
-#define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
-#define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
-#define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
-#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
-
-/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * power consumption.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
*/
-#define __TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
-#define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
-#define __USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
-#define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
-#define __SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
-#define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
-#define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
-#define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
-#define __TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
-#define __TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
-#define __TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
-#define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
-#define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
-
-#define __TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
-#define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
-#define __USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
-#define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
-#define __SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
-#define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
-#define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
-#define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
-#define __TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
-#define __TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
-#define __TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
-#define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
-#define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI_Configuration HSI Configuration
+ * @{
+ */
/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
* It is used (enabled by hardware) as system clock source after startup
- * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+ * from Reset, wake-up from STOP and STANDBY mode, or in case of failure
* of the HSE used directly or indirectly as system clock (if the Clock
* Security System CSS is enabled).
* @note HSI can not be stopped if it is used as system clock source. In this case,
@@ -997,8 +1264,8 @@ typedef struct
* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
* clock cycles.
*/
-#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) CR_HSION_BB = ENABLE)
-#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) CR_HSION_BB = DISABLE)
+#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
+#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
* @note The calibration is used to compensate for the variations in voltage
@@ -1008,6 +1275,13 @@ typedef struct
*/
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSI_Configuration LSI Configuration
+ * @{
+ */
/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
* @note After enabling the LSI, the application software should wait on
@@ -1017,11 +1291,20 @@ typedef struct
* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
* clock cycles.
*/
-#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) CSR_LSION_BB = ENABLE)
-#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) CSR_LSION_BB = DISABLE)
+#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
+#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSE_Configuration HSE Configuration
+ * @{
+ */
/**
* @brief Macro to configure the External High Speed oscillator (HSE).
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
+ * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
* software should wait on HSERDY flag to be set indicating that HSE clock
* is stable and can be used to clock the PLL and/or system clock.
@@ -1039,10 +1322,18 @@ typedef struct
* @arg RCC_HSE_ON: turn ON the HSE oscillator.
* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
*/
-#define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) CR_BYTE2_ADDRESS = (__STATE__))
+#define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__))
+/**
+ * @}
+ */
+/** @defgroup RCC_LSE_Configuration LSE Configuration
+ * @{
+ */
/**
* @brief Macro to configure the External Low Speed oscillator (LSE).
+ * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
+ * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
* @note As the LSE is in the Backup domain and write access is denied to
* this domain after reset, you have to enable write access using
* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
@@ -1057,13 +1348,21 @@ typedef struct
* @arg RCC_LSE_ON: turn ON the LSE oscillator.
* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
*/
-#define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) BDCR_BYTE0_ADDRESS = (__STATE__))
+#define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
-/** @brief Macros to enable or disable the the RTC clock.
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
+ * @{
+ */
+
+/** @brief Macros to enable or disable the RTC clock.
* @note These macros must be used only after the RTC clock source was selected.
*/
-#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) BDCR_RTCEN_BB = ENABLE)
-#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) BDCR_RTCEN_BB = DISABLE)
+#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
+#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
/** @brief Macros to configure the RTC clock (RTCCLK).
* @note As the RTC clock configuration bits are in the Backup domain and write
@@ -1080,7 +1379,7 @@ typedef struct
* @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
* as RTC clock, where x:[2,31]
* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
- * work in STOP and STANDBY modes, and can be used as wakeup source.
+ * work in STOP and STANDBY modes, and can be used as wake-up source.
* However, when the HSE clock is used as RTC clock source, the RTC
* cannot be used in STOP and STANDBY modes.
* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
@@ -1098,8 +1397,15 @@ typedef struct
* and the RTC clock source selection in RCC_CSR register.
* @note The BKPSRAM is not affected by this reset.
*/
-#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) BDCR_BDRST_BB = ENABLE)
-#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) BDCR_BDRST_BB = DISABLE)
+#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
+#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Configuration PLL Configuration
+ * @{
+ */
/** @brief Macros to enable or disable the main PLL.
* @note After enabling the main PLL, the application software should wait on
@@ -1108,13 +1414,14 @@ typedef struct
* @note The main PLL can not be disabled if it is used as system clock source
* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
*/
-#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) CR_PLLON_BB = ENABLE)
-#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) CR_PLLON_BB = DISABLE)
+#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
+#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
+
/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
* @note This function must be used only when the main PLL is disabled.
* @param __RCC_PLLSource__: specifies the PLL entry clock source.
- * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
@@ -1127,37 +1434,57 @@ typedef struct
* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
* @note You have to set the PLLN parameter correctly to ensure that the VCO
* output frequency is between 192 and 432 MHz.
+ *
* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
* This parameter must be a number in the range {2, 4, 6, or 8}.
- * @note You have to set the PLLP parameter correctly to not exceed 120 MHz on
- * the System clock frequency.
+ *
* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
- * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
* @note If the USB OTG FS is used in your application, you have to set the
* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
* correctly.
+ *
*/
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
- (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
- ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
+ (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \
+ ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
+ ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
+/**
+ * @}
+ */
-/** @brief Macro to configure the I2S clock source (I2SCLK).
- * @note This function must be called before enabling the I2S APB clock.
- * @param __SOURCE__: specifies the I2S clock source.
+/** @brief Macro to configure the PLL clock source.
+ * @note This function must be used only when the main PLL is disabled.
+ * @param __PLLSOURCE__: specifies the PLL entry clock source.
* This parameter can be one of the following values:
- * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
- * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
- * used as I2S clock source.
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+ *
+ */
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
+
+/** @brief Macro to configure the PLL multiplication factor.
+ * @note This function must be used only when the main PLL is disabled.
+ * @param __PLLM__: specifies the division factor for PLL VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLL jitter.
+ *
+ */
+#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
+
+/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
+ * @{
*/
-#define __HAL_RCC_I2SCLK(__SOURCE__) (*(__IO uint32_t *) CFGR_I2SSRC_BB = (__SOURCE__))
/** @brief Macros to enable or disable the PLLI2S.
* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
*/
-#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) CR_PLLI2SON_BB = ENABLE)
-#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) CR_PLLI2SON_BB = DISABLE)
+#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
+#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
* @note This macro must be used only when the PLLI2S is disabled.
@@ -1174,12 +1501,79 @@ typedef struct
*/
#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) | ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
+/** @brief Macro to configure the I2S clock source (I2SCLK).
+ * @note This function must be called before enabling the I2S APB clock.
+ * @param __SOURCE__: specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
+ * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source.
+ */
+#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the MCO1 clock.
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+ * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+ * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+ * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
+ * @param __MCODIV__ specifies the MCO clock prescaler.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCODIV_1: no division applied to MCOx clock
+ * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+ * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+ * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+ * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+ */
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
+
+/** @brief Macro to configure the MCO2 clock.
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+ * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
+ * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+ * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
+ * @param __MCODIV__ specifies the MCO clock prescaler.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCODIV_1: no division applied to MCOx clock
+ * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+ * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+ * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+ * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+ */
+#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Get_Clock_source Get Clock source
+ * @{
+ */
+/**
+ * @brief Macro to configure the system clock source.
+ * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
+ * This parameter can be one of the following values:
+ * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
+ */
+#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
+
/** @brief Macro to get the clock source used as system clock.
* @retval The clock source used as system clock. The returned value can be one
* of the following:
- * - RCC_CFGR_SWS_HSI: HSI used as system clock.
- * - RCC_CFGR_SWS_HSE: HSE used as system clock.
- * - RCC_CFGR_SWS_PLL: PLL used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
*/
#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
@@ -1190,8 +1584,11 @@ typedef struct
* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
*/
#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
+/**
+ * @}
+ */
-/** @defgroup RCC_Flags_Interrupts_Management
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
* @brief macros to manage the specified RCC Flags and interrupts.
* @{
*/
@@ -1207,7 +1604,7 @@ typedef struct
* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
*/
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
* the selected interrupts).
@@ -1220,7 +1617,7 @@ typedef struct
* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
*/
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
* bits to clear the selected interrupt pending bits.
@@ -1234,7 +1631,7 @@ typedef struct
* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
* @arg RCC_IT_CSS: Clock Security System interrupt
*/
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE2_ADDRESS = (__INTERRUPT__))
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
/** @brief Check the RCC's interrupt has occurred or not.
* @param __INTERRUPT__: specifies the RCC interrupt source to check.
@@ -1275,23 +1672,37 @@ typedef struct
*/
#define RCC_FLAG_MASK ((uint8_t)0x1F)
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
+
+#define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
+/**
+ * @}
+ */
+
/**
* @}
*/
-#define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
-
-
-/* Include RCC HAL Extension module */
+/* Include RCC HAL Extended module */
#include "stm32f2xx_hal_rcc_ex.h"
-
/* Exported functions --------------------------------------------------------*/
-
+ /** @addtogroup RCC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group1
+ * @{
+ */
/* Initialization and de-initialization functions ******************************/
void HAL_RCC_DeInit(void);
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+/**
+ * @}
+ */
+/** @addtogroup RCC_Exported_Functions_Group2
+ * @{
+ */
/* Peripheral Control functions ************************************************/
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
void HAL_RCC_EnableCSS(void);
@@ -1307,7 +1718,161 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t
void HAL_RCC_NMI_IRQHandler(void);
/* User Callbacks in non blocking mode (IT mode) */
-void HAL_RCC_CCSCallback(void);
+void HAL_RCC_CSSCallback(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+ * @{
+ */
+
+/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
+ * @brief RCC registers bit address in the alias region
+ * @{
+ */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+/* --- CR Register ---*/
+/* Alias word address of HSION bit */
+#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
+#define RCC_HSION_BIT_NUMBER 0x00
+#define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_HSION_BIT_NUMBER * 4))
+/* Alias word address of CSSON bit */
+#define RCC_CSSON_BIT_NUMBER 0x13
+#define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_CSSON_BIT_NUMBER * 4))
+/* Alias word address of PLLON bit */
+#define RCC_PLLON_BIT_NUMBER 0x18
+#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLON_BIT_NUMBER * 4))
+/* Alias word address of PLLI2SON bit */
+#define RCC_PLLI2SON_BIT_NUMBER 0x1A
+#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4))
+
+/* --- CFGR Register ---*/
+/* Alias word address of I2SSRC bit */
+#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
+#define RCC_I2SSRC_BIT_NUMBER 0x17
+#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_I2SSRC_BIT_NUMBER * 4))
+
+/* --- BDCR Register ---*/
+/* Alias word address of RTCEN bit */
+#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
+#define RCC_RTCEN_BIT_NUMBER 0x0F
+#define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_RTCEN_BIT_NUMBER * 4))
+/* Alias word address of BDRST bit */
+#define RCC_BDRST_BIT_NUMBER 0x10
+#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_BDRST_BIT_NUMBER * 4))
+
+/* --- CSR Register ---*/
+/* Alias word address of LSION bit */
+#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
+#define RCC_LSION_BIT_NUMBER 0x00
+#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RCC_LSION_BIT_NUMBER * 4))
+
+/* CR register byte 3 (Bits[23:16]) base address */
+#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
+
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
+
+/* BDCR register base address */
+#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
+
+#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
+#define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)
+
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+
+#define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_Private_Macros RCC Private Macros
+ * @{
+ */
+
+/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
+ * @{
+ */
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
+
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+ ((HSE) == RCC_HSE_BYPASS))
+
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+ ((LSE) == RCC_LSE_BYPASS))
+
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
+
+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
+
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
+
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
+ ((SOURCE) == RCC_PLLSOURCE_HSE))
+
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
+
+#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
+
+#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+
+#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
+
+#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
+
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
+ ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
+ ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
+ ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
+ ((HCLK) == RCC_SYSCLK_DIV512))
+
+#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
+
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
+ ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
+ ((PCLK) == RCC_HCLK_DIV16))
+
+#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
+ ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
+
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
+ ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
+ ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
+ ((DIV) == RCC_MCODIV_5))
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_rcc_ex.h b/f2/include/stm32f2xx_hal_rcc_ex.h
index 58b9ca4709b1597a46633d73fa15b4e9b834cb88..bd8516fc503eb3b473cf9c62d5faa03fc9b5584b 100755
--- a/f2/include/stm32f2xx_hal_rcc_ex.h
+++ b/f2/include/stm32f2xx_hal_rcc_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_rcc_ex.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,20 +54,22 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
-
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+ * @{
+ */
/**
* @brief PLLI2S Clock structure definition
*/
typedef struct
{
- uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock
- This parameter must be a number between Min_Data = 192 and Max_Data = 432
- This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+ uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+ This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S */
- uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock
- This parameter must be a number between Min_Data = 2 and Max_Data = 7
- This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S */
}RCC_PLLI2SInitTypeDef;
@@ -79,36 +81,38 @@ typedef struct
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
- RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
- This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+ RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S */
- uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
This parameter can be a value of @ref RCC_RTC_Clock_Source */
- uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection
+ uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
}RCC_PeriphCLKInitTypeDef;
-
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Constants
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
* @{
*/
-/** @defgroup RCCEx_Periph_Clock_Selection
+/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
* @{
*/
#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
-#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000004)
-#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000008)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000000f))
+#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000008)
/**
* @}
*/
-/** @defgroup RCCEx_TIM_PRescaler_Selection
+/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
* @{
*/
#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
@@ -122,143 +126,203 @@ typedef struct
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
+ * @{
+ */
-/** @brief Enables or disables the AHB1 peripheral clock.
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
-
#if defined(STM32F207xx) || defined(STM32F217xx)
-#define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
-#define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
-#define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
-#define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
-
-#define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
-#define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
-#define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
-#define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
-#endif /* STM32F207xx || STM32F217xx */
+#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
+#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
+#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
+#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
/**
* @brief Enable ETHERNET clock.
*/
-#if defined(STM32F207xx) || defined(STM32F217xx)
-#define __ETH_CLK_ENABLE() do { \
- __ETHMAC_CLK_ENABLE(); \
- __ETHMACTX_CLK_ENABLE(); \
- __ETHMACRX_CLK_ENABLE(); \
- } while(0)
-
+#define __HAL_RCC_ETH_CLK_ENABLE() do { \
+ __HAL_RCC_ETHMAC_CLK_ENABLE(); \
+ __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
+ __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
+ } while(0)
/**
* @brief Disable ETHERNET clock.
*/
-#define __ETH_CLK_DISABLE() do { \
- __ETHMACTX_CLK_DISABLE(); \
- __ETHMACRX_CLK_DISABLE(); \
- __ETHMAC_CLK_DISABLE(); \
- } while(0)
+#define __HAL_RCC_ETH_CLK_DISABLE() do { \
+ __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
+ __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
+ __HAL_RCC_ETHMAC_CLK_DISABLE(); \
+ } while(0)
#endif /* STM32F207xx || STM32F217xx */
+/**
+ * @}
+ */
-/** @brief Enable or disable the AHB2 peripheral clock.
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
#if defined(STM32F207xx) || defined(STM32F217xx)
-#define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
-#define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
+#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
#endif /* STM32F207xx || STM32F217xx */
#if defined(STM32F215xx) || defined(STM32F217xx)
-#define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
-#define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
-
-
-#define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
-#define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
-
+#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_HASH_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
+#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
#endif /* STM32F215xx || STM32F217xx */
+/**
+ * @}
+ */
-/** @brief Force or release AHB1 peripheral reset.
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
+ * @brief Force or release AHB1 peripheral reset.
*/
#if defined(STM32F207xx) || defined(STM32F217xx)
-#define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
-
-#define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
-#endif /* STM32F207xx || STM32F217xx */
+#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
+#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
+#endif /* STM32F207xx || STM32F217xx */
+/**
+ * @}
+ */
-/** @brief Force or release AHB2 peripheral reset.
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
+ * @brief Force or release AHB2 peripheral reset.
+ * @{
*/
#if defined(STM32F207xx) || defined(STM32F217xx)
-#define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
-#define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
+#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
#endif /* STM32F207xx || STM32F217xx */
#if defined(STM32F215xx) || defined(STM32F217xx)
-#define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
-#define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
-
-
-#define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
-#define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
+#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
+#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
#endif /* STM32F215xx || STM32F217xx */
-/** @brief Force or release AHB3 peripheral reset
- */
-
-/** @brief Force or release APB1 peripheral reset.
- */
-
-/** @brief Force or release APB2 peripheral reset.
+/**
+ * @}
*/
-/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
*/
-
#if defined(STM32F207xx) || defined(STM32F217xx)
-#define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
-#define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
-#define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
-#define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
-
-#define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
-#define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
-#define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
-#define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
+
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
#endif /* STM32F207xx || STM32F217xx */
+/**
+ * @}
+ */
-/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
*/
#if defined(STM32F207xx) || defined(STM32F217xx)
-#define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
-#define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
#endif /* STM32F207xx || STM32F217xx */
#if defined(STM32F215xx) || defined(STM32F217xx)
-#define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
-#define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
-
-
-#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
-#define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
#endif /* STM32F215xx || STM32F217xx */
+/**
+ * @}
+ */
-/* Exported functions --------------------------------------------------------*/
-
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCCEx_Exported_Functions_Group1
+ * @{
+ */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
@@ -269,7 +333,51 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
/**
* @}
*/
-
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
+ * @{
+ */
+
+/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
+ * @brief RCC registers bit address in the alias region
+ * @{
+ */
+#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
+ * @{
+ */
+/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
+ * @{
+ */
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000000F))
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
#ifdef __cplusplus
}
#endif
diff --git a/f2/include/stm32f2xx_hal_rng.h b/f2/include/stm32f2xx_hal_rng.h
index 27838c89281cfcf4561784eb29c581198fbdf00e..56a7cccb808eb33ff35f5c32e41d712bbd493a29 100755
--- a/f2/include/stm32f2xx_hal_rng.h
+++ b/f2/include/stm32f2xx_hal_rng.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_rng.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of RNG HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F2xx_HAL_RNG_H
@@ -50,15 +50,20 @@
* @{
*/
-/** @addtogroup RNG
+/** @defgroup RNG RNG
+ * @brief RNG HAL module driver
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
-/**
- * @brief RNG HAL State Structure definition
- */
+/** @defgroup RNG_Exported_Types RNG Exported Types
+ * @{
+ */
+
+/** @defgroup RNG_Exported_Types_Group1 RNG State Structure definition
+ * @{
+ */
typedef enum
{
HAL_RNG_STATE_RESET = 0x00, /*!< RNG not yet initialized or disabled */
@@ -70,47 +75,55 @@ typedef enum
}HAL_RNG_StateTypeDef;
/**
- * @brief RNG Handle Structure definition
+ * @}
+ */
+
+/** @defgroup RNG_Exported_Types_Group2 RNG Handle Structure definition
+ * @{
*/
typedef struct
{
- RNG_TypeDef *Instance; /*!< Register base address */
+ RNG_TypeDef *Instance; /*!< Register base address */
- HAL_LockTypeDef Lock; /*!< RNG locking object */
+ HAL_LockTypeDef Lock; /*!< RNG locking object */
- __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
+ __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
+
+ uint32_t RandomNumber; /*!< Last Generated RNG Data */
}RNG_HandleTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup RNG_Exported_Constants
+/** @defgroup RNG_Exported_Constants RNG Exported Constants
* @{
*/
-/** @defgroup RNG_Interrupt_definition
+/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
* @{
- */
-#define RNG_IT_CEI ((uint32_t)0x20) /*!< Clock error interrupt */
-#define RNG_IT_SEI ((uint32_t)0x40) /*!< Seed error interrupt */
-
-#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
- ((IT) == RNG_IT_SEI))
+ */
+#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */
+#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */
+#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */
/**
* @}
*/
-
-/** @defgroup RNG_Flag_definition
+/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
* @{
- */
-#define RNG_FLAG_DRDY ((uint32_t)0x0001) /*!< Data ready */
-#define RNG_FLAG_CECS ((uint32_t)0x0002) /*!< Clock error current status */
-#define RNG_FLAG_SECS ((uint32_t)0x0004) /*!< Seed error current status */
+ */
+#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */
+#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */
+#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */
-#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
- ((FLAG) == RNG_FLAG_CECS) || \
- ((FLAG) == RNG_FLAG_SECS))
/**
* @}
*/
@@ -119,7 +132,17 @@ typedef struct
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup RNG_Exported_Macros RNG Exported Macros
+ * @{
+ */
+
+/** @brief Reset RNG handle state
+ * @param __HANDLE__: RNG Handle
+ * @retval None
+ */
+#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
/**
* @brief Enables the RNG peripheral.
@@ -136,21 +159,27 @@ typedef struct
#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
/**
- * @brief Gets the selected RNG's flag status.
+ * @brief Check the selected RNG flag status.
* @param __HANDLE__: RNG Handle
* @param __FLAG__: RNG flag
- * @retval The new state of RNG_FLAG (SET or RESET).
+ * This parameter can be one of the following values:
+ * @arg RNG_FLAG_DRDY: Data ready
+ * @arg RNG_FLAG_CECS: Clock error current status
+ * @arg RNG_FLAG_SECS: Seed error current status
+ * @retval The new state of __FLAG__ (SET or RESET).
*/
#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/**
- * @brief Clears the RNG's pending flags.
- * @param __HANDLE__: RNG Handle
- * @param __FLAG__: RNG flag
+ * @brief Clears the selected RNG flag status.
+ * @param __HANDLE__: RNG handle
+ * @param __FLAG__: RNG flag to clear
+ * @note WARNING: This is a dummy macro for HAL code alignment,
+ * flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
* @retval None
*/
-#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) &= ~(__FLAG__))
-
+#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
+
/**
* @brief Enables the RNG interrupts.
* @param __HANDLE__: RNG Handle
@@ -168,33 +197,148 @@ typedef struct
/**
* @brief Checks whether the specified RNG interrupt has occurred or not.
* @param __HANDLE__: RNG Handle
- * @param __INTERRUPT__: specifies the RNG interrupt source to check.
+ * @param __INTERRUPT__: specifies the RNG interrupt status flag to check.
* This parameter can be one of the following values:
- * @arg RNG_FLAG_DRDY: Data ready interrupt
- * @arg RNG_FLAG_CECS: Clock error interrupt
- * @arg RNG_FLAG_SECS: Seed error interrupt
- * @retval The new state of RNG_FLAG (SET or RESET).
+ * @arg RNG_IT_DRDY: Data ready interrupt
+ * @arg RNG_IT_CEI: Clock error interrupt
+ * @arg RNG_IT_SEI: Seed error interrupt
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
+/**
+ * @brief Clear the RNG interrupt status flags.
+ * @param __HANDLE__: RNG Handle
+ * @param __INTERRUPT__: specifies the RNG interrupt status flag to clear.
+ * This parameter can be one of the following values:
+ * @arg RNG_IT_CEI: Clock error interrupt
+ * @arg RNG_IT_SEI: Seed error interrupt
+ * @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
+ * @retval None
+ */
+#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
+
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
+/** @defgroup RNG_Exported_Functions RNG Exported Functions
+ * @{
+ */
-/* Initialization/de-initialization functions **********************************/
+/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
-/* Peripheral Control functions ************************************************/
-uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);
-uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng);
+/**
+ * @}
+ */
+
+/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead */
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
+
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
+uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
+
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ReadyCallback(RNG_HandleTypeDef* hrng);
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
+void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
-/* Peripheral State functions **************************************************/
+/**
+ * @}
+ */
+
+/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
+ * @{
+ */
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup RNG_Private_Types RNG Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup RNG_Private_Defines RNG Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RNG_Private_Variables RNG Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RNG_Private_Constants RNG Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RNG_Private_Macros RNG Private Macros
+ * @{
+ */
+#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
+ ((IT) == RNG_IT_SEI))
+
+#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
+ ((FLAG) == RNG_FLAG_CECS) || \
+ ((FLAG) == RNG_FLAG_SECS))
+
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup RNG_Private_Functions RNG Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/**
* @}
*/
diff --git a/f2/include/stm32f2xx_hal_rtc.h b/f2/include/stm32f2xx_hal_rtc.h
index 8bee867a5f367c26be52b7d56b5ce733c1386e16..825d8f9fd3cce84aad910b38b3c3c3a583b0f173 100755
--- a/f2/include/stm32f2xx_hal_rtc.h
+++ b/f2/include/stm32f2xx_hal_rtc.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_rtc.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,7 +54,11 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTC_Exported_Types RTC Exported Types
+ * @{
+ */
+
/**
* @brief HAL State structures definition
*/
@@ -80,7 +84,7 @@ typedef struct
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FFF */
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
This parameter can be a value of @ref RTC_Output_selection_Definitions */
@@ -98,7 +102,7 @@ typedef struct
typedef struct
{
uint8_t Hours; /*!< Specifies the RTC Time Hour.
- This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected
+ This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
@@ -110,7 +114,7 @@ typedef struct
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
This parameter can be a value of @ref RTC_AM_PM_Definitions */
- uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
+ uint32_t DayLightSaving; /*!< Specifies DayLight Save Operation.
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
@@ -159,7 +163,7 @@ typedef struct
}RTC_AlarmTypeDef;
/**
- * @brief Time Handle Structure definition
+ * @brief RTC Handle Structure definition
*/
typedef struct
{
@@ -173,164 +177,93 @@ typedef struct
}RTC_HandleTypeDef;
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Constants
+/** @defgroup RTC_Exported_Constants RTC Exported Constants
* @{
- */
-
-/* Masks Definition */
-#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
-#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
-#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
-#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
-#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
- RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
- RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
- RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F))
+ */
-#define RTC_TIMEOUT_VALUE 1000
-
-/** @defgroup RTC_Hour_Formats
+/** @defgroup RTC_Hour_Formats RTC Hour Formats
* @{
*/
#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040)
-
-#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
- ((FORMAT) == RTC_HOURFORMAT_24))
/**
* @}
*/
-/** @defgroup RTC_Output_selection_Definitions
+/** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions
* @{
*/
#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)
#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000)
#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)
-
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
- ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
- ((OUTPUT) == RTC_OUTPUT_ALARMB) || \
- ((OUTPUT) == RTC_OUTPUT_WAKEUP))
/**
* @}
*/
-/** @defgroup RTC_Output_Polarity_Definitions
+/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
* @{
*/
#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)
-
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
- ((POL) == RTC_OUTPUT_POLARITY_LOW))
/**
* @}
*/
-/** @defgroup RTC_Output_Type_ALARM_OUT
+/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
* @{
*/
#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)0x00040000)
-
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
- ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Asynchronous_Predivider
- * @{
- */
-#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Synchronous_Predivider
- * @{
- */
-#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x1FFF)
-/**
- * @}
- */
-
-/** @defgroup RTC_Time_Definitions
- * @{
- */
-#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
-#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
-#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
/**
* @}
*/
-/** @defgroup RTC_AM_PM_Definitions
+/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
* @{
*/
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
-
-#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
/**
* @}
*/
-/** @defgroup RTC_DayLightSaving_Definitions
+/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
* @{
*/
#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)
#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)
#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
-
-#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
- ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
- ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
/**
* @}
*/
-/** @defgroup RTC_StoreOperation_Definitions
+/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
* @{
*/
#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000)
-
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
- ((OPERATION) == RTC_STOREOPERATION_SET))
/**
* @}
*/
-/** @defgroup RTC_Input_parameter_format_definitions
+/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
* @{
*/
-#define FORMAT_BIN ((uint32_t)0x000000000)
-#define FORMAT_BCD ((uint32_t)0x000000001)
-
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == FORMAT_BIN) || ((FORMAT) == FORMAT_BCD))
+#define RTC_FORMAT_BIN ((uint32_t)0x000000000)
+#define RTC_FORMAT_BCD ((uint32_t)0x000000001)
/**
* @}
*/
-/** @defgroup RTC_Year_Date_Definitions
- * @{
- */
-#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
-/**
- * @}
- */
-
-/** @defgroup RTC_Month_Date_Definitions
+/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
* @{
*/
-
/* Coded in BCD format */
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
@@ -344,14 +277,11 @@ typedef struct
#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
-
-#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
-#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
/**
* @}
*/
-/** @defgroup RTC_WeekDay_Definitions
+/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
* @{
*/
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
@@ -361,48 +291,20 @@ typedef struct
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
-
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarm_Definitions
- * @{
- */
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
/**
* @}
*/
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions
+/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
* @{
*/
#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
- ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
/**
* @}
*/
-
-/** @defgroup RTC_AlarmMask_Definitions
+/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
* @{
*/
#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
@@ -411,24 +313,20 @@ typedef struct
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
-
-#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
/**
* @}
*/
-/** @defgroup RTC_Alarms_Definitions
+/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
* @{
*/
#define RTC_ALARM_A RTC_CR_ALRAE
#define RTC_ALARM_B RTC_CR_ALRBE
-
-#define IS_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
/**
* @}
- */
+ */
-/** @defgroup RTC_Interrupts_Definitions
+/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
* @{
*/
#define RTC_IT_TS ((uint32_t)0x00008000)
@@ -441,10 +339,9 @@ typedef struct
* @}
*/
-/** @defgroup RTC_Flags_Definitions
+/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
* @{
*/
-#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
#define RTC_FLAG_TSF ((uint32_t)0x00000800)
@@ -466,6 +363,15 @@ typedef struct
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RTC_Exported_Macros RTC Exported Macros
+ * @{
+ */
+
+/** @brief Reset RTC handle state
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
/**
* @brief Disable the write protection for RTC registers.
@@ -541,18 +447,18 @@ typedef struct
/**
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
* @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt to check.
* This parameter can be:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __FLAG__) ((((((__HANDLE__)->Instance->ISR)& ((__FLAG__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
/**
* @brief Get the selected RTC Alarm's flag status.
* @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * @param __FLAG__: specifies the RTC Alarm Flag to check.
* This parameter can be:
* @arg RTC_FLAG_ALRAF
* @arg RTC_FLAG_ALRBF
@@ -571,63 +477,136 @@ typedef struct
* @arg RTC_FLAG_ALRBF
* @retval None
*/
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
-
/**
- * @brief Enable the RTC Exti line.
- * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
+ * @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
* This parameter can be:
- * @arg RTC_EXTI_LINE_ALARM_EVENT
- * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
- * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
- */
-#define __HAL_RTC_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__))
+ */
+#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
/**
- * @brief Disable the RTC Exti line.
- * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_EXTI_LINE_ALARM_EVENT
- * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
- * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
+ * @brief Enable interrupt on the RTC Alarm associated Exti line.
* @retval None
*/
-#define __HAL_RTC_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__))
+#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Clear the RTC Exti flags.
- * @param __FLAG__: specifies the RTC Exti sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_EXTI_LINE_ALARM_EVENT
- * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
- * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
+ * @brief Disable interrupt on the RTC Alarm associated Exti line.
* @retval None
*/
-#define __HAL_RTC_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__))
+#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable event on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable event on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+ * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
+ */
+#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Clear the RTC Alarm associated Exti line flag.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
+/**
+ * @}
+ */
/* Include RTC HAL Extension module */
#include "stm32f2xx_hal_rtc_ex.h"
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTC_Exported_Functions
+ * @{
+ */
+/** @addtogroup RTC_Exported_Functions_Group1
+ * @{
+ */
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+/** @addtogroup RTC_Exported_Functions_Group2
+ * @{
+ */
/* RTC Time and Date functions ************************************************/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+/**
+ * @}
+ */
+/** @addtogroup RTC_Exported_Functions_Group3
+ * @{
+ */
/* RTC Alarm functions ********************************************************/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
@@ -636,16 +615,127 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+/** @addtogroup RTC_Exported_Functions_Group4
+ * @{
+ */
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
+/**
+ * @}
+ */
+/** @addtogroup RTC_Exported_Functions_Group5
+ * @{
+ */
/* Peripheral State functions *************************************************/
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTC_Private_Constants RTC Private Constants
+ * @{
+ */
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
+#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
+#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
+#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
+#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
+ RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
+ RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
+ RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F))
+
+#define RTC_TIMEOUT_VALUE 1000
+
+#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RTC_Private_Macros RTC Private Macros
+ * @{
+ */
+
+/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
+ * @{
+ */
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
+ ((FORMAT) == RTC_HOURFORMAT_24))
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMB) || \
+ ((OUTPUT) == RTC_OUTPUT_WAKEUP))
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
+ ((POL) == RTC_OUTPUT_POLARITY_LOW))
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
+ ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x1FFF)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
+#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
+ ((OPERATION) == RTC_STOREOPERATION_SET))
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
+#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
+ ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
+#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup RTC_Private_Functions RTC Private Functions
+ * @{
+ */
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
uint8_t RTC_ByteToBcd2(uint8_t Value);
uint8_t RTC_Bcd2ToByte(uint8_t Value);
+/**
+ * @}
+ */
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_rtc_ex.h b/f2/include/stm32f2xx_hal_rtc_ex.h
index fb276ca17ed716705c6109ba21773e5d2f1969ed..ba115d54aa7153f53dbf73912d9de323520f6812 100755
--- a/f2/include/stm32f2xx_hal_rtc_ex.h
+++ b/f2/include/stm32f2xx_hal_rtc_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_rtc_ex.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of RTC HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -52,12 +52,14 @@
/** @addtogroup RTCEx
* @{
- */
-
+ */
+
/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
+ * @{
+ */
-/**
- * @brief RTC Tamper structure definition
+/** @brief RTC Tamper structure definition
*/
typedef struct
{
@@ -65,18 +67,21 @@ typedef struct
This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
uint32_t PinSelection; /*!< Specifies the Tamper Pin.
- This parameter can be a value of @ref RTCEx_Tamper_Pins_Selection */
+ This parameter can be a value of @ref RTCEx_Tamper_Pins_Selection */
uint32_t Trigger; /*!< Specifies the Tamper Trigger.
This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
}RTC_TamperTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Constants
+/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
* @{
*/
-/** @defgroup RTCEx_Backup_Registers_Definitions
+/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions
* @{
*/
#define RTC_BKP_DR0 ((uint32_t)0x00000000)
@@ -99,90 +104,58 @@ typedef struct
#define RTC_BKP_DR17 ((uint32_t)0x00000011)
#define RTC_BKP_DR18 ((uint32_t)0x00000012)
#define RTC_BKP_DR19 ((uint32_t)0x00000013)
-
-#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
- ((BKP) == RTC_BKP_DR1) || \
- ((BKP) == RTC_BKP_DR2) || \
- ((BKP) == RTC_BKP_DR3) || \
- ((BKP) == RTC_BKP_DR4) || \
- ((BKP) == RTC_BKP_DR5) || \
- ((BKP) == RTC_BKP_DR6) || \
- ((BKP) == RTC_BKP_DR7) || \
- ((BKP) == RTC_BKP_DR8) || \
- ((BKP) == RTC_BKP_DR9) || \
- ((BKP) == RTC_BKP_DR10) || \
- ((BKP) == RTC_BKP_DR11) || \
- ((BKP) == RTC_BKP_DR12) || \
- ((BKP) == RTC_BKP_DR13) || \
- ((BKP) == RTC_BKP_DR14) || \
- ((BKP) == RTC_BKP_DR15) || \
- ((BKP) == RTC_BKP_DR16) || \
- ((BKP) == RTC_BKP_DR17) || \
- ((BKP) == RTC_BKP_DR18) || \
- ((BKP) == RTC_BKP_DR19))
/**
* @}
*/
-/** @defgroup RTCEx_Time_Stamp_Edges_definitions
+/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC TimeStamp Edges Definitions
* @{
*/
#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)
#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008)
-
-#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
- ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Pins_Definitions
+/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions
* @{
*/
#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E
-
-#define IS_TAMPER(TAMPER) ((TAMPER) == RTC_TAMPER_1)
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Pins_Selection
+/** @defgroup RTCEx_Tamper_Pins_Selection RTC tamper Pins Selection
* @{
*/
-#define RTC_TAMPERPIN_PC13 ((uint32_t)0x00000000)
-#define RTC_TAMPERPIN_PI8 ((uint32_t)0x00010000)
+#define RTC_TAMPERPIN_DEFAULT ((uint32_t)0x00000000)
+#define RTC_TAMPERPIN_POS1 ((uint32_t)0x00010000)
-#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TAMPERPIN_PC13) || \
- ((PIN) == RTC_TAMPERPIN_PI8))
/**
* @}
*/
-/** @defgroup RTCEx_TimeStamp_Pin_Selection
+/** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection
* @{
*/
-#define RTC_TIMESTAMPPIN_PC13 ((uint32_t)0x00000000)
-#define RTC_TIMESTAMPPIN_PI8 ((uint32_t)0x00020000)
+#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)
+#define RTC_TIMESTAMPPIN_POS1 ((uint32_t)0x00020000)
-#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_PC13) || \
- ((PIN) == RTC_TIMESTAMPPIN_PI8))
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Trigger_Definitions
+/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions
* @{
*/
#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)
#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)
-#define IS_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE))
/**
* @}
*/
-/** @defgroup RTCEx_Wakeup_Timer_Definitions
+/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wake-up Timer Definitions
* @{
*/
#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)
@@ -191,29 +164,15 @@ typedef struct
#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003)
#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004)
#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006)
-
-#define IS_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
-
-#define IS_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
/**
* @}
*/
-/** @defgroup RTCEx_Digital_Calibration_Definitions
+/** @defgroup RTCEx_Digital_Calibration_Definitions RTC Digital Calib Definitions
* @{
*/
#define RTC_CALIBSIGN_POSITIVE ((uint32_t)0x00000000)
#define RTC_CALIBSIGN_NEGATIVE ((uint32_t)0x00000080)
-
-#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \
- ((SIGN) == RTC_CALIBSIGN_NEGATIVE))
-
-#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
/**
* @}
*/
@@ -221,8 +180,16 @@ typedef struct
/**
* @}
*/
-
+
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
+ * @{
+ */
+
+/* ---------------------------------WAKEUPTIMER---------------------------------*/
+/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
+ * @{
+ */
/**
* @brief Enable the RTC WakeUp Timer peripheral.
@@ -232,67 +199,174 @@ typedef struct
#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
/**
- * @brief Enable the RTC TimeStamp peripheral.
+ * @brief Disable the RTC Wake-up Timer peripheral.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
+#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
/**
- * @brief Disable the RTC WakeUp Timer peripheral.
+ * @brief Enable the RTC WakeUpTimer interrupt.
* @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer A interrupt
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
+#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
- * @brief Disable the RTC TimeStamp peripheral.
+ * @brief Disable the RTC WakeUpTimer interrupt.
* @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer A interrupt
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
+#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/**
- * @brief Enable the Coarse calibration process.
+ * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
* @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer A interrupt
* @retval None
*/
-#define __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE))
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
/**
- * @brief Disable the Coarse calibration process.
+ * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
* @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
* @retval None
*/
-#define __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE))
+#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
/**
- * @brief Enable the RTC calibration output.
+ * @brief Get the selected RTC WakeUpTimer's flag status.
* @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC WakeUpTimer Flag to check.
+ * This parameter can be:
+ * @arg RTC_FLAG_WUTF
+ * @arg RTC_FLAG_WUTWF
* @retval None
*/
-#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
/**
- * @brief Disable the calibration output.
+ * @brief Clear the RTC Wake Up timer's pending flags.
* @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_WUTF
* @retval None
*/
-#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
- * @brief Enable the clock reference detection.
+ * @brief Enable interrupt on the RTC Wake-up Timer associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable interrupt on the RTC Wake-up Timer associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable event on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable event on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable falling edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable rising edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+ * @brief Check whether the RTC Wake-up Timer associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Clear the RTC Wake-up Timer associated Exti line flag.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Generate a Software interrupt on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @}
+ */
+
+/* ---------------------------------TIMESTAMP---------------------------------*/
+/** @defgroup RTCEx_Timestamp RTC Timestamp
+ * @{
+ */
+
+/**
+ * @brief Enable the RTC TimeStamp peripheral.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
*/
-#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
+#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
/**
- * @brief Disable the clock reference detection.
+ * @brief Disable the RTC TimeStamp peripheral.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
*/
-#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
+#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
/**
* @brief Enable the RTC TimeStamp interrupt.
@@ -305,129 +379,272 @@ typedef struct
#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
- * @brief Enable the RTC WakeUpTimer interrupt.
+ * @brief Disable the RTC TimeStamp interrupt.
* @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
* This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/**
- * @brief Disable the RTC TimeStamp interrupt.
+ * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
* @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt to check.
* This parameter can be:
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
/**
- * @brief Disable the RTC WakeUpTimer interrupt.
+ * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
* @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.
* This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
/**
- * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
+ * @brief Get the selected RTC TimeStamp's flag status.
* @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper interrupt sources to be enabled or disabled.
+ * @param __FLAG__: specifies the RTC TimeStamp flag to check.
* This parameter can be:
- * @arg RTC_IT_TAMP1
+ * @arg RTC_FLAG_TSF
+ * @arg RTC_FLAG_TSOVF
* @retval None
*/
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
/**
- * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
+ * @brief Clear the RTC Time Stamp's pending flags.
* @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
- * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
+ * @}
+ */
+
+/* ---------------------------------TAMPER------------------------------------*/
+/** @defgroup RTCEx_Tamper RTC Tamper
+ * @{
+ */
+
+/**
+ * @brief Enable the RTC Tamper1 input detection.
* @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
+#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
/**
- * @brief Get the selected RTC TimeStamp's flag status.
+ * @brief Disable the RTC Tamper1 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
* @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC TimeStamp Flag sources to be enabled or disabled.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check.
* This parameter can be:
- * @arg RTC_FLAG_TSF
- * @arg RTC_FLAG_TSOVF
+ * @arg RTC_IT_TAMP1
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
/**
- * @brief Get the selected RTC WakeUpTimer's flag status.
+ * @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
* @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC WakeUpTimer Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_WUTF
- * @arg RTC_FLAG_WUTWF
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP: Tamper interrupt
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
/**
* @brief Get the selected RTC Tamper's flag status.
* @param __HANDLE__: specifies the RTC handle.
* @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
* This parameter can be:
- * @arg RTC_FLAG_TAMP1F
+ * @arg RTC_FLAG_TAMP1F
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
/**
- * @brief Clear the RTC Time Stamp's pending flags.
+ * @brief Clear the RTC Tamper's pending flags.
* @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * @param __FLAG__: specifies the RTC Tamper Flag to clear.
* This parameter can be:
- * @arg RTC_FLAG_TSF
+ * @arg RTC_FLAG_TAMP1F
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+/**
+ * @}
+ */
+
+/* --------------------------TAMPER/TIMESTAMP---------------------------------*/
+/** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Tamper Timestamp EXTI
+ * @{
+ */
/**
- * @brief Clear the RTC Tamper's pending flags.
+ * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable event on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable event on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+ * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+/**
+ * @}
+ */
+
+/* ------------------------------Calibration----------------------------------*/
+/** @defgroup RTCEx_Calibration RTC Calibration
+ * @{
+ */
+
+/**
+ * @brief Enable the Coarse calibration process.
* @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_TAMP1F
* @retval None
*/
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#define __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE))
/**
- * @brief Clear the RTC Wake Up timer's pending flags.
+ * @brief Disable the Coarse calibration process.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE))
+
+/**
+ * @brief Enable the RTC calibration output.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
+
+/**
+ * @brief Disable the calibration output.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
+
+/**
+ * @brief Enable the clock reference detection.
* @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_WUTF
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
+
+/**
+ * @brief Disable the clock reference detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
+ * @{
+ */
+/** @addtogroup RTCEx_Exported_Functions_Group1
+ * @{
+ */
/* RTC TimeStamp and Tamper functions *****************************************/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
@@ -437,39 +654,134 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe
HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
-void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+ * @}
+ */
+/** @addtogroup RTCEx_Exported_Functions_Group2
+ * @{
+ */
/* RTC Wake-up functions ******************************************************/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
-uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+ * @}
+ */
+/** @addtogroup RTCEx_Exported_Functions_Group3
+ * @{
+ */
/* Extension Control functions ************************************************/
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value);
HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc);
HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+/** @addtogroup RTCEx_Exported_Functions_Group4
+ * @{
+ */
/* Extension RTC features functions *******************************************/
-void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
+ * @{
+ */
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR21) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR22) /*!< External interrupt line 22 Connected to the RTC Wake-up event */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
+ * @{
+ */
+
+/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
+ * @{
+ */
+#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
+ ((BKP) == RTC_BKP_DR1) || \
+ ((BKP) == RTC_BKP_DR2) || \
+ ((BKP) == RTC_BKP_DR3) || \
+ ((BKP) == RTC_BKP_DR4) || \
+ ((BKP) == RTC_BKP_DR5) || \
+ ((BKP) == RTC_BKP_DR6) || \
+ ((BKP) == RTC_BKP_DR7) || \
+ ((BKP) == RTC_BKP_DR8) || \
+ ((BKP) == RTC_BKP_DR9) || \
+ ((BKP) == RTC_BKP_DR10) || \
+ ((BKP) == RTC_BKP_DR11) || \
+ ((BKP) == RTC_BKP_DR12) || \
+ ((BKP) == RTC_BKP_DR13) || \
+ ((BKP) == RTC_BKP_DR14) || \
+ ((BKP) == RTC_BKP_DR15) || \
+ ((BKP) == RTC_BKP_DR16) || \
+ ((BKP) == RTC_BKP_DR17) || \
+ ((BKP) == RTC_BKP_DR18) || \
+ ((BKP) == RTC_BKP_DR19))
+#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
+ ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
+
+#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TAMPERPIN_DEFAULT) || \
+ ((PIN) == RTC_TAMPERPIN_POS1))
+
+#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT) || \
+ ((PIN) == RTC_TIMESTAMPPIN_POS1))
+
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE))
+
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
+
+#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
+#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \
+ ((SIGN) == RTC_CALIBSIGN_NEGATIVE))
+
+#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)!(RTC_TAFCR_TAMP1E))) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+/**
+ * @}
+ */
+/**
+ * @}
+ */
/**
* @}
@@ -478,7 +790,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
/**
* @}
*/
-
+
#ifdef __cplusplus
}
#endif
diff --git a/f2/include/stm32f2xx_hal_sd.h b/f2/include/stm32f2xx_hal_sd.h
index 0cba96d27d6d6663849eb5f3d5c4f84221aff387..6f05875a8915abe7bd83f86ad6405f0154933730 100755
--- a/f2/include/stm32f2xx_hal_sd.h
+++ b/f2/include/stm32f2xx_hal_sd.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_sd.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of SD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,24 +50,29 @@
* @{
*/
-/** @addtogroup SD
+/** @defgroup SD SD
+ * @brief SD HAL module driver
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
+/** @defgroup SD_Exported_Types SD Exported Types
+ * @{
+ */
+
+/** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition
+ * @{
+ */
#define SD_InitTypeDef SDIO_InitTypeDef
#define SD_TypeDef SDIO_TypeDef
-/**
- * @brief SDIO Handle Structure definition
- */
typedef struct
{
- SD_TypeDef *Instance; /*!< SDIO register base address */
+ SD_TypeDef *Instance; /*!< SDIO register base address */
SD_InitTypeDef Init; /*!< SD required parameters */
- HAL_LockTypeDef Lock; /*!< SD locking object */
+ HAL_LockTypeDef Lock; /*!< SD locking object */
uint32_t CardType; /*!< SD card type */
@@ -79,20 +84,23 @@ typedef struct
__IO uint32_t SdTransferCplt; /*!< SD transfer complete flag in non blocking mode */
- __IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */
+ __IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */
__IO uint32_t DmaTransferCplt; /*!< SD DMA transfer complete flag */
__IO uint32_t SdOperation; /*!< SD transfer operation (read/write) */
- DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
+ DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
}SD_HandleTypeDef;
-
/**
- * @brief Card Specific Data: CSD Register
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register
+ * @{
*/
typedef struct
{
@@ -135,10 +143,13 @@ typedef struct
__IO uint8_t Reserved4; /*!< Always 1 */
}HAL_SD_CSDTypedef;
-
/**
- * @brief Card Identification Data: CID Register
+ * @}
*/
+
+/** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register
+ * @{
+ */
typedef struct
{
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */
@@ -153,10 +164,13 @@ typedef struct
__IO uint8_t Reserved2; /*!< Always 1 */
}HAL_SD_CIDTypedef;
-
/**
- * @brief SD Card Status returned by ACMD13
+ * @}
*/
+
+/** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13
+ * @{
+ */
typedef struct
{
__IO uint8_t DAT_BUS_WIDTH; /*!< Shows the currently defined data bus width */
@@ -171,10 +185,13 @@ typedef struct
__IO uint8_t ERASE_OFFSET; /*!< Carries information about the erase offset */
}HAL_SD_CardStatusTypedef;
-
/**
- * @brief SD Card information structure
+ * @}
*/
+
+/** @defgroup SD_Exported_Types_Group5 SD Card information structure
+ * @{
+ */
typedef struct
{
HAL_SD_CSDTypedef SD_csd; /*!< SD card specific data register */
@@ -185,10 +202,13 @@ typedef struct
uint8_t CardType; /*!< SD card type */
}HAL_SD_CardInfoTypedef;
-
/**
- * @brief SD Error status enumeration Structure definition
+ * @}
*/
+
+/** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition
+ * @{
+ */
typedef enum
{
/**
@@ -199,7 +219,7 @@ typedef enum
SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */
SD_DATA_TIMEOUT = (4), /*!< Data timeout */
SD_TX_UNDERRUN = (5), /*!< Transmit FIFO underrun */
- SD_RX_OVERRUN = (6), /*!< Receive FIFO overrun */
+ SD_RX_OVERRUN = (6), /*!< Receive FIFO overrun */
SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in wide bus mode */
SD_CMD_OUT_OF_RANGE = (8), /*!< Command's argument was out of range. */
SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */
@@ -231,21 +251,24 @@ typedef enum
/**
* @brief Standard error defines
*/
- SD_INTERNAL_ERROR = (34),
+ SD_INTERNAL_ERROR = (34),
SD_NOT_CONFIGURED = (35),
- SD_REQUEST_PENDING = (36),
- SD_REQUEST_NOT_APPLICABLE = (37),
- SD_INVALID_PARAMETER = (38),
- SD_UNSUPPORTED_FEATURE = (39),
- SD_UNSUPPORTED_HW = (40),
- SD_ERROR = (41),
+ SD_REQUEST_PENDING = (36),
+ SD_REQUEST_NOT_APPLICABLE = (37),
+ SD_INVALID_PARAMETER = (38),
+ SD_UNSUPPORTED_FEATURE = (39),
+ SD_UNSUPPORTED_HW = (40),
+ SD_ERROR = (41),
SD_OK = (0)
}HAL_SD_ErrorTypedef;
-
/**
- * @brief SD Transfer state enumeration structure
- */
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure
+ * @{
+ */
typedef enum
{
SD_TRANSFER_OK = 0, /*!< Transfer success */
@@ -253,10 +276,13 @@ typedef enum
SD_TRANSFER_ERROR = 2 /*!< Transfer failed */
}HAL_SD_TransferStateTypedef;
-
/**
- * @brief SD Card State enumeration structure
- */
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure
+ * @{
+ */
typedef enum
{
SD_CARD_READY = ((uint32_t)0x00000001), /*!< Card state is ready */
@@ -270,10 +296,13 @@ typedef enum
SD_CARD_ERROR = ((uint32_t)0x000000FF) /*!< Card is in error state */
}HAL_SD_CardStateTypedef;
-
/**
- * @brief SD Operation enumeration structure
- */
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure
+ * @{
+ */
typedef enum
{
SD_READ_SINGLE_BLOCK = 0, /*!< Read single block operation */
@@ -282,10 +311,16 @@ typedef enum
SD_WRITE_MULTIPLE_BLOCK = 3 /*!< Write multiple blocks operation */
}HAL_SD_OperationTypedef;
+/**
+ * @}
+ */
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup SD_Exported_Constants
+/** @defgroup SD_Exported_Constants SD Exported Constants
* @{
*/
@@ -351,7 +386,7 @@ typedef enum
*/
#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
widths are given in SCR register. */
-#define SD_CMD_SD_APP_STAUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */
+#define SD_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */
#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
32bit+CRC data block. */
#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
@@ -393,11 +428,10 @@ typedef enum
*/
/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup SD_Interrupt_Clock
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
+/** @defgroup SD_Exported_macros SD Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
/**
* @brief Enable the SD device.
@@ -606,14 +640,24 @@ typedef enum
*/
/* Exported functions --------------------------------------------------------*/
+/** @defgroup SD_Exported_Functions SD Exported Functions
+ * @{
+ */
-/* Initialization/de-initialization functions **********************************/
+/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
+/**
+ * @}
+ */
-/* I/O operation functions *****************************************************/
+/** @defgroup SD_Exported_Functions_Group2 I/O operation functions
+ * @{
+ */
/* Blocking mode: Polling */
HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
@@ -635,31 +679,111 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pRead
HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
+/**
+ * @}
+ */
-/* Peripheral Control functions ************************************************/
+/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
-
-/* Peripheral State functions **************************************************/
+/**
+ * @}
+ */
+
+/* Peripheral State functions ************************************************/
+/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup SD_Private_Types SD Private Types
+ * @{
+ */
/**
* @}
*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SD_Private_Defines SD Private Defines
+ * @{
+ */
+
/**
* @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup SD_Private_Variables SD Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SD_Private_Constants SD Private Constants
+ * @{
*/
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SD_Private_Macros SD Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SD_Private_Functions SD Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
-
-#endif /* __STM32F2xx_HAL_SD_H */
+#endif /* __STM32F2xx_HAL_SD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f2/include/stm32f2xx_hal_smartcard.h b/f2/include/stm32f2xx_hal_smartcard.h
index dd923fa56d45a7c0aceb0a5a5e7fdb286a205efd..d734d343336b40fcbb9f8955efb45ed665465681 100755
--- a/f2/include/stm32f2xx_hal_smartcard.h
+++ b/f2/include/stm32f2xx_hal_smartcard.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_smartcard.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,7 +54,11 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
+ * @{
+ */
+
/**
* @brief SMARTCARD Init Structure definition
*/
@@ -78,7 +82,7 @@ typedef struct
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits).*/
- uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref SMARTCARD_Mode */
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
@@ -91,14 +95,16 @@ typedef struct
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref SMARTCARD_Last_Bit */
- uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler
- This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
-
- uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time
- This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
+ uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler value used for dividing the system clock
+ to provide the smartcard clock
+ This parameter can be a value of @ref SMARTCARD_Prescaler */
+
+ uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks
+ The value given in the register (5 significant bits) is multiplied by 2
+ to give the division factor of the source clock frequency */
- uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state
- This parameter can be a value of @ref SmartCard_NACK_State */
+ uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state.
+ This parameter can be a value of @ref SMARTCARD_NACK_State */
}SMARTCARD_InitTypeDef;
/**
@@ -106,28 +112,16 @@ typedef struct
*/
typedef enum
{
- HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
- HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
- HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
- HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
- HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */
+ HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
+ HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */
}HAL_SMARTCARD_StateTypeDef;
-/**
- * @brief HAL SMARTCARD Error Code structure definition
- */
-typedef enum
-{
- HAL_SMARTCARD_ERROR_NONE = 0x00, /*!< No error */
- HAL_SMARTCARD_ERROR_PE = 0x01, /*!< Parity error */
- HAL_SMARTCARD_ERROR_NE = 0x02, /*!< Noise error */
- HAL_SMARTCARD_ERROR_FE = 0x04, /*!< frame error */
- HAL_SMARTCARD_ERROR_ORE = 0x08, /*!< Overrun error */
- HAL_SMARTCARD_ERROR_DMA = 0x10 /*!< DMA transfer error */
-}HAL_SMARTCARD_ErrorTypeDef;
-
/**
* @brief SMARTCARD handle Structure definition
*/
@@ -135,7 +129,7 @@ typedef struct
{
USART_TypeDef *Instance; /* USART registers base address */
- SMARTCARD_InitTypeDef Init; /* SmartCard communication parameters */
+ SMARTCARD_InitTypeDef Init; /* SmartCard communication parameters */
uint8_t *pTxBuffPtr; /* Pointer to SmartCard Tx transfer Buffer */
@@ -153,127 +147,160 @@ typedef struct
DMA_HandleTypeDef *hdmarx; /* SmartCard Rx DMA Handle parameters */
- HAL_LockTypeDef Lock; /* Locking object */
+ HAL_LockTypeDef Lock; /* Locking object */
- __IO HAL_SMARTCARD_StateTypeDef State; /* SmartCard communication state */
+ __IO HAL_SMARTCARD_StateTypeDef State; /* SmartCard communication state */
+
+ __IO uint32_t ErrorCode; /* SmartCard Error code */
- __IO HAL_SMARTCARD_ErrorTypeDef ErrorCode; /* SMARTCARD Error code */
}SMARTCARD_HandleTypeDef;
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Constants
+/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants
* @{
*/
+/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
+ * @brief SMARTCARD Error Code
+ * @{
+ */
+#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004) /*!< Frame error */
+#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+/**
+ * @}
+ */
-/** @defgroup SMARTCARD_Word_Length
+/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
* @{
*/
-#define SMARTCARD_WORDLENGTH_8B ((uint32_t)0x00000000)
#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-#define IS_SMARTCARD_WORD_LENGTH(LENGTH) (((LENGTH) == SMARTCARD_WORDLENGTH_8B) || \
- ((LENGTH) == SMARTCARD_WORDLENGTH_9B))
/**
* @}
*/
-/** @defgroup SMARTCARD_Stop_Bits
+/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
* @{
*/
-#define SMARTCARD_STOPBITS_1 ((uint32_t)0x00000000)
#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
-#define SMARTCARD_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
-#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_1) || \
- ((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
- ((STOPBITS) == SMARTCARD_STOPBITS_1_5) || \
- ((STOPBITS) == SMARTCARD_STOPBITS_2))
/**
* @}
*/
-/** @defgroup SMARTCARD_Parity
+/** @defgroup SMARTCARD_Parity SMARTCARD Parity
* @{
*/
-#define SMARTCARD_PARITY_NONE ((uint32_t)0x00000000)
#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_NONE) || \
- ((PARITY) == SMARTCARD_PARITY_EVEN) || \
- ((PARITY) == SMARTCARD_PARITY_ODD))
/**
* @}
*/
-/** @defgroup SMARTCARD_Mode
+/** @defgroup SMARTCARD_Mode SMARTCARD Mode
* @{
*/
#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
/**
* @}
*/
-/** @defgroup SMARTCARD_Clock_Polarity
+/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
* @{
*/
#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000)
#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
-#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
/**
* @}
*/
-/** @defgroup SMARTCARD_Clock_Phase
+/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
* @{
*/
#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000)
#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
-#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
/**
* @}
*/
-/** @defgroup SMARTCARD_Last_Bit
+/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
* @{
*/
#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000)
#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
-#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
- ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
/**
* @}
*/
-/** @defgroup SmartCard_NACK_State
+/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State
* @{
*/
-#define SMARTCARD_NACK_ENABLED ((uint32_t)USART_CR3_NACK)
-#define SMARTCARD_NACK_DISABLED ((uint32_t)0x00000000)
-#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLED) || \
- ((NACK) == SMARTCARD_NACK_DISABLED))
+#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
+#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000)
/**
* @}
*/
-/** @defgroup SmartCard_DMA_Requests
+/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests
* @{
*/
-
#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
+/**
+ * @}
+ */
+/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
+ * @{
+ */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV2 ((uint32_t)0x00000001) /*!< SYSCLK divided by 2 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV4 ((uint32_t)0x00000002) /*!< SYSCLK divided by 4 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV6 ((uint32_t)0x00000003) /*!< SYSCLK divided by 6 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV8 ((uint32_t)0x00000004) /*!< SYSCLK divided by 8 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV10 ((uint32_t)0x00000005) /*!< SYSCLK divided by 10 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV12 ((uint32_t)0x00000006) /*!< SYSCLK divided by 12 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV14 ((uint32_t)0x00000007) /*!< SYSCLK divided by 14 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV16 ((uint32_t)0x00000008) /*!< SYSCLK divided by 16 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV18 ((uint32_t)0x00000009) /*!< SYSCLK divided by 18 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV20 ((uint32_t)0x0000000A) /*!< SYSCLK divided by 20 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV22 ((uint32_t)0x0000000B) /*!< SYSCLK divided by 22 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV24 ((uint32_t)0x0000000C) /*!< SYSCLK divided by 24 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV26 ((uint32_t)0x0000000D) /*!< SYSCLK divided by 26 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV28 ((uint32_t)0x0000000E) /*!< SYSCLK divided by 28 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV30 ((uint32_t)0x0000000F) /*!< SYSCLK divided by 30 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV32 ((uint32_t)0x00000010) /*!< SYSCLK divided by 32 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV34 ((uint32_t)0x00000011) /*!< SYSCLK divided by 34 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV36 ((uint32_t)0x00000012) /*!< SYSCLK divided by 36 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV38 ((uint32_t)0x00000013) /*!< SYSCLK divided by 38 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV40 ((uint32_t)0x00000014) /*!< SYSCLK divided by 40 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV42 ((uint32_t)0x00000015) /*!< SYSCLK divided by 42 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV44 ((uint32_t)0x00000016) /*!< SYSCLK divided by 44 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV46 ((uint32_t)0x00000017) /*!< SYSCLK divided by 46 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV48 ((uint32_t)0x00000018) /*!< SYSCLK divided by 48 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV50 ((uint32_t)0x00000019) /*!< SYSCLK divided by 50 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV52 ((uint32_t)0x0000001A) /*!< SYSCLK divided by 52 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV54 ((uint32_t)0x0000001B) /*!< SYSCLK divided by 54 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV56 ((uint32_t)0x0000001C) /*!< SYSCLK divided by 56 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV58 ((uint32_t)0x0000001D) /*!< SYSCLK divided by 58 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV60 ((uint32_t)0x0000001E) /*!< SYSCLK divided by 60 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV62 ((uint32_t)0x0000001F) /*!< SYSCLK divided by 62 */
/**
* @}
*/
-/** @defgroup SmartCard_Flags
+/** @defgroup SMARTCARD_Flags SMARTCARD Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the SR register
* @{
*/
-
#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080)
#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040)
#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020)
@@ -286,23 +313,20 @@ typedef struct
* @}
*/
-/** @defgroup SmartCard_Interrupt_definition
+/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition
* Elements values convention: 0xY000XXXX
* - XXXX : Interrupt mask in the XX register
* - Y : Interrupt source register (2bits)
* - 01: CR1 register
* - 10: CR3 register
-
- *
* @{
*/
-#define SMARTCARD_IT_PE ((uint32_t)0x10000100)
-#define SMARTCARD_IT_TXE ((uint32_t)0x10000080)
-#define SMARTCARD_IT_TC ((uint32_t)0x10000040)
-#define SMARTCARD_IT_RXNE ((uint32_t)0x10000020)
-#define SMARTCARD_IT_IDLE ((uint32_t)0x10000010)
-#define SMARTCARD_IT_ERR ((uint32_t)0x20000001)
-
+#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
+#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
+#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
+#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
+#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
+#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28 | USART_CR3_EIE))
/**
* @}
*/
@@ -312,8 +336,17 @@ typedef struct
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
+ * @{
+ */
-/** @brief Flushs the Smartcard DR register
+/** @brief Reset SMARTCARD handle state
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
+
+/** @brief Flushes the Smartcard DR register
* @param __HANDLE__: specifies the SMARTCARD Handle.
*/
#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
@@ -326,7 +359,7 @@ typedef struct
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
* @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag
- * @arg SMARTCARD_FLAG_ORE: OverRun Error flag
+ * @arg SMARTCARD_FLAG_ORE: Overrun Error flag
* @arg SMARTCARD_FLAG_NE: Noise Error flag
* @arg SMARTCARD_FLAG_FE: Framing Error flag
* @arg SMARTCARD_FLAG_PE: Parity Error flag
@@ -341,7 +374,7 @@ typedef struct
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag.
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
*
- * @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (OverRun
+ * @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (Overrun
* error) flags are cleared by software sequence: a read operation to
* USART_SR register followed by a read operation to USART_DR register.
* @note RXNE flag can be also cleared by a read to the USART_DR register.
@@ -349,7 +382,54 @@ typedef struct
* USART_SR register followed by a write operation to USART_DR register.
* @note TXE flag is cleared only by a write to the USART_DR register.
*/
-#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/** @brief Clear the SMARTCARD PE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ UNUSED(tmpreg); \
+ } while(0)
+
+/** @brief Clear the SMARTCARD FE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the SMARTCARD NE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the SMARTCARD ORE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the SMARTCARD IDLE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
+
/** @brief Enables or disables the specified SmartCard interrupts.
* @param __HANDLE__: specifies the SMARTCARD Handle.
@@ -362,11 +442,10 @@ typedef struct
* @arg SMARTCARD_IT_PE: Parity Error interrupt
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
*/
-#define SMARTCARD_IT_MASK ((uint32_t)0x0000FFFF)
-#define __SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
-#define __SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
* @param __HANDLE__: specifies the SmartCard Handle.
@@ -382,11 +461,31 @@ typedef struct
*/
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
-/** @brief Macros to enable or disable the SmartCard interface.
- * @param __HANDLE__: specifies the SmartCard Handle.
+/** @brief Macro to enable the SMARTCARD's one bit sample method
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Macro to disable the SMARTCARD's one bit sample method
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
+
+/** @brief Enable the USART associated to the SMARTCARD Handle
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable the USART associated to the SMARTCARD Handle
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
*/
-#define __SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-#define __SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/** @brief Macros to enable or disable the SmartCard DMA request.
* @param __HANDLE__: specifies the SmartCard Handle.
@@ -395,23 +494,34 @@ typedef struct
* @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
* @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
*/
-#define __SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
-#define __SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
+#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
+#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
-#define __DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
-#define __DIVMANT(_PCLK_, _BAUD_) (__DIV((_PCLK_), (_BAUD_))/100)
-#define __DIVFRAQ(_PCLK_, _BAUD_) (((__DIV((_PCLK_), (_BAUD_)) - (__DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-#define __SMARTCARD_BRR(_PCLK_, _BAUD_) ((__DIVMANT((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
-
-#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 7500001)
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARD_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SMARTCARD_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
+/**
+ * @}
+ */
+
+/** @addtogroup SMARTCARD_Exported_Functions_Group2
+ * @{
+ */
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -423,10 +533,16 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
+/**
+ * @}
+ */
+/** @addtogroup SMARTCARD_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral State functions **************************************************/
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
/**
* @}
@@ -435,7 +551,66 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
/**
* @}
*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
+ * @{
+ */
+/** @brief SMARTCARD interruptions flag mask
+ *
+ */
+#define SMARTCARD_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
+ USART_CR1_IDLEIE | USART_CR3_EIE )
+#define SMARTCARD_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
+#define SMARTCARD_DIVMANT(_PCLK_, _BAUD_) (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100)
+#define SMARTCARD_DIVFRAQ(_PCLK_, _BAUD_) (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define SMARTCARD_BRR(_PCLK_, _BAUD_) ((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4)|(SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define SMARTCARD_CR1_REG_INDEX 1
+#define SMARTCARD_CR3_REG_INDEX 3
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
+ * @{
+ */
+#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
+#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
+ ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
+#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
+ ((PARITY) == SMARTCARD_PARITY_ODD))
+#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
+#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
+#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
+#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
+ ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
+#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \
+ ((NACK) == SMARTCARD_NACK_DISABLE))
+#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 7500001)
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
#ifdef __cplusplus
}
#endif
diff --git a/f2/include/stm32f2xx_hal_spi.h b/f2/include/stm32f2xx_hal_spi.h
index 086d9360a536de78e4d0bd4cdd64c0eee6ba7003..1cd4c09dd4c2b7a6404c1cc1739a13098c679ab9 100755
--- a/f2/include/stm32f2xx_hal_spi.h
+++ b/f2/include/stm32f2xx_hal_spi.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_spi.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,7 +55,10 @@
*/
/* Exported types ------------------------------------------------------------*/
-
+/** @defgroup SPI_Exported_Types SPI Exported Types
+ * @{
+ */
+
/**
* @brief SPI Configuration Structure definition
*/
@@ -115,21 +118,6 @@ typedef enum
}HAL_SPI_StateTypeDef;
-/**
- * @brief HAL SPI Error Code structure definition
- */
-typedef enum
-{
- HAL_SPI_ERROR_NONE = 0x00, /*!< No error */
- HAL_SPI_ERROR_MODF = 0x01, /*!< MODF error */
- HAL_SPI_ERROR_CRC = 0x02, /*!< CRC error */
- HAL_SPI_ERROR_OVR = 0x04, /*!< OVR error */
- HAL_SPI_ERROR_FRE = 0x08, /*!< FRE error */
- HAL_SPI_ERROR_DMA = 0x10, /*!< DMA transfer error */
- HAL_SPI_ERROR_FLAG = 0x20 /*!< Flag: RXNE,TXE, BSY */
-
-}HAL_SPI_ErrorTypeDef;
-
/**
* @brief SPI handle Structure definition
*/
@@ -163,99 +151,90 @@ typedef struct __SPI_HandleTypeDef
__IO HAL_SPI_StateTypeDef State; /* SPI communication state */
- __IO HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */
+ __IO uint32_t ErrorCode; /* SPI Error code */
}SPI_HandleTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPI_Exported_Constants SPI Exported Constants
+ * @{
+ */
-/** @defgroup SPI_Exported_Constants
+/** @defgroup SPI_Error_Code SPI Error Code
+ * @brief SPI Error Code
* @{
+ */
+#define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001) /*!< MODF error */
+#define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002) /*!< CRC error */
+#define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004) /*!< OVR error */
+#define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008) /*!< FRE error */
+#define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+#define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020) /*!< Flag: RXNE,TXE, BSY */
+/**
+ * @}
*/
-/** @defgroup SPI_mode
+/** @defgroup SPI_mode SPI Mode
* @{
*/
#define SPI_MODE_SLAVE ((uint32_t)0x00000000)
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
-
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
- ((MODE) == SPI_MODE_MASTER))
/**
* @}
*/
-/** @defgroup SPI_Direction_mode
+/** @defgroup SPI_Direction_mode SPI Direction Mode
* @{
*/
#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
-
-#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
- ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
- ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
- ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
-
/**
* @}
*/
-/** @defgroup SPI_data_size
+/** @defgroup SPI_data_size SPI Data Size
* @{
*/
#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000)
#define SPI_DATASIZE_16BIT SPI_CR1_DFF
-
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
- ((DATASIZE) == SPI_DATASIZE_8BIT))
/**
* @}
*/
-/** @defgroup SPI_Clock_Polarity
+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
* @{
*/
#define SPI_POLARITY_LOW ((uint32_t)0x00000000)
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
-
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
- ((CPOL) == SPI_POLARITY_HIGH))
/**
* @}
*/
-/** @defgroup SPI_Clock_Phase
+/** @defgroup SPI_Clock_Phase SPI Clock Phase
* @{
*/
#define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
-
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
- ((CPHA) == SPI_PHASE_2EDGE))
/**
* @}
*/
-/** @defgroup SPI_Slave_Select_management
+/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
* @{
*/
#define SPI_NSS_SOFT SPI_CR1_SSM
#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
-
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
- ((NSS) == SPI_NSS_HARD_INPUT) || \
- ((NSS) == SPI_NSS_HARD_OUTPUT))
/**
* @}
*/
-/** @defgroup SPI_BaudRate_Prescaler
+/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
* @{
*/
#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
@@ -266,56 +245,38 @@ typedef struct __SPI_HandleTypeDef
#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
-
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
/**
* @}
*/
-/** @defgroup SPI_MSB_LSB_transmission
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transsmission
* @{
*/
#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
-
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
- ((BIT) == SPI_FIRSTBIT_LSB))
/**
* @}
*/
-/** @defgroup SPI_TI_mode
+/** @defgroup SPI_TI_mode SPI TI Mode
* @{
*/
-#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000)
-#define SPI_TIMODE_ENABLED SPI_CR2_FRF
-
-#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \
- ((MODE) == SPI_TIMODE_ENABLED))
+#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000)
+#define SPI_TIMODE_ENABLE SPI_CR2_FRF
/**
* @}
*/
-/** @defgroup SPI_CRC_Calculation
+/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
* @{
*/
-#define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000)
-#define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN
-
-#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \
- ((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
+#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)
+#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
/**
* @}
*/
-/** @defgroup SPI_Interrupt_configuration_definition
+/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
* @{
*/
#define SPI_IT_TXE SPI_CR2_TXEIE
@@ -325,7 +286,7 @@ typedef struct __SPI_HandleTypeDef
* @}
*/
-/** @defgroup SPI_Flag_definition
+/** @defgroup SPI_Flags_definition SPI Flags Definition
* @{
*/
#define SPI_FLAG_RXNE SPI_SR_RXNE
@@ -335,7 +296,6 @@ typedef struct __SPI_HandleTypeDef
#define SPI_FLAG_OVR SPI_SR_OVR
#define SPI_FLAG_BSY SPI_SR_BSY
#define SPI_FLAG_FRE SPI_SR_FRE
-
/**
* @}
*/
@@ -345,6 +305,15 @@ typedef struct __SPI_HandleTypeDef
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Macros SPI Exported Macros
+ * @{
+ */
+/** @brief Reset SPI handle state
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
/** @brief Enable or disable the specified SPI interrupts.
* @param __HANDLE__: specifies the SPI handle.
@@ -392,51 +361,81 @@ typedef struct __SPI_HandleTypeDef
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR &= ~(SPI_FLAG_CRCERR))
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR))
/** @brief Clear the SPI MODF pending flag.
* @param __HANDLE__: specifies the SPI handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
- (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);}while(0)
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
+ UNUSED(tmpreg); \
+ } while(0)
/** @brief Clear the SPI OVR pending flag.
* @param __HANDLE__: specifies the SPI handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
- (__HANDLE__)->Instance->SR;}while(0)
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ } while(0)
/** @brief Clear the SPI FRE pending flag.
* @param __HANDLE__: specifies the SPI handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
+ */
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ }while(0)
+
+/** @brief Enable SPI
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
*/
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR)
-
#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
-#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_SPE)
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
-
-#define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
-
-#define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_BIDIOE)
-
-#define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_CRCEN);\
- (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
+/** @brief Disable SPI
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_SPE)
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_Exported_Functions
+ * @{
+ */
+/** @addtogroup SPI_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+/** @addtogroup SPI_Exported_Functions_Group2
+ * @{
+ */
/* I/O operation functions *****************************************************/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -447,15 +446,116 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
-
+void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral State and Control functions **************************************/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SPI_Private_Constants SPI Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
+ * @{
+ */
+
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
+ ((MODE) == SPI_MODE_MASTER))
+
+
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
+ ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
+
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_8BIT))
+
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
+ ((CPOL) == SPI_POLARITY_HIGH))
+
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
+ ((CPHA) == SPI_PHASE_2EDGE))
+
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
+ ((NSS) == SPI_NSS_HARD_INPUT) || \
+ ((NSS) == SPI_NSS_HARD_OUTPUT))
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
+
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
+ ((BIT) == SPI_FIRSTBIT_LSB))
+
+#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
+ ((MODE) == SPI_TIMODE_ENABLE))
+
+#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
+ ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
+
+#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
+
+#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_BIDIOE)
+
+#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_CRCEN);\
+ (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SPI_Private_Functions SPI Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
/**
* @}
@@ -464,6 +564,7 @@ HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
/**
* @}
*/
+
#ifdef __cplusplus
}
diff --git a/f2/include/stm32f2xx_hal_sram.h b/f2/include/stm32f2xx_hal_sram.h
index f44b7e937af4a11fb08eff1d35c165ae7bdfeba4..6ccc63c3531caf4e5e037a9370fedc1e0eed8717 100755
--- a/f2/include/stm32f2xx_hal_sram.h
+++ b/f2/include/stm32f2xx_hal_sram.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_sram.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of SRAM HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -56,6 +56,9 @@
/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup SRAM_Exported_Types SRAM Exported Types
+ * @{
+ */
/**
* @brief HAL SRAM State structures definition
*/
@@ -74,11 +77,11 @@ typedef enum
*/
typedef struct
{
- FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
+ FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
- FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
+ FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
- FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
+ FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
HAL_LockTypeDef Lock; /*!< SRAM locking object */
@@ -88,16 +91,49 @@ typedef struct
}SRAM_HandleTypeDef;
-/* Exported constants --------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
+ * @{
+ */
+/** @brief Reset SRAM handle state
+ * @param __HANDLE__: SRAM handle
+ * @retval None
+ */
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
+
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SRAM_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
-void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
-void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
+
+void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+/** @addtogroup SRAM_Exported_Functions_Group2
+ * @{
+ */
/* I/O operation functions *****************************************************/
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
@@ -107,17 +143,38 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+/**
+ * @}
+ */
-void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
-
+/** @addtogroup SRAM_Exported_Functions_Group3
+ * @{
+ */
/* SRAM Control functions ******************************************************/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
+/**
+ * @}
+ */
+/** @addtogroup SRAM_Exported_Functions_Group4
+ * @{
+ */
/* SRAM State functions *********************************************************/
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
@@ -125,7 +182,6 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
/**
* @}
*/
-
#ifdef __cplusplus
}
#endif
diff --git a/f2/include/stm32f2xx_hal_tim.h b/f2/include/stm32f2xx_hal_tim.h
index 1d09776e9a702bddcd0f17700daa3255f39295cf..9673b6678711e317b78a009a9c3abc9c4454f46a 100755
--- a/f2/include/stm32f2xx_hal_tim.h
+++ b/f2/include/stm32f2xx_hal_tim.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_tim.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -46,16 +46,19 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f2xx_hal_def.h"
-/** @addtogroup STM32F2xx_HAL
+/** @addtogroup STM32F2xx_HAL_Driver
* @{
*/
/** @addtogroup TIM
* @{
- */
-
-/* Exported types ------------------------------------------------------------*/
+ */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+ * @{
+ */
+
/**
* @brief TIM Time base Configuration Structure definition
*/
@@ -69,7 +72,7 @@ typedef struct
uint32_t Period; /*!< Specifies the period value to be loaded into the active
Auto-Reload Register at the next update event.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t ClockDivision; /*!< Specifies the clock division.
This parameter can be a value of @ref TIM_ClockDivision */
@@ -89,12 +92,12 @@ typedef struct
*/
typedef struct
-{
+{
uint32_t OCMode; /*!< Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t OCPolarity; /*!< Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
@@ -121,12 +124,12 @@ typedef struct
* @brief TIM One Pulse Mode Configuration Structure definition
*/
typedef struct
-{
+{
uint32_t OCMode; /*!< Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t OCPolarity; /*!< Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
@@ -159,7 +162,7 @@ typedef struct
*/
typedef struct
-{
+{
uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
@@ -204,7 +207,7 @@ typedef struct
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t IC2Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_Encoder_InitTypeDef;
/**
@@ -212,14 +215,14 @@ typedef struct
*/
typedef struct
{
- uint32_t ClockSource; /*!< TIM clock sources
+ uint32_t ClockSource; /*!< TIM clock sources.
This parameter can be a value of @ref TIM_Clock_Source */
- uint32_t ClockPolarity; /*!< TIM clock polarity
+ uint32_t ClockPolarity; /*!< TIM clock polarity.
This parameter can be a value of @ref TIM_Clock_Polarity */
- uint32_t ClockPrescaler; /*!< TIM clock prescaler
+ uint32_t ClockPrescaler; /*!< TIM clock prescaler.
This parameter can be a value of @ref TIM_Clock_Prescaler */
- uint32_t ClockFilter; /*!< TIM clock filter
- This parameter can be a value of @ref TIM_Clock_Filter */
+ uint32_t ClockFilter; /*!< TIM clock filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
}TIM_ClockConfigTypeDef;
/**
@@ -227,16 +230,16 @@ typedef struct
*/
typedef struct
{
- uint32_t ClearInputState; /*!< TIM clear Input state
+ uint32_t ClearInputState; /*!< TIM clear Input state.
This parameter can be ENABLE or DISABLE */
- uint32_t ClearInputSource; /*!< TIM clear Input sources
+ uint32_t ClearInputSource; /*!< TIM clear Input sources.
This parameter can be a value of @ref TIM_ClearInput_Source */
- uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
+ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
This parameter can be a value of @ref TIM_ClearInput_Polarity */
- uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
+ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
This parameter can be a value of @ref TIM_ClearInput_Prescaler */
- uint32_t ClearInputFilter; /*!< TIM Clear Input filter
- This parameter can be a value of @ref TIM_ClearInput_Filter */
+ uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
}TIM_ClearInputConfigTypeDef;
/**
@@ -252,7 +255,7 @@ typedef struct {
uint32_t TriggerPrescaler; /*!< Input trigger prescaler
This parameter can be a value of @ref TIM_Trigger_Prescaler */
uint32_t TriggerFilter; /*!< Input trigger filter
- This parameter can be a value of @ref TIM_Trigger_Filter */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
}TIM_SlaveConfigTypeDef;
@@ -263,9 +266,9 @@ typedef enum
{
HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
- HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+ HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
+ HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
}HAL_TIM_StateTypeDef;
/**
@@ -275,9 +278,9 @@ typedef enum
{
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
- HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
- HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
}HAL_TIM_ActiveChannel;
/**
@@ -285,21 +288,24 @@ typedef enum
*/
typedef struct
{
- TIM_TypeDef *Instance; /*!< Register base address */
+ TIM_TypeDef *Instance; /*!< Register base address */
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
- HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
This array is accessed by a @ref DMA_Handle_index */
HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
}TIM_HandleTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Constants
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
* @{
*/
-/** @defgroup TIM_Input_Channel_Polarity
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
* @{
*/
#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
@@ -309,18 +315,18 @@ typedef struct
* @}
*/
-/** @defgroup TIM_ETR_Polarity
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
* @{
*/
-#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
/**
* @}
*/
-/** @defgroup TIM_ETR_Prescaler
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
* @{
- */
+ */
#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
@@ -329,44 +335,31 @@ typedef struct
* @}
*/
-/** @defgroup TIM_Counter_Mode
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
* @{
*/
-
#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
-
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
- ((MODE) == TIM_COUNTERMODE_DOWN) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
/**
* @}
- */
-
-/** @defgroup TIM_ClockDivision
- * @{
*/
+/** @defgroup TIM_ClockDivision TIM Clock Division
+ * @{
+ */
#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
-
-#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
- ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
- ((DIV) == TIM_CLOCKDIVISION_DIV4))
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_and_PWM_modes
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
* @{
*/
-
#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
@@ -376,208 +369,123 @@ typedef struct
#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
-#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
- ((MODE) == TIM_OCMODE_PWM2))
-
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
- ((MODE) == TIM_OCMODE_ACTIVE) || \
- ((MODE) == TIM_OCMODE_INACTIVE) || \
- ((MODE) == TIM_OCMODE_TOGGLE) || \
- ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
- ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_State
- * @{
- */
-
-#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
-#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
-
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
- ((STATE) == TIM_OUTPUTSTATE_ENABLE))
-/**
- * @}
- */
-/** @defgroup TIM_Output_Fast_State
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
* @{
*/
#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
-
-#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
- ((STATE) == TIM_OCFAST_ENABLE))
/**
* @}
- */
-/** @defgroup TIM_Output_Compare_N_State
- * @{
*/
-#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
-#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
-
-#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
- ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Polarity
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
* @{
*/
-
#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
-
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
- ((POLARITY) == TIM_OCPOLARITY_LOW))
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_N_Polarity
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
* @{
*/
-
#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
-
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
- ((POLARITY) == TIM_OCNPOLARITY_LOW))
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_Idle_State
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
* @{
*/
-
#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
- ((STATE) == TIM_OCIDLESTATE_RESET))
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_N_Idle_State
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
* @{
*/
-
#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
- ((STATE) == TIM_OCNIDLESTATE_RESET))
/**
* @}
*/
-/** @defgroup TIM_Channel
+/** @defgroup TIM_Channel TIM Channel
* @{
*/
-
#define TIM_CHANNEL_1 ((uint32_t)0x0000)
#define TIM_CHANNEL_2 ((uint32_t)0x0004)
#define TIM_CHANNEL_3 ((uint32_t)0x0008)
#define TIM_CHANNEL_4 ((uint32_t)0x000C)
#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
-#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4) || \
- ((CHANNEL) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2))
-
-#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2))
-
-#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3))
/**
* @}
- */
-
+ */
-/** @defgroup TIM_Input_Capture_Polarity
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
* @{
*/
-
#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
-
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
- ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
- ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
/**
* @}
- */
+ */
-/** @defgroup TIM_Input_Capture_Selection
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
-
#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
connected to IC1, IC2, IC3 or IC4, respectively */
#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
connected to IC2, IC1, IC4 or IC3, respectively */
#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
- ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
- ((SELECTION) == TIM_ICSELECTION_TRC))
/**
* @}
- */
+ */
-/** @defgroup TIM_Input_Capture_Prescaler
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
* @{
*/
-
#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
-
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
- ((PRESCALER) == TIM_ICPSC_DIV2) || \
- ((PRESCALER) == TIM_ICPSC_DIV4) || \
- ((PRESCALER) == TIM_ICPSC_DIV8))
/**
* @}
*/
-/** @defgroup TIM_One_Pulse_Mode
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
* @{
*/
-
#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
- ((MODE) == TIM_OPMODE_REPETITIVE))
/**
* @}
- */
-/** @defgroup TIM_Encoder_Mode
+ */
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
* @{
- */
+ */
#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
- ((MODE) == TIM_ENCODERMODE_TI2) || \
- ((MODE) == TIM_ENCODERMODE_TI12))
+
/**
* @}
- */
-/** @defgroup TIM_Interrupt_definition
+ */
+
+/** @defgroup TIM_Interrupt_definition TIM Interrupt definition
* @{
*/
#define TIM_IT_UPDATE (TIM_DIER_UIE)
@@ -588,27 +496,22 @@ typedef struct
#define TIM_IT_COM (TIM_DIER_COMIE)
#define TIM_IT_TRIGGER (TIM_DIER_TIE)
#define TIM_IT_BREAK (TIM_DIER_BIE)
-
-#define IS_TIM_IT(IT) ((((IT) & 0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000))
-
-#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) || \
- ((IT) == TIM_IT_CC1) || \
- ((IT) == TIM_IT_CC2) || \
- ((IT) == TIM_IT_CC3) || \
- ((IT) == TIM_IT_CC4) || \
- ((IT) == TIM_IT_COM) || \
- ((IT) == TIM_IT_TRIGGER) || \
- ((IT) == TIM_IT_BREAK))
/**
* @}
*/
+
+/** @defgroup TIM_Commutation_Source TIM Commutation Source
+ * @{
+ */
#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
+/**
+ * @}
+ */
-/** @defgroup TIM_DMA_sources
+/** @defgroup TIM_DMA_sources TIM DMA sources
* @{
*/
-
#define TIM_DMA_UPDATE (TIM_DIER_UDE)
#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
@@ -616,34 +519,29 @@ typedef struct
#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
#define TIM_DMA_COM (TIM_DIER_COMDE)
#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
-
/**
* @}
*/
-
-/** @defgroup TIM_Event_Source
+
+/** @defgroup TIM_Event_Source TIM Event Source
* @{
*/
+#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
+#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
+#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
+#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
-#define TIM_EventSource_Update TIM_EGR_UG
-#define TIM_EventSource_CC1 TIM_EGR_CC1G
-#define TIM_EventSource_CC2 TIM_EGR_CC2G
-#define TIM_EventSource_CC3 TIM_EGR_CC3G
-#define TIM_EventSource_CC4 TIM_EGR_CC4G
-#define TIM_EventSource_COM TIM_EGR_COMG
-#define TIM_EventSource_Trigger TIM_EGR_TG
-#define TIM_EventSource_Break TIM_EGR_BG
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
-
/**
* @}
- */
+ */
-/** @defgroup TIM_Flag_definition
+/** @defgroup TIM_Flag_definition TIM Flag definition
* @{
- */
-
+ */
#define TIM_FLAG_UPDATE (TIM_SR_UIF)
#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
@@ -656,26 +554,13 @@ typedef struct
#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
-
-#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \
- ((FLAG) == TIM_FLAG_CC1) || \
- ((FLAG) == TIM_FLAG_CC2) || \
- ((FLAG) == TIM_FLAG_CC3) || \
- ((FLAG) == TIM_FLAG_CC4) || \
- ((FLAG) == TIM_FLAG_COM) || \
- ((FLAG) == TIM_FLAG_TRIGGER) || \
- ((FLAG) == TIM_FLAG_BREAK) || \
- ((FLAG) == TIM_FLAG_CC1OF) || \
- ((FLAG) == TIM_FLAG_CC2OF) || \
- ((FLAG) == TIM_FLAG_CC3OF) || \
- ((FLAG) == TIM_FLAG_CC4OF))
/**
* @}
*/
-/** @defgroup TIM_Clock_Source
+/** @defgroup TIM_Clock_Source TIM Clock Source
* @{
- */
+ */
#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
@@ -686,22 +571,11 @@ typedef struct
#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
-
-#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
/**
* @}
- */
+ */
-/** @defgroup TIM_Clock_Polarity
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
* @{
*/
#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
@@ -709,159 +583,106 @@ typedef struct
#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
-
-#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
/**
* @}
*/
-/** @defgroup TIM_Clock_Prescaler
- * @{
- */
-#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
-#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
-/**
- * @}
- */
-/** @defgroup TIM_Clock_Filter
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
* @{
*/
-
-#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
/**
* @}
- */
+ */
-/** @defgroup TIM_ClearInput_Source
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
* @{
*/
#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
-
-#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
- ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
/**
* @}
*/
-/** @defgroup TIM_ClearInput_Polarity
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
* @{
*/
#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
-#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
- ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
/**
* @}
- */
+ */
-/** @defgroup TIM_ClearInput_Prescaler
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
* @{
*/
#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
-#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
/**
* @}
*/
-
-/** @defgroup TIM_ClearInput_Filter
- * @{
- */
-#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
* @{
*/
#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
-#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
-
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
- ((STATE) == TIM_OSSR_DISABLE))
+#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
/**
* @}
*/
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
* @{
*/
#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
-
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
- ((STATE) == TIM_OSSI_DISABLE))
/**
* @}
*/
-/** @defgroup TIM_Lock_level
+
+/** @defgroup TIM_Lock_level TIM Lock level
* @{
*/
#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
-
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
- ((LEVEL) == TIM_LOCKLEVEL_1) || \
- ((LEVEL) == TIM_LOCKLEVEL_2) || \
- ((LEVEL) == TIM_LOCKLEVEL_3))
/**
* @}
*/
-/** @defgroup TIM_Break_Input_enable_disable
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
* @{
*/
#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
-
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
- ((STATE) == TIM_BREAK_DISABLE))
/**
* @}
*/
-/** @defgroup TIM_Break_Polarity
+
+/** @defgroup TIM_Break_Polarity TIM Break Polarity
* @{
*/
#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
-
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
- ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
/**
* @}
*/
-/** @defgroup TIM_AOE_Bit_Set_Reset
+
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
* @{
*/
#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
- ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
/**
* @}
*/
-/** @defgroup TIM_Master_Mode_Selection
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
* @{
*/
#define TIM_TRGO_RESET ((uint32_t)0x0000)
@@ -871,22 +692,12 @@ typedef struct
#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
-#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
- ((SOURCE) == TIM_TRGO_ENABLE) || \
- ((SOURCE) == TIM_TRGO_UPDATE) || \
- ((SOURCE) == TIM_TRGO_OC1) || \
- ((SOURCE) == TIM_TRGO_OC1REF) || \
- ((SOURCE) == TIM_TRGO_OC2REF) || \
- ((SOURCE) == TIM_TRGO_OC3REF) || \
- ((SOURCE) == TIM_TRGO_OC4REF))
-
-
+#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
/**
* @}
*/
-/** @defgroup TIM_Slave_Mode
+
+/** @defgroup TIM_Slave_Mode TIM Slave Mode
* @{
*/
#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
@@ -894,31 +705,22 @@ typedef struct
#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
-
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
- ((MODE) == TIM_SLAVEMODE_GATED) || \
- ((MODE) == TIM_SLAVEMODE_RESET) || \
- ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
- ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
/**
* @}
- */
+ */
-/** @defgroup TIM_Master_Slave_Mode
+/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
* @{
*/
-
#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
- ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
/**
* @}
*/
-/** @defgroup TIM_Trigger_Selection
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
* @{
*/
-
#define TIM_TS_ITR0 ((uint32_t)0x0000)
#define TIM_TS_ITR1 ((uint32_t)0x0010)
#define TIM_TS_ITR2 ((uint32_t)0x0020)
@@ -928,28 +730,11 @@ typedef struct
#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
#define TIM_TS_ETRF ((uint32_t)0x0070)
#define TIM_TS_NONE ((uint32_t)0xFFFF)
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_TI1F_ED) || \
- ((SELECTION) == TIM_TS_TI1FP1) || \
- ((SELECTION) == TIM_TS_TI2FP2) || \
- ((SELECTION) == TIM_TS_ETRF))
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3))
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_NONE))
/**
* @}
*/
-/** @defgroup TIM_Trigger_Polarity
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
* @{
*/
#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
@@ -957,156 +742,84 @@ typedef struct
#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-
-#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
/**
* @}
*/
-/** @defgroup TIM_Trigger_Prescaler
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
* @{
- */
+ */
#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
-
-#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
/**
* @}
*/
-/** @defgroup TIM_Trigger_Filter
- * @{
- */
-
-#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
-/**
- * @}
- */
- /** @defgroup TIM_TI1_Selection
+/** @defgroup TIM_TI1_Selection TIM TI1 Selection
* @{
*/
-
#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
-
-#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
- ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Base_address
- * @{
- */
-
-#define TIM_DMABase_CR1 (0x00000000)
-#define TIM_DMABase_CR2 (0x00000001)
-#define TIM_DMABase_SMCR (0x00000002)
-#define TIM_DMABase_DIER (0x00000003)
-#define TIM_DMABase_SR (0x00000004)
-#define TIM_DMABase_EGR (0x00000005)
-#define TIM_DMABase_CCMR1 (0x00000006)
-#define TIM_DMABase_CCMR2 (0x00000007)
-#define TIM_DMABase_CCER (0x00000008)
-#define TIM_DMABase_CNT (0x00000009)
-#define TIM_DMABase_PSC (0x0000000A)
-#define TIM_DMABase_ARR (0x0000000B)
-#define TIM_DMABase_RCR (0x0000000C)
-#define TIM_DMABase_CCR1 (0x0000000D)
-#define TIM_DMABase_CCR2 (0x0000000E)
-#define TIM_DMABase_CCR3 (0x0000000F)
-#define TIM_DMABase_CCR4 (0x00000010)
-#define TIM_DMABase_BDTR (0x00000011)
-#define TIM_DMABase_DCR (0x00000012)
-#define TIM_DMABase_OR (0x00000013)
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
- ((BASE) == TIM_DMABase_CR2) || \
- ((BASE) == TIM_DMABase_SMCR) || \
- ((BASE) == TIM_DMABase_DIER) || \
- ((BASE) == TIM_DMABase_SR) || \
- ((BASE) == TIM_DMABase_EGR) || \
- ((BASE) == TIM_DMABase_CCMR1) || \
- ((BASE) == TIM_DMABase_CCMR2) || \
- ((BASE) == TIM_DMABase_CCER) || \
- ((BASE) == TIM_DMABase_CNT) || \
- ((BASE) == TIM_DMABase_PSC) || \
- ((BASE) == TIM_DMABase_ARR) || \
- ((BASE) == TIM_DMABase_RCR) || \
- ((BASE) == TIM_DMABase_CCR1) || \
- ((BASE) == TIM_DMABase_CCR2) || \
- ((BASE) == TIM_DMABase_CCR3) || \
- ((BASE) == TIM_DMABase_CCR4) || \
- ((BASE) == TIM_DMABase_BDTR) || \
- ((BASE) == TIM_DMABase_DCR) || \
- ((BASE) == TIM_DMABase_OR))
/**
* @}
*/
-/** @defgroup TIM_DMA_Burst_Length
- * @{
- */
-
-#define TIM_DMABurstLength_1Transfer (0x00000000)
-#define TIM_DMABurstLength_2Transfers (0x00000100)
-#define TIM_DMABurstLength_3Transfers (0x00000200)
-#define TIM_DMABurstLength_4Transfers (0x00000300)
-#define TIM_DMABurstLength_5Transfers (0x00000400)
-#define TIM_DMABurstLength_6Transfers (0x00000500)
-#define TIM_DMABurstLength_7Transfers (0x00000600)
-#define TIM_DMABurstLength_8Transfers (0x00000700)
-#define TIM_DMABurstLength_9Transfers (0x00000800)
-#define TIM_DMABurstLength_10Transfers (0x00000900)
-#define TIM_DMABurstLength_11Transfers (0x00000A00)
-#define TIM_DMABurstLength_12Transfers (0x00000B00)
-#define TIM_DMABurstLength_13Transfers (0x00000C00)
-#define TIM_DMABurstLength_14Transfers (0x00000D00)
-#define TIM_DMABurstLength_15Transfers (0x00000E00)
-#define TIM_DMABurstLength_16Transfers (0x00000F00)
-#define TIM_DMABurstLength_17Transfers (0x00001000)
-#define TIM_DMABurstLength_18Transfers (0x00001100)
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
- ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_18Transfers))
+/** @defgroup TIM_DMA_Base_address TIM DMA Base address
+ * @{
+ */
+#define TIM_DMABASE_CR1 (0x00000000)
+#define TIM_DMABASE_CR2 (0x00000001)
+#define TIM_DMABASE_SMCR (0x00000002)
+#define TIM_DMABASE_DIER (0x00000003)
+#define TIM_DMABASE_SR (0x00000004)
+#define TIM_DMABASE_EGR (0x00000005)
+#define TIM_DMABASE_CCMR1 (0x00000006)
+#define TIM_DMABASE_CCMR2 (0x00000007)
+#define TIM_DMABASE_CCER (0x00000008)
+#define TIM_DMABASE_CNT (0x00000009)
+#define TIM_DMABASE_PSC (0x0000000A)
+#define TIM_DMABASE_ARR (0x0000000B)
+#define TIM_DMABASE_RCR (0x0000000C)
+#define TIM_DMABASE_CCR1 (0x0000000D)
+#define TIM_DMABASE_CCR2 (0x0000000E)
+#define TIM_DMABASE_CCR3 (0x0000000F)
+#define TIM_DMABASE_CCR4 (0x00000010)
+#define TIM_DMABASE_BDTR (0x00000011)
+#define TIM_DMABASE_DCR (0x00000012)
+#define TIM_DMABASE_OR (0x00000013)
/**
* @}
*/
-/** @defgroup TIM_Input_Capture_Filer_Value
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{
*/
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
+#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
+#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
+#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
+#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
+#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
+#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
+#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
+#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
+#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
+#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
+#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
+#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
+#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
+#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
+#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
+#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
+#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
/**
* @}
- */
+ */
-/** @defgroup DMA_Handle_index
+/** @defgroup DMA_Handle_index DMA Handle index
* @{
*/
#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
@@ -1120,7 +833,7 @@ typedef struct
* @}
*/
-/** @defgroup Channel_CC_State
+/** @defgroup Channel_CC_State Channel CC State
* @{
*/
#define TIM_CCx_ENABLE ((uint32_t)0x0001)
@@ -1136,6 +849,14 @@ typedef struct
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+ * @{
+ */
+/** @brief Reset TIM handle state
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
/**
* @brief Enable the TIM peripheral.
@@ -1152,11 +873,6 @@ typedef struct
#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
-#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-#define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
-
/**
* @brief Disable the TIM peripheral.
* @param __HANDLE__: TIM handle
@@ -1164,17 +880,17 @@ typedef struct
*/
#define __HAL_TIM_DISABLE(__HANDLE__) \
do { \
- if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
{ \
- if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
{ \
(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
} \
} \
} while(0)
-/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
+/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
/**
* @brief Disable the TIM main Output.
* @param __HANDLE__: TIM handle
@@ -1182,40 +898,52 @@ typedef struct
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \
- if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
{ \
- if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
{ \
(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
} \
} \
- } while(0)
+ } while(0)
#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
-#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR &= ~(__INTERRUPT__))
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
-#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
-#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC |= (__PRESC__))
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
-#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
-#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
-
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+ ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
+
/**
* @brief Sets the TIM Capture Compare Register value on runtime without
* calling another time ConfigChannel function.
@@ -1229,16 +957,37 @@ typedef struct
* @param __COMPARE__: specifies the Capture Compare register new value.
* @retval None
*/
-#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
+/**
+ * @brief Gets the TIM Capture Compare Register value on runtime
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__ : TIM Channel associated with the capture compare register
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value
+ * @retval None
+ */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+ (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
+
/**
* @brief Sets the TIM Counter Register value on runtime.
* @param __HANDLE__: TIM handle.
* @param __COUNTER__: specifies the Counter register new value.
* @retval None
*/
-#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+ * @brief Gets the TIM Counter Register value on runtime.
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
/**
* @brief Sets the TIM Autoreload Register value on runtime without calling
@@ -1247,11 +996,17 @@ typedef struct
* @param __AUTORELOAD__: specifies the Counter register new value.
* @retval None
*/
-#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
- do{ \
- (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
- (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+ do{ \
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
} while(0)
+/**
+ * @brief Gets the TIM Autoreload Register value on runtime
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
/**
* @brief Sets the TIM Clock Division value on runtime without calling
@@ -1261,16 +1016,22 @@ typedef struct
* This parameter can be one of the following value:
* @arg TIM_CLOCKDIVISION_DIV1
* @arg TIM_CLOCKDIVISION_DIV2
- * @arg TIM_CLOCKDIVISION_DIV4
+ * @arg TIM_CLOCKDIVISION_DIV4
* @retval None
*/
-#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
- do{ \
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
+ do{ \
(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
- (__HANDLE__)->Instance->CR1 |= (__CKD__); \
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
(__HANDLE__)->Init.ClockDivision = (__CKD__); \
} while(0)
-
+/**
+ * @brief Gets the TIM Clock Division value on runtime
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
/**
* @brief Sets the TIM Input Capture prescaler on runtime without calling
* another time HAL_TIM_IC_ConfigChannel() function.
@@ -1289,16 +1050,90 @@ typedef struct
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
* @retval None
*/
-#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
do{ \
- __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
- __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
- } while(0)
+ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+ } while(0)
+
+/**
+ * @brief Gets the TIM Input Capture prescaler on runtime
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__ : TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+ * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+ * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+ * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+ * @retval None
+ */
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
+
+/**
+ * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
+ * @param __HANDLE__: TIM handle.
+ * @note When the USR bit of the TIMx_CR1 register is set, only counter
+ * overflow/underflow generates an update interrupt or DMA request (if
+ * enabled)
+ * @retval None
+ */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
+
+/**
+ * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
+ * @param __HANDLE__: TIM handle.
+ * @note When the USR bit of the TIMx_CR1 register is reset, any of the
+ * following events generate an update interrupt or DMA request (if
+ * enabled):
+ * _ Counter overflow/underflow
+ * _ Setting the UG bit
+ * _ Update generation through the slave mode controller
+ * @retval None
+ */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
+
+/**
+ * @brief Sets the TIM Capture x input polarity on runtime.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__: TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __POLARITY__: Polarity for TIx source
+ * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+ * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
+ * @retval None
+ */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+ do{ \
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+ }while(0)
+/**
+ * @}
+ */
/* Include TIM HAL Extension module */
#include "stm32f2xx_hal_tim_ex.h"
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group1
+ * @{
+ */
/* Time Base functions ********************************************************/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
@@ -1314,7 +1149,13 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+/** @addtogroup TIM_Exported_Functions_Group2
+ * @{
+ */
/* Timer Output Compare functions **********************************************/
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
@@ -1330,6 +1171,13 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group3
+ * @{
+ */
/* Timer PWM functions *********************************************************/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
@@ -1345,6 +1193,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group4
+ * @{
+ */
/* Timer Input Capture functions ***********************************************/
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
@@ -1360,6 +1215,13 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group5
+ * @{
+ */
/* Timer One Pulse functions ***************************************************/
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
@@ -1373,6 +1235,13 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group6
+ * @{
+ */
/* Timer Encoder functions *****************************************************/
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
@@ -1388,9 +1257,23 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group7
+ * @{
+ */
/* Interrupt Handler functions **********************************************/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group8
+ * @{
+ */
/* Control functions *********************************************************/
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
@@ -1400,6 +1283,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
@@ -1409,6 +1293,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group9
+ * @{
+ */
/* Callback in non blocking modes (Interrupt and DMA) *************************/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
@@ -1417,6 +1308,13 @@ void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group10
+ * @{
+ */
/* Peripheral State functions **************************************************/
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
@@ -1425,14 +1323,275 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+ * @{
+ */
+
+/** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
+ * @{
+ */
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
+ ((MODE) == TIM_COUNTERMODE_DOWN) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
+ ((MODE) == TIM_OCMODE_PWM2))
+
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
+ ((MODE) == TIM_OCMODE_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_INACTIVE) || \
+ ((MODE) == TIM_OCMODE_TOGGLE) || \
+ ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
+
+#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
+ ((STATE) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
+ ((STATE) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
+ ((STATE) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))
+
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
+ ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \
+ ((PRESCALER) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
+ ((MODE) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
+
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
+ ((MODE) == TIM_ENCODERMODE_TI2) || \
+ ((MODE) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
+
+#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
+
+#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
+#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
+ ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
+
+#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
+ ((STATE) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
+ ((STATE) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
+ ((LEVEL) == TIM_LOCKLEVEL_1) || \
+ ((LEVEL) == TIM_LOCKLEVEL_2) || \
+ ((LEVEL) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
+ ((STATE) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
+ ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+ ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
+ ((SOURCE) == TIM_TRGO_ENABLE) || \
+ ((SOURCE) == TIM_TRGO_UPDATE) || \
+ ((SOURCE) == TIM_TRGO_OC1) || \
+ ((SOURCE) == TIM_TRGO_OC1REF) || \
+ ((SOURCE) == TIM_TRGO_OC2REF) || \
+ ((SOURCE) == TIM_TRGO_OC3REF) || \
+ ((SOURCE) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
+ ((MODE) == TIM_SLAVEMODE_GATED) || \
+ ((MODE) == TIM_SLAVEMODE_RESET) || \
+ ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
+ ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
+
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
+ ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_TI1F_ED) || \
+ ((SELECTION) == TIM_TS_TI1FP1) || \
+ ((SELECTION) == TIM_TS_TI2FP2) || \
+ ((SELECTION) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
+
+#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
+#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
+ ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
+ ((BASE) == TIM_DMABASE_CR2) || \
+ ((BASE) == TIM_DMABASE_SMCR) || \
+ ((BASE) == TIM_DMABASE_DIER) || \
+ ((BASE) == TIM_DMABASE_SR) || \
+ ((BASE) == TIM_DMABASE_EGR) || \
+ ((BASE) == TIM_DMABASE_CCMR1) || \
+ ((BASE) == TIM_DMABASE_CCMR2) || \
+ ((BASE) == TIM_DMABASE_CCER) || \
+ ((BASE) == TIM_DMABASE_CNT) || \
+ ((BASE) == TIM_DMABASE_PSC) || \
+ ((BASE) == TIM_DMABASE_ARR) || \
+ ((BASE) == TIM_DMABASE_RCR) || \
+ ((BASE) == TIM_DMABASE_CCR1) || \
+ ((BASE) == TIM_DMABASE_CCR2) || \
+ ((BASE) == TIM_DMABASE_CCR3) || \
+ ((BASE) == TIM_DMABASE_CCR4) || \
+ ((BASE) == TIM_DMABASE_BDTR) || \
+ ((BASE) == TIM_DMABASE_DCR) || \
+ ((BASE) == TIM_DMABASE_OR))
+
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Mask_Definitions TIM Mask Definition
+ * @{
+ */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Functions TIM Private Functions
+ * @{
+ */
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
-void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
-void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
-
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
+/**
+ * @}
+ */
+
/**
* @}
*/
diff --git a/f2/include/stm32f2xx_hal_tim_ex.h b/f2/include/stm32f2xx_hal_tim_ex.h
index 82cbc030c336bc80148bc76baebac403db5b1ca3..88245f7822d6c500dff7e9a7a64a079315b2081d 100755
--- a/f2/include/stm32f2xx_hal_tim_ex.h
+++ b/f2/include/stm32f2xx_hal_tim_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_tim_ex.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of TIM HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -46,7 +46,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f2xx_hal_def.h"
-/** @addtogroup STM32F2xx_HAL
+/** @addtogroup STM32F2xx_HAL_Driver
* @{
*/
@@ -55,7 +55,10 @@
*/
/* Exported types ------------------------------------------------------------*/
-
+/** @defgroup TIMEx_Exported_Types TIM Exported Types
+ * @{
+ */
+
/**
* @brief TIM Hall sensor Configuration Structure definition
*/
@@ -79,9 +82,9 @@ typedef struct
* @brief TIM Master configuration Structure definition
*/
typedef struct {
- uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection.
This parameter can be a value of @ref TIM_Master_Mode_Selection */
- uint32_t MasterSlaveMode; /*!< Master/slave mode selection
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection.
This parameter can be a value of @ref TIM_Master_Slave_Mode */
}TIM_MasterConfigTypeDef;
@@ -90,31 +93,33 @@ typedef struct {
*/
typedef struct
{
- uint32_t OffStateRunMode; /*!< TIM off state in run mode
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode.
This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
- uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode.
This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
- uint32_t LockLevel; /*!< TIM Lock level
+ uint32_t LockLevel; /*!< TIM Lock level.
This parameter can be a value of @ref TIM_Lock_level */
- uint32_t DeadTime; /*!< TIM dead Time
+ uint32_t DeadTime; /*!< TIM dead Time.
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
- uint32_t BreakState; /*!< TIM Break State
+ uint32_t BreakState; /*!< TIM Break State.
This parameter can be a value of @ref TIM_Break_Input_enable_disable */
- uint32_t BreakPolarity; /*!< TIM Break input polarity
+ uint32_t BreakPolarity; /*!< TIM Break input polarity.
This parameter can be a value of @ref TIM_Break_Polarity */
- uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state.
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
}TIM_BreakDeadTimeConfigTypeDef;
-
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Constants
+/** @defgroup TIMEx_Exported_Constants TIM Exported Constants
* @{
*/
-
-/** @defgroup TIMEx_Remap
+
+/** @defgroup TIMEx_Remap TIM Remap
* @{
*/
-
#define TIM_TIM2_TIM8_TRGO (0x00000000)
#define TIM_TIM2_ETH_PTP (0x00000400)
#define TIM_TIM2_USBFS_SOF (0x00000800)
@@ -126,29 +131,23 @@ typedef struct
#define TIM_TIM11_GPIO (0x00000000)
#define TIM_TIM11_HSE (0x00000002)
-#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
- ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
- ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
- ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
- ((TIM_REMAP) == TIM_TIM5_GPIO)||\
- ((TIM_REMAP) == TIM_TIM5_LSI)||\
- ((TIM_REMAP) == TIM_TIM5_LSE)||\
- ((TIM_REMAP) == TIM_TIM5_RTC)||\
- ((TIM_REMAP) == TIM_TIM11_GPIO)||\
- ((TIM_REMAP) == TIM_TIM11_HSE))
-
/**
* @}
*/
/**
* @}
- */
+ */
/* Exported macro ------------------------------------------------------------*/
-
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions
+ * @{
+ */
+/** @addtogroup TIMEx_Exported_Functions_Group1
+ * @{
+ */
/* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
@@ -165,7 +164,13 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
+/**
+ * @}
+ */
+/** @addtogroup TIMEx_Exported_Functions_Group2
+ * @{
+ */
/* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
@@ -178,7 +183,13 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channe
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
+/**
+ * @}
+ */
+/** @addtogroup TIMEx_Exported_Functions_Group3
+ * @{
+ */
/* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
@@ -190,7 +201,13 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Chann
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
+/**
+ * @}
+ */
+/** @addtogroup TIMEx_Exported_Functions_Group4
+ * @{
+ */
/* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
@@ -199,23 +216,40 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t Out
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+/**
+ * @}
+ */
-/* Extnsion Control functions ************************************************/
+/** @addtogroup TIMEx_Exported_Functions_Group5
+ * @{
+ */
+/* Extension Control functions ************************************************/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
+/**
+ * @}
+ */
+/** @addtogroup TIMEx_Exported_Functions_Group6
+ * @{
+ */
/* Extension Callback *********************************************************/
void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
-void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+/** @addtogroup TIMEx_Exported_Functions_Group7
+ * @{
+ */
/* Extension Peripheral State functions **************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
-
/**
* @}
*/
@@ -223,7 +257,47 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
/**
* @}
*/
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Private Macros
+ * @{
+ */
+#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
+ ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
+ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
+ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
+ ((TIM_REMAP) == TIM_TIM5_GPIO)||\
+ ((TIM_REMAP) == TIM_TIM5_LSI)||\
+ ((TIM_REMAP) == TIM_TIM5_LSE)||\
+ ((TIM_REMAP) == TIM_TIM5_RTC)||\
+ ((TIM_REMAP) == TIM_TIM11_GPIO)||\
+ ((TIM_REMAP) == TIM_TIM11_HSE))
+
+#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF)
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIM Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
diff --git a/f2/include/stm32f2xx_hal_uart.h b/f2/include/stm32f2xx_hal_uart.h
index 248a08ef5783497d1cbb9eb52a91fbf5f98e98a9..5db2e7112ac6abee2ba97d868cfde6544702da43 100755
--- a/f2/include/stm32f2xx_hal_uart.h
+++ b/f2/include/stm32f2xx_hal_uart.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_uart.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of UART HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,6 +55,9 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Types UART Exported Types
+ * @{
+ */
/**
* @brief UART Init Structure definition
@@ -80,14 +83,14 @@ typedef struct
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
- uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref UART_Mode */
- uint32_t HwFlowCtl; /*!< Specifies wether the hardware flow control mode is enabled
+ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
or disabled.
This parameter can be a value of @ref UART_Hardware_Flow_Control */
- uint32_t OverSampling; /*!< Specifies wether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
This parameter can be a value of @ref UART_Over_Sampling */
}UART_InitTypeDef;
@@ -106,213 +109,212 @@ typedef enum
HAL_UART_STATE_ERROR = 0x04 /*!< Error */
}HAL_UART_StateTypeDef;
-/**
- * @brief HAL UART Error Code structure definition
- */
-typedef enum
-{
- HAL_UART_ERROR_NONE = 0x00, /*!< No error */
- HAL_UART_ERROR_PE = 0x01, /*!< Parity error */
- HAL_UART_ERROR_NE = 0x02, /*!< Noise error */
- HAL_UART_ERROR_FE = 0x04, /*!< frame error */
- HAL_UART_ERROR_ORE = 0x08, /*!< Overrun error */
- HAL_UART_ERROR_DMA = 0x10 /*!< DMA transfer error */
-}HAL_UART_ErrorTypeDef;
-
/**
* @brief UART handle Structure definition
*/
typedef struct
{
- USART_TypeDef *Instance; /* UART registers base address */
+ USART_TypeDef *Instance; /*!< UART registers base address */
- UART_InitTypeDef Init; /* UART communication parameters */
+ UART_InitTypeDef Init; /*!< UART communication parameters */
- uint8_t *pTxBuffPtr; /* Pointer to UART Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
- uint16_t TxXferSize; /* UART Tx Transfer size */
+ uint16_t TxXferSize; /*!< UART Tx Transfer size */
- uint16_t TxXferCount; /* UART Tx Transfer Counter */
+ uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
- uint8_t *pRxBuffPtr; /* Pointer to UART Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
- uint16_t RxXferSize; /* UART Rx Transfer size */
+ uint16_t RxXferSize; /*!< UART Rx Transfer size */
- uint16_t RxXferCount; /* UART Rx Transfer Counter */
+ uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
- DMA_HandleTypeDef *hdmatx; /* UART Tx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
- DMA_HandleTypeDef *hdmarx; /* UART Rx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
- HAL_LockTypeDef Lock; /* Locking object */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_UART_StateTypeDef State; /* UART communication state */
-
- __IO HAL_UART_ErrorTypeDef ErrorCode; /* UART Error code */
+ __IO HAL_UART_StateTypeDef State; /*!< UART communication state */
+ __IO uint32_t ErrorCode; /*!< UART Error code */
+
}UART_HandleTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup UART_Exported_Constants
+/** @defgroup UART_Exported_Constants UART Exported constants
* @{
*/
-
-/** @defgroup UART_Word_Length
+
+/** @defgroup UART_Error_Code UART Error Code
+ * @brief UART Error Code
+ * @{
+ */
+#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_UART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_UART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_UART_ERROR_FE ((uint32_t)0x00000004) /*!< Frame error */
+#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Word_Length UART Word Length
* @{
*/
#define UART_WORDLENGTH_8B ((uint32_t)0x00000000)
#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
- ((LENGTH) == UART_WORDLENGTH_9B))
/**
* @}
*/
-/** @defgroup UART_Stop_Bits
+/** @defgroup UART_Stop_Bits UART Number of Stop Bits
* @{
*/
#define UART_STOPBITS_1 ((uint32_t)0x00000000)
#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
-#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
- ((STOPBITS) == UART_STOPBITS_2))
/**
* @}
*/
-/** @defgroup UART_Parity
+/** @defgroup UART_Parity UART Parity
* @{
*/
#define UART_PARITY_NONE ((uint32_t)0x00000000)
#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
- ((PARITY) == UART_PARITY_EVEN) || \
- ((PARITY) == UART_PARITY_ODD))
/**
* @}
*/
-/** @defgroup UART_Hardware_Flow_Control
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
* @{
*/
#define UART_HWCONTROL_NONE ((uint32_t)0x00000000)
#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
- (((CONTROL) == UART_HWCONTROL_NONE) || \
- ((CONTROL) == UART_HWCONTROL_RTS) || \
- ((CONTROL) == UART_HWCONTROL_CTS) || \
- ((CONTROL) == UART_HWCONTROL_RTS_CTS))
/**
* @}
*/
-/** @defgroup UART_Mode
+/** @defgroup UART_Mode UART Transfer Mode
* @{
*/
#define UART_MODE_RX ((uint32_t)USART_CR1_RE)
#define UART_MODE_TX ((uint32_t)USART_CR1_TE)
#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-#define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
/**
* @}
*/
- /** @defgroup UART_State
+ /** @defgroup UART_State UART State
* @{
*/
#define UART_STATE_DISABLE ((uint32_t)0x00000000)
#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
-#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
- ((STATE) == UART_STATE_ENABLE))
/**
* @}
*/
-/** @defgroup UART_Over_Sampling
+/** @defgroup UART_Over_Sampling UART Over Sampling
* @{
*/
#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000)
#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
-#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
- ((SAMPLING) == UART_OVERSAMPLING_8))
/**
* @}
*/
-/** @defgroup UART_LIN_Break_Detection_Length
+/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length
* @{
*/
#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000)
#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)0x00000020)
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
- ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
/**
* @}
*/
-/** @defgroup UART_WakeUp_functions
+/** @defgroup UART_WakeUp_functions UART Wakeup Functions
* @{
*/
-#define UART_WAKEUPMETHODE_IDLELINE ((uint32_t)0x00000000)
-#define UART_WAKEUPMETHODE_ADDRESSMARK ((uint32_t)0x00000800)
-#define IS_UART_WAKEUPMETHODE(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHODE_IDLELINE) || \
- ((WAKEUP) == UART_WAKEUPMETHODE_ADDRESSMARK))
+#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000)
+#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)0x00000800)
/**
* @}
*/
-/** @defgroup UART_Flags
+/** @defgroup UART_Flags UART FLags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the SR register
* @{
*/
-#define UART_FLAG_CTS ((uint32_t)0x00000200)
-#define UART_FLAG_LBD ((uint32_t)0x00000100)
-#define UART_FLAG_TXE ((uint32_t)0x00000080)
-#define UART_FLAG_TC ((uint32_t)0x00000040)
-#define UART_FLAG_RXNE ((uint32_t)0x00000020)
-#define UART_FLAG_IDLE ((uint32_t)0x00000010)
-#define UART_FLAG_ORE ((uint32_t)0x00000008)
-#define UART_FLAG_NE ((uint32_t)0x00000004)
-#define UART_FLAG_FE ((uint32_t)0x00000002)
-#define UART_FLAG_PE ((uint32_t)0x00000001)
+#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS)
+#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD)
+#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE)
+#define UART_FLAG_TC ((uint32_t)USART_SR_TC)
+#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
+#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
+#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE)
+#define UART_FLAG_NE ((uint32_t)USART_SR_NE)
+#define UART_FLAG_FE ((uint32_t)USART_SR_FE)
+#define UART_FLAG_PE ((uint32_t)USART_SR_PE)
/**
* @}
*/
-/** @defgroup UART_Interrupt_definition
+/** @defgroup UART_Interrupt_definition UART Interrupt Definitions
* Elements values convention: 0xY000XXXX
- * - XXXX : Interrupt mask in the XX register
+ * - XXXX : Interrupt mask (16 bits) in the Y register
* - Y : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
+ * - 0001: CR1 register
+ * - 0010: CR2 register
+ * - 0011: CR3 register
*
* @{
- */
-#define UART_IT_PE ((uint32_t)0x10000100)
-#define UART_IT_TXE ((uint32_t)0x10000080)
-#define UART_IT_TC ((uint32_t)0x10000040)
-#define UART_IT_RXNE ((uint32_t)0x10000020)
-#define UART_IT_IDLE ((uint32_t)0x10000010)
+ */
+
+#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
+#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
+#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
+#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
+#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
-#define UART_IT_LBD ((uint32_t)0x20000040)
-#define UART_IT_CTS ((uint32_t)0x30000400)
-
-#define UART_IT_ERR ((uint32_t)0x30000001)
+#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
+#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
+#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
/**
* @}
*/
-
+
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
-
+/** @defgroup UART_Exported_Macros UART Exported Macros
+ * @{
+ */
+
+/** @brief Reset UART handle state
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
+
+/** @brief Flushes the UART DR register
+ * @param __HANDLE__: specifies the UART Handle.
+ */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
+
/** @brief Checks whether the specified UART flag is set or not.
* @param __HANDLE__: specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
@@ -325,7 +327,7 @@ typedef struct
* @arg UART_FLAG_TC: Transmission Complete flag
* @arg UART_FLAG_RXNE: Receive data register not empty flag
* @arg UART_FLAG_IDLE: Idle Line detection flag
- * @arg UART_FLAG_ORE: OverRun Error flag
+ * @arg UART_FLAG_ORE: Overrun Error flag
* @arg UART_FLAG_NE: Noise Error flag
* @arg UART_FLAG_FE: Framing Error flag
* @arg UART_FLAG_PE: Parity Error flag
@@ -345,7 +347,7 @@ typedef struct
* @arg UART_FLAG_TC: Transmission Complete flag.
* @arg UART_FLAG_RXNE: Receive data register not empty flag.
*
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
* error) and IDLE (Idle line detected) flags are cleared by software
* sequence: a read operation to USART_SR register followed by a read
* operation to USART_DR register.
@@ -356,13 +358,59 @@ typedef struct
*
* @retval None
*/
-#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-/** @brief Enables or disables the specified UART interrupt.
+/** @brief Clear the UART PE pending flag.
* @param __HANDLE__: specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
- * @param __INTERRUPT__: specifies the UART interrupt source to check.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ UNUSED(tmpreg); \
+ } while(0)
+
+/** @brief Clear the UART FE pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the UART NE pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the UART ORE pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the UART IDLE pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Enable the specified UART interrupt.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __INTERRUPT__: specifies the UART interrupt source to enable.
* This parameter can be one of the following values:
* @arg UART_IT_CTS: CTS change interrupt
* @arg UART_IT_LBD: LIN Break detection interrupt
@@ -372,14 +420,28 @@ typedef struct
* @arg UART_IT_IDLE: Idle line detection interrupt
* @arg UART_IT_PE: Parity Error interrupt
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @param NewState: new state of the specified UART interrupt.
- * This parameter can be: ENABLE or DISABLE.
* @retval None
*/
#define UART_IT_MASK ((uint32_t)0x0000FFFF)
#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
(((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
+/** @brief Disable the specified UART interrupt.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __INTERRUPT__: specifies the UART interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_CTS: CTS change interrupt
+ * @arg UART_IT_LBD: LIN Break detection interrupt
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg UART_IT_PE: Parity Error interrupt
+ * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
(((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
@@ -402,39 +464,132 @@ typedef struct
#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
-/** @brief macros to enables or disables the UART's one bit sampling method
+/** @brief Enable CTS flow control
+ * This macro allows to enable CTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__: specifies the UART Handle.
+ * The Handle Instance can be USART1, USART2 or LPUART.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
+ } while(0)
+
+/** @brief Disable CTS flow control
+ * This macro allows to disable CTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__: specifies the UART Handle.
+ * The Handle Instance can be USART1, USART2 or LPUART.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
+ do{ \
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
+ } while(0)
+
+/** @brief Enable RTS flow control
+ * This macro allows to enable RTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__: specifies the UART Handle.
+ * The Handle Instance can be USART1, USART2 or LPUART.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
+ } while(0)
+
+/** @brief Disable RTS flow control
+ * This macro allows to disable RTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__: specifies the UART Handle.
+ * The Handle Instance can be USART1, USART2 or LPUART.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
+ do{ \
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
+ } while(0)
+
+/** @brief macros to enables the UART's one bit sample method
* @param __HANDLE__: specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_ONEBIT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-#define __HAL_UART_ONEBIT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
-#define __DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
-#define __DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (__DIV_SAMPLING16((_PCLK_), (_BAUD_))/100)
-#define __DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((__DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (__DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-#define __UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((__DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F))
+/** @brief macros to disables the UART's one bit sample method
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
-#define __DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25)/(2*(_BAUD_)))
-#define __DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (__DIV_SAMPLING8((_PCLK_), (_BAUD_))/100)
-#define __DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((__DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (__DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-#define __UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((__DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x0F))
+/** @brief Enable UART
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 7500001)
-#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+/** @brief Disable UART
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UART_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UART_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethode);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
void HAL_UART_MspInit(UART_HandleTypeDef *huart);
void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+/** @addtogroup UART_Exported_Functions_Group2
+ * @{
+ */
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -451,18 +606,29 @@ void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+/** @addtogroup UART_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+/** @addtogroup UART_Exported_Functions_Group4
+ * @{
+ */
/* Peripheral State functions **************************************************/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
-
/**
* @}
*/
@@ -470,7 +636,82 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
/**
* @}
*/
-
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+ * @{
+ */
+/** @brief UART interruptions flag mask
+ *
+ */
+#define UART_CR1_REG_INDEX 1
+#define UART_CR2_REG_INDEX 2
+#define UART_CR3_REG_INDEX 3
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UART_Private_Macros UART Private Macros
+ * @{
+ */
+#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
+ ((LENGTH) == UART_WORDLENGTH_9B))
+#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
+#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
+ ((STOPBITS) == UART_STOPBITS_2))
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
+ ((PARITY) == UART_PARITY_EVEN) || \
+ ((PARITY) == UART_PARITY_ODD))
+#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
+ (((CONTROL) == UART_HWCONTROL_NONE) || \
+ ((CONTROL) == UART_HWCONTROL_RTS) || \
+ ((CONTROL) == UART_HWCONTROL_CTS) || \
+ ((CONTROL) == UART_HWCONTROL_RTS_CTS))
+#define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
+#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
+ ((STATE) == UART_STATE_ENABLE))
+#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
+ ((SAMPLING) == UART_OVERSAMPLING_8))
+#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
+ ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
+#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
+ ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
+#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 7500001)
+#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+
+#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
+#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100)
+#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4)|(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25)/(2*(_BAUD_)))
+#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100)
+#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4)|(UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x0F))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
#ifdef __cplusplus
}
#endif
diff --git a/f2/include/stm32f2xx_hal_usart.h b/f2/include/stm32f2xx_hal_usart.h
index 94cf8f2768d72be0c3881991f7a14c4f5c90e5c5..d3503e71a66e86e15dc77bf9fd860206f4f7d0af 100755
--- a/f2/include/stm32f2xx_hal_usart.h
+++ b/f2/include/stm32f2xx_hal_usart.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_usart.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,6 +55,10 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup USART_Exported_Types USART Exported Types
+ * @{
+ */
+
/**
* @brief USART Init Structure definition
*/
@@ -62,7 +66,7 @@ typedef struct
{
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
The baud rate is computed using the following formula:
- - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
+ - IntegerDivider = ((PCLKx) / (8 * (husart->Init.BaudRate)))
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
@@ -78,7 +82,7 @@ typedef struct
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
- uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode */
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
@@ -107,19 +111,6 @@ typedef enum
HAL_USART_STATE_ERROR = 0x04 /*!< Error */
}HAL_USART_StateTypeDef;
-/**
- * @brief HAL USART Error Code structure definition
- */
-typedef enum
-{
- HAL_USART_ERROR_NONE = 0x00, /*!< No error */
- HAL_USART_ERROR_PE = 0x01, /*!< Parity error */
- HAL_USART_ERROR_NE = 0x02, /*!< Noise error */
- HAL_USART_ERROR_FE = 0x04, /*!< frame error */
- HAL_USART_ERROR_ORE = 0x08, /*!< Overrun error */
- HAL_USART_ERROR_DMA = 0x10 /*!< DMA transfer error */
-}HAL_USART_ErrorTypeDef;
-
/**
* @brief USART handle Structure definition
*/
@@ -149,125 +140,122 @@ typedef struct
__IO HAL_USART_StateTypeDef State; /* Usart communication state */
- __IO HAL_USART_ErrorTypeDef ErrorCode; /* USART Error code */
-
-}USART_HandleTypeDef;
+ __IO uint32_t ErrorCode; /* USART Error code */
+}USART_HandleTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_Exported_Constants
+/** @defgroup USART_Exported_Constants USART Exported Constants
* @{
*/
-/** @defgroup USART_Word_Length
+/** @defgroup USART_Error_Code USART Error Code
+ * @brief USART Error Code
+ * @{
+ */
+#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_USART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_USART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_USART_ERROR_FE ((uint32_t)0x00000004) /*!< Frame error */
+#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Word_Length USART Word Length
* @{
*/
#define USART_WORDLENGTH_8B ((uint32_t)0x00000000)
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
- ((LENGTH) == USART_WORDLENGTH_9B))
/**
* @}
*/
-/** @defgroup USART_Stop_Bits
+/** @defgroup USART_Stop_Bits USART Number of Stop Bits
* @{
*/
#define USART_STOPBITS_1 ((uint32_t)0x00000000)
#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
- ((STOPBITS) == USART_STOPBITS_0_5) || \
- ((STOPBITS) == USART_STOPBITS_1_5) || \
- ((STOPBITS) == USART_STOPBITS_2))
/**
* @}
*/
-/** @defgroup USART_Parity
+/** @defgroup USART_Parity USART Parity
* @{
*/
#define USART_PARITY_NONE ((uint32_t)0x00000000)
#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
- ((PARITY) == USART_PARITY_EVEN) || \
- ((PARITY) == USART_PARITY_ODD))
+#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
* @}
*/
-/** @defgroup USART_Mode
+/** @defgroup USART_Mode USART Mode
* @{
*/
#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFF3) == 0x00) && ((MODE) != (uint32_t)0x00))
/**
* @}
*/
-/** @defgroup USART_Clock
+/** @defgroup USART_Clock USART Clock
* @{
*/
-#define USART_CLOCK_DISABLED ((uint32_t)0x00000000)
-#define USART_CLOCK_ENABLED ((uint32_t)USART_CR2_CLKEN)
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLED) || \
- ((CLOCK) == USART_CLOCK_ENABLED))
+#define USART_CLOCK_DISABLE ((uint32_t)0x00000000)
+#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
/**
* @}
*/
-/** @defgroup USART_Clock_Polarity
+/** @defgroup USART_Clock_Polarity USART Clock Polarity
* @{
*/
#define USART_POLARITY_LOW ((uint32_t)0x00000000)
#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
-#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
/**
* @}
*/
-/** @defgroup USART_Clock_Phase
+/** @defgroup USART_Clock_Phase USART Clock Phase
* @{
*/
#define USART_PHASE_1EDGE ((uint32_t)0x00000000)
#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
-#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
/**
* @}
*/
-/** @defgroup USART_Last_Bit
+/** @defgroup USART_Last_Bit USART Last Bit
* @{
*/
#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000)
#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
- ((LASTBIT) == USART_LASTBIT_ENABLE))
/**
* @}
*/
-/** @defgroup Usart_NACK_State
+/** @defgroup USART_NACK_State USART NACK State
* @{
*/
-#define USARTNACK_ENABLED ((uint32_t)USART_CR3_NACK)
-#define USARTNACK_DISABLED ((uint32_t)0x00000000)
-#define IS_USART_NACK_STATE(NACK) (((NACK) == USARTNACK_ENABLED) || \
- ((NACK) == USARTNACK_DISABLED))
+#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
+#define USART_NACK_DISABLE ((uint32_t)0x00000000)
/**
* @}
*/
-/** @defgroup Usart_Flags
+/** @defgroup USART_Flags USART Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the SR register
* @{
*/
-
#define USART_FLAG_TXE ((uint32_t)0x00000080)
#define USART_FLAG_TC ((uint32_t)0x00000040)
#define USART_FLAG_RXNE ((uint32_t)0x00000020)
@@ -280,7 +268,7 @@ typedef struct
* @}
*/
-/** @defgroup USART_Interrupt_definition
+/** @defgroup USART_Interrupt_definition USART Interrupts Definition
* Elements values convention: 0xY000XXXX
* - XXXX : Interrupt mask in the XX register
* - Y : Interrupt source register (2bits)
@@ -290,57 +278,62 @@ typedef struct
*
* @{
*/
-#define USART_IT_PE ((uint32_t)0x10000100)
-#define USART_IT_TXE ((uint32_t)0x10000080)
-#define USART_IT_TC ((uint32_t)0x10000040)
-#define USART_IT_RXNE ((uint32_t)0x10000020)
-#define USART_IT_IDLE ((uint32_t)0x10000010)
-
-#define USART_IT_LBD ((uint32_t)0x20000040)
-#define USART_IT_CTS ((uint32_t)0x30000400)
-
-#define USART_IT_ERR ((uint32_t)0x30000001)
+#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
+#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
+#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
+#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
+#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
+#define USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
+#define USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
+#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
/**
* @}
*/
-
+
/**
* @}
*/
-
+
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_Exported_Macros USART Exported Macros
+ * @{
+ */
+
+/** @brief Reset USART handle state
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @retval None
+ */
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
/** @brief Checks whether the specified Smartcard flag is set or not.
* @param __HANDLE__: specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg USART_FLAG_TXE: Transmit data register empty flag
* @arg USART_FLAG_TC: Transmission Complete flag
* @arg USART_FLAG_RXNE: Receive data register not empty flag
* @arg USART_FLAG_IDLE: Idle Line detection flag
- * @arg USART_FLAG_ORE: OverRun Error flag
+ * @arg USART_FLAG_ORE: Overrun Error flag
* @arg USART_FLAG_NE: Noise Error flag
* @arg USART_FLAG_FE: Framing Error flag
* @arg USART_FLAG_PE: Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-
#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/** @brief Clears the specified Smartcard pending flags.
* @param __HANDLE__: specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @param __FLAG__: specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg USART_FLAG_TC: Transmission Complete flag.
* @arg USART_FLAG_RXNE: Receive data register not empty flag.
*
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
* error) and IDLE (Idle line detected) flags are cleared by software
* sequence: a read operation to USART_SR register followed by a read
* operation to USART_DR register.
@@ -351,13 +344,52 @@ typedef struct
*
* @retval None
*/
-#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+/** @brief Clear the USART PE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ UNUSED(tmpreg); \
+ } while(0)
+
+/** @brief Clear the USART FE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-/** @brief Enables or disables the specified Usart interrupts.
+/** @brief Clear the USART NE pending flag.
* @param __HANDLE__: specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the UART ORE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the USART IDLE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Enables or disables the specified USART interrupts.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @param __INTERRUPT__: specifies the USART interrupt source to check.
* This parameter can be one of the following values:
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
@@ -366,23 +398,19 @@ typedef struct
* @arg USART_IT_IDLE: Idle line detection interrupt
* @arg USART_IT_PE: Parity Error interrupt
* @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @param NewState: new state of the specified Usart interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
-#define USART_IT_MASK ((uint32_t)0x0000FFFF)
-#define __USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
- (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
-#define __USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
- (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
-
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
-/** @brief Checks whether the specified Usart interrupt has occurred or not.
+/** @brief Checks whether the specified USART interrupt has occurred or not.
* @param __HANDLE__: specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @param __IT__: specifies the USART interrupt source to check.
* This parameter can be one of the following values:
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
@@ -396,22 +424,55 @@ typedef struct
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
-#define __USART_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-#define __USART_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
-#define __DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
-#define __DIVMANT(_PCLK_, _BAUD_) (__DIV((_PCLK_), (_BAUD_))/100)
-#define __DIVFRAQ(_PCLK_, _BAUD_) (((__DIV((_PCLK_), (_BAUD_)) - (__DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-#define __USART_BRR(_PCLK_, _BAUD_) ((__DIVMANT((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+/** @brief Macro to enable the USART's one bit sample method
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 7500001)
-
+/** @brief Macro to disable the USART's one bit sample method
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
+
+/** @brief Enable USART
+ * @param __HANDLE__: specifies the USART Handle.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_USART_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable USART
+ * @param __HANDLE__: specifies the USART Handle.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_USART_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup USART_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
void HAL_USART_MspInit(USART_HandleTypeDef *husart);
void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Functions_Group2
+ * @{
+ */
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
@@ -432,10 +493,82 @@ void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
+/**
+ * @}
+ */
-/* Peripheral State functions **************************************************/
+/** @addtogroup USART_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions ************************************************/
HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_Private_Constants USART Private Constants
+ * @{
+ */
+/** @brief USART interruptions flag mask
+ *
+ */
+#define USART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
+ USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
+
+#define USART_CR1_REG_INDEX 1
+#define USART_CR2_REG_INDEX 2
+#define USART_CR3_REG_INDEX 3
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup USART_Private_Macros USART Private Macros
+ * @{
+ */
+#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
+ ((NACK) == USART_NACK_DISABLE))
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
+ ((LASTBIT) == USART_LASTBIT_ENABLE))
+#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
+#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
+ ((CLOCK) == USART_CLOCK_ENABLE))
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
+ ((LENGTH) == USART_WORDLENGTH_9B))
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
+ ((STOPBITS) == USART_STOPBITS_0_5) || \
+ ((STOPBITS) == USART_STOPBITS_1_5) || \
+ ((STOPBITS) == USART_STOPBITS_2))
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
+ ((PARITY) == USART_PARITY_EVEN) || \
+ ((PARITY) == USART_PARITY_ODD))
+#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFF3) == 0x00) && ((MODE) != (uint32_t)0x00))
+
+#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 7500001)
+#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(2*(_BAUD_)))
+#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100)
+#define USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define USART_BRR(_PCLK_, _BAUD_) ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup USART_Private_Functions USART Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
/**
* @}
diff --git a/f2/include/stm32f2xx_hal_wwdg.h b/f2/include/stm32f2xx_hal_wwdg.h
index a2502d4e351b1581a0d53dbf289833a3dce26791..3b792d3734f36aabe5cd246e25c87600bea01989 100755
--- a/f2/include/stm32f2xx_hal_wwdg.h
+++ b/f2/include/stm32f2xx_hal_wwdg.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_wwdg.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,19 +54,21 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief WWDG HAL State Structure definition
- */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup WWDG_Exported_Types WWDG Exported Types
+ * @{
+ */
+
+/**
+ * @brief WWDG HAL State Structure definition
+ */
typedef enum
{
HAL_WWDG_STATE_RESET = 0x00, /*!< WWDG not yet initialized or disabled */
HAL_WWDG_STATE_READY = 0x01, /*!< WWDG initialized and ready for use */
- HAL_WWDG_STATE_BUSY = 0x02, /*!< WWDG internal process is ongoing */
+ HAL_WWDG_STATE_BUSY = 0x02, /*!< WWDG internal process is ongoing */
HAL_WWDG_STATE_TIMEOUT = 0x03, /*!< WWDG timeout state */
HAL_WWDG_STATE_ERROR = 0x04 /*!< WWDG error state */
-
}HAL_WWDG_StateTypeDef;
/**
@@ -74,14 +76,14 @@ typedef enum
*/
typedef struct
{
- uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
+ uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
This parameter can be a value of @ref WWDG_Prescaler */
uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
This parameter must be a number lower than Max_Data = 0x80 */
- uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
- This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
+ uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
+ This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
}WWDG_InitTypeDef;
@@ -90,7 +92,7 @@ typedef struct
*/
typedef struct
{
- WWDG_TypeDef *Instance; /*!< Register base address */
+ WWDG_TypeDef *Instance; /*!< Register base address */
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
@@ -99,96 +101,116 @@ typedef struct
__IO HAL_WWDG_StateTypeDef State; /*!< WWDG communication state */
}WWDG_HandleTypeDef;
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Constants
+/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
* @{
*/
-/** @defgroup WWDG_BitAddress_AliasRegion
+/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
* @{
- */
-
-/* --- CFR Register ---*/
-/* Alias word address of EWI bit */
-#define CFR_BASE (uint32_t)(WWDG_BASE + 0x04)
-
+ */
+#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
/**
* @}
*/
-/** @defgroup WWDG_Interrupt_definition
+/** @defgroup WWDG_Flag_definition WWDG Flag definition
+ * @brief WWDG Flag definition
* @{
*/
-#define WWDG_IT_EWI ((uint32_t)WWDG_CFR_EWI)
-
-#define IS_WWDG_IT(IT) ((IT) == WWDG_IT_EWI)
-
+#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
/**
* @}
*/
-/** @defgroup WWDG_Flag_definition
- * @brief WWDG Flag definition
+/** @defgroup WWDG_Prescaler WWDG Prescaler
* @{
*/
-#define WWDG_FLAG_EWIF ((uint32_t)0x0001) /*!< Early wakeup interrupt flag */
-
-#define IS_WWDG_FLAG(FLAG) ((FLAG) == WWDG_FLAG_EWIF))
-
+#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */
/**
* @}
- */
-
-/** @defgroup WWDG_Prescaler
- * @{
*/
-#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define WWDG_PRESCALER_2 ((uint32_t)0x00000080) /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define WWDG_PRESCALER_4 ((uint32_t)0x00000100) /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define WWDG_PRESCALER_8 ((uint32_t)0x00000180) /*!< WWDG counter clock = (PCLK1/4096)/8 */
-
-#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_PRESCALER_1) || \
- ((PRESCALER) == WWDG_PRESCALER_2) || \
- ((PRESCALER) == WWDG_PRESCALER_4) || \
- ((PRESCALER) == WWDG_PRESCALER_8))
/**
* @}
*/
-/** @defgroup WWDG_Window
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
* @{
- */
-#define IS_WWDG_WINDOW(WINDOW) ((WINDOW) <= 0x7F)
+ */
-/**
- * @}
- */
+/** @brief Reset WWDG handle state
+ * @param __HANDLE__: WWDG handle
+ * @retval None
+ */
+#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
-/** @defgroup WWDG_Counter
- * @{
- */
-#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+/**
+ * @brief Enables the WWDG peripheral.
+ * @param __HANDLE__: WWDG handle
+ * @retval None
+ */
+#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
/**
- * @}
- */
+ * @brief Disables the WWDG peripheral.
+ * @param __HANDLE__: WWDG handle
+ * @note WARNING: This is a dummy macro for HAL code alignment.
+ * Once enable, WWDG Peripheral cannot be disabled except by a system reset.
+ * @retval None
+ */
+#define __HAL_WWDG_DISABLE(__HANDLE__) /* dummy macro */
/**
- * @}
+ * @brief Gets the selected WWDG's it status.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the it to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
+ * @retval The new state of WWDG_FLAG (SET or RESET).
*/
+#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
-/* Exported macro ------------------------------------------------------------*/
+/** @brief Clear the WWDG's interrupt pending bits
+ * bits to clear the selected interrupt pending bits.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ */
+#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
/**
- * @brief Enables the WWDG peripheral.
+ * @brief Enables the WWDG early wakeup interrupt.
* @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early wakeup interrupt
+ * @note Once enabled this interrupt cannot be disabled except by a system reset.
* @retval None
*/
-#define __HAL_WWDG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= WWDG_CR_WDGA)
-
+#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
+
+/**
+ * @brief Disables the WWDG early wakeup interrupt.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the interrupt to disable.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early wakeup interrupt
+ * @note WARNING: This is a dummy macro for HAL code alignment.
+ * Once enabled this interrupt cannot be disabled except by a system reset.
+ * @retval None
+ */
+#define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__) /* dummy macro */
+
/**
* @brief Gets the selected WWDG's flag status.
* @param __HANDLE__: WWDG handle
@@ -207,42 +229,117 @@ typedef struct
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
* @retval None
*/
-#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) &= ~(__FLAG__))
+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
+
+/** @brief Checks if the specified WWDG interrupt source is enabled or disabled.
+ * @param __HANDLE__: WWDG Handle.
+ * @param __INTERRUPT__: specifies the WWDG interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early Wakeup Interrupt
+ * @retval state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
/**
- * @brief Enables the WWDG early wakeup interrupt.
- * @note Once enabled this interrupt cannot be disabled except by a system reset.
- * @retval None
+ * @}
*/
-#define __HAL_WWDG_ENABLE_IT(__INTERRUPT__) (*(__IO uint32_t *) CFR_BASE |= (__INTERRUPT__))
-
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup WWDG_Exported_Functions
+ * @{
+ */
+/** @addtogroup WWDG_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
+/**
+ * @}
+ */
+/** @addtogroup WWDG_Exported_Functions_Group2
+ * @{
+ */
/* I/O operation functions ******************************************************/
HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg);
HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg);
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter);
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+/**
+ * @}
+ */
+/** @addtogroup WWDG_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral State functions **************************************************/
HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
-
/**
* @}
*/
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup WWDG_Private_Constants WWDG Private Constants
+ * @{
+ */
+/** @defgroup WWDG_BitAddress_AliasRegion WWDG BitAddress
+ * @brief WWDG registers bit address in the alias region
+ * @{
+ */
+
+/* --- CFR Register ---*/
+/* Alias word address of EWI bit */
+#define WWDG_CFR_BASE (uint32_t)(WWDG_BASE + 0x04)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup WWDG_Private_Macros WWDG Private Macros
+ * @{
+ */
+#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_2) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_8))
+#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F)
+#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup WWDG_Private_Functions WWDG Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/**
* @}
*/
-
+
+/**
+ * @}
+ */
#ifdef __cplusplus
}
#endif
diff --git a/f2/include/stm32f2xx_ll_fsmc.h b/f2/include/stm32f2xx_ll_fsmc.h
index eaa63757834386356b3ab5688b559201d785f0e9..259396c9ff75a608ef9accf5b6f876b693042df0 100755
--- a/f2/include/stm32f2xx_ll_fsmc.h
+++ b/f2/include/stm32f2xx_ll_fsmc.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_ll_fsmc.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of FSMC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -49,80 +49,73 @@
/** @addtogroup STM32F2xx_HAL_Driver
* @{
*/
-
-/** @addtogroup FSMC
+
+/** @addtogroup FSMC_LL
* @{
- */
-
-/* Exported typedef ----------------------------------------------------------*/
-#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
-#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
-#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
+ */
-#define FSMC_NORSRAM_DEVICE FSMC_Bank1
-#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
-#define FSMC_NAND_DEVICE FSMC_Bank2_3
-#define FSMC_PCCARD_DEVICE FSMC_Bank4
+/* Private types -------------------------------------------------------------*/
+/** @defgroup FSMC_LL_Private_Types FSMC Private Types
+ * @{
+ */
/**
- * @brief FSMC_NORSRAM Configuration Structure definition
+ * @brief FSMC NORSRAM Configuration Structure definition
*/
typedef struct
{
uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
- This parameter can be a value of @ref FSMC_NORSRAM_Bank */
-
+ This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+
uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the data bus or not.
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
-
+
uint32_t MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory device.
This parameter can be a value of @ref FSMC_Memory_Type */
-
+
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
-
+
uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
-
+
uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
-
+
uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
memory, valid only when accessing Flash memories in burst mode.
This parameter can be a value of @ref FSMC_Wrap_Mode */
-
+
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
This parameter can be a value of @ref FSMC_Wait_Timing */
-
+
uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
This parameter can be a value of @ref FSMC_Write_Operation */
-
+
uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal */
-
+
uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
This parameter can be a value of @ref FSMC_Extended_Mode */
-
+
uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
This parameter can be a value of @ref FSMC_AsynchronousWait */
-
+
uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FSMC_Write_Burst */
+ This parameter can be a value of @ref FSMC_Write_Burst */
}FSMC_NORSRAM_InitTypeDef;
-
/**
- * @brief FSMC_NORSRAM Timing parameters structure definition
+ * @brief FSMC NORSRAM Timing parameters structure definition
*/
typedef struct
{
@@ -130,28 +123,28 @@ typedef struct
the duration of the address setup time.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
-
+
uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
This parameter can be a value between Min_Data = 1 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
-
+
uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between Min_Data = 1 and Max_Data = 255.
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
NOR Flash memories. */
-
+
uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is only used for multiplexed NOR Flash memories. */
-
+
uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
accesses. */
-
+
uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The parameter value depends on the memory type as shown below:
@@ -159,44 +152,44 @@ typedef struct
- It is don't care in asynchronous NOR, SRAM or ROM accesses
- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
with synchronous burst mode enable */
-
+
uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
This parameter can be a value of @ref FSMC_Access_Mode */
-
+
}FSMC_NORSRAM_TimingTypeDef;
/**
- * @brief FSMC_NAND Configuration Structure definition
+ * @brief FSMC NAND Configuration Structure definition
*/
typedef struct
{
uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
- This parameter can be a value of @ref FSMC_NAND_Bank */
-
+ This parameter can be a value of @ref FSMC_NAND_Bank */
+
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
This parameter can be any value of @ref FSMC_Wait_feature */
-
+
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be any value of @ref FSMC_NAND_Data_Width */
-
+
uint32_t EccComputation; /*!< Enables or disables the ECC computation.
This parameter can be any value of @ref FSMC_ECC */
-
+
uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
This parameter can be any value of @ref FSMC_ECC_Page_Size */
-
+
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
+
}FSMC_NAND_InitTypeDef;
/**
- * @brief FSMC_NAND_PCCARD Timing parameters structure definition
+ * @brief FSMC NAND/PCCARD Timing parameters structure definition
*/
typedef struct
{
@@ -205,113 +198,98 @@ typedef struct
to common/Attribute or I/O memory space (depending on
the memory space timing to be configured).
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
command for NAND-Flash read or write access to
common/Attribute or I/O memory space (depending on the
memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
(and data for write access) after the command de-assertion
for NAND-Flash read or write access to common/Attribute
or I/O memory space (depending on the memory space timing
to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
data bus is kept in HiZ after the start of a NAND-Flash
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
+
}FSMC_NAND_PCC_TimingTypeDef;
/**
- * @brief FSMC_NAND Configuration Structure definition
- */
+ * @brief FSMC NAND Configuration Structure definition
+ */
typedef struct
{
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
This parameter can be any value of @ref FSMC_Wait_feature */
-
+
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
-}FSMC_PCCARD_InitTypeDef;
-/* Exported constants --------------------------------------------------------*/
+}FSMC_PCCARD_InitTypeDef;
+/**
+ * @}
+ */
-/** @defgroup FSMC_NOR_SRAM_Controller
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
+ * @{
+ */
+
+/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
* @{
*/
-
-/** @defgroup FSMC_NORSRAM_Bank
+/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
* @{
*/
#define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
#define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
#define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
#define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
-
-#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_NORSRAM_BANK1) || \
- ((BANK) == FSMC_NORSRAM_BANK2) || \
- ((BANK) == FSMC_NORSRAM_BANK3) || \
- ((BANK) == FSMC_NORSRAM_BANK4))
/**
* @}
*/
-/** @defgroup FSMC_Data_Address_Bus_Multiplexing
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
* @{
*/
-
#define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
-
-#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
- ((MUX) == FSMC_DATA_ADDRESS_MUX_ENABLE))
/**
* @}
*/
-/** @defgroup FSMC_Memory_Type
+/** @defgroup FSMC_Memory_Type FSMC Memory Type
* @{
*/
-
#define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
#define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
-
-
-#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MEMORY_TYPE_SRAM) || \
- ((MEMORY) == FSMC_MEMORY_TYPE_PSRAM)|| \
- ((MEMORY) == FSMC_MEMORY_TYPE_NOR))
/**
* @}
*/
-/** @defgroup FSMC_NORSRAM_Data_Width
+/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
* @{
*/
-
#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
-
-#define IS_FSMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
- ((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
- ((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
/**
* @}
*/
-/** @defgroup FSMC_NORSRAM_Flash_Access
+/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
* @{
*/
#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
@@ -320,232 +298,132 @@ typedef struct
* @}
*/
-/** @defgroup FSMC_Burst_Access_Mode
+/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
* @{
*/
-
#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
-
-#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
- ((STATE) == FSMC_BURST_ACCESS_MODE_ENABLE))
/**
* @}
*/
-
-/** @defgroup FSMC_Wait_Signal_Polarity
+/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
* @{
*/
#define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
-
-#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
- ((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
/**
* @}
*/
-/** @defgroup FSMC_Wrap_Mode
+/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
* @{
*/
#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
#define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
-
-#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WRAP_MODE_DISABLE) || \
- ((MODE) == FSMC_WRAP_MODE_ENABLE))
/**
* @}
*/
-/** @defgroup FSMC_Wait_Timing
+/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
* @{
*/
#define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
-
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WAIT_TIMING_BEFORE_WS) || \
- ((ACTIVE) == FSMC_WAIT_TIMING_DURING_WS))
/**
* @}
*/
-/** @defgroup FSMC_Write_Operation
+/** @defgroup FSMC_Write_Operation FSMC Write Operation
* @{
*/
#define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
-
-#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WRITE_OPERATION_DISABLE) || \
- ((OPERATION) == FSMC_WRITE_OPERATION_ENABLE))
/**
* @}
*/
-/** @defgroup FSMC_Wait_Signal
+/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
* @{
*/
#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
-
-#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WAIT_SIGNAL_DISABLE) || \
- ((SIGNAL) == FSMC_WAIT_SIGNAL_ENABLE))
-
/**
* @}
*/
-/** @defgroup FSMC_Extended_Mode
+/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
* @{
*/
#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
-
-#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_EXTENDED_MODE_DISABLE) || \
- ((MODE) == FSMC_EXTENDED_MODE_ENABLE))
/**
* @}
*/
-/** @defgroup FSMC_AsynchronousWait
+/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
* @{
*/
#define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
-
-#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
- ((STATE) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
-
/**
* @}
*/
-/** @defgroup FSMC_Write_Burst
+/** @defgroup FSMC_Write_Burst FSMC Write Burst
* @{
*/
-
#define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
#define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
-
-#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WRITE_BURST_DISABLE) || \
- ((BURST) == FSMC_WRITE_BURST_ENABLE))
-
/**
* @}
*/
-/** @defgroup FSMC_Continous_Clock
+/** @defgroup FSMC_Continuous_Clock FSMC Continuous Clock
* @{
*/
-
#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
-
-#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
- ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Address_Setup_Time
- * @{
- */
-#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
/**
* @}
*/
-/** @defgroup FSMC_Address_Hold_Time
- * @{
- */
-#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Setup_Time
- * @{
- */
-#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Bus_Turn_around_Duration
- * @{
- */
-#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
-/**
- * @}
- */
-
-/** @defgroup FSMC_CLK_Division
- * @{
- */
-#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Latency
- * @{
- */
-#define IS_FSMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Access_Mode
+/** @defgroup FSMC_Access_Mode FSMC Access Mode
* @{
*/
#define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000)
#define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000)
#define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000)
#define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000)
-
-#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_ACCESS_MODE_A) || \
- ((MODE) == FSMC_ACCESS_MODE_B) || \
- ((MODE) == FSMC_ACCESS_MODE_C) || \
- ((MODE) == FSMC_ACCESS_MODE_D))
/**
* @}
*/
-
/**
* @}
- */
+ */
-/** @defgroup FSMC_NAND_Controller
+/** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
* @{
*/
-
-/** @defgroup FSMC_NAND_Bank
+/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
* @{
- */
+ */
#define FSMC_NAND_BANK2 ((uint32_t)0x00000010)
#define FSMC_NAND_BANK3 ((uint32_t)0x00000100)
-
-#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
- ((BANK) == FSMC_NAND_BANK3))
-
/**
* @}
*/
-/** @defgroup FSMC_Wait_feature
+/** @defgroup FSMC_Wait_feature FSMC Wait feature
* @{
*/
#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
-
-#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
- ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
/**
* @}
*/
-/** @defgroup FSMC_PCR_Memory_Type
+/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
* @{
*/
#define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
@@ -554,31 +432,25 @@ typedef struct
* @}
*/
-/** @defgroup FSMC_NAND_Data_Width
+/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
* @{
*/
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
-
-#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
- ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
/**
* @}
*/
-/** @defgroup FSMC_ECC
+/** @defgroup FSMC_ECC FSMC ECC
* @{
*/
#define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
#define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
-
-#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
- ((STATE) == FSMC_NAND_ECC_ENABLE))
/**
* @}
*/
-/** @defgroup FSMC_ECC_Page_Size
+/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
* @{
*/
#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
@@ -587,154 +459,65 @@ typedef struct
#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
-
-#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
- ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
- ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
- ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
- ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
- ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
-/**
- * @}
- */
-
-/** @defgroup FSMC_TCLR_Setup_Time
- * @{
- */
-#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FSMC_TAR_Setup_Time
- * @{
- */
-#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
/**
* @}
*/
-
-/** @defgroup FSMC_Setup_Time
- * @{
- */
-#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Setup_Time
- * @{
- */
-#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Hold_Setup_Time
- * @{
- */
-#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FSMC_HiZ_Setup_Time
- * @{
- */
-#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
/**
* @}
*/
-
-/**
- * @}
- */
-
-
-/** @defgroup FSMC_NORSRAM_Device_Instance
- * @{
- */
-#define IS_FSMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_DEVICE)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance
- * @{
- */
-#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_EXTENDED_DEVICE)
-
-/**
- * @}
- */
-
- /** @defgroup FSMC_NAND_Device_Instance
- * @{
- */
-#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_PCCARD_Device_Instance
- * @{
- */
-#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
-
-/**
- * @}
- */
-/** @defgroup FSMC_Interrupt_definition
- * @brief FSMC Interrupt definition
+/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
* @{
*/
#define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008)
#define FSMC_IT_LEVEL ((uint32_t)0x00000010)
#define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
#define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
-
-#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
-#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RISING_EDGE) || \
- ((IT) == FSMC_IT_LEVEL) || \
- ((IT) == FSMC_IT_FALLING_EDGE) || \
- ((IT) == FSMC_IT_REFRESH_ERROR))
/**
* @}
*/
-/** @defgroup FSMC_Flag_definition
- * @brief FSMC Flag definition
+/** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
* @{
*/
#define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
#define FSMC_FLAG_LEVEL ((uint32_t)0x00000002)
#define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
+/**
+ * @}
+ */
-#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RISING_EDGE) || \
- ((FLAG) == FSMC_FLAG_LEVEL) || \
- ((FLAG) == FSMC_FLAG_FALLING_EDGE) || \
- ((FLAG) == FSMC_FLAG_FEMPT))
+/** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
+ * @{
+ */
+#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
+#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
+#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
-#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
-
+#define FSMC_NORSRAM_DEVICE FSMC_Bank1
+#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
+#define FSMC_NAND_DEVICE FSMC_Bank2_3
+#define FSMC_PCCARD_DEVICE FSMC_Bank4
/**
* @}
*/
+/**
+ * @}
+ */
-/* Exported macro ------------------------------------------------------------*/
-
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
+ * @{
+ */
-/** @defgroup FSMC_NOR_Macros
+/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
* @brief macros to handle NOR device enable/disable and read/write operations
* @{
*/
-
/**
* @brief Enable the NORSRAM device access.
* @param __INSTANCE__: FSMC_NORSRAM Instance
@@ -750,17 +533,14 @@ typedef struct
* @retval none
*/
#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
-
/**
* @}
*/
-
-/** @defgroup FSMC_NAND_Macros
+/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
* @brief macros to handle NAND device enable/disable
* @{
*/
-
/**
* @brief Enable the NAND device access.
* @param __INSTANCE__: FSMC_NAND Instance
@@ -769,7 +549,6 @@ typedef struct
*/
#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
-
/**
* @brief Disable the NAND device access.
@@ -779,17 +558,14 @@ typedef struct
*/
#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
-
-
/**
* @}
*/
-/** @defgroup FSMC_PCCARD_Macros
- * @brief macros to handle SRAM read/write operations
- * @{
- */
-
+/** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
+ * @brief macros to handle SRAM read/write operations
+ * @{
+ */
/**
* @brief Enable the PCCARD device access.
* @param __INSTANCE__: FSMC_PCCARD Instance
@@ -803,16 +579,14 @@ typedef struct
* @retval none
*/
#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
-
/**
* @}
*/
-/** @defgroup FSMC_Interrupt
- * @brief macros to handle FSMC interrupts
+/** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
+ * @brief macros to handle FSMC flags and interrupts
* @{
*/
-
/**
* @brief Enable the NAND device interrupt.
* @param __INSTANCE__: FSMC_NAND Instance
@@ -844,8 +618,8 @@ typedef struct
/**
* @brief Get flag status of the NAND device.
* @param __INSTANCE__: FSMC_NAND Instance
- * @param __BANK__: FSMC_NAND Bank
- * @param __FLAG__: FSMC_NAND flag
+ * @param __BANK__ : FSMC_NAND Bank
+ * @param __FLAG__ : FSMC_NAND flag
* This parameter can be any combination of the following values:
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
@@ -888,14 +662,14 @@ typedef struct
* This parameter can be any combination of the following values:
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FSMC_IT_LEVEL: Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
/**
* @brief Get flag status of the PCCARD device.
- * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __INSTANCE__: FSMC_PCCARD Instance
* @param __FLAG__: FSMC_PCCARD flag
* This parameter can be any combination of the following values:
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
@@ -908,7 +682,7 @@ typedef struct
/**
* @brief Clear flag status of the PCCARD device.
- * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __INSTANCE__: FSMC_PCCARD Instance
* @param __FLAG__: FSMC_PCCARD flag
* This parameter can be any combination of the following values:
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
@@ -918,111 +692,203 @@ typedef struct
* @retval None
*/
#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
+ * @{
+ */
+#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
+ ((__BANK__) == FSMC_NORSRAM_BANK2) || \
+ ((__BANK__) == FSMC_NORSRAM_BANK3) || \
+ ((__BANK__) == FSMC_NORSRAM_BANK4))
+
+#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
+ ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
+
+#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
+ ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
+ ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
+
+#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
+ ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+ ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
+#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
+ ((__MODE__) == FSMC_ACCESS_MODE_B) || \
+ ((__MODE__) == FSMC_ACCESS_MODE_C) || \
+ ((__MODE__) == FSMC_ACCESS_MODE_D))
+
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
+ ((BANK) == FSMC_NAND_BANK3))
+
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
+ ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+
+#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
+ ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
+
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
+ ((STATE) == FSMC_NAND_ECC_ENABLE))
+
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
+
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
+
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
+
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
+
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
+
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
+
+#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
+
+#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
+
+#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
+
+#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
+
+#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
+ ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
+
+#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
+ ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
+
+#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
+ ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
+
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
+ ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
+
+#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
+ ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
+
+#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
+ ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
+
+#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
+ ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
+
+#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+ ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
+
+#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
+
+#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
+ ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
+
+#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
+
+#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
+
+#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
+
+#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
+
+#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+ ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+
+#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
+
+/**
+ * @}
+ */
/**
* @}
*/
-/* Exported functions --------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
+ * @{
+ */
+
+/** @defgroup FSMC_LL_NORSRAM NOR SRAM
+ * @{
+ */
-/* FSMC_NORSRAM Controller functions ******************************************/
-/* Initialization/de-initialization functions */
+/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
+ * @{
+ */
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+/**
+ * @}
+ */
-/* FSMC_NORSRAM Control functions */
+/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
+ * @{
+ */
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
-/* FSMC_NAND Controller functions *********************************************/
-/* Initialization/de-initialization functions */
+/** @defgroup FSMC_LL_NAND NAND
+ * @{
+ */
+/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
+ * @{
+ */
HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
+/**
+ * @}
+ */
-/* FSMC_NAND Control functions */
+/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
+ * @{
+ */
HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
-/* FSMC_PCCARD Controller functions *******************************************/
-/* Initialization/de-initialization functions */
+/** @defgroup FSMC_LL_PCCARD PCCARD
+ * @{
+ */
+/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
+ * @{
+ */
HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
-/* FSMC APIs, macros and typedefs redefinition */
-#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
-#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
-#define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
-#define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
-
-#define FMC_NORSRAM_Init FSMC_NORSRAM_Init
-#define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
-#define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
-#define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
-#define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
-#define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
-
-#define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
-#define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
-
-#define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
-#define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
-#define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
-
-#define FMC_NAND_Init FSMC_NAND_Init
-#define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
-#define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
-#define FMC_NAND_DeInit FSMC_NAND_DeInit
-#define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
-#define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
-#define FMC_NAND_GetECC FSMC_NAND_GetECC
-#define FMC_PCCARD_Init FSMC_PCCARD_Init
-#define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
-#define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
-#define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
-#define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
-
-#define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
-#define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
-#define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
-#define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
-#define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
-#define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
-#define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
-#define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
-#define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
-#define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
-#define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
-#define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
-
-#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
-#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
-#define FMC_NAND_TypeDef FSMC_NAND_TypeDef
-#define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
-
-#define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
-#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
-#define FMC_NAND_DEVICE FSMC_NAND_DEVICE
-#define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
-
-#define FMC_NAND_BANK2 FSMC_NAND_BANK2
-
-#define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
-#define FMC_IT_LEVEL FSMC_IT_LEVEL
-#define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
-#define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
-
-#define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
-#define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
-#define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
-#define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
/**
* @}
diff --git a/f2/include/stm32f2xx_ll_sdmmc.h b/f2/include/stm32f2xx_ll_sdmmc.h
index 140e0e1ab623eea864b0e8942a4cca62e131cdc7..016393da95b0df6d4a584853da5276ef7093df12 100755
--- a/f2/include/stm32f2xx_ll_sdmmc.h
+++ b/f2/include/stm32f2xx_ll_sdmmc.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_ll_sdmmc.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of SDMMC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,12 +50,15 @@
* @{
*/
-/** @addtogroup SDMMC
+/** @addtogroup SDMMC_LL
* @{
*/
/* Exported types ------------------------------------------------------------*/
-
+/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
+ * @{
+ */
+
/**
* @brief SDMMC Configuration Structure definition
*/
@@ -134,17 +137,20 @@ typedef struct
This parameter can be a value of @ref SDIO_DPSM_State */
}SDIO_DataInitTypeDef;
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SDIO_Exported_Constants
+/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
* @{
*/
-/** @defgroup SDIO_Clock_Edge
+/** @defgroup SDIO_Clock_Edge Clock Edge
* @{
*/
#define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
-#define SDIO_CLOCK_EDGE_FALLING ((uint32_t)0x00002000)
+#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
((EDGE) == SDIO_CLOCK_EDGE_FALLING))
@@ -152,11 +158,11 @@ typedef struct
* @}
*/
-/** @defgroup SDIO_Clock_Bypass
+/** @defgroup SDIO_Clock_Bypass Clock Bypass
* @{
*/
#define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
-#define SDIO_CLOCK_BYPASS_ENABLE ((uint32_t)0x00000400)
+#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
@@ -164,11 +170,11 @@ typedef struct
* @}
*/
-/** @defgroup SDIO_Clock_Power_Save
+/** @defgroup SDIO_Clock_Power_Save Clock Power Saving
* @{
*/
#define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
-#define SDIO_CLOCK_POWER_SAVE_ENABLE ((uint32_t)0x00000200)
+#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
@@ -176,12 +182,12 @@ typedef struct
* @}
*/
-/** @defgroup SDIO_Bus_Wide
+/** @defgroup SDIO_Bus_Wide Bus Width
* @{
*/
#define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
-#define SDIO_BUS_WIDE_4B ((uint32_t)0x00000800)
-#define SDIO_BUS_WIDE_8B ((uint32_t)0x00001000)
+#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
+#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
((WIDE) == SDIO_BUS_WIDE_4B) || \
@@ -190,11 +196,11 @@ typedef struct
* @}
*/
-/** @defgroup SDIO_Hardware_Flow_Control
+/** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control
* @{
*/
#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
-#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE ((uint32_t)0x00004000)
+#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
@@ -202,19 +208,15 @@ typedef struct
* @}
*/
-/** @defgroup SDIO_Clock_Division
+/** @defgroup SDIO_Clock_Division Clock Division
* @{
*/
#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
/**
* @}
*/
-
-/**
- * @}
- */
-/** @defgroup SDIO_Command_Index
+/** @defgroup SDIO_Command_Index Command Index
* @{
*/
#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
@@ -222,12 +224,12 @@ typedef struct
* @}
*/
-/** @defgroup SDIO_Response_Type
+/** @defgroup SDIO_Response_Type Response Type
* @{
*/
#define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
-#define SDIO_RESPONSE_SHORT ((uint32_t)0x00000040)
-#define SDIO_RESPONSE_LONG ((uint32_t)0x000000C0)
+#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
+#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
((RESPONSE) == SDIO_RESPONSE_SHORT) || \
@@ -236,12 +238,12 @@ typedef struct
* @}
*/
-/** @defgroup SDIO_Wait_Interrupt_State
+/** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt
* @{
*/
#define SDIO_WAIT_NO ((uint32_t)0x00000000)
-#define SDIO_WAIT_IT ((uint32_t)0x00000100)
-#define SDIO_WAIT_PEND ((uint32_t)0x00000200)
+#define SDIO_WAIT_IT SDIO_CMD_WAITINT
+#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
((WAIT) == SDIO_WAIT_IT) || \
@@ -250,11 +252,11 @@ typedef struct
* @}
*/
-/** @defgroup SDIO_CPSM_State
+/** @defgroup SDIO_CPSM_State CPSM State
* @{
*/
#define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
-#define SDIO_CPSM_ENABLE ((uint32_t)0x00000400)
+#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
((CPSM) == SDIO_CPSM_ENABLE))
@@ -262,7 +264,7 @@ typedef struct
* @}
*/
-/** @defgroup SDIO_Response_Registers
+/** @defgroup SDIO_Response_Registers Response Register
* @{
*/
#define SDIO_RESP1 ((uint32_t)0x00000000)
@@ -278,7 +280,7 @@ typedef struct
* @}
*/
-/** @defgroup SDIO_Data_Length
+/** @defgroup SDIO_Data_Length Data Lenght
* @{
*/
#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
@@ -286,18 +288,18 @@ typedef struct
* @}
*/
-/** @defgroup SDIO_Data_Block_Size
+/** @defgroup SDIO_Data_Block_Size Data Block Size
* @{
*/
#define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
-#define SDIO_DATABLOCK_SIZE_2B ((uint32_t)0x00000010)
-#define SDIO_DATABLOCK_SIZE_4B ((uint32_t)0x00000020)
+#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
+#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
#define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030)
-#define SDIO_DATABLOCK_SIZE_16B ((uint32_t)0x00000040)
+#define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
#define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050)
#define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060)
#define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070)
-#define SDIO_DATABLOCK_SIZE_256B ((uint32_t)0x00000080)
+#define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
#define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090)
#define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0)
#define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0)
@@ -324,11 +326,11 @@ typedef struct
* @}
*/
-/** @defgroup SDIO_Transfer_Direction
+/** @defgroup SDIO_Transfer_Direction Transfer Direction
* @{
*/
#define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
-#define SDIO_TRANSFER_DIR_TO_SDIO ((uint32_t)0x00000002)
+#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
@@ -336,11 +338,11 @@ typedef struct
* @}
*/
-/** @defgroup SDIO_Transfer_Type
+/** @defgroup SDIO_Transfer_Type Transfer Type
* @{
*/
#define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
-#define SDIO_TRANSFER_MODE_STREAM ((uint32_t)0x00000004)
+#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
((MODE) == SDIO_TRANSFER_MODE_STREAM))
@@ -348,11 +350,11 @@ typedef struct
* @}
*/
-/** @defgroup SDIO_DPSM_State
+/** @defgroup SDIO_DPSM_State DPSM State
* @{
*/
#define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
-#define SDIO_DPSM_ENABLE ((uint32_t)0x00000001)
+#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
((DPSM) == SDIO_DPSM_ENABLE))
@@ -360,11 +362,11 @@ typedef struct
* @}
*/
-/** @defgroup SDIO_Read_Wait_Mode
+/** @defgroup SDIO_Read_Wait_Mode Read Wait Mode
* @{
*/
-#define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000000)
-#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000001)
+#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000)
+#define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000001)
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
((MODE) == SDIO_READ_WAIT_MODE_DATA2))
@@ -372,243 +374,192 @@ typedef struct
* @}
*/
-/** @defgroup SDIO_Interrupt_sources
+/** @defgroup SDIO_Interrupt_sources Interrupt Sources
* @{
*/
-#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
-#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
-#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
-#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
-#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
-#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
-#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
-#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
-#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
-#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
-#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
-#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
-#define SDIO_IT_TXACT ((uint32_t)0x00001000)
-#define SDIO_IT_RXACT ((uint32_t)0x00002000)
-#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
-#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
-#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
-#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
-#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
-#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
-#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
-#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
-#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
-#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
-
-#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
+#define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
+#define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
+#define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
+#define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
+#define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
+#define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
+#define SDIO_IT_CMDREND SDIO_STA_CMDREND
+#define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
+#define SDIO_IT_DATAEND SDIO_STA_DATAEND
+#define SDIO_IT_STBITERR SDIO_STA_STBITERR
+#define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
+#define SDIO_IT_CMDACT SDIO_STA_CMDACT
+#define SDIO_IT_TXACT SDIO_STA_TXACT
+#define SDIO_IT_RXACT SDIO_STA_RXACT
+#define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
+#define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
+#define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
+#define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
+#define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
+#define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
+#define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
+#define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
+#define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
+#define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
/**
* @}
*/
-/** @defgroup SDIO_Flags
+/** @defgroup SDIO_Flags Flags
* @{
*/
-#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
-#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
-#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
-#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
-#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
-#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
-#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
-#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
-#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
-#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
-#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
-#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
-#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
-#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
-#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
-#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
-#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
-#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
-#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
-#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
-#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
-#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
-#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
-#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
-
-#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
- ((FLAG) == SDIO_FLAG_DCRCFAIL) || \
- ((FLAG) == SDIO_FLAG_CTIMEOUT) || \
- ((FLAG) == SDIO_FLAG_DTIMEOUT) || \
- ((FLAG) == SDIO_FLAG_TXUNDERR) || \
- ((FLAG) == SDIO_FLAG_RXOVERR) || \
- ((FLAG) == SDIO_FLAG_CMDREND) || \
- ((FLAG) == SDIO_FLAG_CMDSENT) || \
- ((FLAG) == SDIO_FLAG_DATAEND) || \
- ((FLAG) == SDIO_FLAG_STBITERR) || \
- ((FLAG) == SDIO_FLAG_DBCKEND) || \
- ((FLAG) == SDIO_FLAG_CMDACT) || \
- ((FLAG) == SDIO_FLAG_TXACT) || \
- ((FLAG) == SDIO_FLAG_RXACT) || \
- ((FLAG) == SDIO_FLAG_TXFIFOHE) || \
- ((FLAG) == SDIO_FLAG_RXFIFOHF) || \
- ((FLAG) == SDIO_FLAG_TXFIFOF) || \
- ((FLAG) == SDIO_FLAG_RXFIFOF) || \
- ((FLAG) == SDIO_FLAG_TXFIFOE) || \
- ((FLAG) == SDIO_FLAG_RXFIFOE) || \
- ((FLAG) == SDIO_FLAG_TXDAVL) || \
- ((FLAG) == SDIO_FLAG_RXDAVL) || \
- ((FLAG) == SDIO_FLAG_SDIOIT) || \
- ((FLAG) == SDIO_FLAG_CEATAEND))
-
-#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
-
-#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
- ((IT) == SDIO_IT_DCRCFAIL) || \
- ((IT) == SDIO_IT_CTIMEOUT) || \
- ((IT) == SDIO_IT_DTIMEOUT) || \
- ((IT) == SDIO_IT_TXUNDERR) || \
- ((IT) == SDIO_IT_RXOVERR) || \
- ((IT) == SDIO_IT_CMDREND) || \
- ((IT) == SDIO_IT_CMDSENT) || \
- ((IT) == SDIO_IT_DATAEND) || \
- ((IT) == SDIO_IT_STBITERR) || \
- ((IT) == SDIO_IT_DBCKEND) || \
- ((IT) == SDIO_IT_CMDACT) || \
- ((IT) == SDIO_IT_TXACT) || \
- ((IT) == SDIO_IT_RXACT) || \
- ((IT) == SDIO_IT_TXFIFOHE) || \
- ((IT) == SDIO_IT_RXFIFOHF) || \
- ((IT) == SDIO_IT_TXFIFOF) || \
- ((IT) == SDIO_IT_RXFIFOF) || \
- ((IT) == SDIO_IT_TXFIFOE) || \
- ((IT) == SDIO_IT_RXFIFOE) || \
- ((IT) == SDIO_IT_TXDAVL) || \
- ((IT) == SDIO_IT_RXDAVL) || \
- ((IT) == SDIO_IT_SDIOIT) || \
- ((IT) == SDIO_IT_CEATAEND))
-
-#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
-
+#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
+#define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
+#define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
+#define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
+#define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
+#define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
+#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
+#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
+#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
+#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
+#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
+#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
+#define SDIO_FLAG_TXACT SDIO_STA_TXACT
+#define SDIO_FLAG_RXACT SDIO_STA_RXACT
+#define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
+#define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
+#define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
+#define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
+#define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
+#define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
+#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
+#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
+#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
+#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
/**
* @}
*/
-
-/** @defgroup SDIO_Instance_definition
- * @{
- */
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
/**
* @}
*/
-
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
+ * @{
+ */
+
+/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
+ * @{
+ */
/* ------------ SDIO registers bit address in the alias region -------------- */
#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
/* --- CLKCR Register ---*/
/* Alias word address of CLKEN bit */
#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
-#define CLKEN_BitNumber 0x08
-#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
+#define CLKEN_BITNUMBER 0x08
+#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4))
/* --- CMD Register ---*/
/* Alias word address of SDIOSUSPEND bit */
#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
-#define SDIOSUSPEND_BitNumber 0x0B
-#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
+#define SDIOSUSPEND_BITNUMBER 0x0B
+#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4))
/* Alias word address of ENCMDCOMPL bit */
-#define ENCMDCOMPL_BitNumber 0x0C
-#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
+#define ENCMDCOMPL_BITNUMBER 0x0C
+#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4))
/* Alias word address of NIEN bit */
-#define NIEN_BitNumber 0x0D
-#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
+#define NIEN_BITNUMBER 0x0D
+#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4))
/* Alias word address of ATACMD bit */
-#define ATACMD_BitNumber 0x0E
-#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
+#define ATACMD_BITNUMBER 0x0E
+#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4))
/* --- DCTRL Register ---*/
/* Alias word address of DMAEN bit */
#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
-#define DMAEN_BitNumber 0x03
-#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
+#define DMAEN_BITNUMBER 0x03
+#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4))
/* Alias word address of RWSTART bit */
-#define RWSTART_BitNumber 0x08
-#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
+#define RWSTART_BITNUMBER 0x08
+#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4))
/* Alias word address of RWSTOP bit */
-#define RWSTOP_BitNumber 0x09
-#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
+#define RWSTOP_BITNUMBER 0x09
+#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4))
/* Alias word address of RWMOD bit */
-#define RWMOD_BitNumber 0x0A
-#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
+#define RWMOD_BITNUMBER 0x0A
+#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4))
/* Alias word address of SDIOEN bit */
-#define SDIOEN_BitNumber 0x0B
-#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
+#define SDIOEN_BITNUMBER 0x0B
+#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4))
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
+ * @brief SDMMC_LL registers bit address in the alias region
+ * @{
+ */
/* ---------------------- SDIO registers bit mask --------------------------- */
/* --- CLKCR Register ---*/
-/* CLKCR register clear mask */
-#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
+/* CLKCR register clear mask */
+#define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\
+ SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\
+ SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
/* --- PWRCTRL Register ---*/
-/* SDIO PWRCTRL Mask */
-#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
-
/* --- DCTRL Register ---*/
/* SDIO DCTRL Clear Mask */
-#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
+#define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\
+ SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE))
/* --- CMD Register ---*/
/* CMD Register clear mask */
-#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
+#define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
+ SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\
+ SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND))
/* SDIO RESP Registers Address */
#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
-/* SD FLASH SDIO Interface */
-#define SDIO_FIFO_ADDRESS ((uint32_t)0x40012C80)
-
-/* SDIO Intialization Frequency (400KHz max) */
+/* SDIO Initialization Frequency (400KHz max) */
#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
/* SDIO Data Transfer Frequency (25MHz max) */
#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
+/**
+ * @}
+ */
+
+/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
-/** @defgroup SDIO_Interrupt_Clock
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-
/**
* @brief Enable the SDIO device.
- * @param None
* @retval None
*/
#define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
/**
* @brief Disable the SDIO device.
- * @param None
* @retval None
*/
#define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
/**
* @brief Enable the SDIO DMA transfer.
- * @param None
* @retval None
*/
#define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
/**
* @brief Disable the SDIO DMA transfer.
- * @param None
* @retval None
*/
#define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
@@ -716,7 +667,7 @@ typedef struct
/**
- * @brief Clears the SDIO's pending flags.
+ * @brief Clears the SDIO pending flags.
* @param __INSTANCE__ : Pointer to SDIO register base
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
@@ -795,98 +746,84 @@ typedef struct
/**
* @brief Enable Start the SD I/O Read Wait operation.
- * @param None
* @retval None
*/
#define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
/**
* @brief Disable Start the SD I/O Read Wait operations.
- * @param None
* @retval None
*/
#define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
/**
* @brief Enable Start the SD I/O Read Wait operation.
- * @param None
* @retval None
*/
#define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
/**
* @brief Disable Stop the SD I/O Read Wait operations.
- * @param None
* @retval None
*/
#define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
/**
* @brief Enable the SD I/O Mode Operation.
- * @param None
* @retval None
*/
#define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
/**
* @brief Disable the SD I/O Mode Operation.
- * @param None
* @retval None
*/
#define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
/**
* @brief Enable the SD I/O Suspend command sending.
- * @param None
* @retval None
*/
#define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
/**
* @brief Disable the SD I/O Suspend command sending.
- * @param None
* @retval None
*/
#define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
/**
* @brief Enable the command completion signal.
- * @param None
* @retval None
*/
#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
/**
* @brief Disable the command completion signal.
- * @param None
* @retval None
*/
#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
/**
* @brief Enable the CE-ATA interrupt.
- * @param None
* @retval None
*/
#define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
/**
* @brief Disable the CE-ATA interrupt.
- * @param None
* @retval None
*/
#define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
/**
* @brief Enable send CE-ATA command (CMD61).
- * @param None
* @retval None
*/
#define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
/**
* @brief Disable send CE-ATA command (CMD61).
- * @param None
* @retval None
*/
#define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
@@ -895,17 +832,39 @@ typedef struct
* @}
*/
-/* Exported functions --------------------------------------------------------*/
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SDMMC_LL_Exported_Functions
+ * @{
+ */
+
/* Initialization/de-initialization functions **********************************/
+/** @addtogroup HAL_SDMMC_LL_Group1
+ * @{
+ */
HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
-
+/**
+ * @}
+ */
+
/* I/O operation functions *****************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group2
+ * @{
+ */
/* Blocking mode: Polling */
uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
-
+/**
+ * @}
+ */
+
/* Peripheral Control functions ************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group3
+ * @{
+ */
HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
@@ -926,11 +885,18 @@ HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
/**
* @}
*/
-
+
/**
* @}
*/
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
#ifdef __cplusplus
}
@@ -938,12 +904,4 @@ HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
#endif /* __STM32F2xx_LL_SDMMC_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f2/include/stm32f2xx_ll_usb.h b/f2/include/stm32f2xx_ll_usb.h
index 91f9bb54ccb7b624f5b3aa1584414bdd85053529..5f2956a32efd316b12d5e70da939558a56a642ce 100755
--- a/f2/include/stm32f2xx_ll_usb.h
+++ b/f2/include/stm32f2xx_ll_usb.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_ll_usb.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Header file of USB Core HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,7 +50,7 @@
* @{
*/
-/** @addtogroup USB
+/** @addtogroup USB_Core
* @{
*/
@@ -224,11 +224,11 @@ typedef struct
/* Exported constants --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Constants
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
-/** @defgroup USB_Core_Mode_
+/** @defgroup USB_Core_Mode_ USB Core Mode
* @{
*/
#define USB_OTG_MODE_DEVICE 0
@@ -238,7 +238,7 @@ typedef struct
* @}
*/
-/** @defgroup USB_Core_Speed_
+/** @defgroup USB_Core_Speed_ USB Core Speed
* @{
*/
#define USB_OTG_SPEED_HIGH 0
@@ -249,7 +249,7 @@ typedef struct
* @}
*/
-/** @defgroup USB_Core_PHY_
+/** @defgroup USB_Core_PHY_ USB Core PHY
* @{
*/
#define USB_OTG_ULPI_PHY 1
@@ -258,7 +258,7 @@ typedef struct
* @}
*/
-/** @defgroup USB_Core_MPS_
+/** @defgroup USB_Core_MPS_ USB Core MPS
* @{
*/
#define USB_OTG_HS_MAX_PACKET_SIZE 512
@@ -268,7 +268,7 @@ typedef struct
* @}
*/
-/** @defgroup USB_Core_Phy_Frequency_
+/** @defgroup USB_Core_Phy_Frequency_ USB Core Phy Frequency
* @{
*/
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0 << 1)
@@ -279,7 +279,7 @@ typedef struct
* @}
*/
-/** @defgroup USB_CORE_Frame_Interval_
+/** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval
* @{
*/
#define DCFG_FRAME_INTERVAL_80 0
@@ -290,7 +290,7 @@ typedef struct
* @}
*/
-/** @defgroup USB_EP0_MPS_
+/** @defgroup USB_EP0_MPS_ USB EP0 MPS
* @{
*/
#define DEP0CTL_MPS_64 0
@@ -301,7 +301,7 @@ typedef struct
* @}
*/
-/** @defgroup USB_EP_Speed_
+/** @defgroup USB_EP_Speed_ USB EP Speed
* @{
*/
#define EP_SPEED_LOW 0
@@ -311,7 +311,7 @@ typedef struct
* @}
*/
-/** @defgroup USB_EP_Type_
+/** @defgroup USB_EP_Type_ USB EP Type
* @{
*/
#define EP_TYPE_CTRL 0
@@ -323,7 +323,7 @@ typedef struct
* @}
*/
-/** @defgroup USB_STS_Defines_
+/** @defgroup USB_STS_Defines_ USB STS Defines
* @{
*/
#define STS_GOUT_NAK 1
@@ -335,7 +335,7 @@ typedef struct
* @}
*/
-/** @defgroup HCFG_SPEED_Defines_
+/** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines
* @{
*/
#define HCFG_30_60_MHZ 0
@@ -345,7 +345,7 @@ typedef struct
* @}
*/
-/** @defgroup HPRT0_PRTSPD_SPEED_Defines_
+/** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines
* @{
*/
#define HPRT0_PRTSPD_HIGH_SPEED 0
@@ -354,11 +354,7 @@ typedef struct
/**
* @}
*/
-
-/**
- * @}
- */
-
+
#define HCCHAR_CTRL 0
#define HCCHAR_ISOC 1
#define HCCHAR_BULK 2
@@ -384,7 +380,9 @@ typedef struct
#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
-
+/**
+ * @}
+ */
/* Exported macro ------------------------------------------------------------*/
#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
diff --git a/f2/src/devices/system_stm32f2xx.c b/f2/src/devices/system_stm32f2xx.c
index 6f01232b1744bd3f3ee17c8eca586a2248197859..1c4af190edb5d9794cb05fc485c4fb736af24958 100755
--- a/f2/src/devices/system_stm32f2xx.c
+++ b/f2/src/devices/system_stm32f2xx.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f2xx.c
* @author MCD Application Team
- * @version V2.0.1
- * @date 25-March-2014
+ * @version V2.1.0
+ * @date 09-October-2015
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@@ -23,7 +23,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -62,7 +62,15 @@
* @{
*/
-#include "stm32f2xx_hal.h"
+#include "stm32f2xx.h"
+
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
/**
* @}
@@ -107,7 +115,7 @@
* @{
*/
- /* This varaible can be updated in Three ways :
+ /* This variable can be updated in Three ways :
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
@@ -116,7 +124,7 @@
variable is updated automatically.
*/
uint32_t SystemCoreClock = 12000000;
- __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+ const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
@@ -245,7 +253,7 @@ void SystemCoreClockUpdate(void)
else
{
/* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
@@ -262,12 +270,6 @@ void SystemCoreClockUpdate(void)
SystemCoreClock >>= tmp;
}
-/**
- * @brief Setup the external memory controller. Called in startup_stm32f2xx.s
- * before jump to __main
- * @param None
- * @retval None
- */
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
@@ -279,111 +281,71 @@ void SystemCoreClockUpdate(void)
*/
void SystemInit_ExtMemCtl(void)
{
+ __IO uint32_t tmp = 0x00;
+
/*-- GPIOs Configuration -----------------------------------------------------*/
-/*
- +-------------------+--------------------+------------------+------------------+
- + SRAM pins assignment +
- +-------------------+--------------------+------------------+------------------+
- | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
- | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
- | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
- | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
- | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
- | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
- | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
- | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
- | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
- | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
- | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+
- +-------------------+--------------------+
-*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
- RCC->AHB1ENR = 0x00000078;
-
+ RCC->AHB1ENR |= 0x00000078;
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
+ (void)(tmp);
+
/* Connect PDx pins to FSMC Alternate function */
- GPIOD->AFR[0] = 0x00cc00cc;
- GPIOD->AFR[1] = 0xcc0ccccc;
+ GPIOD->AFR[0] = 0x00CCC0CC;
+ GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */
- GPIOD->MODER = 0xa2aa0a0a;
+ GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */
- GPIOD->OSPEEDR = 0xf3ff0f0f;
+ GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FSMC Alternate function */
- GPIOE->AFR[0] = 0xc00000cc;
- GPIOE->AFR[1] = 0xcccccccc;
+ GPIOE->AFR[0] = 0xC00CC0CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
- GPIOE->MODER = 0xaaaa800a;
+ GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 100 MHz */
- GPIOE->OSPEEDR = 0xffffc00f;
+ GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FSMC Alternate function */
- GPIOF->AFR[0] = 0x00cccccc;
- GPIOF->AFR[1] = 0xcccc0000;
+ GPIOF->AFR[0] = 0x00CCCCCC;
+ GPIOF->AFR[1] = 0xCCCC0000;
/* Configure PFx pins in Alternate function mode */
- GPIOF->MODER = 0xaa000aaa;
+ GPIOF->MODER = 0xAA000AAA;
/* Configure PFx pins speed to 100 MHz */
- GPIOF->OSPEEDR = 0xff000fff;
+ GPIOF->OSPEEDR = 0xFF000FFF;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FSMC Alternate function */
- GPIOG->AFR[0] = 0x00cccccc;
- GPIOG->AFR[1] = 0x000000c0;
+ GPIOG->AFR[0] = 0x00CCCCCC;
+ GPIOG->AFR[1] = 0x000000C0;
/* Configure PGx pins in Alternate function mode */
- GPIOG->MODER = 0x00080aaa;
+ GPIOG->MODER = 0x00085AAA;
/* Configure PGx pins speed to 100 MHz */
- GPIOG->OSPEEDR = 0x000c0fff;
+ GPIOG->OSPEEDR = 0x000CAFFF;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
-/*-- FSMC Configuration ------------------------------------------------------*/
+/*--FSMC Configuration -------------------------------------------------------*/
/* Enable the FSMC interface clock */
- RCC->AHB3ENR = 0x00000001;
+ RCC->AHB3ENR |= 0x00000001;
/* Configure and enable Bank1_SRAM2 */
- FSMC_Bank1->BTCR[2] = 0x00001015;
- FSMC_Bank1->BTCR[3] = 0x00010400;
- FSMC_Bank1E->BWTR[2] = 0x0fffffff;
-/*
- Bank1_SRAM2 is configured as follow:
-
- p.FSMC_AddressSetupTime = 0;
- p.FSMC_AddressHoldTime = 0;
- p.FSMC_DataSetupTime = 4;
- p.FSMC_BusTurnAroundDuration = 1;
- p.FSMC_CLKDivision = 0;
- p.FSMC_DataLatency = 0;
- p.FSMC_AccessMode = FSMC_AccessMode_A;
-
- FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
- FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
- FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
- FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
- FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
- FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
- FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
- FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
- FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
- FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
- FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
- FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
- FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
- FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
- FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
-*/
-
+ FSMC_Bank1->BTCR[2] = 0x00001011;
+ FSMC_Bank1->BTCR[3] = 0x00000201;
+ FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
}
#endif /* DATA_IN_ExtSRAM */
diff --git a/f2/src/stm32f2xx_hal.c b/f2/src/stm32f2xx_hal.c
index 6c60ecbcd53d3879562a6d744e81dc8c318851f7..ba1555c3d3e3fb58c7358fc4ed1b6da2238a3035 100755
--- a/f2/src/stm32f2xx_hal.c
+++ b/f2/src/stm32f2xx_hal.c
@@ -2,11 +2,11 @@
******************************************************************************
* @file stm32f2xx_hal.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief HAL module driver.
* This is the common part of the HAL initialization
- *
+ *
@verbatim
==============================================================================
##### How to use this driver #####
@@ -23,7 +23,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -57,25 +57,28 @@
* @{
*/
-/** @defgroup HAL
+/** @defgroup HAL HAL
* @brief HAL module driver.
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup HAL_Private_Constants
+ * @{
+ */
/**
- * @brief STM32F2xx HAL Driver version number V1.0.1
- */
+ * @brief STM32F2xx HAL Driver version number V1.1.0
+ */
#define __STM32F2xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32F2xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
-#define __STM32F2xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
+#define __STM32F2xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F2xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F2xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F2xx_HAL_VERSION ((__STM32F2xx_HAL_VERSION_MAIN << 24)\
|(__STM32F2xx_HAL_VERSION_SUB1 << 16)\
|(__STM32F2xx_HAL_VERSION_SUB2 << 8 )\
|(__STM32F2xx_HAL_VERSION_RC))
-
+
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
/* ------------ RCC registers bit address in the alias region ----------- */
@@ -83,26 +86,35 @@
/* --- MEMRMP Register ---*/
/* Alias word address of UFB_MODE bit */
#define MEMRMP_OFFSET SYSCFG_OFFSET
-#define UFB_MODE_BitNumber ((uint8_t)0x8)
-#define UFB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BitNumber * 4))
+#define UFB_MODE_BIT_NUMBER POSITION_VAL(SYSCFG_MEMRMP_UFB_MODE)
+#define UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BIT_NUMBER * 4))
/* --- CMPCR Register ---*/
/* Alias word address of CMP_PD bit */
#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20)
-#define CMP_PD_BitNumber ((uint8_t)0x00)
-#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4))
+#define CMP_PD_BIT_NUMBER POSITION_VAL(SYSCFG_CMPCR_CMP_PD)
+#define CMPCR_CMP_PD_BB (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BIT_NUMBER * 4))
+/**
+ * @}
+ */
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/** @addtogroup HAL_Private_Variables
+ * @{
+ */
static __IO uint32_t uwTick;
-
+/**
+ * @}
+ */
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup HAL_Private_Functions
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
* @{
*/
-/** @defgroup HAL_Group1 Initialization and de-initialization Functions
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
* @brief Initialization and de-initialization functions
*
@verbatim
@@ -114,7 +126,23 @@ static __IO uint32_t uwTick;
configuration. It initializes the systick also when timeout is needed
and the backup domain when enabled.
(+) de-Initializes common part of the HAL
-
+ (+) Configure The time base source to have 1ms time base with a dedicated
+ Tick interrupt priority.
+ (++) Systick timer is used by default as source of time base, but user
+ can eventually implement his proper time base source (a general purpose
+ timer for example or other time source), keeping in mind that Time base
+ duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+ handled in milliseconds basis.
+ (++) Time base configuration function (HAL_InitTick ()) is called automatically
+ at the beginning of the program after reset by HAL_Init() or at any time
+ when clock is configured, by HAL_RCC_ClockConfig().
+ (++) Source of time base is configured to generate interrupts at regular
+ time intervals. Care must be taken if HAL_Delay() is called from a
+ peripheral ISR process, the Tick interrupt line must have higher priority
+ (numerically lower) than the peripheral interrupt. Otherwise the caller
+ ISR process will be blocked.
+ (++) functions affecting time base configurations are declared as __weak
+ to make override possible in case of other implementations in user file.
@endverbatim
* @{
*/
@@ -123,19 +151,17 @@ static __IO uint32_t uwTick;
* @brief This function is used to initialize the HAL Library; it must be the first
* instruction to be executed in the main program (before to call any other
* HAL function), it performs the following:
- * - Configure the Flash prefetch, instruction and Data caches
- * - Configures the SysTick to generate an interrupt each 1 millisecond,
- * which is clocked by the HSI (at this stage, the clock is not yet
- * configured and thus the system is running from the internal HSI at 16 MHz)
- * - Set NVIC Group Priority to 4
- * - Calls the HAL_MspInit() callback function defined in user file
- * stm32f4xx_hal_msp.c to do the global low level hardware initialization
+ * Configure the Flash prefetch, instruction and Data caches.
+ * Configures the SysTick to generate an interrupt each 1 millisecond,
+ * which is clocked by the HSI (at this stage, the clock is not yet
+ * configured and thus the system is running from the internal HSI at 16 MHz).
+ * Set NVIC Group Priority to 4.
+ * Calls the HAL_MspInit() callback function defined in user file
+ * "stm32f2xx_hal_msp.c" to do the global low level hardware initialization
*
* @note SysTick is used as time base for the HAL_Delay() function, the application
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
- * @note
- * @param None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
@@ -153,11 +179,11 @@ HAL_StatusTypeDef HAL_Init(void)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
- /* Enable systick and configure 1ms tick (default clock after Reset is HSI) */
- HAL_SYSTICK_Config(HSI_VALUE/ 1000);
-
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+ HAL_InitTick(TICK_INT_PRIORITY);
/* Init the low level hardware */
HAL_MspInit();
@@ -169,26 +195,25 @@ HAL_StatusTypeDef HAL_Init(void)
/**
* @brief This function de-Initializes common part of the HAL and stops the systick.
* This function is optional.
- * @param None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DeInit(void)
{
/* Reset of all peripherals */
- __APB1_FORCE_RESET();
- __APB1_RELEASE_RESET();
+ __HAL_RCC_APB1_FORCE_RESET();
+ __HAL_RCC_APB1_RELEASE_RESET();
- __APB2_FORCE_RESET();
- __APB2_RELEASE_RESET();
+ __HAL_RCC_APB2_FORCE_RESET();
+ __HAL_RCC_APB2_RELEASE_RESET();
- __AHB1_FORCE_RESET();
- __AHB1_RELEASE_RESET();
+ __HAL_RCC_AHB1_FORCE_RESET();
+ __HAL_RCC_AHB1_RELEASE_RESET();
- __AHB2_FORCE_RESET();
- __AHB2_RELEASE_RESET();
+ __HAL_RCC_AHB2_FORCE_RESET();
+ __HAL_RCC_AHB2_RELEASE_RESET();
- __AHB3_FORCE_RESET();
- __AHB3_RELEASE_RESET();
+ __HAL_RCC_AHB3_FORCE_RESET();
+ __HAL_RCC_AHB3_RELEASE_RESET();
/* De-Init the low level hardware */
HAL_MspDeInit();
@@ -199,19 +224,17 @@ HAL_StatusTypeDef HAL_DeInit(void)
/**
* @brief Initializes the MSP.
- * @param None
* @retval None
*/
__weak void HAL_MspInit(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MspInit could be implemented in the user file
- */
+ */
}
/**
* @brief DeInitializes the MSP.
- * @param None
* @retval None
*/
__weak void HAL_MspDeInit(void)
@@ -221,77 +244,140 @@ __weak void HAL_MspDeInit(void)
*/
}
+/**
+ * @brief This function configures the source of the time base.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
+ * @note In the default implementation, SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals.
+ * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+ * The the SysTick interrupt must have higher priority (numerically lower)
+ * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+ * The function is declared as __weak to be overwritten in case of other
+ * implementation in user file.
+ * @param TickPriority: Tick interrupt priority.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ /*Configure the SysTick to have interrupt in 1ms time basis*/
+ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
+
+ /*Configure the SysTick IRQ priority */
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
/**
* @}
*/
-/** @defgroup HAL_Group2 HAL Control functions
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
* @brief HAL Control functions
*
-@verbatim
+@verbatim
===============================================================================
##### HAL Control functions #####
===============================================================================
[..] This section provides functions allowing to:
- (+) provide a tick value in millisecond
- (+) provide a blocking delay in millisecond
+ (+) Provide a tick value in millisecond
+ (+) Provide a blocking delay in millisecond
+ (+) Suspend the time base source interrupt
+ (+) Resume the time base source interrupt
(+) Get the HAL API driver version
(+) Get the device identifier
(+) Get the device revision identifier
- (+) Enable/Disable Debug module during Sleep mode
+ (+) Enable/Disable Debug module during SLEEP mode
(+) Enable/Disable Debug module during STOP mode
(+) Enable/Disable Debug module during STANDBY mode
-
@endverbatim
* @{
*/
/**
- * @brief This function is called from SysTick ISR each 1 millisecond, to increment
- * a global variable "uwTick" used as time base.
- * @param None
+ * @brief This function is called to increment a global variable "uwTick"
+ * used as application time base.
+ * @note In the default implementation, this variable is incremented each 1ms
+ * in Systick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
* @retval None
*/
-void HAL_IncTick(void)
+__weak void HAL_IncTick(void)
{
uwTick++;
}
/**
- * @brief Povides a tick value in millisecond.
- * @param Non
+ * @brief Provides a tick value in millisecond.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
* @retval tick value
*/
-uint32_t HAL_GetTick(void)
+__weak uint32_t HAL_GetTick(void)
{
- return uwTick;
+ return uwTick;
}
/**
- * @brief Provides a blocking delay in millisecond.
- * @note Care must be taken when using HAL_Delay(), this function provides accurate delay
- * (in milliseconds) based on variable incremented in SysTick ISR. This implies that
- * if HAL_Delay() is called from a peripheral ISR process, then the SysTick interrupt
- * must have higher priority (numerically lower) than the peripheral interrupt.
- * Otherwise the caller ISR process will be blocked. To change the SysTick interrupt
- * priority you have to use HAL_NVIC_SetPriority() function.
- * @param Delay : specifies the delay time length, in milliseconds.
+ * @brief This function provides accurate delay (in milliseconds) based
+ * on variable incremented.
+ * @note In the default implementation , SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals where uwTick
+ * is incremented.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @param Delay: specifies the delay time length, in milliseconds.
* @retval None
*/
-void HAL_Delay(__IO uint32_t Delay)
+__weak void HAL_Delay(__IO uint32_t Delay)
{
- uint32_t timingdelay;
-
- timingdelay = HAL_GetTick() + Delay;
- while(HAL_GetTick() < timingdelay)
+ uint32_t tickstart = 0;
+ tickstart = HAL_GetTick();
+ while((HAL_GetTick() - tickstart) < Delay)
{
}
}
+/**
+ * @brief Suspend Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+ * is called, the SysTick interrupt will be disabled and so Tick increment
+ * is suspended.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_SuspendTick(void)
+{
+ /* Disable SysTick Interrupt */
+ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+ * is called, the SysTick interrupt will be enabled and so Tick increment
+ * is resumed.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_ResumeTick(void)
+{
+ /* Enable SysTick Interrupt */
+ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+}
+
/**
* @brief Returns the HAL revision
- * @param None
* @retval version : 0xXYZR (8bits for each decimal, R for RC)
*/
uint32_t HAL_GetHalVersion(void)
@@ -301,7 +387,6 @@ uint32_t HAL_GetHalVersion(void)
/**
* @brief Returns the device revision identifier.
- * @param None
* @retval Device revision identifier
*/
uint32_t HAL_GetREVID(void)
@@ -311,7 +396,6 @@ uint32_t HAL_GetREVID(void)
/**
* @brief Returns the device identifier.
- * @param None
* @retval Device identifier
*/
uint32_t HAL_GetDEVID(void)
@@ -320,61 +404,55 @@ uint32_t HAL_GetDEVID(void)
}
/**
- * @brief Enable the Debug Module during SLEEP mode
- * @param None
+ * @brief Enable the Debug Module during SLEEP mode
* @retval None
*/
-void HAL_EnableDBGSleepMode(void)
+void HAL_DBGMCU_EnableDBGSleepMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
- * @brief Disable the Debug Module during SLEEP mode
- * @param None
+ * @brief Disable the Debug Module during SLEEP mode
* @retval None
*/
-void HAL_DisableDBGSleepMode(void)
+void HAL_DBGMCU_DisableDBGSleepMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
- * @brief Enable the Debug Module during STOP mode
- * @param None
+ * @brief Enable the Debug Module during STOP mode
* @retval None
*/
-void HAL_EnableDBGStopMode(void)
+void HAL_DBGMCU_EnableDBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
- * @brief Disable the Debug Module during STOP mode
- * @param None
+ * @brief Disable the Debug Module during STOP mode
* @retval None
*/
-void HAL_DisableDBGStopMode(void)
+void HAL_DBGMCU_DisableDBGStopMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
- * @brief Enable the Debug Module during STANDBY mode
- * @param None
+ * @brief Enable the Debug Module during STANDBY mode
* @retval None
*/
-void HAL_EnableDBGStandbyMode(void)
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
- * @brief Disable the Debug Module during STANDBY mode
- * @param None
+ * @brief Disable the Debug Module during STANDBY mode
* @retval None
*/
-void HAL_DisableDBGStandbyMode(void)
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
diff --git a/f2/src/stm32f2xx_hal_adc.c b/f2/src/stm32f2xx_hal_adc.c
index 1a3466afac5b47e4668a4028f52ef25ee787f3b2..fd076807fd34d2f6bdf85f6f9456b3991fc94310 100755
--- a/f2/src/stm32f2xx_hal_adc.c
+++ b/f2/src/stm32f2xx_hal_adc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_adc.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* + Initialization and de-initialization functions
@@ -36,35 +36,56 @@
##### How to use this driver #####
==============================================================================
- [..]
- (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
- (##) Enable the ADC interface clock using __ADC_CLK_ENABLE()
+ [..]
+ (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
+ (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
(##) ADC pins configuration
(+++) Enable the clock for the ADC GPIOs using the following function:
- __GPIOx_CLK_ENABLE()
+ __HAL_RCC_GPIOx_CLK_ENABLE()
(+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
(##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
(+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
(+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
- (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
- (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+ (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
(+++) Configure and enable two DMA streams stream for managing data
transfer from peripheral to memory (output stream)
- (+++) Associate the initilalized DMA handle to the CRYP DMA handle
+ (+++) Associate the initialized DMA handle to the CRYP DMA handle
using __HAL_LINKDMA()
(+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the two DMA Streams. The output stream should have higher
priority than the input stream.
- (#) Configure the ADC Prescaler, conversion resolution and data alignment
- using the HAL_ADC_Init() function.
-
- (#) Configure the ADC regular channels group features, use HAL_ADC_Init()
- and HAL_ADC_ConfigChannel() functions.
-
- (#) Three mode of operations are available within this driver :
-
+ *** Configuration of ADC, groups regular/injected, channels parameters ***
+ ==============================================================================
+ [..]
+ (#) Configure the ADC parameters (resolution, data alignment, ...)
+ and regular group parameters (conversion trigger, sequencer, ...)
+ using function HAL_ADC_Init().
+
+ (#) Configure the channels for regular group parameters (channel number,
+ channel rank into sequencer, ..., into regular group)
+ using function HAL_ADC_ConfigChannel().
+
+ (#) Optionally, configure the injected group parameters (conversion trigger,
+ sequencer, ..., of injected group)
+ and the channels for injected group parameters (channel number,
+ channel rank into sequencer, ..., into injected group)
+ using function HAL_ADCEx_InjectedConfigChannel().
+
+ (#) Optionally, configure the analog watchdog parameters (channels
+ monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
+
+ (#) Optionally, for devices with several ADC instances: configure the
+ multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
+
+ *** Execution of ADC conversions ***
+ ==============================================================================
+ [..]
+ (#) ADC driver can be used among three modes: polling, interruption,
+ transfer by DMA.
+
*** Polling mode IO operation ***
=================================
[..]
@@ -80,20 +101,20 @@
(+) Start the ADC peripheral using HAL_ADC_Start_IT()
(+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
(+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
- add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
+ add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
(+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_ADC_ErrorCallback
- (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
+ add his own code by customization of function pointer HAL_ADC_ErrorCallback
+ (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
*** DMA mode IO operation ***
==============================
[..]
(+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
- of data to be transfered at each end of conversion
+ of data to be transferred at each end of conversion
(+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
- add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
+ add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
(+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_ADC_ErrorCallback
+ add his own code by customization of function pointer HAL_ADC_ErrorCallback
(+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
*** ADC HAL driver macros list ***
@@ -108,16 +129,42 @@
(+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
(+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
(+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
- (+) __HAL_ADC_GET_RESOLUTION: Return resolution bits in CR1 register
+ (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register
[..]
- (@) You can refer to the ADC HAL driver header file for more useful macros
-
+ (@) You can refer to the ADC HAL driver header file for more useful macros
+
+ *** Deinitialization of ADC ***
+ ==============================================================================
+ [..]
+ (#) Disable the ADC interface
+ (++) ADC clock can be hard reset and disabled at RCC top level.
+ (++) Hard reset of ADC peripherals
+ using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
+ (++) ADC clock disable using the equivalent macro/functions as configuration step.
+ (+++) Example:
+ Into HAL_ADC_MspDeInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
+ (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
+ (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+ (#) ADC pins configuration
+ (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Deinitialize the DMA using function HAL_DMA_DeInit().
+ (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -151,7 +198,7 @@
* @{
*/
-/** @defgroup ADC
+/** @defgroup ADC ADC
* @brief ADC driver modules
* @{
*/
@@ -159,21 +206,26 @@
#ifdef HAL_ADC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/** @addtogroup ADC_Private_Functions
+ * @{
+ */
/* Private function prototypes -----------------------------------------------*/
static void ADC_Init(ADC_HandleTypeDef* hadc);
static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
static void ADC_DMAError(DMA_HandleTypeDef *hdma);
-static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Functions
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
* @{
- */
+ */
-/** @defgroup ADC_Group1 Initialization and de-initialization functions
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -205,10 +257,12 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
/* Check ADC handle */
if(hadc == NULL)
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Check the parameters */
@@ -217,7 +271,6 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
- assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
@@ -225,29 +278,53 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+ if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ {
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ }
+
if(hadc->State == HAL_ADC_STATE_RESET)
{
+ /* Initialize ADC error code */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Allocate lock resource and initialize it */
+ hadc->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
}
- /* Initialize the ADC state */
- hadc->State = HAL_ADC_STATE_BUSY;
-
- /* Set ADC parameters */
- ADC_Init(hadc);
-
- /* Set ADC error code to none */
- hadc->ErrorCode = HAL_ADC_ERROR_NONE;
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Set ADC parameters */
+ ADC_Init(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set the ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
- /* Initialize the ADC state */
- hadc->State = HAL_ADC_STATE_READY;
-
/* Release Lock */
__HAL_UNLOCK(hadc);
/* Return function status */
- return HAL_OK;
+ return tmp_hal_status;
}
/**
@@ -258,29 +335,43 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
*/
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
/* Check ADC handle */
if(hadc == NULL)
{
- return HAL_ERROR;
- }
+ return HAL_ERROR;
+ }
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY;
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
- /* DeInit the low level hardware */
- HAL_ADC_MspDeInit(hadc);
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
- /* Set ADC error code to none */
- hadc->ErrorCode = HAL_ADC_ERROR_NONE;
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed. */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* DeInit the low level hardware */
+ HAL_ADC_MspDeInit(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set ADC state */
+ hadc->State = HAL_ADC_STATE_RESET;
+ }
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_RESET;
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
/* Return function status */
- return HAL_OK;
+ return tmp_hal_status;
}
/**
@@ -313,7 +404,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
* @}
*/
-/** @defgroup ADC_Group2 IO operation functions
+/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
@@ -341,7 +432,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
{
- uint16_t i = 0;
+ __IO uint32_t counter = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -350,55 +441,82 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
/* Process locked */
__HAL_LOCK(hadc);
- /* Check if an injected conversion is ongoing */
- if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
- }
- else
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_REG;
- }
-
+ /* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
- Tstab time the ADC's stabilization */
+ Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay inserted to wait during Tstab time the ADC's stabilazation */
- for(; i <= 540; i++)
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
{
- __NOP();
+ counter--;
}
}
-
- /* Check if Multimode enabled */
- if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+
+ /* Start conversion if ADC is effectively enabled */
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
- /* if no external trigger present enable software conversion of regular channels */
- if(hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular group operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
{
- /* Enable the selected ADC software conversion for regular group */
- hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
}
- }
- else
- {
- /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
- if((hadc->Instance == ADC1) && (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
{
- /* Enable the selected ADC software conversion for regular group */
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+
+ /* Check if Multimode enabled */
+ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+ {
+ /* if no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+ {
+ /* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+ }
+ else
+ {
+ /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
}
}
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
/* Return function status */
return HAL_OK;
}
@@ -410,16 +528,32 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
*
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
- * last transfer and End of conversion selection).
+ *
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
{
- /* Disable the Peripheral */
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
__HAL_ADC_DISABLE(hadc);
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
+ /* Check if ADC is effectively disabled */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
@@ -427,6 +561,14 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
/**
* @brief Poll for regular conversion complete
+ * @note ADC conversion flags EOS (end of sequence) and EOC (end of
+ * conversion) are cleared by this function.
+ * @note This function cannot be used in a particular setup: ADC configured
+ * in DMA mode and polling for end of each conversion (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+ * In this case, DMA resets the flag EOC and polling cannot be
+ * performed on each conversion. Nevertheless, polling can still
+ * be performed on the complete sequence.
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param Timeout: Timeout value in millisecond.
@@ -434,37 +576,72 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
*/
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
{
- uint32_t timeout;
+ uint32_t tickstart = 0;
- /* Get timeout */
- timeout = HAL_GetTick() + Timeout;
+ /* Verification that ADC configuration is compliant with polling for */
+ /* each conversion: */
+ /* Particular case is ADC configured in DMA mode and ADC sequencer with */
+ /* several ranks and polling for end of each conversion. */
+ /* For code simplicity sake, this particular case is generalized to */
+ /* ADC configured in DMA mode and polling for end of each conversion. */
+ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
+ HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Check End of conversion flag */
while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
{
- /* Check for the Timeout */
+ /* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
{
- hadc->State= HAL_ADC_STATE_TIMEOUT;
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
/* Process unlocked */
__HAL_UNLOCK(hadc);
+
return HAL_TIMEOUT;
}
}
}
- /* Check if an injected conversion is ready */
- if(hadc->State == HAL_ADC_STATE_EOC_INJ)
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F2, there is no independent flag of end of sequence. */
+ /* The test of scan sequence on going is done either with scan */
+ /* sequence disabled or with end of conversion flag set to */
+ /* of end of sequence. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
- }
- else
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_REG;
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
}
/* Return ADC state */
@@ -477,20 +654,21 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
* the configuration information for the specified ADC.
* @param EventType: the ADC event type.
* This parameter can be one of the following values:
- * @arg AWD_EVENT: ADC Analog watch Dog event.
- * @arg OVR_EVENT: ADC Overrun event.
+ * @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
+ * @arg ADC_OVR_EVENT: ADC Overrun event.
* @param Timeout: Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
{
+ uint32_t tickstart = 0;
+
/* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_EVENT_TYPE(EventType));
-
- uint32_t timeout;
- /* Get timeout */
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Check selected event flag */
while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
@@ -498,32 +676,38 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
{
- hadc->State= HAL_ADC_STATE_TIMEOUT;
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
/* Process unlocked */
__HAL_UNLOCK(hadc);
+
return HAL_TIMEOUT;
}
}
}
- /* Check analog watchdog flag */
- if(EventType == AWD_EVENT)
+ /* Analog watchdog (level out of window) event */
+ if(EventType == ADC_AWD_EVENT)
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_AWD;
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
- /* Clear the ADCx's analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
}
+ /* Overrun event */
else
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_ERROR;
-
- /* Clear the ADCx's Overrun flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+ /* Set ADC error code to overrun */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+
+ /* Clear ADC overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
}
/* Return ADC state */
@@ -539,73 +723,94 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
*/
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
{
- uint16_t i = 0;
+ __IO uint32_t counter = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
- assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
/* Process locked */
__HAL_LOCK(hadc);
- /* Check if an injected conversion is ongoing */
- if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
- }
- else
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_REG;
- }
-
- /* Set ADC error code to none */
- hadc->ErrorCode = HAL_ADC_ERROR_NONE;
-
+ /* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
- Tstab time the ADC's stabilization */
+ Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay inserted to wait during Tstab time the ADC's stabilazation */
- for(; i <= 540; i++)
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
{
- __NOP();
+ counter--;
}
}
- /* Enable the ADC overrun interrupt */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-
- /* Enable the ADC end of conversion interrupt for regular group */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
-
- /* Check if Multimode enabled */
- if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+ /* Start conversion if ADC is effectively enabled */
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
- /* if no externel trigger present enable software conversion of regular channels */
- if (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular group operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
{
- /* Enable the selected ADC software conversion for regular group */
- hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
}
- }
- else
- {
- /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
- if ((hadc->Instance == (ADC_TypeDef*)0x40012000) && (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+
+ /* Enable end of conversion interrupt for regular group */
+ __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
+
+ /* Check if Multimode enabled */
+ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
{
- /* Enable the selected ADC software conversion for regular group */
+ /* if no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+ {
+ /* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+ }
+ else
+ {
+ /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
}
}
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
/* Return function status */
return HAL_OK;
}
@@ -621,17 +826,30 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
*/
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
{
- /* Disable the ADC end of conversion interrupt for regular group */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- /* Disable the ADC end of conversion interrupt for injected group */
- __HAL_ADC_DISABLE_IT(hadc, ADC_CR1_JEOCIE);
+ /* Process locked */
+ __HAL_LOCK(hadc);
- /* Enable the Periphral */
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
__HAL_ADC_DISABLE(hadc);
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
+ /* Check if ADC is effectively disabled */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Disable ADC end of conversion interrupt for regular group */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
@@ -657,55 +875,44 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
/* Check End of conversion flag for regular channels */
if(tmp1 && tmp2)
{
- /* Check if an injected conversion is ready */
- if(hadc->State == HAL_ADC_STATE_EOC_INJ)
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
- }
- else
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_REG;
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
}
-
- if((hadc->Init.ContinuousConvMode == DISABLE) && (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F2, there is no independent flag of end of sequence. */
+ /* The test of scan sequence on going is done either with scan */
+ /* sequence disabled or with end of conversion flag set to */
+ /* of end of sequence. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
{
- if(hadc->Init.EOCSelection == EOC_SEQ_CONV)
- {
- /* DISABLE the ADC end of conversion interrupt for regular group */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-
- /* DISABLE the ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
- }
- else
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
{
- if (hadc->NbrOfCurrentConversionRank == 0)
- {
- hadc->NbrOfCurrentConversionRank = hadc->Init.NbrOfConversion;
- }
-
- /* Decrement the number of conversion when an interrupt occurs */
- hadc->NbrOfCurrentConversionRank--;
-
- /* Check if all conversions are finished */
- if(hadc->NbrOfCurrentConversionRank == 0)
- {
- /* DISABLE the ADC end of conversion interrupt for regular group */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-
- /* DISABLE the ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
- }
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
}
}
/* Conversion complete callback */
HAL_ADC_ConvCpltCallback(hadc);
- /* Clear the ADCx flag for regular end of conversion */
- __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_EOC);
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
}
tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);
@@ -713,31 +920,41 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
/* Check End of conversion flag for injected channels */
if(tmp1 && tmp2)
{
- /* Check if a regular conversion is ready */
- if(hadc->State == HAL_ADC_STATE_EOC_REG)
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
}
- else
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_INJ;
- }
-
- tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
- tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
- if(((hadc->Init.ContinuousConvMode == DISABLE) || tmp1) && tmp2)
+
+ /* Determine whether any further conversion upcoming on group injected */
+ /* by external trigger, scan sequence on going or by automatic injected */
+ /* conversion from group regular (same conditions as group regular */
+ /* interruption disabling above). */
+ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+ (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
{
- /* DISABLE the ADC end of conversion interrupt for injected group */
+ /* Disable ADC end of single conversion interrupt on group injected */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
}
-
+
/* Conversion complete callback */
HAL_ADCEx_InjectedConvCpltCallback(hadc);
- /* Clear the ADCx flag for injected end of conversion */
- __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_JEOC);
+ /* Clear injected group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
}
tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);
@@ -745,14 +962,17 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
/* Check Analog watchdog flag */
if(tmp1 && tmp2)
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_AWD;
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
- /* Clear the ADCx's Analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD);
-
- /* Level out of window callback */
- HAL_ADC_LevelOutOfWindowCallback(hadc);
+ /* Level out of window callback */
+ HAL_ADC_LevelOutOfWindowCallback(hadc);
+
+ /* Clear the ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+ }
}
tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);
@@ -760,17 +980,21 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
/* Check Overrun flag */
if(tmp1 && tmp2)
{
- /* Change ADC state to overrun state */
- hadc->State = HAL_ADC_STATE_ERROR;
+ /* Note: On STM32F2, ADC overrun can be set through other parameters */
+ /* refer to description of parameter "EOCSelection" for more */
+ /* details. */
/* Set ADC error code to overrun */
- hadc->ErrorCode |= HAL_ADC_ERROR_OVR;
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
- /* Clear the Overrun flag */
- __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_OVR);
+ /* Clear ADC overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
/* Error callback */
HAL_ADC_ErrorCallback(hadc);
+
+ /* Clear the Overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
}
}
@@ -780,64 +1004,117 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
* the configuration information for the specified ADC.
* @param pData: The destination Buffer address.
* @param Length: The length of data to be transferred from ADC peripheral to memory.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
- uint16_t i = 0;
+ __IO uint32_t counter = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
- assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
/* Process locked */
__HAL_LOCK(hadc);
- /* Enable ADC overrun interrupt */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-
- /* Enable ADC DMA mode */
- hadc->Instance->CR2 |= ADC_CR2_DMA;
-
- /* Set the DMA transfer complete callback */
- hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
-
- /* Set the DMA half transfer complete callback */
- hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
-
- /* Set the DMA error callback */
- hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
-
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_REG;
-
+ /* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
- Tstab time the ADC's stabilization */
+ Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay inserted to wait during Tstab time the ADC's stabilazation */
- for(; i <= 540; i++)
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
{
- __NOP();
+ counter--;
}
}
- /* if no external trigger present enable software conversion of regular channels */
- if (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
+ /* Start conversion if ADC is effectively enabled */
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
- /* Enable the selected ADC software conversion for regular group */
- hadc->Instance->CR2 |= ADC_CR2_SWSTART;
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular group operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+
+ /* Enable ADC overrun interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Enable ADC DMA mode */
+ hadc->Instance->CR2 |= ADC_CR2_DMA;
+
+ /* Start the DMA channel */
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+
+ /* Check if Multimode enabled */
+ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+ {
+ /* if no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+ }
+ else
+ {
+ /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+ }
}
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
/* Return function status */
return HAL_OK;
}
@@ -846,27 +1123,46 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
* @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
{
- /* Disable the Periphral */
- __HAL_ADC_DISABLE(hadc);
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- /* Disable the selected ADC DMA mode */
- hadc->Instance->CR2 &= ~ADC_CR2_DMA;
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
- /* Disable the ADC DMA Stream */
- HAL_DMA_Abort(hadc->DMA_Handle);
+ /* Check if ADC is effectively disabled */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Disable the selected ADC DMA mode */
+ hadc->Instance->CR2 &= ~ADC_CR2_DMA;
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* DMA transfer is on going) */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
/* Return function status */
- return HAL_OK;
+ return tmp_hal_status;
}
/**
@@ -937,7 +1233,7 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
* @}
*/
-/** @defgroup ADC_Group3 Peripheral Control functions
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
@@ -964,6 +1260,8 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
+ __IO uint32_t counter = 0;
+
/* Check the parameters */
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
@@ -976,46 +1274,46 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
if (sConfig->Channel > ADC_CHANNEL_9)
{
/* Clear the old sample time */
- hadc->Instance->SMPR1 &= ~__HAL_ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
+ hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
/* Set the new sample time */
- hadc->Instance->SMPR1 |= __HAL_ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
+ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
}
else /* ADC_Channel include in ADC_Channel_[0..9] */
{
/* Clear the old sample time */
- hadc->Instance->SMPR2 &= ~__HAL_ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
+ hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
/* Set the new sample time */
- hadc->Instance->SMPR2 |= __HAL_ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
+ hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
}
/* For Rank 1 to 6 */
if (sConfig->Rank < 7)
{
/* Clear the old SQx bits for the selected rank */
- hadc->Instance->SQR3 &= ~__HAL_ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
+ hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
/* Set the SQx bits for the selected rank */
- hadc->Instance->SQR3 |= __HAL_ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
+ hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
}
/* For Rank 7 to 12 */
else if (sConfig->Rank < 13)
{
/* Clear the old SQx bits for the selected rank */
- hadc->Instance->SQR2 &= ~__HAL_ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
+ hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
/* Set the SQx bits for the selected rank */
- hadc->Instance->SQR2 |= __HAL_ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
+ hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
}
/* For Rank 13 to 16 */
else
{
/* Clear the old SQx bits for the selected rank */
- hadc->Instance->SQR1 &= ~__HAL_ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
+ hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
/* Set the SQx bits for the selected rank */
- hadc->Instance->SQR1 |= __HAL_ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
+ hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
}
/* if ADC1 Channel_18 is selected enable VBAT Channel */
@@ -1030,6 +1328,17 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
{
/* Enable the TSVREFE channel*/
ADC->CCR |= ADC_CCR_TSVREFE;
+
+ if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
+ {
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
+ {
+ counter--;
+ }
+ }
}
/* Process unlocked */
@@ -1059,7 +1368,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
#ifdef USE_FULL_ASSERT
- tmp = __HAL_ADC_GET_RESOLUTION(hadc);
+ tmp = ADC_GET_RESOLUTION(hadc);
assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
#endif /* USE_FULL_ASSERT */
@@ -1094,7 +1403,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
/* Set the Analog watchdog channel */
- hadc->Instance->CR1 |= AnalogWDGConfig->Channel;
+ hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));
/* Process unlocked */
__HAL_UNLOCK(hadc);
@@ -1107,7 +1416,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
* @}
*/
-/** @defgroup ADC_Group4 ADC Peripheral State functions
+/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions
* @brief ADC Peripheral State functions
*
@verbatim
@@ -1129,7 +1438,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
* the configuration information for the specified ADC.
* @retval HAL state
*/
-HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
{
/* Return ADC state */
return hadc->State;
@@ -1150,6 +1459,10 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
* @}
*/
+/** @addtogroup ADC_Private_Functions
+ * @{
+ */
+
/**
* @brief Initializes the ADCx peripheral according to the specified parameters
* in the ADC_InitStruct without initializing the ADC MSP.
@@ -1159,7 +1472,6 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
*/
static void ADC_Init(ADC_HandleTypeDef* hadc)
{
-
/* Set ADC parameters */
/* Set the ADC clock prescaler */
ADC->CCR &= ~(ADC_CCR_ADCPRE);
@@ -1167,7 +1479,7 @@ static void ADC_Init(ADC_HandleTypeDef* hadc)
/* Set ADC scan mode */
hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
- hadc->Instance->CR1 |= __HAL_ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
+ hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
/* Set ADC resolution */
hadc->Instance->CR1 &= ~(ADC_CR1_RES);
@@ -1177,19 +1489,33 @@ static void ADC_Init(ADC_HandleTypeDef* hadc)
hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
hadc->Instance->CR2 |= hadc->Init.DataAlign;
- /* Select external trigger to start conversion */
- hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
- hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
-
- /* Select external trigger polarity */
- hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
- hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ {
+ /* Select external trigger to start conversion */
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
+ hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
+
+ /* Select external trigger polarity */
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
+ hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
+ }
+ else
+ {
+ /* Reset the external trigger */
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
+ }
/* Enable or disable ADC continuous conversion mode */
hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
- hadc->Instance->CR2 |= __HAL_ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);
+ hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);
- if (hadc->Init.DiscontinuousConvMode != DISABLE)
+ if(hadc->Init.DiscontinuousConvMode != DISABLE)
{
assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
@@ -1198,7 +1524,7 @@ static void ADC_Init(ADC_HandleTypeDef* hadc)
/* Set the number of channels to be converted in discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
- hadc->Instance->CR1 |= __HAL_ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
+ hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
}
else
{
@@ -1208,67 +1534,101 @@ static void ADC_Init(ADC_HandleTypeDef* hadc)
/* Set ADC number of conversion */
hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
- hadc->Instance->SQR1 |= __HAL_ADC_SQR1(hadc->Init.NbrOfConversion);
+ hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
/* Enable or disable ADC DMA continuous request */
hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
- hadc->Instance->CR2 |= __HAL_ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);
+ hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);
/* Enable or disable ADC end of conversion selection */
hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
- hadc->Instance->CR2 |= __HAL_ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
+ hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
}
/**
* @brief DMA transfer complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
{
+ /* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Check if an injected conversion is ready */
- if(hadc->State == HAL_ADC_STATE_EOC_INJ)
+
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F2, there is no independent flag of end of sequence. */
+ /* The test of scan sequence on going is done either with scan */
+ /* sequence disabled or with end of conversion flag set to */
+ /* of end of sequence. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
+ {
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Conversion complete callback */
+ HAL_ADC_ConvCpltCallback(hadc);
}
else
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_REG;
+ /* Call DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback(hdma);
}
-
- HAL_ADC_ConvCpltCallback(hadc);
}
/**
* @brief DMA half transfer complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
{
- ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* Conversion complete callback */
- HAL_ADC_ConvHalfCpltCallback(hadc);
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Conversion complete callback */
+ HAL_ADC_ConvHalfCpltCallback(hadc);
}
/**
* @brief DMA error callback
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_DMAError(DMA_HandleTypeDef *hdma)
{
- ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hadc->State= HAL_ADC_STATE_ERROR;
- /* Set ADC error code to DMA error */
- hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
- HAL_ADC_ErrorCallback(hadc);
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hadc->State= HAL_ADC_STATE_ERROR_DMA;
+ /* Set ADC error code to DMA error */
+ hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
+ HAL_ADC_ErrorCallback(hadc);
}
+/**
+ * @}
+ */
/**
* @}
diff --git a/f2/src/stm32f2xx_hal_adc_ex.c b/f2/src/stm32f2xx_hal_adc_ex.c
index c271d2af322e8d878a9f06b45945ad8bfbe1cf85..de7a4fd72bddd60b09f50a03227e10dfaf7ce153 100755
--- a/f2/src/stm32f2xx_hal_adc_ex.c
+++ b/f2/src/stm32f2xx_hal_adc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_adc_ex.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief This file provides firmware functions to manage the following
* functionalities of the ADC extension peripheral:
* + Extended features functions
@@ -14,32 +14,31 @@
==============================================================================
[..]
(#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
- (##) Enable the ADC interface clock using __ADC_CLK_ENABLE()
+ (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
(##) ADC pins configuration
(+++) Enable the clock for the ADC GPIOs using the following function:
- __GPIOx_CLK_ENABLE()
+ __HAL_RCC_GPIOx_CLK_ENABLE()
(+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
(##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
(+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
(+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
(##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
- (++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
- (++) Configure and enable two DMA streams stream for managing data
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
+ (+++) Configure and enable two DMA streams stream for managing data
transfer from peripheral to memory (output stream)
- (++) Associate the initilalized DMA handle to the CRYP DMA handle
+ (+++) Associate the initialized DMA handle to the ADC DMA handle
using __HAL_LINKDMA()
- (++) Configure the priority and enable the NVIC for the transfer complete
+ (+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the two DMA Streams. The output stream should have higher
priority than the input stream.
-
(#) Configure the ADC Prescaler, conversion resolution and data alignment
using the HAL_ADC_Init() function.
(#) Configure the ADC Injected channels group features, use HAL_ADC_Init()
and HAL_ADC_ConfigChannel() functions.
- (#) Three mode of operations are available within this driver :
+ (#) Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -66,7 +65,7 @@
==============================
[..]
(+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length
- of data to be transfered at each end of conversion
+ of data to be transferred at each end of conversion
(+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
(+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
@@ -79,7 +78,7 @@
(+) Select the Multi mode ADC regular channels features (dual or triple mode)
and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions.
(+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length
- of data to be transfered at each end of conversion
+ of data to be transferred at each end of conversion
(+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.
@@ -87,7 +86,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -121,7 +120,7 @@
* @{
*/
-/** @defgroup ADCEx
+/** @defgroup ADCEx ADCEx
* @brief ADC Extended driver modules
* @{
*/
@@ -132,19 +131,25 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/** @addtogroup ADCEx_Private_Functions
+ * @{
+ */
/* Private function prototypes -----------------------------------------------*/
static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);
static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);
static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
-/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
-/** @defgroup ADCEx_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Functions ADC Exported Functions
* @{
- */
+ */
-/** @defgroup ADCEx_Group1 Extended features functions
- * @brief Extended features functions
- *
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ *
@verbatim
===============================================================================
##### Extended features functions #####
@@ -171,22 +176,13 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
{
- uint32_t i = 0, tmp1 = 0, tmp2 = 0;
+ __IO uint32_t counter = 0;
+ uint32_t tmp1 = 0, tmp2 = 0;
/* Process locked */
__HAL_LOCK(hadc);
- /* Check if a regular conversion is ongoing */
- if(hadc->State == HAL_ADC_STATE_BUSY_REG)
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
- }
- else
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_INJ;
- }
+ /* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
@@ -195,38 +191,67 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay inserted to wait during Tstab time the ADC's stabilazation */
- for(; i <= 540; i++)
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
{
- __NOP();
+ counter--;
}
}
- /* Check if Multimode enabled */
- if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+ /* Start conversion if ADC is effectively enabled */
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
- tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
- tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
- if(tmp1 && tmp2)
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+ /* Check if a regular conversion is ongoing */
+ /* Note: On this device, there is no ADC error code fields related to */
+ /* conversions on group injected only. In case of conversion on */
+ /* going on group regular, no error code is reset. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
{
- /* Enable the selected ADC software conversion for injected group */
- hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
}
- }
- else
- {
- tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
- tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
- if((hadc->Instance == ADC1) && tmp1 && tmp2)
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+
+ /* Check if Multimode enabled */
+ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
{
- /* Enable the selected ADC software conversion for injected group */
- hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ if(tmp1 && tmp2)
+ {
+ /* Enable the selected ADC software conversion for injected group */
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ }
+ }
+ else
+ {
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ if((hadc->Instance == ADC1) && tmp1 && tmp2)
+ {
+ /* Enable the selected ADC software conversion for injected group */
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ }
}
}
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
/* Return function status */
return HAL_OK;
}
@@ -240,25 +265,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
{
- uint32_t i = 0, tmp1 = 0, tmp2 =0;
+ __IO uint32_t counter = 0;
+ uint32_t tmp1 = 0, tmp2 = 0;
/* Process locked */
__HAL_LOCK(hadc);
- /* Check if a regular conversion is ongoing */
- if(hadc->State == HAL_ADC_STATE_BUSY_REG)
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
- }
- else
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_INJ;
- }
-
- /* Set ADC error code to none */
- hadc->ErrorCode = HAL_ADC_ERROR_NONE;
+ /* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
@@ -267,67 +280,131 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay inserted to wait during Tstab time the ADC's stabilazation */
- for(; i <= 540; i++)
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
{
- __NOP();
+ counter--;
}
}
- /* Enable the ADC end of conversion interrupt for injected group */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
-
- /* Enable the ADC overrun interrupt */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-
- /* Check if Multimode enabled */
- if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+ /* Start conversion if ADC is effectively enabled */
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
- tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
- tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
- if(tmp1 && tmp2)
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+ /* Check if a regular conversion is ongoing */
+ /* Note: On this device, there is no ADC error code fields related to */
+ /* conversions on group injected only. In case of conversion on */
+ /* going on group regular, no error code is reset. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
{
- /* Enable the selected ADC software conversion for injected group */
- hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
}
- }
- else
- {
- tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
- tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
- if((hadc->Instance == ADC1) && tmp1 && tmp2)
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+
+ /* Enable end of conversion interrupt for injected channels */
+ __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_OVR));
+
+ /* Check if Multimode enabled */
+ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+ {
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ if(tmp1 && tmp2)
+ {
+ /* Enable the selected ADC software conversion for injected group */
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ }
+ }
+ else
{
- /* Enable the selected ADC software conversion for injected group */
- hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ if((hadc->Instance == ADC1) && tmp1 && tmp2)
+ {
+ /* Enable the selected ADC software conversion for injected group */
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ }
}
}
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
/* Return function status */
return HAL_OK;
}
/**
- * @brief Disables ADC and stop conversion of injected channels.
- *
- * @note Caution: This function will stop also regular channels.
- *
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
- * @retval HAL status.
+ * @brief Stop conversion of injected channels. Disable ADC peripheral if
+ * no regular conversion is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @note If injected group mode auto-injection is enabled,
+ * function HAL_ADC_Stop must be used.
+ * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
+ * @param hadc: ADC handle
+ * @retval None
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
{
- /* Disable the Peripheral */
- __HAL_ADC_DISABLE(hadc);
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion and disable ADC peripheral */
+ /* Conditioned to: */
+ /* - No conversion on the other group (regular group) is intended to */
+ /* continue (injected and regular groups stop conversion and ADC disable */
+ /* are common) */
+ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
+ if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
+ {
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
/* Return function status */
- return HAL_OK;
+ return tmp_hal_status;
}
/**
@@ -339,10 +416,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
{
- uint32_t timeout;
-
- /* Get timeout */
- timeout = HAL_GetTick() + Timeout;
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Check End of conversion flag */
while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
@@ -350,7 +427,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
hadc->State= HAL_ADC_STATE_TIMEOUT;
/* Process unlocked */
@@ -360,16 +437,32 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
}
}
- /* Check if a regular conversion is ready */
- if(hadc->State == HAL_ADC_STATE_EOC_REG)
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
- }
- else
+ /* Clear injected group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+
+ /* Determine whether any further conversion upcoming on group injected */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F2, there is no independent flag of end of sequence. */
+ /* The test of scan sequence on going is done either with scan */
+ /* sequence disabled or with end of conversion flag set to */
+ /* of end of sequence. */
+ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+ (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_INJ;
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
}
/* Return ADC state */
@@ -377,30 +470,65 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
}
/**
- * @brief Disables the interrupt and stop ADC conversion of injected channels.
- *
- * @note Caution: This function will stop also regular channels.
- *
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
- * @retval HAL status.
+ * @brief Stop conversion of injected channels, disable interruption of
+ * end-of-conversion. Disable ADC peripheral if no regular conversion
+ * is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @note If injected group mode auto-injection is enabled,
+ * function HAL_ADC_Stop must be used.
+ * @param hadc: ADC handle
+ * @retval None
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
{
- /* Disable the ADC end of conversion interrupt for regular group */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-
- /* Disable the ADC end of conversion interrupt for injected group */
- __HAL_ADC_DISABLE_IT(hadc, ADC_CR1_JEOCIE);
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- /* Enable the Periphral */
- __HAL_ADC_DISABLE(hadc);
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion and disable ADC peripheral */
+ /* Conditioned to: */
+ /* - No conversion on the other group (regular group) is intended to */
+ /* continue (injected and regular groups stop conversion and ADC disable */
+ /* are common) */
+ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
+ if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
+ {
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Disable ADC end of conversion interrupt for injected channels */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_OVR));
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
/* Return function status */
- return HAL_OK;
+ return tmp_hal_status;
}
/**
@@ -409,10 +537,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
* the configuration information for the specified ADC.
* @param InjectedRank: the ADC injected rank.
* This parameter can be one of the following values:
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected
+ * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
+ * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
+ * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
+ * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
* @retval None
*/
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
@@ -422,8 +550,9 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa
/* Check the parameters */
assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
- /* Clear the ADCx's flag for injected end of conversion */
- __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_JEOC);
+ /* Clear injected group conversion flag to have similar behaviour as */
+ /* regular group: reading data register also clears end of conversion flag. */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
/* Return the selected ADC converted value */
switch(InjectedRank)
@@ -463,11 +592,11 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa
* the configuration information for the specified ADC.
* @param pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored.
* @param Length: The length of data to be transferred from ADC peripheral to memory.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
- uint16_t counter = 0;
+ __IO uint32_t counter = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -477,35 +606,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
/* Process locked */
__HAL_LOCK(hadc);
- /* Enable ADC overrun interrupt */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-
- if (hadc->Init.DMAContinuousRequests != DISABLE)
- {
- /* Enable the selected ADC DMA request after last transfer */
- ADC->CCR |= ADC_CCR_DDS;
- }
- else
- {
- /* Disable the selected ADC EOC rising on each regular channel conversion */
- ADC->CCR &= ~ADC_CCR_DDS;
- }
-
- /* Set the DMA transfer complete callback */
- hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
-
- /* Set the DMA half transfer complete callback */
- hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
-
- /* Set the DMA error callback */
- hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
-
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_REG;
-
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
@@ -513,23 +613,90 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay inserted to wait during Tstab time the ADC's stabilazation */
- for(; counter <= 540; counter++)
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
{
- __NOP();
+ counter--;
}
}
- /* if no external trigger present enable software conversion of regular channels */
- if (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
+ /* Start conversion if ADC is effectively enabled */
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
- /* Enable the selected ADC software conversion for regular group */
- hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular group operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+
+ /* Enable ADC overrun interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ if (hadc->Init.DMAContinuousRequests != DISABLE)
+ {
+ /* Enable the selected ADC DMA request after last transfer */
+ ADC->CCR |= ADC_CCR_DDS;
+ }
+ else
+ {
+ /* Disable the selected ADC EOC rising on each regular channel conversion */
+ ADC->CCR &= ~ADC_CCR_DDS;
+ }
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
+
+ /* if no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
}
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
/* Return function status */
return HAL_OK;
}
@@ -538,33 +705,46 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
* @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
/* Process locked */
__HAL_LOCK(hadc);
- /* Enable the Peripheral */
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
__HAL_ADC_DISABLE(hadc);
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-
- /* Disable the selected ADC DMA request after last transfer */
- ADC->CCR &= ~ADC_CCR_DDS;
-
- /* Disable the ADC DMA Stream */
- HAL_DMA_Abort(hadc->DMA_Handle);
-
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
+ /* Check if ADC is effectively disabled */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Disable the selected ADC DMA mode for multimode */
+ ADC->CCR &= ~ADC_CCR_DDS;
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* DMA transfer is on going) */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
/* Process unlocked */
__HAL_UNLOCK(hadc);
-
+
/* Return function status */
- return HAL_OK;
+ return tmp_hal_status;
}
/**
@@ -613,16 +793,20 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));
- assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
#ifdef USE_FULL_ASSERT
- tmp = __HAL_ADC_GET_RESOLUTION(hadc);
+ tmp = ADC_GET_RESOLUTION(hadc);
assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
#endif /* USE_FULL_ASSERT */
+ if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)
+ {
+ assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
+ }
+
/* Process locked */
__HAL_LOCK(hadc);
@@ -630,39 +814,53 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)
{
/* Clear the old sample time */
- hadc->Instance->SMPR1 &= ~__HAL_ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);
+ hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);
/* Set the new sample time */
- hadc->Instance->SMPR1 |= __HAL_ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
+ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
}
else /* ADC_Channel include in ADC_Channel_[0..9] */
{
/* Clear the old sample time */
- hadc->Instance->SMPR2 &= ~__HAL_ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);
+ hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);
/* Set the new sample time */
- hadc->Instance->SMPR2 |= __HAL_ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
+ hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
}
/*---------------------------- ADCx JSQR Configuration -----------------*/
hadc->Instance->JSQR &= ~(ADC_JSQR_JL);
- hadc->Instance->JSQR |= __HAL_ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
+ hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
/* Rank configuration */
/* Clear the old SQx bits for the selected rank */
- hadc->Instance->JSQR &= ~__HAL_ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
+ hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
/* Set the SQx bits for the selected rank */
- hadc->Instance->JSQR |= __HAL_ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
+ hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
- /* Select external trigger to start conversion */
- hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
- hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv;
-
- /* Select external trigger polarity */
- hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
- hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+ {
+ /* Select external trigger to start conversion */
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
+ hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv;
+
+ /* Select external trigger polarity */
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
+ hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
+ }
+ else
+ {
+ /* Reset the external trigger */
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
+ }
if (sConfigInjected->AutoInjectedConv != DISABLE)
{
@@ -774,31 +972,61 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
/**
* @brief DMA transfer complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)
{
- ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Check if an injected conversion is ready */
- if(hadc->State == HAL_ADC_STATE_EOC_INJ)
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F2, there is no independent flag of end of sequence. */
+ /* The test of scan sequence on going is done either with scan */
+ /* sequence disabled or with end of conversion flag set to */
+ /* of end of sequence. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
+ {
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Conversion complete callback */
+ HAL_ADC_ConvCpltCallback(hadc);
}
else
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_REG;
+ /* Call DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback(hdma);
}
-
- HAL_ADC_ConvCpltCallback(hadc);
}
/**
* @brief DMA half transfer complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)
@@ -810,13 +1038,14 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA error callback
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)
{
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hadc->State= HAL_ADC_STATE_ERROR;
+ hadc->State= HAL_ADC_STATE_ERROR_DMA;
/* Set ADC error code to DMA error */
hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
HAL_ADC_ErrorCallback(hadc);
diff --git a/f2/src/stm32f2xx_hal_can.c b/f2/src/stm32f2xx_hal_can.c
index 9fac2473b573a3dfb084e7c9c7c1e055b8d73790..a0dbcd6a35a6fd5d46b850e8890092c30acb0e6c 100755
--- a/f2/src/stm32f2xx_hal_can.c
+++ b/f2/src/stm32f2xx_hal_can.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_can.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
* + Initialization and de-initialization functions
@@ -17,7 +17,7 @@
==============================================================================
[..]
(#) Enable the CAN controller interface clock using
- __CAN1_CLK_ENABLE() for CAN1 and __CAN1_CLK_ENABLE() for CAN2
+ __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
-@- In case you are using CAN2 only, you have to enable the CAN1 clock.
(#) CAN pins configuration
@@ -26,11 +26,11 @@
(++) Connect and configure the involved CAN pins to AF9 using the
following function HAL_GPIO_Init()
- (#) Initialise and configure the CAN using CAN_Init() function.
+ (#) Initialize and configure the CAN using CAN_Init() function.
(#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
- (#) Receive a CAN frame using HAL_CAN_Recieve() function.
+ (#) Receive a CAN frame using HAL_CAN_Receive() function.
*** Polling mode IO operation ***
=================================
@@ -72,7 +72,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -106,7 +106,7 @@
* @{
*/
-/** @defgroup CAN
+/** @defgroup CAN CAN
* @brief CAN driver modules
* @{
*/
@@ -115,18 +115,31 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup CAN_Private_Constants
+ * @{
+ */
+#define CAN_TIMEOUT_VALUE 10
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup CAN_Private_Functions
+ * @{
+ */
static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
-/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
-/** @defgroup CAN_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CAN_Exported_Functions CAN Exported Functions
* @{
*/
-/** @defgroup CAN_Group1 Initialization and de-initialization functions
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -151,7 +164,7 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
{
uint32_t InitStatus = 3;
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Check CAN handle */
if(hcan == NULL)
@@ -176,6 +189,8 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
if(hcan->State == HAL_CAN_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hcan->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_CAN_MspInit(hcan);
}
@@ -189,13 +204,13 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
/* Request initialisation */
hcan->Instance->MCR |= CAN_MCR_INRQ ;
- /* Get timeout */
- timeout = HAL_GetTick() + 10;
-
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait the acknowledge */
while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
{
hcan->State= HAL_CAN_STATE_TIMEOUT;
/* Process unlocked */
@@ -281,13 +296,13 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
/* Request leave initialisation */
hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
- /* Get timeout */
- timeout = HAL_GetTick() + 10;
-
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait the acknowledge */
while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
{
hcan->State= HAL_CAN_STATE_TIMEOUT;
/* Process unlocked */
@@ -495,7 +510,7 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
* @}
*/
-/** @defgroup CAN_Group2 IO operation functions
+/** @defgroup CAN_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
@@ -522,9 +537,8 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
{
uint32_t transmitmailbox = 5;
-
- uint32_t timeout;
-
+ uint32_t tickstart = 0;
+
/* Check the parameters */
assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
@@ -597,8 +611,8 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
/* Request transmission */
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
- /* Get timeout */
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Check End of transmission flag */
while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
@@ -606,12 +620,12 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
- {
- hcan->State = HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
}
}
}
@@ -639,7 +653,10 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
-
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
/* Return function status */
return HAL_ERROR;
}
@@ -769,14 +786,13 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
* @brief Receives a correct CAN frame.
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
- * @param FIFONumber: FIFO Number value
- * @param Timeout: Specify Timeout value
+ * @param FIFONumber: FIFO Number value
+ * @param Timeout: Specify Timeout value
* @retval HAL status
- * @retval None
*/
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
{
- uint32_t timeout;
+ uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_CAN_FIFO(FIFONumber));
@@ -795,8 +811,8 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u
hcan->State = HAL_CAN_STATE_BUSY_RX;
}
- /* Get timeout */
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Check pending message */
while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)
@@ -804,7 +820,7 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
hcan->State = HAL_CAN_STATE_TIMEOUT;
/* Process unlocked */
@@ -879,7 +895,6 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u
* the configuration information for the specified CAN.
* @param FIFONumber: Specify the FIFO number
* @retval HAL status
- * @retval None
*/
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
{
@@ -955,7 +970,7 @@ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber
*/
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
{
- uint32_t timeout;
+ uint32_t tickstart = 0;
/* Process locked */
__HAL_LOCK(hcan);
@@ -969,17 +984,20 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
/* Sleep mode status */
if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
{
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
/* Return function status */
return HAL_ERROR;
}
- /* Get timeout */
- timeout = HAL_GetTick() + 10;
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Wait the acknowledge */
while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
hcan->State = HAL_CAN_STATE_TIMEOUT;
/* Process unlocked */
@@ -1007,7 +1025,7 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
*/
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
{
- uint32_t timeout;
+ uint32_t tickstart = 0;
/* Process locked */
__HAL_LOCK(hcan);
@@ -1017,14 +1035,14 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
/* Wake up request */
hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
-
- /* Get timeout */
- timeout = HAL_GetTick() + 10;
-
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Sleep mode status */
while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
hcan->State= HAL_CAN_STATE_TIMEOUT;
/* Process unlocked */
@@ -1034,6 +1052,9 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
}
if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
{
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
/* Return function status */
return HAL_ERROR;
}
@@ -1219,7 +1240,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
* @}
*/
-/** @defgroup CAN_Group3 Peripheral State and Error functions
+/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
* @brief CAN Peripheral State functions
*
@verbatim
@@ -1227,7 +1248,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
##### Peripheral State and Error functions #####
==============================================================================
[..]
- This subsection provides functions allowing to
+ This subsection provides functions allowing to :
(+) Check the CAN state.
(+) Check CAN Errors detected during interrupt process
diff --git a/f2/src/stm32f2xx_hal_cortex.c b/f2/src/stm32f2xx_hal_cortex.c
index b9cc5535e39acae02705aa0e9a6e2bbf29caaef2..2a489b4d864472012027693f92e22085fecc851f 100755
--- a/f2/src/stm32f2xx_hal_cortex.c
+++ b/f2/src/stm32f2xx_hal_cortex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_cortex.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
@@ -16,55 +16,33 @@
==============================================================================
[..]
- *** How to configure Interrupts using Cortex HAL driver ***
+ *** How to configure Interrupts using CORTEX HAL driver ***
===========================================================
[..]
- This section provide functions allowing to configure the NVIC interrupts (IRQ).
+ This section provides functions allowing to configure the NVIC interrupts (IRQ).
The Cortex-M3 exceptions are managed by CMSIS functions.
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
function according to the following table.
-
- The table below gives the allowed values of the pre-emption priority and subpriority according
- to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
- ==========================================================================================================================
- NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
- ==========================================================================================================================
- NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
- | | | 4 bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
- | | | 3 bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
- | | | 2 bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
- | | | 1 bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
- | | | 0 bits for subpriority
- ==========================================================================================================================
- (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
-
- (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
+ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
+ (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+ (#) please refer to programing manual for details in how to configure priority.
-
- -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
+ -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
-@- IRQ priority order (sorted by highest to lowest priority):
- (+@) Lowest pre-emption priority
+ (+@) Lowest preemption priority
(+@) Lowest sub priority
(+@) Lowest hardware priority (IRQ number)
[..]
- *** How to configure Systick using Cortex HAL driver ***
+ *** How to configure Systick using CORTEX HAL driver ***
========================================================
[..]
- Setup SysTick Timer for 1 msec interrupts.
+ Setup SysTick Timer for time base.
- (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
+ (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter.
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
@@ -92,7 +70,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -126,26 +104,26 @@
* @{
*/
-/** @defgroup CORTEX
+/** @defgroup CORTEX CORTEX
* @brief CORTEX HAL module driver
* @{
*/
#ifdef HAL_CORTEX_MODULE_ENABLED
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Functions
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{
*/
-/** @defgroup CORTEX_Group1 Initialization and de-initialization functions
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -153,7 +131,7 @@
##### Initialization and de-initialization functions #####
==============================================================================
[..]
- This section provide the Cortex HAL driver functions allowing to configure Interrupts
+ This section provides the CORTEX HAL driver functions allowing to configure Interrupts
Systick functionalities
@endverbatim
@@ -162,21 +140,21 @@
/**
- * @brief Sets the priority grouping field (pre-emption priority and subpriority)
+ * @brief Sets the priority grouping field (preemption priority and subpriority)
* using the required unlock sequence.
* @param PriorityGroup: The priority grouping bits length.
* This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
* 4 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
* 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
* 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
* 1 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
* 0 bits for subpriority
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
@@ -191,10 +169,10 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
/**
* @brief Sets the priority of an interrupt.
- * @param IRQn: External interrupt number
- * This parameter can be an enumerator of @ref IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f2xx.h file)
- * @param PreemptPriority: The pre-emption priority for the IRQn channel.
+ * @param IRQn: External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
+ * @param PreemptPriority: The preemption priority for the IRQn channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority
* @param SubPriority: the subpriority level for the IRQ channel.
@@ -219,33 +197,38 @@ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t Sub
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before.
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of @ref IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f2xx.h file)
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
}
/**
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of @ref IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f2xx.h file)
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
* @retval None
*/
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Disable interrupt */
NVIC_DisableIRQ(IRQn);
}
/**
* @brief Initiates a system reset request to reset the MCU.
- * @param None
* @retval None
*/
void HAL_NVIC_SystemReset(void)
@@ -269,7 +252,7 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
* @}
*/
-/** @defgroup CORTEX_Group2 Peripheral Control functions
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
* @brief Cortex control functions
*
@verbatim
@@ -278,16 +261,62 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
==============================================================================
[..]
This subsection provides a set of functions allowing to control the CORTEX
- (NVIC, SYSTICK) functionalities.
+ (NVIC, SYSTICK, MPU) functionalities.
@endverbatim
* @{
*/
+#if (__MPU_PRESENT == 1)
+/**
+ * @brief Initializes and configures the Region and the memory to be protected.
+ * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
+ * the initialization and configuration information.
+ * @retval None
+ */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+ assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+ /* Set the Region number */
+ MPU->RNR = MPU_Init->Number;
+
+ if ((MPU_Init->Enable) != RESET)
+ {
+ /* Check the parameters */
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+ MPU->RBAR = MPU_Init->BaseAddress;
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
+ }
+ else
+ {
+ MPU->RBAR = 0x00;
+ MPU->RASR = 0x00;
+ }
+}
+#endif /* __MPU_PRESENT */
+
/**
* @brief Gets the priority grouping field from the NVIC Interrupt Controller.
- * @param None
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
*/
uint32_t HAL_NVIC_GetPriorityGrouping(void)
@@ -298,20 +327,20 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void)
/**
* @brief Gets the priority of an interrupt.
- * @param IRQn: External interrupt number
- * This parameter can be an enumerator of @ref IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f2xx.h file)
+ * @param IRQn: External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
* @param PriorityGroup: the priority grouping bits length.
* This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
* 4 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
* 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
* 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
* 1 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
* 0 bits for subpriority
* @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
* @param pSubPriority: Pointer on the Subpriority value (starting from 0).
@@ -328,12 +357,15 @@ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPre
/**
* @brief Sets Pending bit of an external interrupt.
* @param IRQn External interrupt number
- * This parameter can be an enumerator of @ref IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f2xx.h file)
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
* @retval None
*/
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
}
@@ -341,27 +373,33 @@ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
/**
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
* and returns the pending bit for the specified interrupt).
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of @ref IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f2xx.h file)
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Return 1 if pending else 0 */
return NVIC_GetPendingIRQ(IRQn);
}
/**
* @brief Clears the pending bit of an external interrupt.
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of @ref IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f2xx.h file)
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
* @retval None
*/
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Clear pending interrupt */
NVIC_ClearPendingIRQ(IRQn);
}
@@ -369,13 +407,16 @@ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
/**
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
* @param IRQn External interrupt number
- * This parameter can be an enumerator of @ref IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f2xx.h file)
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
-{
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Return 1 if active else 0 */
return NVIC_GetActive(IRQn);
}
@@ -404,7 +445,6 @@ void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
/**
* @brief This function handles SYSTICK interrupt request.
- * @param None
* @retval None
*/
void HAL_SYSTICK_IRQHandler(void)
@@ -414,7 +454,6 @@ void HAL_SYSTICK_IRQHandler(void)
/**
* @brief SYSTICK callback.
- * @param None
* @retval None
*/
__weak void HAL_SYSTICK_Callback(void)
diff --git a/f2/src/stm32f2xx_hal_crc.c b/f2/src/stm32f2xx_hal_crc.c
index 9874ef844165ab7e328dca9d000b0358a79fd2ab..9daf79b7e33ecbfc65ce92f8d50c2c499bf2f9b9 100755
--- a/f2/src/stm32f2xx_hal_crc.c
+++ b/f2/src/stm32f2xx_hal_crc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_crc.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@@ -18,7 +18,7 @@
[..]
The CRC HAL driver can be used as follows:
- (#) Enable CRC AHB clock using __CRC_CLK_ENABLE();
+ (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
(#) Use HAL_CRC_Accumulate() function to compute the CRC value of
a 32-bit data buffer using combination of the previous CRC value
@@ -32,7 +32,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -66,8 +66,7 @@
* @{
*/
-/** @defgroup CRC
- * @brief CRC HAL module driver.
+/** @addtogroup CRC
* @{
*/
@@ -79,15 +78,16 @@
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRC_Private_Functions
+/** @addtogroup CRC_Exported_Functions
* @{
*/
-/** @defgroup CRC_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
+/** @addtogroup CRC_Exported_Functions_Group1
+ * @brief Initialization and de-initialization functions
*
-@verbatim
+@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
@@ -105,7 +105,8 @@
/**
* @brief Initializes the CRC according to the specified
* parameters in the CRC_InitTypeDef and creates the associated handle.
- * @param hcrc: CRC handle
+ * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
@@ -121,6 +122,8 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
if(hcrc->State == HAL_CRC_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hcrc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_CRC_MspInit(hcrc);
}
@@ -137,7 +140,8 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
/**
* @brief DeInitializes the CRC peripheral.
- * @param hcrc: CRC handle
+ * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
@@ -169,7 +173,8 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
/**
* @brief Initializes the CRC MSP.
- * @param hcrc: CRC handle
+ * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
* @retval None
*/
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
@@ -181,7 +186,8 @@ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
/**
* @brief DeInitializes the CRC MSP.
- * @param hcrc: CRC handle
+ * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
* @retval None
*/
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
@@ -193,12 +199,12 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
/**
* @}
- */
+ */
-/** @defgroup CRC_Group2 Peripheral Control functions
- * @brief management functions.
+/** @addtogroup CRC_Exported_Functions_Group2
+ * @brief Peripheral Control functions
*
-@verbatim
+@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
@@ -215,7 +221,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
/**
* @brief Computes the 32-bit CRC of 32-bit data buffer using combination
* of the previous CRC value and the new one.
- * @param hcrc: CRC handle
+ * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
* @param pBuffer: pointer to the buffer containing the data to be computed
* @param BufferLength: length of the buffer to be computed
* @retval 32-bit CRC
@@ -249,7 +256,8 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_
/**
* @brief Computes the 32-bit CRC of 32-bit data buffer independently
* of the previous CRC value.
- * @param hcrc: CRC handle
+ * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
* @param pBuffer: Pointer to the buffer containing the data to be computed
* @param BufferLength: Length of the buffer to be computed
* @retval 32-bit CRC
@@ -285,10 +293,11 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
/**
* @}
- */
+ */
-/** @defgroup CRC_Group3 Peripheral State functions
- * @brief Peripheral State functions.
+
+/** @addtogroup CRC_Exported_Functions_Group3
+ * @brief Peripheral State functions
*
@verbatim
==============================================================================
@@ -304,7 +313,8 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
/**
* @brief Returns the CRC state.
- * @param hcrc: CRC handle
+ * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
* @retval HAL state
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
diff --git a/f2/src/stm32f2xx_hal_cryp.c b/f2/src/stm32f2xx_hal_cryp.c
index 711a3f7f6a3dac6e6e69d7d1545bfcd5517669c0..7d9d916cfc149e92e7bfba8f82749606157b6171 100755
--- a/f2/src/stm32f2xx_hal_cryp.c
+++ b/f2/src/stm32f2xx_hal_cryp.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_cryp.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief CRYP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
@@ -23,24 +23,21 @@
The CRYP HAL driver can be used as follows:
(#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
- (##) Enable the CRYP interface clock using __CRYP_CLK_ENABLE()
+ (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
(##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
(+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
(+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
(##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
- (++) Enable the DMAx interface clock using
- (+++) __DMAx_CLK_ENABLE()
- (++) Configure and enable two DMA streams one for managing data transfer from
+ (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+ (+++) Configure and enable two DMA streams one for managing data transfer from
memory to peripheral (input stream) and another stream for managing data
transfer from peripheral to memory (output stream)
- (++) Associate the initilalized DMA handle to the CRYP DMA handle
+ (+++) Associate the initialized DMA handle to the CRYP DMA handle
using __HAL_LINKDMA()
- (++) Configure the priority and enable the NVIC for the transfer complete
+ (+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the two DMA Streams. The output stream should have higher
- priority than the input stream.
- (+++) HAL_NVIC_SetPriority()
- (+++) HAL_NVIC_EnableIRQ()
+ priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
(#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
(##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
@@ -51,13 +48,13 @@
(#)Three processing (encryption/decryption) functions are available:
(##) Polling mode: encryption and decryption APIs are blocking functions
- i.e. they process the data and wait till the processing is finished
+ i.e. they process the data and wait till the processing is finished,
e.g. HAL_CRYP_AESCBC_Encrypt()
(##) Interrupt mode: encryption and decryption APIs are not blocking functions
- i.e. they process the data under interrupt
+ i.e. they process the data under interrupt,
e.g. HAL_CRYP_AESCBC_Encrypt_IT()
(##) DMA mode: encryption and decryption APIs are not blocking functions
- i.e. the data transfer is ensured by DMA
+ i.e. the data transfer is ensured by DMA,
e.g. HAL_CRYP_AESCBC_Encrypt_DMA()
(#)When the processing function is called at first time after HAL_CRYP_Init()
@@ -73,7 +70,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -107,7 +104,7 @@
* @{
*/
-/** @defgroup CRYP
+/** @defgroup CRYP CRYP
* @brief CRYP HAL module driver.
* @{
*/
@@ -118,9 +115,20 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @defgroup CRYP_Private_define CRYP Private define
+ * @{
+ */
+#define CRYP_TIMEOUT_VALUE 1
+/**
+ * @}
+ */
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CRYP_Private_Functions_prototypes CRYP Private Functions prototypes
+ * @{
+ */
static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize);
static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);
static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
@@ -133,489 +141,640 @@ static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
-
+/**
+ * @}
+ */
+
/* Private functions ---------------------------------------------------------*/
-/** @defgroup CRYP_Private_Functions
+/** @addtogroup CRYP_Private_Functions
* @{
*/
-/** @defgroup CRYP_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the CRYP according to the specified parameters
- in the CRYP_InitTypeDef and creates the associated handle
- (+) DeInitialize the CRYP peripheral
- (+) Initialize the CRYP MSP
- (+) DeInitialize CRYP MSP
-
-@endverbatim
- * @{
- */
/**
- * @brief Initializes the CRYP according to the specified
- * parameters in the CRYP_InitTypeDef and creates the associated handle.
- * @param hcryp: CRYP handle
- * @retval HAL status
+ * @brief DMA CRYP Input Data process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
-{
- /* Check the CRYP handle allocation */
- if(hcryp == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
- assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
-
- if(hcryp->State == HAL_CRYP_STATE_RESET)
- {
- /* Init the low level hardware */
- HAL_CRYP_MspInit(hcryp);
- }
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Set the key size and data type*/
- CRYP->CR = (uint32_t) (hcryp->Init.KeySize | hcryp->Init.DataType);
-
- /* Reset CrypInCount and CrypOutCount */
- hcryp->CrypInCount = 0;
- hcryp->CrypOutCount = 0;
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- /* Set the default CRYP phase */
- hcryp->Phase = HAL_CRYP_PHASE_READY;
+ /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
+ in the DMACR register */
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
- /* Return function status */
- return HAL_OK;
+ /* Call input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
}
/**
- * @brief DeInitializes the CRYP peripheral.
- * @param hcryp: CRYP handle
- * @retval HAL status
+ * @brief DMA CRYP Output Data process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
{
- /* Check the CRYP handle allocation */
- if(hcryp == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Set the default CRYP phase */
- hcryp->Phase = HAL_CRYP_PHASE_READY;
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- /* Reset CrypInCount and CrypOutCount */
- hcryp->CrypInCount = 0;
- hcryp->CrypOutCount = 0;
+ /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit
+ in the DMACR register */
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
- /* Disable the CRYP Peripheral Clock */
- __HAL_CRYP_DISABLE();
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
- /* DeInit the low level hardware: CLOCK, NVIC.*/
- HAL_CRYP_MspDeInit(hcryp);
+ /* Change the CRYP state to ready */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
+ /* Call output data transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
}
/**
- * @brief Initializes the CRYP MSP.
- * @param hcryp: CRYP handle
+ * @brief DMA CRYP communication error callback.
+ * @param hdma: DMA handle
* @retval None
*/
-__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_MspInit could be implemented in the user file
- */
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ hcryp->State= HAL_CRYP_STATE_READY;
+ HAL_CRYP_ErrorCallback(hcryp);
}
/**
- * @brief DeInitializes CRYP MSP.
- * @param hcryp: CRYP handle
+ * @brief Writes the Key in Key registers.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Key: Pointer to Key buffer
+ * @param KeySize: Size of Key
* @retval None
*/
-__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_MspDeInit could be implemented in the user file
- */
+ uint32_t keyaddr = (uint32_t)Key;
+
+ switch(KeySize)
+ {
+ case CRYP_KEYSIZE_256B:
+ /* Key Initialisation */
+ hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
+ break;
+ case CRYP_KEYSIZE_192B:
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
+ break;
+ case CRYP_KEYSIZE_128B:
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
+ break;
+ default:
+ break;
+ }
}
/**
- * @}
- */
-
-/** @defgroup CRYP_Group2 AES processing functions
- * @brief processing functions.
- *
-@verbatim
- ==============================================================================
- ##### AES processing functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Encrypt plaintext using AES-128/192/256 using chaining modes
- (+) Decrypt cyphertext using AES-128/192/256 using chaining modes
- [..] Three processing functions are available:
- (+) Polling mode
- (+) Interrupt mode
- (+) DMA mode
-
-@endverbatim
- * @{
+ * @brief Writes the InitVector/InitCounter in IV registers.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param InitVector: Pointer to InitVector/InitCounter buffer
+ * @param IVSize: Size of the InitVector/InitCounter
+ * @retval None
*/
+static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize)
+{
+ uint32_t ivaddr = (uint32_t)InitVector;
+
+ switch(IVSize)
+ {
+ case CRYP_KEYSIZE_128B:
+ hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4;
+ hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4;
+ hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4;
+ hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));
+ break;
+ /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */
+ case CRYP_KEYSIZE_192B:
+ hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4;
+ hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
+ break;
+ case CRYP_KEYSIZE_256B:
+ hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4;
+ hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
+ break;
+ default:
+ break;
+ }
+}
/**
- * @brief Initializes the CRYP peripheral in AES ECB encryption mode
- * then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp: CRYP handle
- * @param pPlainData: Pointer to the plaintext buffer
- * @param Size: Length of the plaintext buffer, must be a multiple of 16.
- * @param pCypherData: Pointer to the cyphertext buffer
- * @param Timeout: Specify Timeout value
- * @retval HAL status
+ * @brief Process Data: Writes Input data in polling mode and read the output data
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Input: Pointer to the Input buffer
+ * @param Ilength: Length of the Input buffer, must be a multiple of 16.
+ * @param Output: Pointer to the returned buffer
+ * @param Timeout: Timeout value
+ * * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ uint32_t tickstart = 0;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ uint32_t i = 0;
+ uint32_t inputaddr = (uint32_t)Input;
+ uint32_t outputaddr = (uint32_t)Output;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ for(i=0; (i < Ilength); i+=16)
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ }
/* Return function status */
return HAL_OK;
}
/**
- * @brief Initializes the CRYP peripheral in AES CBC encryption mode
- * then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp: CRYP handle
- * @param pPlainData: Pointer to the plaintext buffer
- * @param Size: Length of the plaintext buffer, must be a multiple of 16.
- * @param pCypherData: Pointer to the cyphertext buffer
+ * @brief Process Data: Write Input data in polling mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Input: Pointer to the Input buffer
+ * @param Ilength: Length of the Input buffer, must be a multiple of 8
+ * @param Output: Pointer to the returned buffer
* @param Timeout: Specify Timeout value
- * @retval HAL status
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ uint32_t tickstart = 0;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ uint32_t i = 0;
+ uint32_t inputaddr = (uint32_t)Input;
+ uint32_t outputaddr = (uint32_t)Output;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ for(i=0; (i < Ilength); i+=8)
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC);
-
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
- /* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
- return HAL_TIMEOUT;
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
}
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ }
/* Return function status */
return HAL_OK;
}
/**
- * @brief Initializes the CRYP peripheral in AES CTR encryption mode
- * then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp: CRYP handle
- * @param pPlainData: Pointer to the plaintext buffer
- * @param Size: Length of the plaintext buffer, must be a multiple of 16.
- * @param pCypherData: Pointer to the cyphertext buffer
- * @param Timeout: Specify Timeout value
- * @retval HAL status
+ * @brief Set the DMA configuration and start the DMA transfer
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param inputaddr: address of the Input buffer
+ * @param Size: Size of the Input buffer, must be a multiple of 16.
+ * @param outputaddr: address of the Output buffer
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
+{
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
+ /* Set the DMA error callback */
+ hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
+ /* Set the DMA error callback */
+ hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4);
+
+ /* Enable In DMA request */
+ hcryp->Instance->DMACR = (CRYP_DMACR_DIEN);
+
+ /* Enable the DMA Out DMA Stream */
+ HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4);
+ /* Enable Out DMA request */
+ hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;
+
+}
+
+/**
+ * @brief Sets the CRYP peripheral in DES ECB mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Direction: Encryption or decryption
+ * @retval None
+ */
+static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
+{
/* Check if initialization phase has already been performed */
if(hcryp->Phase == HAL_CRYP_PHASE_READY)
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
/* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_ECB | Direction);
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ /* Set the key */
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
-
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
}
-
-
/**
- * @brief Initializes the CRYP peripheral in AES ECB decryption mode
- * then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp: CRYP handle
- * @param pCypherData: Pointer to the cyphertext buffer
- * @param Size: Length of the plaintext buffer, must be a multiple of 16.
- * @param pPlainData: Pointer to the plaintext buffer
- * @param Timeout: Specify Timeout value
- * @retval HAL status
+ * @brief Sets the CRYP peripheral in DES CBC mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Direction: Encryption or decryption
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
{
- uint32_t timeout = 0;
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
/* Check if initialization phase has already been performed */
if(hcryp->Phase == HAL_CRYP_PHASE_READY)
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE();
-
- /* Get timeout */
- timeout = HAL_GetTick() + Timeout;
-
- while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if(HAL_GetTick() >= timeout)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_CBC | Direction);
- /* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ /* Set the key */
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
- /* Reset the ALGOMODE bits*/
- CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
- /* Set the CRYP peripheral in AES ECB decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
-
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
}
/**
- * @brief Initializes the CRYP peripheral in AES ECB decryption mode
- * then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp: CRYP handle
- * @param pCypherData: Pointer to the cyphertext buffer
- * @param Size: Length of the plaintext buffer, must be a multiple of 16.
- * @param pPlainData: Pointer to the plaintext buffer
- * @param Timeout: Specify Timeout value
- * @retval HAL status
+ * @brief Sets the CRYP peripheral in TDES ECB mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Direction: Encryption or decryption
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
{
- uint32_t timeout = 0;
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
/* Check if initialization phase has already been performed */
if(hcryp->Phase == HAL_CRYP_PHASE_READY)
{
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_ECB | Direction);
+
/* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
- /* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
- /* Get Timeout */
- timeout = HAL_GetTick() + Timeout;
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+}
- while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if(HAL_GetTick() >= timeout)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Reset the ALGOMODE bits*/
- CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+/**
+ * @brief Sets the CRYP peripheral in TDES CBC mode
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Direction: Encryption or decryption
+ * @retval None
+ */
+static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
+{
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the CRYP peripheral in AES CBC mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_CBC | Direction);
- /* Set the CRYP peripheral in AES CBC decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
/* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+}
+
+/**
+ * @}
+ */
+
+ /* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRYP_Exported_Functions
+ * @{
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CRYP according to the specified parameters
+ in the CRYP_InitTypeDef and creates the associated handle
+ (+) DeInitialize the CRYP peripheral
+ (+) Initialize the CRYP MSP
+ (+) DeInitialize CRYP MSP
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CRYP according to the specified
+ * parameters in the CRYP_InitTypeDef and creates the associated handle.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
+{
+ /* Check the CRYP handle allocation */
+ if(hcryp == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
+ assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
+
+ if(hcryp->State == HAL_CRYP_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcryp->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_CRYP_MspInit(hcryp);
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set the key size and data type*/
+ CRYP->CR = (uint32_t) (hcryp->Init.KeySize | hcryp->Init.DataType);
+
+ /* Reset CrypInCount and CrypOutCount */
+ hcryp->CrypInCount = 0;
+ hcryp->CrypOutCount = 0;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Set the default CRYP phase */
+ hcryp->Phase = HAL_CRYP_PHASE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the CRYP peripheral.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
+{
+ /* Check the CRYP handle allocation */
+ if(hcryp == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set the default CRYP phase */
+ hcryp->Phase = HAL_CRYP_PHASE_READY;
+
+ /* Reset CrypInCount and CrypOutCount */
+ hcryp->CrypInCount = 0;
+ hcryp->CrypOutCount = 0;
+
+ /* Disable the CRYP Peripheral Clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ HAL_CRYP_MspDeInit(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP MSP.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes CRYP MSP.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions
+ * @brief processing functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### AES processing functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Encrypt plaintext using AES-128/192/256 using chaining modes
+ (+) Decrypt cyphertext using AES-128/192/256 using chaining modes
+ [..] Three processing functions are available:
+ (+) Polling mode
+ (+) Interrupt mode
+ (+) DMA mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CRYP peripheral in AES ECB encryption mode
+ * then encrypt pPlainData. The cypher data are available in pCypherData
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @param Timeout: Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
/* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -631,47 +790,48 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
}
/**
- * @brief Initializes the CRYP peripheral in AES CTR decryption mode
- * then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp: CRYP handle
- * @param pCypherData: Pointer to the cyphertext buffer
- * @param Size: Length of the plaintext buffer, must be a multiple of 16.
+ * @brief Initializes the CRYP peripheral in AES CBC encryption mode
+ * then encrypt pPlainData. The cypher data are available in pCypherData
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.
+ * @param pCypherData: Pointer to the cyphertext buffer
* @param Timeout: Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
/* Process Locked */
__HAL_LOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
/* Check if initialization phase has already been performed */
if(hcryp->Phase == HAL_CRYP_PHASE_READY)
{
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
/* Set the key */
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
- /* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
/* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -687,322 +847,309 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
}
/**
- * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
- * @param hcryp: CRYP handle
+ * @brief Initializes the CRYP peripheral in AES CTR encryption mode
+ * then encrypt pPlainData. The cypher data are available in pCypherData
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
- * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pCypherData: Pointer to the cyphertext buffer
+ * @param Timeout: Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16;
- hcryp->CrypInCount -= 16;
- if(hcryp->CrypInCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
- }
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
- {
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- hcryp->pCrypOutBuffPtr += 16;
- hcryp->CrypOutCount -= 16;
- if(hcryp->CrypOutCount == 0)
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
- /* Process Locked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
+ return HAL_TIMEOUT;
}
- }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
/* Return function status */
return HAL_OK;
}
+
+
/**
- * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
- * @param hcryp: CRYP handle
- * @param pPlainData: Pointer to the plaintext buffer
- * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode
+ * then decrypted pCypherData. The cypher data are available in pPlainData
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @param Timeout: Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint32_t tickstart = 0;
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
+ /* Set the CRYP peripheral in AES Key mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES CBC mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC);
-
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
}
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Reset the ALGOMODE bits*/
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+
+ /* Set the CRYP peripheral in AES ECB decryption mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16;
- hcryp->CrypInCount -= 16;
- if(hcryp->CrypInCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
- }
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
- {
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- hcryp->pCrypOutBuffPtr += 16;
- hcryp->CrypOutCount -= 16;
- if(hcryp->CrypOutCount == 0)
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
- /* Process Locked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
+ return HAL_TIMEOUT;
}
- }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
/* Return function status */
return HAL_OK;
}
/**
- * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
- * @param hcryp: CRYP handle
- * @param pPlainData: Pointer to the plaintext buffer
- * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode
+ * then decrypted pCypherData. The cypher data are available in pPlainData
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @param Timeout: Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint32_t tickstart = 0;
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR);
-
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ /* Set the CRYP peripheral in AES Key mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16;
- hcryp->CrypInCount -= 16;
- if(hcryp->CrypInCount == 0)
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
}
+
+ /* Reset the ALGOMODE bits*/
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+
+ /* Set the CRYP peripheral in AES CBC decryption mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
- {
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- hcryp->pCrypOutBuffPtr += 16;
- hcryp->CrypOutCount -= 16;
- if(hcryp->CrypOutCount == 0)
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
+ return HAL_TIMEOUT;
}
- }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
/* Return function status */
return HAL_OK;
}
-
/**
- * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
- * @param hcryp: CRYP handle
+ * @brief Initializes the CRYP peripheral in AES CTR decryption mode
+ * then decrypted pCypherData. The cypher data are available in pPlainData
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pPlainData: Pointer to the plaintext buffer
+ * @param Timeout: Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t timeout = 0;
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES CTR mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+/**
+ * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
uint32_t inputaddr;
uint32_t outputaddr;
@@ -1012,101 +1159,75 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
__HAL_LOCK(hcryp);
hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
+ hcryp->pCrypInBuffPtr = pPlainData;
+ hcryp->pCrypOutBuffPtr = pCypherData;
hcryp->CrypOutCount = Size;
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_BUSY;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
- /* Enable CRYP */
- __HAL_CRYP_ENABLE();
-
- /* Get timeout */
- timeout = HAL_GetTick() + 1;
-
- while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
{
- /* Check for the Timeout */
- if(HAL_GetTick() >= timeout)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Reset the ALGOMODE bits*/
- CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
-
- /* Set the CRYP peripheral in AES ECB decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
-
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
+ }
+
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
- /* Process Unlocked */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Process Locked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
@@ -1120,17 +1241,16 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
}
/**
- * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT.
- * @param hcryp: CRYP handle
- * @param pCypherData: Pointer to the cyphertext buffer
- * @param Size: Length of the plaintext buffer, must be a multiple of 16
+ * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @param pCypherData: Pointer to the cyphertext buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
{
-
- uint32_t timeout = 0;
uint32_t inputaddr;
uint32_t outputaddr;
@@ -1139,10 +1259,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/* Process Locked */
__HAL_LOCK(hcryp);
- /* Get the buffer addresses and sizes */
hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
+ hcryp->pCrypInBuffPtr = pPlainData;
+ hcryp->pCrypOutBuffPtr = pCypherData;
hcryp->CrypOutCount = Size;
/* Change the CRYP state */
@@ -1150,99 +1269,68 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/* Check if initialization phase has already been performed */
if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
+ {
/* Set the key */
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
- /* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ /* Set the CRYP peripheral in AES CBC mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
- /* Get timeout */
- timeout = HAL_GetTick() + 1;
-
- while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(HAL_GetTick() >= timeout)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Reset the ALGOMODE bits*/
- CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
-
- /* Set the CRYP peripheral in AES CBC decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
-
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
-
+
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
-
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
- /* Process Unlocked */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Process Locked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
@@ -1256,14 +1344,15 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
}
/**
- * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
- * @param hcryp: CRYP handle
- * @param pCypherData: Pointer to the cyphertext buffer
- * @param Size: Length of the plaintext buffer, must be a multiple of 16
+ * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @param pCypherData: Pointer to the cyphertext buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
{
uint32_t inputaddr;
uint32_t outputaddr;
@@ -1273,10 +1362,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/* Process Locked */
__HAL_LOCK(hcryp);
- /* Get the buffer addresses and sizes */
hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
+ hcryp->pCrypInBuffPtr = pPlainData;
+ hcryp->pCrypOutBuffPtr = pCypherData;
hcryp->CrypOutCount = Size;
/* Change the CRYP state */
@@ -1289,63 +1377,62 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
-
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -1359,196 +1446,572 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
return HAL_OK;
}
+
/**
- * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
- * @param hcryp: CRYP handle
- * @param pPlainData: Pointer to the plaintext buffer
- * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.
+ * @param pPlainData: Pointer to the plaintext buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
{
+ uint32_t tickstart = 0;
+
uint32_t inputaddr;
uint32_t outputaddr;
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ if(hcryp->State == HAL_CRYP_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hcryp);
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pCypherData;
+ hcryp->pCrypOutBuffPtr = pPlainData;
+ hcryp->CrypOutCount = Size;
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_BUSY;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES Key mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
}
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Reset the ALGOMODE bits*/
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+
+ /* Set the CRYP peripheral in AES ECB decryption mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
/* Return function status */
return HAL_OK;
}
- else
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
- return HAL_ERROR;
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16;
+ hcryp->CrypInCount -= 16;
+ if(hcryp->CrypInCount == 0)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ hcryp->pCrypOutBuffPtr += 16;
+ hcryp->CrypOutCount -= 16;
+ if(hcryp->CrypOutCount == 0)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
}
+
+ /* Return function status */
+ return HAL_OK;
}
/**
- * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
- * @param hcryp: CRYP handle
- * @param pPlainData: Pointer to the plaintext buffer
- * @param Size: Length of the plaintext buffer, must be a multiple of 16.
+ * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16
+ * @param pPlainData: Pointer to the plaintext buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
{
+
+ uint32_t tickstart = 0;
uint32_t inputaddr;
uint32_t outputaddr;
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ if(hcryp->State == HAL_CRYP_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hcryp);
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
+ /* Get the buffer addresses and sizes */
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pCypherData;
+ hcryp->pCrypOutBuffPtr = pPlainData;
+ hcryp->CrypOutCount = Size;
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_BUSY;
-
+
/* Check if initialization phase has already been performed */
if(hcryp->Phase == HAL_CRYP_PHASE_READY)
{
/* Set the key */
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC);
+ /* Set the CRYP peripheral in AES Key mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset the ALGOMODE bits*/
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+
+ /* Set the CRYP peripheral in AES CBC decryption mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
-
+
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
}
- else
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
- return HAL_ERROR;
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16;
+ hcryp->CrypInCount -= 16;
+ if(hcryp->CrypInCount == 0)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ hcryp->pCrypOutBuffPtr += 16;
+ hcryp->CrypOutCount -= 16;
+ if(hcryp->CrypOutCount == 0)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
}
+
+ /* Return function status */
+ return HAL_OK;
}
/**
- * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
- * @param hcryp: CRYP handle
- * @param pPlainData: Pointer to the plaintext buffer
- * @param Size: Length of the plaintext buffer, must be a multiple of 16.
+ * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16
+ * @param pPlainData: Pointer to the plaintext buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
{
uint32_t inputaddr;
uint32_t outputaddr;
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ if(hcryp->State == HAL_CRYP_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hcryp);
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
+ /* Get the buffer addresses and sizes */
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pCypherData;
+ hcryp->pCrypOutBuffPtr = pPlainData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
/* Check if initialization phase has already been performed */
if(hcryp->Phase == HAL_CRYP_PHASE_READY)
{
/* Set the key */
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR);
+ /* Set the CRYP peripheral in AES CTR mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
- return HAL_ERROR;
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16;
+ hcryp->CrypInCount -= 16;
+ if(hcryp->CrypInCount == 0)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
}
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
- * @param hcryp: CRYP handle
- * @param pCypherData: Pointer to the cyphertext buffer
- * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
- * @param pPlainData: Pointer to the plaintext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t timeout = 0;
- uint32_t inputaddr;
- uint32_t outputaddr;
-
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- inputaddr = (uint32_t)pCypherData;
- outputaddr = (uint32_t)pPlainData;
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ hcryp->pCrypOutBuffPtr += 16;
+ hcryp->CrypOutCount -= 16;
+ if(hcryp->CrypOutCount == 0)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pPlainData;
+ outputaddr = (uint32_t)pCypherData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pPlainData;
+ outputaddr = (uint32_t)pCypherData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pPlainData;
+ outputaddr = (uint32_t)pCypherData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t tickstart = 0;
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pCypherData;
+ outputaddr = (uint32_t)pPlainData;
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_BUSY;
@@ -1560,23 +2023,23 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
- /* Get timeout */
- timeout = HAL_GetTick() + 1;
+ /* Get tick */
+ tickstart = HAL_GetTick();
- while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
/* Check for the Timeout */
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
{
/* Change state */
hcryp->State = HAL_CRYP_STATE_TIMEOUT;
- /* Process Unlocked */
+ /* Process Unlocked */
__HAL_UNLOCK(hcryp);
return HAL_TIMEOUT;
@@ -1587,10 +2050,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
/* Set the CRYP peripheral in AES ECB decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1613,7 +2076,8 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
* @param pPlainData: Pointer to the plaintext buffer
@@ -1621,7 +2085,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
*/
HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
uint32_t inputaddr;
uint32_t outputaddr;
@@ -1643,23 +2107,23 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
- /* Get timeout */
- timeout = HAL_GetTick() + 1;
+ /* Get tick */
+ tickstart = HAL_GetTick();
- while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
/* Check for the Timeout */
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
{
/* Change state */
hcryp->State = HAL_CRYP_STATE_TIMEOUT;
- /* Process Unlocked */
+ /* Process Unlocked */
__HAL_UNLOCK(hcryp);
return HAL_TIMEOUT;
@@ -1670,13 +2134,13 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
/* Set the CRYP peripheral in AES CBC decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1699,7 +2163,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16
* @param pPlainData: Pointer to the plaintext buffer
@@ -1728,13 +2193,13 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1759,7 +2224,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @}
*/
-/** @defgroup CRYP_Group3 DES processing functions
+
+/** @defgroup CRYP_Exported_Functions_Group3 DES processing functions
* @brief processing functions.
*
@verbatim
@@ -1768,10 +2234,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
==============================================================================
[..] This section provides functions allowing to:
(+) Encrypt plaintext using DES using ECB or CBC chaining modes
- (+) Decrypt cyphertext using using ECB or CBC chaining modes
+ (+) Decrypt cyphertext using ECB or CBC chaining modes
[..] Three processing functions are available:
- (+) polling mode
- (+) interrupt mode
+ (+) Polling mode
+ (+) Interrupt mode
(+) DMA mode
@endverbatim
@@ -1780,7 +2246,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in DES ECB encryption mode.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -1799,7 +2266,7 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
CRYP_SetDESECBMode(hcryp, 0);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -1819,7 +2286,8 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
/**
* @brief Initializes the CRYP peripheral in DES ECB decryption mode.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -1838,7 +2306,7 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -1858,7 +2326,8 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
/**
* @brief Initializes the CRYP peripheral in DES CBC encryption mode.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -1877,7 +2346,7 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
CRYP_SetDESCBCMode(hcryp, 0);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -1897,7 +2366,8 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
/**
* @brief Initializes the CRYP peripheral in DES ECB decryption mode.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -1916,7 +2386,7 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -1936,7 +2406,8 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
/**
* @brief Initializes the CRYP peripheral in DES ECB encryption mode using IT.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -1964,47 +2435,47 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetDESECBMode(hcryp, 0);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
/* Disable IT */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -2020,7 +2491,8 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in DES CBC encryption mode using interrupt.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2048,48 +2520,48 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetDESCBCMode(hcryp, 0);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
/* Disable IT */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -2105,7 +2577,8 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in DES ECB decryption mode using IT.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2133,47 +2606,47 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
/* Disable IT */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -2189,7 +2662,8 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in DES ECB decryption mode using interrupt.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2217,47 +2691,47 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
/* Disable IT */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -2273,7 +2747,8 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in DES ECB encryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2315,7 +2790,8 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in DES CBC encryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2357,13 +2833,14 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
{
uint32_t inputaddr;
uint32_t outputaddr;
@@ -2399,7 +2876,8 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2443,7 +2921,7 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
* @}
*/
-/** @defgroup CRYP_Group4 TDES processing functions
+/** @defgroup CRYP_Exported_Functions_Group4 TDES processing functions
* @brief processing functions.
*
@verbatim
@@ -2451,11 +2929,11 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
##### TDES processing functions #####
==============================================================================
[..] This section provides functions allowing to:
- (+) Encrypt plaintext using TDES using ECB or CBC chaining modes
- (+) Decrypt cyphertext using TDES using ECB or CBC chaining modes
+ (+) Encrypt plaintext using TDES based on ECB or CBC chaining modes
+ (+) Decrypt cyphertext using TDES based on ECB or CBC chaining modes
[..] Three processing functions are available:
- (+) polling mode
- (+) interrupt mode
+ (+) Polling mode
+ (+) Interrupt mode
(+) DMA mode
@endverbatim
@@ -2465,7 +2943,8 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in TDES ECB encryption mode
* then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2484,7 +2963,7 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
CRYP_SetTDESECBMode(hcryp, 0);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -2505,7 +2984,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
/**
* @brief Initializes the CRYP peripheral in TDES ECB decryption mode
* then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2524,7 +3004,7 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Cypher Data and Get Plain Data */
if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
@@ -2545,7 +3025,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
/**
* @brief Initializes the CRYP peripheral in TDES CBC encryption mode
* then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2564,7 +3045,7 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
CRYP_SetTDESCBCMode(hcryp, 0);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -2585,7 +3066,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
/**
* @brief Initializes the CRYP peripheral in TDES CBC decryption mode
* then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pPlainData: Pointer to the plaintext buffer
@@ -2604,7 +3086,7 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Cypher Data and Get Plain Data */
if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
@@ -2624,7 +3106,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
/**
* @brief Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2652,47 +3135,47 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetTDESECBMode(hcryp, 0);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
/* Disable IT */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -2708,7 +3191,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in TDES CBC encryption mode.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2736,46 +3220,46 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetTDESCBCMode(hcryp, 0);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -2791,7 +3275,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in TDES ECB decryption mode.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2819,46 +3304,46 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -2874,7 +3359,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in TDES CBC decryption mode.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pPlainData: Pointer to the plaintext buffer
@@ -2902,46 +3388,46 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -2957,7 +3443,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/**
* @brief Initializes the CRYP peripheral in TDES ECB encryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2999,7 +3486,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_
/**
* @brief Initializes the CRYP peripheral in TDES CBC encryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -3041,7 +3529,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_
/**
* @brief Initializes the CRYP peripheral in TDES ECB decryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -3083,7 +3572,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_
/**
* @brief Initializes the CRYP peripheral in TDES CBC decryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pPlainData: Pointer to the plaintext buffer
@@ -3127,7 +3617,7 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_
* @}
*/
-/** @defgroup CRYP_Group5 DMA callback functions
+/** @defgroup CRYP_Exported_Functions_Group5 DMA callback functions
* @brief DMA callback functions.
*
@verbatim
@@ -3145,7 +3635,8 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_
/**
* @brief Input FIFO transfer completed callbacks.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @retval None
*/
__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
@@ -3157,7 +3648,8 @@ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
/**
* @brief Output FIFO transfer completed callbacks.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @retval None
*/
__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
@@ -3169,7 +3661,8 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
/**
* @brief CRYP error callbacks.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @retval None
*/
__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
@@ -3183,7 +3676,7 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
* @}
*/
-/** @defgroup CRYP_Group6 CRYP IRQ handler management
+/** @defgroup CRYP_Exported_Functions_Group6 CRYP IRQ handler management
* @brief CRYP IRQ handler.
*
@verbatim
@@ -3198,7 +3691,8 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
/**
* @brief This function handles CRYP interrupt request.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @retval None
*/
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
@@ -3270,7 +3764,7 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
* @}
*/
-/** @defgroup CRYP_Group7 Peripheral State functions
+/** @defgroup CRYP_Exported_Functions_Group7 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
@@ -3286,7 +3780,8 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
/**
* @brief Returns the CRYP state.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @retval HAL state
*/
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
@@ -3298,415 +3793,6 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
* @}
*/
-/**
- * @brief DMA CRYP Input Data process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
- in the DMACR register */
- CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
-
- /* Call input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
-}
-
-/**
- * @brief DMA CRYP Output Data process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit
- in the DMACR register */
- CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
-
- /* Disable CRYP */
- __HAL_CRYP_DISABLE();
-
- /* Change the CRYP state to ready */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Call output data transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
-}
-
-/**
- * @brief DMA CRYP communication error callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- hcryp->State= HAL_CRYP_STATE_READY;
- HAL_CRYP_ErrorCallback(hcryp);
-}
-
-/**
- * @brief Writes the Key in Key registers.
- * @param hcryp: CRYP handle
- * @param Key: Pointer to Key buffer
- * @param KeySize: Size of Key
- * @retval None
- */
-static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
-{
- uint32_t keyaddr = (uint32_t)Key;
-
- switch(KeySize)
- {
- case CRYP_KEYSIZE_256B:
- /* Key Initialisation */
- CRYP->K0LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K0RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- case CRYP_KEYSIZE_192B:
- CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- case CRYP_KEYSIZE_128B:
- CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Writes the InitVector/InitCounter in IV registers.
- * @param hcryp: CRYP handle
- * @param InitVector: Pointer to InitVector/InitCounter buffer
- * @param IVSize: Size of the InitVector/InitCounter
- * @retval None
- */
-static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize)
-{
- uint32_t ivaddr = (uint32_t)InitVector;
-
- switch(IVSize)
- {
- case CRYP_KEYSIZE_128B:
- CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- CRYP->IV1LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- CRYP->IV1RR = __REV(*(uint32_t*)(ivaddr));
- break;
- /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */
- case CRYP_KEYSIZE_192B:
- CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
- break;
- case CRYP_KEYSIZE_256B:
- CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Process Data: Writes Input data in polling mode and read the output data
- * @param hcryp: CRYP handle
- * @param Input: Pointer to the Input buffer
- * @param Ilength: Length of the Input buffer, must be a multiple of 16.
- * @param Output: Pointer to the returned buffer
- * @retval None
- */
-static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
-{
- uint32_t timeout = 0;
-
- uint32_t i = 0;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
-
- for(i=0; (i < Ilength); i+=16)
- {
- /* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
-
- /* Get timeout */
- timeout = HAL_GetTick() + Timeout;
-
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if(HAL_GetTick() >= timeout)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Process Data: Write Input data in polling mode.
- * @param hcryp: CRYP handle
- * @param Input: Pointer to the Input buffer
- * @param Ilength: Length of the Input buffer, must be a multiple of 8
- * @param Output: Pointer to the returned buffer
- * @param Timeout: Specify Timeout value
- * @retval None
- */
-static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
-{
- uint32_t timeout = 0;
-
- uint32_t i = 0;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
-
- for(i=0; (i < Ilength); i+=8)
- {
- /* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
-
- /* Get timeout */
- timeout = HAL_GetTick() + Timeout;
-
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if(HAL_GetTick() >= timeout)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
- outputaddr+=4;
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Set the DMA configuration and start the DMA transfer
- * @param hcryp: CRYP handle
- * @param inputaddr: address of the Input buffer
- * @param Size: Size of the Input buffer, must be a multiple of 16.
- * @param outputaddr: address of the Output buffer
- * @retval None
- */
-static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
-{
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
- /* Set the DMA error callback */
- hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
-
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
- /* Set the DMA error callback */
- hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE();
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&CRYP->DR, Size/4);
-
- /* Enable In DMA request */
- CRYP->DMACR = (CRYP_DMACR_DIEN);
-
- /* Enable the DMA Out DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&CRYP->DOUT, outputaddr, Size/4);
-
- /* Enable Out DMA request */
- CRYP->DMACR |= CRYP_DMACR_DOEN;
-
-}
-
-/**
- * @brief Sets the CRYP peripheral in DES ECB mode.
- * @param hcryp: CRYP handle
- * @param Direction: Encryption or decryption
- * @retval None
- */
-static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
-{
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_DES_ECB | Direction);
-
- /* Set the key */
- CRYP->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
- CRYP->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-}
-
-/**
- * @brief Sets the CRYP peripheral in DES CBC mode.
- * @param hcryp: CRYP handle
- * @param Direction: Encryption or decryption
- * @retval None
- */
-static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
-{
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_DES_CBC | Direction);
-
- /* Set the key */
- CRYP->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
- CRYP->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
-
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-}
-
-/**
- * @brief Sets the CRYP peripheral in TDES ECB mode.
- * @param hcryp: CRYP handle
- * @param Direction: Encryption or decryption
- * @retval None
- */
-static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
-{
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_TDES_ECB | Direction);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-}
-
-/**
- * @brief Sets the CRYP peripheral in TDES CBC mode
- * @param hcryp: CRYP handle
- * @param Direction: Encryption or decryption
- * @retval None
- */
-static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
-{
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the CRYP peripheral in AES CBC mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_TDES_CBC | Direction);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
-
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-}
/**
* @}
diff --git a/f2/src/stm32f2xx_hal_dac.c b/f2/src/stm32f2xx_hal_dac.c
index c033efbd863f5f69c087bee8e80ba1f33cfa8843..309f6bd607f740226d4d0e3a052177b498b48678 100755
--- a/f2/src/stm32f2xx_hal_dac.c
+++ b/f2/src/stm32f2xx_hal_dac.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_dac.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
@@ -29,17 +29,17 @@
*** DAC Triggers ***
====================
[..]
- Digital to Analog conversion can be non-triggered using DAC_Trigger_None
+ Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
[..]
Digital to Analog conversion can be triggered by:
- (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
+ (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9.
The used pin (GPIOx_Pin9) must be configured in input mode.
(#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
- (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
+ (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
- (#) Software using DAC_Trigger_Software
+ (#) Software using DAC_TRIGGER_SOFTWARE
*** DAC Buffer mode feature ***
===============================
@@ -48,7 +48,7 @@
reduce the output impedance, and to drive external loads directly
without having to add an external operational amplifier.
To enable, the output buffer use
- sConfig.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+ sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
[..]
(@) Refer to the device datasheet for more details about output
impedance value with and without output buffer.
@@ -109,14 +109,14 @@
=================================
[..]
(+) Start the DAC peripheral using HAL_DAC_Start()
- (+) To read the DAC last data output value value, use the HAL_DAC_GetValue() function.
+ (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
(+) Stop the DAC peripheral using HAL_DAC_Stop()
*** DMA mode IO operation ***
==============================
[..]
(+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
- of data to be transfered at each end of conversion
+ of data to be transferred at each end of conversion
(+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
function is executed and user can add his own code by customization of function pointer
HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
@@ -141,7 +141,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -176,7 +176,7 @@
* @{
*/
-/** @defgroup DAC
+/** @defgroup DAC DAC
* @brief DAC driver modules
* @{
*/
@@ -187,18 +187,23 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/** @addtogroup DAC_Private_Functions
+ * @{
+ */
/* Private function prototypes -----------------------------------------------*/
static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DAC_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DAC_Exported_Functions DAC Exported Functions
* @{
*/
-/** @defgroup DAC_Group1 Initialization and de-initialization functions
+/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -232,6 +237,8 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
if(hdac->State == HAL_DAC_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hdac->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_DAC_MspInit(hdac);
}
@@ -315,7 +322,7 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
* @}
*/
-/** @defgroup DAC_Group2 IO operation functions
+/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
@@ -356,7 +363,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
- /* Enable the Peripharal */
+ /* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, Channel);
if(Channel == DAC_CHANNEL_1)
@@ -409,7 +416,7 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, Channel);
-
+
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -429,9 +436,9 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
* @param Length: The length of data to be transferred from memory to DAC peripheral
* @param Alignment: Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
@@ -447,27 +454,18 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Set the DMA transfer complete callback for channel1 */
- hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
-
- /* Set the DMA half transfer complete callback for channel1 */
- hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
-
- /* Set the DMA error callback for channel1 */
- hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
-
- /* Set the DMA transfer complete callback for channel2 */
- hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
-
- /* Set the DMA half transfer complete callback for channel2 */
- hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
-
- /* Set the DMA error callback for channel2 */
- hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
-
+
if(Channel == DAC_CHANNEL_1)
{
+ /* Set the DMA transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+
+ /* Set the DMA half transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+
+ /* Set the DMA error callback for channel1 */
+ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+
/* Enable the selected DAC channel1 DMA request */
hdac->Instance->CR |= DAC_CR_DMAEN1;
@@ -492,9 +490,18 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
}
else
{
+ /* Set the DMA transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
+
+ /* Set the DMA half transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
+
+ /* Set the DMA error callback for channel2 */
+ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
+
/* Enable the selected DAC channel2 DMA request */
hdac->Instance->CR |= DAC_CR_DMAEN2;
-
+
/* Case of use of channel 2 */
switch(Alignment)
{
@@ -533,7 +540,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
}
- /* Enable the Peripharal */
+ /* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, Channel);
/* Process Unlocked */
@@ -555,20 +562,42 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
*/
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
/* Disable the selected DAC channel DMA request */
- hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
+ hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
- /* Disable the Peripharal */
+ /* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, Channel);
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
+ /* Disable the DMA Channel */
+ /* Channel1 is used */
+ if(Channel == DAC_CHANNEL_1)
+ {
+ status = HAL_DMA_Abort(hdac->DMA_Handle1);
+ }
+ else /* Channel2 is used for */
+ {
+ status = HAL_DMA_Abort(hdac->DMA_Handle2);
+ }
+
+ /* Check if DMA Channel effectively disabled */
+ if(status != HAL_OK)
+ {
+ /* Update DAC state machine to error */
+ hdac->State = HAL_DAC_STATE_ERROR;
+ }
+ else
+ {
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+ }
+
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -605,13 +634,13 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
*/
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
{
- /* Check Overrun flag */
+ /* Check underrun channel 1 flag */
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
- /* Set DAC error code to chanel1 DMA underrun error */
+ /* Set DAC error code to channel1 DMA underrun error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
/* Clear the underrun flag */
@@ -623,7 +652,8 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
/* Error callback */
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
}
- else
+ /* Check underrun channel 2 flag */
+ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
@@ -677,7 +707,7 @@ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DAC_ErrorCallback could be implemented in the user file
+ the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
*/
}
@@ -698,7 +728,7 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
* @}
*/
-/** @defgroup DAC_Group3 Peripheral Control functions
+/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
@@ -731,7 +761,6 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
- assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_CHANNEL(Channel));
/* Process locked */
@@ -741,7 +770,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf
hdac->State = HAL_DAC_STATE_BUSY;
/* Get the DAC CR value */
- tmpreg1 = DAC->CR;
+ tmpreg1 = hdac->Instance->CR;
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
/* Configure for the selected DAC channel: buffer output, trigger */
@@ -751,9 +780,9 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << Channel;
/* Write to DAC CR */
- DAC->CR = tmpreg1;
+ hdac->Instance->CR = tmpreg1;
/* Disable wave generation */
- DAC->CR &= ~(DAC_CR_WAVE1 << Channel);
+ hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -775,9 +804,9 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param Alignment: Specifies the data alignment.
* This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @param Data: Data to be loaded in the selected data holding register.
* @retval HAL status
*/
@@ -793,11 +822,11 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui
tmp = (uint32_t)hdac->Instance;
if(Channel == DAC_CHANNEL_1)
{
- tmp += __HAL_DHR12R1_ALIGNEMENT(Alignment);
+ tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
}
else
{
- tmp += __HAL_DHR12R2_ALIGNEMENT(Alignment);
+ tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
}
/* Set the DAC channel1 selected data holding register */
@@ -811,7 +840,7 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui
* @}
*/
-/** @defgroup DAC_Group4 Peripheral State and Errors functions
+/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
* @brief Peripheral State and Errors functions
*
@verbatim
@@ -857,7 +886,8 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
/**
* @brief DMA conversion complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
@@ -871,7 +901,8 @@ static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
/**
* @brief DMA half transfer complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
@@ -883,7 +914,8 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
/**
* @brief DMA error callback
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
diff --git a/f2/src/stm32f2xx_hal_dac_ex.c b/f2/src/stm32f2xx_hal_dac_ex.c
index a58df5f7b4035f4e7911f3331724d0aada40c0d0..d3498f91ee15e3d9f3f03829af96c628d03540f7 100755
--- a/f2/src/stm32f2xx_hal_dac_ex.c
+++ b/f2/src/stm32f2xx_hal_dac_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_dac_ex.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DAC extension peripheral:
@@ -25,7 +25,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -60,7 +60,7 @@
* @{
*/
-/** @defgroup DACEx
+/** @defgroup DACEx DACEx
* @brief DAC driver modules
* @{
*/
@@ -73,12 +73,12 @@
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DACEx_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DACEx_Exported_Functions DAC Exported Functions
* @{
*/
-/** @defgroup DACEx_Group1 Extended features functions
+/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
*
@verbatim
@@ -121,8 +121,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
* the configuration information for the specified DAC.
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * DAC_CHANNEL_1 / DAC_CHANNEL_2
* @param Amplitude: Select max triangle amplitude.
* This parameter can be one of the following values:
* @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
@@ -152,7 +151,7 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the selected wave generation for the selected DAC channel */
- hdac->Instance->CR |= (DAC_WAVE_TRIANGLE | Amplitude) << Channel;
+ MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -170,8 +169,7 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32
* the configuration information for the specified DAC.
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * DAC_CHANNEL_1 / DAC_CHANNEL_2
* @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
* This parameter can be one of the following values:
* @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
@@ -201,7 +199,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the selected wave generation for the selected DAC channel */
- hdac->Instance->CR |= (DAC_WAVE_NOISE | Amplitude) << Channel;
+ MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -219,9 +217,9 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t
* the configuration information for the specified DAC.
* @param Alignment: Specifies the data alignment for dual channel DAC.
* This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
+ * DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * DAC_ALIGN_12B_R: 12bit right data alignment selected
* @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
* @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register.
* @note In dual mode, a unique register access is required to write in both
@@ -248,7 +246,7 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align
}
tmp = (uint32_t)hdac->Instance;
- tmp += __HAL_DHR12RD_ALIGNEMENT(Alignment);
+ tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
/* Set the dual DAC selected data holding register */
*(__IO uint32_t *)tmp = data;
@@ -315,7 +313,8 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
/**
* @brief DMA conversion complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
@@ -329,7 +328,8 @@ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
/**
* @brief DMA half transfer complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
@@ -341,7 +341,8 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
/**
* @brief DMA error callback
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
diff --git a/f2/src/stm32f2xx_hal_dcmi.c b/f2/src/stm32f2xx_hal_dcmi.c
index c484a709246f5c72763d08872b9dcfc23c76eccd..43e0f4ab4d5800090671bc36129eef172e4efabf 100755
--- a/f2/src/stm32f2xx_hal_dcmi.c
+++ b/f2/src/stm32f2xx_hal_dcmi.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_dcmi.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief DCMI HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the Digital Camera Interface (DCMI) peripheral:
@@ -39,9 +39,9 @@
window from the received image using HAL_DCMI_ConfigCrop()
and HAL_DCMI_EnableCROP() functions
- (#) The capture can be stopped using the following HAL_DCMI_Stop() function.
+ (#) The capture can be stopped using HAL_DCMI_Stop() function.
- (#) To control DCMI state you can use the following function : HAL_DCMI_GetState()
+ (#) To control DCMI state you can use the function HAL_DCMI_GetState().
*** DCMI HAL driver macros list ***
=============================================
@@ -63,7 +63,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -96,7 +96,7 @@
/** @addtogroup STM32F2xx_HAL_Driver
* @{
*/
-/** @defgroup DCMI
+/** @defgroup DCMI DCMI
* @brief DCMI HAL module driver
* @{
*/
@@ -113,15 +113,15 @@
static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma);
static void DCMI_DMAError(DMA_HandleTypeDef *hdma);
-/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
-/** @defgroup DCMI_Private_Functions
+/** @defgroup DCMI_Exported_Functions DCMI Exported Functions
* @{
*/
-/** @defgroup DCMI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
+/** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
@@ -161,13 +161,14 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
if(hdcmi->State == HAL_DCMI_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hdcmi->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_DCMI_MspInit(hdcmi);
}
/* Change the DCMI state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
-
/* Configures the HS, VS, DE and PC polarity */
hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |
DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |
@@ -183,6 +184,7 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << 8)|
((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << 16) |
((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << 24));
+
}
/* Enable the Line interrupt */
@@ -217,9 +219,8 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
* values.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
- * @retval None
+ * @retval HAL status
*/
-
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
{
/* DeInit the low level hardware */
@@ -266,9 +267,9 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
/**
* @}
*/
-/** @defgroup DCMI_Group2 IO operation functions
- * @brief IO operation functions
- *
+/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -290,11 +291,11 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
* @param DCMI_Mode: DCMI capture mode snapshot or continuous grab.
* @param pData: The destination memory Buffer address (LCD Frame buffer).
* @param Length: The length of capture to be transferred.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
{
- /* Initialise the second memory address */
+ /* Initialize the second memory address */
uint32_t SecondMemAddress = 0;
/* Check function parameters */
@@ -329,7 +330,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
/* Set the DMA memory1 conversion complete callback */
hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAConvCplt;
- /* Initialise transfer parameters */
+ /* Initialize transfer parameters */
hdcmi->XferCount = 1;
hdcmi->XferSize = Length;
hdcmi->pBuffPtr = pData;
@@ -363,10 +364,11 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
* @brief Disable DCMI DMA request and Disable DCMI capture
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
{
- uint32_t timeout = 0x00;
+ uint32_t tickstart = 0;
/* Lock the DCMI peripheral state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
@@ -376,13 +378,13 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
/* Disable Capture */
DCMI->CR &= ~(DCMI_CR_CAPTURE);
- /* Get timeout */
- timeout = HAL_GetTick() + HAL_TIMEOUT_DCMI_STOP;
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Check if the DCMI capture effectively disabled */
while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DCMI_STOP)
{
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
@@ -417,7 +419,7 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
* @brief Handles DCMI interrupt request.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for the DCMI.
- * @retval HAL status
+ * @retval None
*/
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
{
@@ -584,16 +586,16 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
* @}
*/
-/** @defgroup DCMI_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
+/** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the CROP feature.
- (+) ENABLE/DISABLE the CROP feature.
+ (+) Enable/Disable the CROP feature.
@endverbatim
* @{
@@ -603,10 +605,10 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
* @brief Configure the DCMI CROP coordinate.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
- * @param YSize: DCMI Line number
- * @param XSize: DCMI Pixel per line
* @param X0: DCMI window X offset
* @param Y0: DCMI window Y offset
+ * @param XSize: DCMI Pixel per line
+ * @param YSize: DCMI Line number
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
@@ -619,9 +621,9 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui
/* Check the parameters */
assert_param(IS_DCMI_WINDOW_COORDINATE(X0));
- assert_param(IS_DCMI_WINDOW_COORDINATE(Y0));
+ assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
- assert_param(IS_DCMI_WINDOW_HEIGHT(YSize));
+ assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));
/* Configure CROP */
DCMI->CWSIZER = (XSize | (YSize << 16));
@@ -640,7 +642,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui
* @brief Disable the Crop feature.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi)
{
@@ -666,7 +668,7 @@ HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi)
* @brief Enable the Crop feature.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)
{
@@ -692,9 +694,9 @@ HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)
* @}
*/
-/** @defgroup DCMI_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
+/** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
@@ -720,11 +722,11 @@ HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
}
/**
-* @brief Return the DCMI error code
-* @param hdcmi : pointer to a DCMI_HandleTypeDef structure that contains
+ * @brief Return the DCMI error code
+ * @param hdcmi : pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
-* @retval DCMI Error Code
-*/
+ * @retval DCMI Error Code
+ */
uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
{
return hdcmi->ErrorCode;
@@ -733,10 +735,15 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
/**
* @}
*/
-
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DCMI_Private_Functions DCMI Private Functions
+ * @{
+ */
+
/**
* @brief DMA conversion complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma)
@@ -789,7 +796,8 @@ static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA error callback
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
@@ -798,6 +806,9 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
hdcmi->State= HAL_DCMI_STATE_READY;
HAL_DCMI_ErrorCallback(hdcmi);
}
+/**
+ * @}
+ */
/**
* @}
diff --git a/f2/src/stm32f2xx_hal_dma.c b/f2/src/stm32f2xx_hal_dma.c
index cb86e88f04843f40fac4adc62a18526d3fe15588..475f51fe5dd440148f9c6532ebb4d77b8cab1da8 100755
--- a/f2/src/stm32f2xx_hal_dma.c
+++ b/f2/src/stm32f2xx_hal_dma.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_dma.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -47,7 +47,7 @@
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
add his own function by customization of function pointer XferCpltCallback and
XferErrorCallback (i.e a member of DMA handle structure).
-
+ [..]
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
detection.
@@ -86,7 +86,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -120,30 +120,50 @@
* @{
*/
-/** @defgroup DMA
+/** @defgroup DMA DMA
* @brief DMA HAL module driver
* @{
*/
#ifdef HAL_DMA_MODULE_ENABLED
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+/* Private types -------------------------------------------------------------*/
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register */
+ __IO uint32_t Reserved0;
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
+} DMA_Base_Registers;
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Constants
+ * @{
+ */
+ #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Functions
+ * @{
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
-/** @defgroup DMA_Private_Functions
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Functions
* @{
*/
-/** @defgroup DMA_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
- *
+/** @addtogroup DMA_Exported_Functions_Group1
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -168,9 +188,9 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
-{
+{
uint32_t tmp = 0;
-
+
/* Check the DMA peripheral state */
if(hdma == NULL)
{
@@ -203,11 +223,11 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
/* Get the CR register value */
tmp = hdma->Instance->CR;
- /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and CT bits */
+ /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
- DMA_SxCR_DIR | DMA_SxCR_CT ));
+ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
/* Prepare the DMA Stream configuration */
tmp |= hdma->Init.Channel | hdma->Init.Direction |
@@ -244,7 +264,11 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
/* Write to DMA Stream FCR */
hdma->Instance->FCR = tmp;
- /* Initialise the error code */
+ /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+ DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+ DMA_CalcBaseAndBitshift(hdma);
+
+ /* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Initialize the DMA state */
@@ -261,6 +285,14 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
*/
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
{
+ DMA_Base_Registers *regs;
+
+ /* Check the DMA peripheral state */
+ if(hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the DMA peripheral state */
if(hdma->State == HAL_DMA_STATE_BUSY)
{
@@ -281,21 +313,20 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
/* Reset DMA Streamx memory 0 address register */
hdma->Instance->M0AR = 0;
-
+
/* Reset DMA Streamx memory 1 address register */
hdma->Instance->M1AR = 0;
-
+
/* Reset DMA Streamx FIFO control register */
hdma->Instance->FCR = (uint32_t)0x00000021;
+
+ /* Get DMA steam Base Address */
+ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+ /* Clear all interrupt flags at correct offset within the register */
+ regs->IFCR = 0x3F << hdma->StreamIndex;
- /* Clear all flags */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
- /* Initialise the error code */
+ /* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Initialize the DMA state */
@@ -311,9 +342,8 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
* @}
*/
-/** @defgroup DMA_Group2 I/O operation functions
- * @brief I/O operation functions
- *
+/** @addtogroup DMA_Exported_Functions_Group2
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -388,20 +418,9 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
/* Configure the source, destination address and the data length */
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
- /* Enable the transfer complete interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
-
- /* Enable the Half transfer complete interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
-
- /* Enable the transfer Error interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
-
- /* Enable the FIFO Error interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE);
-
- /* Enable the direct mode Error interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME);
+ /* Enable all interrupts */
+ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME;
+ hdma->Instance->FCR |= DMA_IT_FE;
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
@@ -423,19 +442,19 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
- uint32_t timeout = 0x00;
+ uint32_t tickstart = 0;
/* Disable the stream */
__HAL_DMA_DISABLE(hdma);
- /* Get timeout */
- timeout = HAL_GetTick() + HAL_TIMEOUT_DMA_ABORT;
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Check if the DMA Stream is effectively disabled */
while((hdma->Instance->CR & DMA_SxCR_EN) != 0)
{
/* Check for the Timeout */
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
{
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
@@ -469,77 +488,94 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
{
uint32_t temp, tmp, tmp1, tmp2;
- uint32_t timeout = 0x00;
+ uint32_t tickstart = 0;
+
+ /* calculate DMA base and stream number */
+ DMA_Base_Registers *regs;
+
+ regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
/* Get the level transfer complete flag */
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
{
/* Transfer Complete flag */
- temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
+ temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
}
else
{
/* Half Transfer Complete flag */
- temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
+ temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
}
- /* Get timeout */
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
- while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
+ while((regs->ISR & temp) == RESET)
{
- tmp = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
- tmp1 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
- tmp2 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ tmp = regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex);
+ tmp1 = regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex);
+ tmp2 = regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex);
if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET))
{
- /* Clear the transfer error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
- /* Clear the FIFO error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
- /* Clear the DIrect Mode error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ if(tmp != RESET)
+ {
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+
+ /* Clear the transfer error flag */
+ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
+ }
+ if(tmp1 != RESET)
+ {
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+
+ /* Clear the FIFO error flag */
+ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
+ }
+ if(tmp2 != RESET)
+ {
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+ /* Clear the Direct Mode error flag */
+ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
+ }
/* Change the DMA state */
hdma->State= HAL_DMA_STATE_ERROR;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
- }
+ }
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
return HAL_TIMEOUT;
}
}
}
- /* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
{
+ /* Clear the half transfer and transfer complete flags */
+ regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
+
/* Multi_Buffering mode enabled */
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
{
- /* Clear the transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-
/* Current memory buffer used is Memory 0 */
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
{
@@ -555,9 +591,6 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
}
else
{
- /* Clear the transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-
/* The selected Streamx EN bit is cleared (DMA is disabled and all transfers
are complete) */
hdma->State = HAL_DMA_STATE_READY_MEM0;
@@ -566,13 +599,13 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
__HAL_UNLOCK(hdma);
}
else
- {
+ {
+ /* Clear the half transfer complete flag */
+ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+
/* Multi_Buffering mode enabled */
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
{
- /* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
/* Current memory buffer used is Memory 0 */
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
{
@@ -588,9 +621,6 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
}
else
{
- /* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
}
@@ -606,8 +636,13 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
+ /* calculate DMA base and stream number */
+ DMA_Base_Registers *regs;
+
+ regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+
/* Transfer Error Interrupt management ***************************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
+ if ((regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
{
@@ -615,7 +650,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
/* Clear the transfer error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_TE;
@@ -624,7 +659,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
hdma->State = HAL_DMA_STATE_ERROR;
/* Process Unlocked */
- __HAL_UNLOCK(hdma);
+ __HAL_UNLOCK(hdma);
if(hdma->XferErrorCallback != NULL)
{
@@ -634,7 +669,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
}
}
/* FIFO Error Interrupt management ******************************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)) != RESET)
+ if ((regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
{
@@ -642,7 +677,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE);
/* Clear the FIFO error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_FE;
@@ -661,7 +696,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
}
}
/* Direct Mode Error Interrupt management ***********************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)) != RESET)
+ if ((regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
{
@@ -669,7 +704,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME);
/* Clear the direct mode error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_DME;
@@ -688,15 +723,15 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
}
}
/* Half Transfer Complete Interrupt management ******************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
+ if ((regs->ISR & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
- {
+ {
/* Multi_Buffering mode enabled */
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
{
/* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
/* Current memory buffer used is Memory 0 */
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
@@ -720,7 +755,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
}
/* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
@@ -734,14 +769,14 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
}
}
/* Transfer Complete Interrupt management ***********************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
+ if ((regs->ISR & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
{
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
{
/* Clear the transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
/* Current memory buffer used is Memory 1 */
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
@@ -753,7 +788,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
}
}
/* Current memory buffer used is Memory 0 */
- else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
+ else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
{
if(hdma->XferCpltCallback != NULL)
{
@@ -771,7 +806,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
}
/* Clear the transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
@@ -780,7 +815,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
hdma->State = HAL_DMA_STATE_READY_MEM0;
/* Process Unlocked */
- __HAL_UNLOCK(hdma);
+ __HAL_UNLOCK(hdma);
if(hdma->XferCpltCallback != NULL)
{
@@ -796,9 +831,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
* @}
*/
-/** @defgroup DMA_Group3 Peripheral State functions
- * @brief Peripheral State functions
- *
+/** @addtogroup DMA_Exported_Functions_Group3
+ *
@verbatim
===============================================================================
##### State and Errors functions #####
@@ -838,6 +872,14 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
* @}
*/
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Functions
+ * @{
+ */
+
/**
* @brief Sets the DMA Transfer parameter.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
@@ -849,6 +891,9 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
+ /* Clear DBM bit */
+ hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
+
/* Configure DMA Stream data length */
hdma->Instance->NDTR = DataLength;
@@ -873,9 +918,36 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
}
/**
- * @}
+ * @brief Returns the DMA Stream base address depending on stream number
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval Stream base address
*/
-
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
+{
+ uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFF) - 16) / 24;
+
+ /* lookup table for necessary bitshift of flags within status registers */
+ static const uint8_t flagBitshiftOffset[8] = {0, 6, 16, 22, 0, 6, 16, 22};
+ hdma->StreamIndex = flagBitshiftOffset[stream_number];
+
+ if (stream_number > 3)
+ {
+ /* return pointer to HISR and HIFCR */
+ hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FF)) + 4);
+ }
+ else
+ {
+ /* return pointer to LISR and LIFCR */
+ hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FF));
+ }
+
+ return hdma->StreamBaseAddress;
+}
+/**
+ * @}
+ */
+
#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
diff --git a/f2/src/stm32f2xx_hal_dma_ex.c b/f2/src/stm32f2xx_hal_dma_ex.c
index 57e8df18e6ccf6417e7358b215d3111015f52776..1ec8dda408ee197879396aec61ac2e3ee3744460 100755
--- a/f2/src/stm32f2xx_hal_dma_ex.c
+++ b/f2/src/stm32f2xx_hal_dma_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_dma_ex.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the DMA Extension peripheral:
@@ -21,13 +21,13 @@
-@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
-@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
-@- In Multi (Double) buffer mode, it is possible to update the base address for
- the AHB memory port on-the-fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
+ the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -61,30 +61,34 @@
* @{
*/
-/** @defgroup DMAEx
+/** @defgroup DMAEx DMAEx
* @brief DMA Extended HAL module driver
* @{
*/
#ifdef HAL_DMA_MODULE_ENABLED
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
+/* Private Constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMAEx_Private_Functions
+ * @{
+ */
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+/**
+ * @}
+ */
-/* Private functions ---------------------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
-/** @defgroup DMAEx_Private_Functions
+/** @addtogroup DMAEx_Exported_Functions
* @{
*/
-
-/** @defgroup DMAEx_Group1 Extended features functions
- * @brief Extended features functions
- *
+/** @addtogroup DMAEx_Exported_Functions_Group1
+ *
@verbatim
===============================================================================
##### Extended features functions #####
@@ -100,11 +104,10 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres
* @{
*/
-
/**
* @brief Starts the multi_buffer DMA Transfer.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
@@ -150,8 +153,8 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t S
/**
* @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
@@ -212,13 +215,13 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_
/**
* @brief Change the memory0 or memory1 address on the fly.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @param Address: The new address
- * @param memory: the memory to be changed, This parameter can be one of
- * the following values:
- * @arg MEMORY0
- * @arg MEMORY1
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param Address: The new address
+ * @param memory: the memory to be changed, This parameter can be one of
+ * the following values:
+ * MEMORY0 /
+ * MEMORY1
* @note The MEMORY0 address can be changed only when the current transfer use
* MEMORY1 and the MEMORY1 address can be changed only when the current
* transfer use MEMORY0.
@@ -244,10 +247,18 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre
* @}
*/
+/**
+ * @}
+ */
+
+/** @addtogroup DMAEx_Private_Functions
+ * @{
+ */
+
/**
* @brief Set the DMA Transfer parameter.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
diff --git a/f2/src/stm32f2xx_hal_eth.c b/f2/src/stm32f2xx_hal_eth.c
index 47fae8a41d8d474f9deedd636c7ff6482f4761fe..b3cc972efdacc47d055943958c03bb33e3df6249 100755
--- a/f2/src/stm32f2xx_hal_eth.c
+++ b/f2/src/stm32f2xx_hal_eth.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_eth.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief ETH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Ethernet (ETH) peripheral:
@@ -26,9 +26,9 @@
(#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
(##) Enable the Ethernet interface clock using
- (+++) __ETHMAC_CLK_ENABLE();
- (+++) __ETHMACTX_CLK_ENABLE();
- (+++) __ETHMACRX_CLK_ENABLE();
+ (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
+ (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
+ (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
(##) Initialize the related GPIO clocks
(##) Configure Ethernet pin-out
@@ -68,7 +68,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -102,7 +102,7 @@
* @{
*/
-/** @defgroup ETH
+/** @defgroup ETH ETH
* @brief ETH HAL module driver
* @{
*/
@@ -113,9 +113,21 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @defgroup ETH_Private_Constants ETH Private Constants
+ * @{
+ */
+#define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
+#define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */
+
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @defgroup ETH_Private_Functions ETH Private Functions
+ * @{
+ */
static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
@@ -128,14 +140,17 @@ static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
+/**
+ * @}
+ */
/* Private functions ---------------------------------------------------------*/
-/** @defgroup ETH_Private_Functions
+/** @defgroup ETH_Exported_Functions ETH Exported Functions
* @{
*/
-/** @defgroup ETH_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
@@ -152,14 +167,15 @@ static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
/**
* @brief Initializes the Ethernet MAC and DMA according to default
* parameters.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
{
- uint32_t tmpreg = 0, phyreg = 0;
+ uint32_t tmpreg1 = 0, phyreg = 0;
uint32_t hclk = 60000000;
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
uint32_t err = ETH_SUCCESS;
/* Check the ETH peripheral state */
@@ -176,12 +192,14 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
if(heth->State == HAL_ETH_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ heth->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC. */
HAL_ETH_MspInit(heth);
}
/* Enable SYSCFG Clock */
- __SYSCFG_CLK_ENABLE();
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
/* Select MII or RMII Mode*/
SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
@@ -199,9 +217,9 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
/*-------------------------------- MAC Initialization ----------------------*/
/* Get the ETHERNET MACMIIAR value */
- tmpreg = (heth->Instance)->MACMIIAR;
+ tmpreg1 = (heth->Instance)->MACMIIAR;
/* Clear CSR Clock Range CR[2:0] bits */
- tmpreg &= MACMIIAR_CR_MASK;
+ tmpreg1 &= ETH_MACMIIAR_CR_MASK;
/* Get hclk frequency value */
hclk = HAL_RCC_GetHCLKFreq();
@@ -210,26 +228,26 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
if((hclk >= 20000000)&&(hclk < 35000000))
{
/* CSR Clock Range between 20-35 MHz */
- tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16;
}
else if((hclk >= 35000000)&&(hclk < 60000000))
{
/* CSR Clock Range between 35-60 MHz */
- tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26;
}
else if((hclk >= 60000000)&&(hclk < 100000000))
{
/* CSR Clock Range between 60-100 MHz */
- tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42;
}
else /* ((hclk >= 100000000)&&(hclk < 120000000)) */
{
/* CSR Clock Range between 100-120 MHz */
- tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62;
}
/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
- (heth->Instance)->MACMIIAR = (uint32_t)tmpreg;
+ (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
/*-------------------- PHY initialization and configuration ----------------*/
/* Put the PHY in reset mode */
@@ -253,30 +271,32 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
{
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* We wait for linked status */
do
{
- timeout++;
HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
- } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS) && (timeout < PHY_READ_TO));
-
- if(timeout == PHY_READ_TO)
- {
- /* In case of write timeout */
- err = ETH_ERROR;
-
- /* Config MAC and DMA */
- ETH_MACDMAConfig(heth, err);
- /* Set the ETH peripheral state to READY */
- heth->State = HAL_ETH_STATE_READY;
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)
+ {
+ /* In case of write timeout */
+ err = ETH_ERROR;
- /* Return HAL_ERROR */
- return HAL_ERROR;
- }
+ /* Config MAC and DMA */
+ ETH_MACDMAConfig(heth, err);
+
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
- /* Reset Timeout counter */
- timeout = 0;
+ return HAL_TIMEOUT;
+ }
+ } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
+
/* Enable Auto-Negotiation */
if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
@@ -294,16 +314,37 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
return HAL_ERROR;
}
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait until the auto-negotiation will be completed */
do
{
- timeout++;
HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
- } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE) && (timeout < PHY_READ_TO));
+
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)
+ {
+ /* In case of write timeout */
+ err = ETH_ERROR;
+
+ /* Config MAC and DMA */
+ ETH_MACDMAConfig(heth, err);
+
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ return HAL_TIMEOUT;
+ }
+
+ } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
- if(timeout == PHY_READ_TO)
+ /* Read the result of the auto-negotiation */
+ if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
{
- /* In case of timeout */
+ /* In case of write timeout */
err = ETH_ERROR;
/* Config MAC and DMA */
@@ -313,15 +354,9 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
heth->State = HAL_ETH_STATE_READY;
/* Return HAL_ERROR */
- return HAL_ERROR;
+ return HAL_ERROR;
}
- /* Reset Timeout counter */
- timeout = 0;
-
- /* Read the result of the auto-negotiation */
- HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg);
-
/* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
{
@@ -384,7 +419,8 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
/**
* @brief De-Initializes the ETH peripheral.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
@@ -397,7 +433,7 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
/* Set ETH HAL state to Disabled */
heth->State= HAL_ETH_STATE_RESET;
-
+
/* Release Lock */
__HAL_UNLOCK(heth);
@@ -407,7 +443,8 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
/**
* @brief Initializes the DMA Tx descriptors in chain mode.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @param DMATxDescTab: Pointer to the first Tx desc list
* @param TxBuff: Pointer to the first TxBuffer list
* @param TxBuffCount: Number of the used Tx desc in the list
@@ -473,7 +510,8 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc
/**
* @brief Initializes the DMA Rx descriptors in chain mode.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @param DMARxDescTab: Pointer to the first Rx desc list
* @param RxBuff: Pointer to the first RxBuffer list
* @param RxBuffCount: Number of the used Rx desc in the list
@@ -542,7 +580,8 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc
/**
* @brief Initializes the ETH MSP.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
@@ -554,7 +593,8 @@ __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
/**
* @brief DeInitializes ETH MSP.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
@@ -568,7 +608,7 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
* @}
*/
-/** @defgroup ETH_Group2 IO operation functions
+/** @defgroup ETH_Exported_Functions_Group2 IO operation functions
* @brief Data transfers functions
*
@verbatim
@@ -583,7 +623,7 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
HAL_ETH_GetReceivedFrame_IT();
(+) Read from an External PHY register
HAL_ETH_ReadPHYRegister();
- (+) Writo to an External PHY register
+ (+) Write to an External PHY register
HAL_ETH_WritePHYRegister();
@endverbatim
@@ -593,7 +633,8 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
/**
* @brief Sends an Ethernet frame.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @param FrameLength: Amount of data to be sent
* @retval HAL status
*/
@@ -706,7 +747,8 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL
/**
* @brief Checks for received frames.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
@@ -779,12 +821,14 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
/* Process Unlocked */
__HAL_UNLOCK(heth);
+ /* Return function status */
return HAL_ERROR;
}
/**
* @brief Gets the Received frame in interrupt mode.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
@@ -863,12 +907,13 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
__HAL_UNLOCK(heth);
/* Return function status */
- return HAL_OK;
+ return HAL_ERROR;
}
/**
* @brief This function handles ETH interrupt request.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval HAL status
*/
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
@@ -927,7 +972,8 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
/**
* @brief Tx Transfer completed callbacks.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
@@ -939,7 +985,8 @@ __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
/**
* @brief Rx Transfer completed callbacks.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
@@ -951,7 +998,8 @@ __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
/**
* @brief Ethernet transfer error callbacks
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
@@ -963,20 +1011,20 @@ __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
/**
* @brief Reads a PHY register
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
* This parameter can be one of the following values:
- * @arg PHY_BCR: Transceiver Basic Control Register
- * @arg PHY_BSR: Transceiver Basic Status Register
- * @arg More PHY register could be read depending on the used PHY
+ * PHY_BCR: Transceiver Basic Control Register,
+ * PHY_BSR: Transceiver Basic Status Register.
+ * More PHY register could be read depending on the used PHY
* @param RegValue: PHY register value
- * @retval HAL_TIMEOUT: in case of timeout
- * MACMIIDR register value: Data read from the selected PHY register (correct read )
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
{
- uint32_t tmpreg = 0;
- uint32_t timeout = 0;
+ uint32_t tmpreg1 = 0;
+ uint32_t tickstart = 0;
/* Check parameters */
assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
@@ -990,34 +1038,38 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR
heth->State = HAL_ETH_STATE_BUSY_RD;
/* Get the ETHERNET MACMIIAR value */
- tmpreg = heth->Instance->MACMIIAR;
+ tmpreg1 = heth->Instance->MACMIIAR;
/* Keep only the CSR Clock Range CR[2:0] bits value */
- tmpreg &= ~MACMIIAR_CR_MASK;
+ tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
/* Prepare the MII address register value */
- tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
- tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
- tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
- tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
+ tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+ tmpreg1 |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
+ tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
+ tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
/* Write the result value into the MII Address register */
- heth->Instance->MACMIIAR = tmpreg;
+ heth->Instance->MACMIIAR = tmpreg1;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Check for the Busy flag */
- do
+ while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
{
- timeout++;
- tmpreg = heth->Instance->MACMIIAR;
- } while (((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) && (timeout < PHY_READ_TO));
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
+ {
+ heth->State= HAL_ETH_STATE_READY;
- /* Return ERROR in case of timeout */
- if(timeout == PHY_READ_TO)
- {
- /* Set ETH HAL State to READY */
- heth->State = HAL_ETH_STATE_READY;
- /* Return HAL_TIMEOUT */
- return HAL_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ return HAL_TIMEOUT;
+ }
+
+ tmpreg1 = heth->Instance->MACMIIAR;
}
/* Get MACMIIDR value */
@@ -1032,18 +1084,19 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR
/**
* @brief Writes to a PHY register.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
* This parameter can be one of the following values:
- * @arg PHY_BCR: Transceiver Control Register
- * @arg More PHY register could be written depending on the used PHY
+ * PHY_BCR: Transceiver Control Register.
+ * More PHY register could be written depending on the used PHY
* @param RegValue: the value to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
{
- uint32_t tmpreg = 0;
- uint32_t timeout = 0;
+ uint32_t tmpreg1 = 0;
+ uint32_t tickstart = 0;
/* Check parameters */
assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
@@ -1057,37 +1110,41 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY
heth->State = HAL_ETH_STATE_BUSY_WR;
/* Get the ETHERNET MACMIIAR value */
- tmpreg = heth->Instance->MACMIIAR;
+ tmpreg1 = heth->Instance->MACMIIAR;
/* Keep only the CSR Clock Range CR[2:0] bits value */
- tmpreg &= ~MACMIIAR_CR_MASK;
+ tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
/* Prepare the MII register address value */
- tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
- tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
- tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
- tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
+ tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+ tmpreg1 |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
+ tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */
+ tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
/* Give the value to the MII data register */
heth->Instance->MACMIIDR = (uint16_t)RegValue;
/* Write the result value into the MII Address register */
- heth->Instance->MACMIIAR = tmpreg;
+ heth->Instance->MACMIIAR = tmpreg1;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Check for the Busy flag */
- do
+ while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
{
- timeout++;
- tmpreg = heth->Instance->MACMIIAR;
- } while (((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) && (timeout < PHY_WRITE_TO));
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
+ {
+ heth->State= HAL_ETH_STATE_READY;
- /* Return TIMETOUT in case of timeout */
- if(timeout == PHY_WRITE_TO)
- {
- /* Set ETH HAL State to READY */
- heth->State = HAL_ETH_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+
+ tmpreg1 = heth->Instance->MACMIIAR;
}
/* Set ETH HAL State to READY */
@@ -1101,7 +1158,7 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY
* @}
*/
-/** @defgroup ETH_Group3 Peripheral Control functions
+/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
@@ -1124,7 +1181,8 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY
/**
* @brief Enables Ethernet MAC and DMA reception/transmission
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
@@ -1162,7 +1220,8 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
/**
* @brief Stop Ethernet MAC and DMA reception/transmission
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
@@ -1200,13 +1259,14 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
/**
* @brief Set ETH MAC Configuration.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @param macconf: MAC Configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0;
/* Process Locked */
__HAL_LOCK(heth);
@@ -1236,7 +1296,7 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
- assert_param(IS_ETH_PROMISCIOUS_MODE(macconf->PromiscuousMode));
+ assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
@@ -1250,11 +1310,11 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
/* Clear WD, PCE, PS, TE and RE bits */
- tmpreg &= MACCR_CLEAR_MASK;
+ tmpreg1 &= ETH_MACCR_CLEAR_MASK;
- tmpreg |= (uint32_t)(macconf->Watchdog |
+ tmpreg1 |= (uint32_t)(macconf->Watchdog |
macconf->Jabber |
macconf->InterFrameGap |
macconf->CarrierSense |
@@ -1269,13 +1329,13 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
macconf->DeferralCheck);
/* Write to ETHERNET MACCR */
- (heth->Instance)->MACCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
/*----------------------- ETHERNET MACFFR Configuration --------------------*/
/* Write to ETHERNET MACFFR */
@@ -1290,9 +1350,9 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACFFR;
+ tmpreg1 = (heth->Instance)->MACFFR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFFR = tmpreg;
+ (heth->Instance)->MACFFR = tmpreg1;
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
/* Write to ETHERNET MACHTHR */
@@ -1303,11 +1363,11 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
/*----------------------- ETHERNET MACFCR Configuration --------------------*/
/* Get the ETHERNET MACFCR value */
- tmpreg = (heth->Instance)->MACFCR;
+ tmpreg1 = (heth->Instance)->MACFCR;
/* Clear xx bits */
- tmpreg &= MACFCR_CLEAR_MASK;
+ tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
- tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
+ tmpreg1 |= (uint32_t)((macconf->PauseTime << 16) |
macconf->ZeroQuantaPause |
macconf->PauseLowThreshold |
macconf->UnicastPauseFrameDetect |
@@ -1315,13 +1375,13 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
macconf->TransmitFlowControl);
/* Write to ETHERNET MACFCR */
- (heth->Instance)->MACFCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACFCR;
+ tmpreg1 = (heth->Instance)->MACFCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFCR = tmpreg;
+ (heth->Instance)->MACFCR = tmpreg1;
/*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
(heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
@@ -1329,29 +1389,29 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACVLANTR;
+ tmpreg1 = (heth->Instance)->MACVLANTR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACVLANTR = tmpreg;
+ (heth->Instance)->MACVLANTR = tmpreg1;
}
else /* macconf == NULL : here we just configure Speed and Duplex mode */
{
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
/* Clear FES and DM bits */
- tmpreg &= ~((uint32_t)0x00004800);
+ tmpreg1 &= ~((uint32_t)0x00004800);
- tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
+ tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
/* Write to ETHERNET MACCR */
- (heth->Instance)->MACCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
}
/* Set the ETH state to Ready */
@@ -1366,13 +1426,14 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
/**
* @brief Sets ETH DMA Configuration.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @param dmaconf: DMA Configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0;
/* Process Locked */
__HAL_LOCK(heth);
@@ -1400,11 +1461,11 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef
/*----------------------- ETHERNET DMAOMR Configuration --------------------*/
/* Get the ETHERNET DMAOMR value */
- tmpreg = (heth->Instance)->DMAOMR;
+ tmpreg1 = (heth->Instance)->DMAOMR;
/* Clear xx bits */
- tmpreg &= DMAOMR_CLEAR_MASK;
+ tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
- tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
+ tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
dmaconf->ReceiveStoreForward |
dmaconf->FlushReceivedFrame |
dmaconf->TransmitStoreForward |
@@ -1415,13 +1476,13 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef
dmaconf->SecondFrameOperate);
/* Write to ETHERNET DMAOMR */
- (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
+ (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMAOMR;
+ tmpreg1 = (heth->Instance)->DMAOMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMAOMR = tmpreg;
+ (heth->Instance)->DMAOMR = tmpreg1;
/*----------------------- ETHERNET DMABMR Configuration --------------------*/
(heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
@@ -1435,9 +1496,9 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMABMR;
+ tmpreg1 = (heth->Instance)->DMABMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMABMR = tmpreg;
+ (heth->Instance)->DMABMR = tmpreg1;
/* Set the ETH state to Ready */
heth->State= HAL_ETH_STATE_READY;
@@ -1453,7 +1514,7 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef
* @}
*/
-/** @defgroup ETH_Group4 Peripheral State functions
+/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
@@ -1473,7 +1534,8 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef
/**
* @brief Return the ETH HAL state
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval HAL state
*/
HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
@@ -1485,10 +1547,19 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
/**
* @}
*/
+
+/**
+ * @}
+ */
+
+/** @addtogroup ETH_Private_Functions
+ * @{
+ */
/**
* @brief Configures Ethernet MAC and DMA with default parameters.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @param err: Ethernet Init error
* @retval HAL status
*/
@@ -1496,7 +1567,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
{
ETH_MACInitTypeDef macinit;
ETH_DMAInitTypeDef dmainit;
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0;
if (err != ETH_SUCCESS) /* Auto-negotiation failed */
{
@@ -1531,7 +1602,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
- macinit.PromiscuousMode = ETH_PROMISCIOUSMODE_DISABLE;
+ macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
macinit.HashTableHigh = 0x0;
@@ -1547,9 +1618,9 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
/* Clear WD, PCE, PS, TE and RE bits */
- tmpreg &= MACCR_CLEAR_MASK;
+ tmpreg1 &= ETH_MACCR_CLEAR_MASK;
/* Set the WD bit according to ETH Watchdog value */
/* Set the JD: bit according to ETH Jabber value */
/* Set the IFG bit according to ETH InterFrameGap value */
@@ -1563,7 +1634,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
/* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
/* Set the BL bit according to ETH BackOffLimit value */
/* Set the DC bit according to ETH DeferralCheck value */
- tmpreg |= (uint32_t)(macinit.Watchdog |
+ tmpreg1 |= (uint32_t)(macinit.Watchdog |
macinit.Jabber |
macinit.InterFrameGap |
macinit.CarrierSense |
@@ -1578,13 +1649,13 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
macinit.DeferralCheck);
/* Write to ETHERNET MACCR */
- (heth->Instance)->MACCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
/*----------------------- ETHERNET MACFFR Configuration --------------------*/
/* Set the RA bit according to ETH ReceiveAll value */
@@ -1607,9 +1678,9 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACFFR;
+ tmpreg1 = (heth->Instance)->MACFFR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFFR = tmpreg;
+ (heth->Instance)->MACFFR = tmpreg1;
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
/* Write to ETHERNET MACHTHR */
@@ -1620,9 +1691,9 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
/*----------------------- ETHERNET MACFCR Configuration -------------------*/
/* Get the ETHERNET MACFCR value */
- tmpreg = (heth->Instance)->MACFCR;
+ tmpreg1 = (heth->Instance)->MACFCR;
/* Clear xx bits */
- tmpreg &= MACFCR_CLEAR_MASK;
+ tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
/* Set the PT bit according to ETH PauseTime value */
/* Set the DZPQ bit according to ETH ZeroQuantaPause value */
@@ -1630,7 +1701,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
/* Set the UP bit according to ETH UnicastPauseFrameDetect value */
/* Set the RFE bit according to ETH ReceiveFlowControl value */
/* Set the TFE bit according to ETH TransmitFlowControl value */
- tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
+ tmpreg1 |= (uint32_t)((macinit.PauseTime << 16) |
macinit.ZeroQuantaPause |
macinit.PauseLowThreshold |
macinit.UnicastPauseFrameDetect |
@@ -1638,13 +1709,13 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
macinit.TransmitFlowControl);
/* Write to ETHERNET MACFCR */
- (heth->Instance)->MACFCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACFCR;
+ tmpreg1 = (heth->Instance)->MACFCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFCR = tmpreg;
+ (heth->Instance)->MACFCR = tmpreg1;
/*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
/* Set the ETV bit according to ETH VLANTagComparison value */
@@ -1654,9 +1725,9 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACVLANTR;
+ tmpreg1 = (heth->Instance)->MACVLANTR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACVLANTR = tmpreg;
+ (heth->Instance)->MACVLANTR = tmpreg1;
/* Ethernet DMA default initialization ************************************/
dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
@@ -1677,9 +1748,9 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
/* Get the ETHERNET DMAOMR value */
- tmpreg = (heth->Instance)->DMAOMR;
+ tmpreg1 = (heth->Instance)->DMAOMR;
/* Clear xx bits */
- tmpreg &= DMAOMR_CLEAR_MASK;
+ tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
/* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
/* Set the RSF bit according to ETH ReceiveStoreForward value */
@@ -1690,7 +1761,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
/* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
/* Set the RTC bit according to ETH ReceiveThresholdControl value */
/* Set the OSF bit according to ETH SecondFrameOperate value */
- tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
+ tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
dmainit.ReceiveStoreForward |
dmainit.FlushReceivedFrame |
dmainit.TransmitStoreForward |
@@ -1701,13 +1772,13 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
dmainit.SecondFrameOperate);
/* Write to ETHERNET DMAOMR */
- (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
+ (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMAOMR;
+ tmpreg1 = (heth->Instance)->DMAOMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMAOMR = tmpreg;
+ (heth->Instance)->DMAOMR = tmpreg1;
/*----------------------- ETHERNET DMABMR Configuration ------------------*/
/* Set the AAL bit according to ETH AddressAlignedBeats value */
@@ -1728,9 +1799,9 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMABMR;
+ tmpreg1 = (heth->Instance)->DMABMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMABMR = tmpreg;
+ (heth->Instance)->DMABMR = tmpreg1;
if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
{
@@ -1744,7 +1815,8 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
/**
* @brief Configures the selected MAC address.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @param MacAddr: The MAC address to configure
* This parameter can be one of the following values:
* @arg ETH_MAC_Address0: MAC Address0
@@ -1756,101 +1828,106 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
*/
static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
{
- uint32_t tmpreg;
+ uint32_t tmpreg1;
/* Check the parameters */
assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
/* Calculate the selected MAC address high register */
- tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
+ tmpreg1 = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
/* Load the selected MAC address high register */
- (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
+ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
/* Calculate the selected MAC address low register */
- tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
+ tmpreg1 = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
/* Load the selected MAC address low register */
- (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
+ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
}
/**
* @brief Enables the MAC transmission.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0;
/* Enable the MAC transmission */
(heth->Instance)->MACCR |= ETH_MACCR_TE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
}
/**
* @brief Disables the MAC transmission.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0;
/* Disable the MAC transmission */
(heth->Instance)->MACCR &= ~ETH_MACCR_TE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
}
/**
* @brief Enables the MAC reception.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0;
/* Enable the MAC reception */
(heth->Instance)->MACCR |= ETH_MACCR_RE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
}
/**
* @brief Disables the MAC reception.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0;
/* Disable the MAC reception */
(heth->Instance)->MACCR &= ~ETH_MACCR_RE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
}
/**
* @brief Enables the DMA transmission.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
@@ -1861,7 +1938,8 @@ static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
/**
* @brief Disables the DMA transmission.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
@@ -1872,7 +1950,8 @@ static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
/**
* @brief Enables the DMA reception.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
@@ -1883,7 +1962,8 @@ static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
/**
* @brief Disables the DMA reception.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
@@ -1894,21 +1974,22 @@ static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
/**
* @brief Clears the ETHERNET transmit FIFO.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0;
/* Set the Flush Transmit FIFO bit */
(heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMAOMR;
+ tmpreg1 = (heth->Instance)->DMAOMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMAOMR = tmpreg;
+ (heth->Instance)->DMAOMR = tmpreg1;
}
/**
diff --git a/f2/src/stm32f2xx_hal_flash.c b/f2/src/stm32f2xx_hal_flash.c
index 9651d4e7e1a84d467fdb9146ec041e44a2ee13f4..d0adf621fcc8a30127b8acdf2cf328161a214540 100755
--- a/f2/src/stm32f2xx_hal_flash.c
+++ b/f2/src/stm32f2xx_hal_flash.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_flash.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@@ -65,7 +65,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -99,7 +99,7 @@
* @{
*/
-/** @defgroup FLASH
+/** @defgroup FLASH FLASH
* @brief FLASH HAL module driver
* @{
*/
@@ -108,31 +108,47 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-#define SECTOR_MASK ((uint32_t)0xFFFFFF07)
-
-#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
+/** @addtogroup FLASH_Private_Constants
+ * @{
+ */
+#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/** @addtogroup FLASH_Private_Variables
+ * @{
+ */
/* Variable used for Erase sectors under interruption */
FLASH_ProcessTypeDef pFlash;
-
+/**
+ * @}
+ */
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
/* Program operations */
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
static void FLASH_Program_Word(uint32_t Address, uint32_t Data);
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
static void FLASH_Program_Byte(uint32_t Address, uint8_t Data);
static void FLASH_SetErrorCode(void);
+extern void FLASH_FlushCaches(void);
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+ * @}
+ */
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Functions FLASH Private functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
* @{
*/
-/** @defgroup FLASH_Group1 Programming operation functions
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
* @brief Programming operation functions
*
@verbatim
@@ -162,26 +178,26 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
/* Process Locked */
__HAL_LOCK(&pFlash);
-
+
/* Check the parameters */
- assert_param(IS_TYPEPROGRAM(TypeProgram));
-
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
- if(TypeProgram == TYPEPROGRAM_BYTE)
+ if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
{
/*Program byte (8-bit) at a specified address.*/
- FLASH_Program_Byte(Address, (uint8_t) Data);
+ FLASH_Program_Byte(Address, (uint8_t) Data);
}
- else if(TypeProgram == TYPEPROGRAM_HALFWORD)
+ else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
{
/*Program halfword (16-bit) at a specified address.*/
FLASH_Program_HalfWord(Address, (uint16_t) Data);
}
- else if(TypeProgram == TYPEPROGRAM_WORD)
+ else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
{
/*Program word (32-bit) at a specified address.*/
FLASH_Program_Word(Address, (uint32_t) Data);
@@ -191,17 +207,17 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
/*Program double word (64-bit) at a specified address.*/
FLASH_Program_DoubleWord(Address, Data);
}
-
+
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
+ FLASH->CR &= (~FLASH_CR_PG);
}
-
+
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
-
+
return status;
}
@@ -212,7 +228,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
* @param Address: specifies the address to be programmed.
* @param Data: specifies the data to be programmed
*
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
@@ -222,32 +238,28 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
__HAL_LOCK(&pFlash);
/* Check the parameters */
- assert_param(IS_TYPEPROGRAM(TypeProgram));
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
/* Enable End of FLASH Operation interrupt */
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
/* Enable Error source interrupt */
__HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
-
- /* Clear pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
- FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR);
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
pFlash.Address = Address;
- if(TypeProgram == TYPEPROGRAM_BYTE)
+ if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
{
/*Program byte (8-bit) at a specified address.*/
FLASH_Program_Byte(Address, (uint8_t) Data);
}
- else if(TypeProgram == TYPEPROGRAM_HALFWORD)
+ else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
{
/*Program halfword (16-bit) at a specified address.*/
FLASH_Program_HalfWord(Address, (uint16_t) Data);
}
- else if(TypeProgram == TYPEPROGRAM_WORD)
+ else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
{
/*Program word (32-bit) at a specified address.*/
FLASH_Program_Word(Address, (uint32_t) Data);
@@ -263,65 +275,90 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
/**
* @brief This function handles FLASH interrupt request.
- * @param None
* @retval None
*/
void HAL_FLASH_IRQHandler(void)
{
- uint32_t temp;
+ uint32_t addresstmp = 0;
+
+ /* Check FLASH operation error flags */
+ if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
+ FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR )) != RESET)
+ {
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
+ {
+ /*return the faulty sector*/
+ addresstmp = pFlash.Sector;
+ pFlash.Sector = 0xFFFFFFFF;
+ }
+ else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
+ {
+ /*return the faulty bank*/
+ addresstmp = pFlash.Bank;
+ }
+ else
+ {
+ /*return the faulty address*/
+ addresstmp = pFlash.Address;
+ }
+
+ /*Save the Error code*/
+ FLASH_SetErrorCode();
+
+ /* FLASH error interrupt user callback */
+ HAL_FLASH_OperationErrorCallback(addresstmp);
+
+ /*Stop the procedure ongoing*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
- /* If the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
-
- /* If the erase operation is completed, disable the SER Bit */
- FLASH->CR &= (~FLASH_CR_SER);
- FLASH->CR &= SECTOR_MASK;
-
- /* if the erase operation is completed, disable the MER Bit */
- FLASH->CR &= (~FLASH_CR_MER);
-
/* Check FLASH End of Operation flag */
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
{
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+
if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
{
/*Nb of sector to erased can be decreased*/
pFlash.NbSectorsToErase--;
-
+
/* Check if there are still sectors to erase*/
if(pFlash.NbSectorsToErase != 0)
{
- temp = pFlash.Sector;
+ addresstmp = pFlash.Sector;
/*Indicate user which sector has been erased*/
- HAL_FLASH_EndOfOperationCallback(temp);
-
- /* Clear pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
- FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR);
-
+ HAL_FLASH_EndOfOperationCallback(addresstmp);
+
/*Increment sector number*/
- temp = ++pFlash.Sector;
- FLASH_Erase_Sector(temp, pFlash.VoltageForErase);
+ pFlash.Sector++;
+ addresstmp = pFlash.Sector;
+ FLASH_Erase_Sector(addresstmp, pFlash.VoltageForErase);
}
else
{
/*No more sectors to Erase, user callback can be called.*/
/*Reset Sector and stop Erase sectors procedure*/
- pFlash.Sector = temp = 0xFFFFFFFF;
+ pFlash.Sector = addresstmp = 0xFFFFFFFF;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+ /* Flush the caches to be sure of the data consistency */
+ FLASH_FlushCaches() ;
+
/* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(temp);
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ HAL_FLASH_EndOfOperationCallback(addresstmp);
}
}
else
{
- if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
{
- /*MassErase ended. Return the selected bank*/
+ /* MassErase ended. Return the selected bank */
+ /* Flush the caches to be sure of the data consistency */
+ FLASH_FlushCaches() ;
+
/* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(1);
+ HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
}
else
{
@@ -330,67 +367,33 @@ void HAL_FLASH_IRQHandler(void)
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
}
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
- }
-
- }
-
- /* Check FLASH operation error flags */
- if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
- FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
- {
- if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
- {
- /*return the faulty sector*/
- temp = pFlash.Sector;
- pFlash.Sector = 0xFFFFFFFF;
- }
- else if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
- {
- /*return the faulty bank*/
- temp = 1;
- }
- else
- {
- /*retrun the faulty address*/
- temp = pFlash.Address;
}
-
- /*Save the Error code*/
- FLASH_SetErrorCode();
-
- /* FLASH error interrupt user callback */
- HAL_FLASH_OperationErrorCallback(temp);
- /* Clear FLASH error pending bits */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR |\
- FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR);
-
- /*Stop the procedure ongoing*/
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
{
+ /* Operation is completed, disable the PG, SER, SNB and MER Bits */
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_SER | FLASH_CR_SNB | FLASH_MER_BIT));
+
/* Disable End of FLASH Operation interrupt */
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
-
+
/* Disable Error source interrupt */
__HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
-
+
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
}
-
}
/**
* @brief FLASH end of operation interrupt callback
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
- * - Sectors Erase: Sector which has been erased
+ * Mass Erase: Bank number which has been requested to erase
+ * Sectors Erase: Sector which has been erased
* (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
- * - Program: Address which was selected for data program
- * @retval none
+ * Program: Address which was selected for data program
+ * @retval None
*/
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
{
@@ -402,9 +405,10 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
/**
* @brief FLASH operation error interrupt callback
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
- * - Sectors Erase: Sector number which returned an error
- * - Program: Address which was selected for data program
- * @retval none
+ * Mass Erase: Bank number which has been requested to erase
+ * Sectors Erase: Sector number which returned an error
+ * Program: Address which was selected for data program
+ * @retval None
*/
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
{
@@ -417,7 +421,7 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
* @}
*/
-/** @defgroup FLASH_Group2 Peripheral Control functions
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
* @brief management functions
*
@verbatim
@@ -434,8 +438,7 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
/**
* @brief Unlock the FLASH control register access
- * @param None
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
@@ -455,8 +458,7 @@ HAL_StatusTypeDef HAL_FLASH_Unlock(void)
/**
* @brief Locks the FLASH control register access
- * @param None
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
@@ -466,11 +468,9 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void)
return HAL_OK;
}
-
/**
* @brief Unlock the FLASH Option Control Registers access.
- * @param None
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
{
@@ -490,8 +490,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
/**
* @brief Lock the FLASH Option Control Registers access.
- * @param None
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
{
@@ -503,8 +502,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
/**
* @brief Launch the option byte loading.
- * @param None
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
{
@@ -512,14 +510,14 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
/* Wait for last operation to be completed */
- return(FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+ return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
}
/**
* @}
*/
-/** @defgroup FLASH_Group3 Peripheral State and Errors functions
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral Errors functions
*
@verbatim
@@ -527,7 +525,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
##### Peripheral Errors functions #####
===============================================================================
[..]
- This subsection permit to get in run-time Errors of the FLASH peripheral.
+ This subsection permits to get in run-time Errors of the FLASH peripheral.
@endverbatim
* @{
@@ -535,16 +533,15 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
/**
* @brief Get the specific FLASH error flag.
- * @param None
- * @retval FLASH_ErrorCode: The returned value can be:
- * @arg FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
- * @arg FLASH_ERROR_PGS: FLASH Programming Sequence error flag
- * @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
- * @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag
- * @arg FLASH_ERROR_WRP: FLASH Write protected error flag
- * @arg FLASH_ERROR_OPERATION: FLASH operation Error flag
- */
-FLASH_ErrorTypeDef HAL_FLASH_GetError(void)
+ * @retval FLASH_ErrorCode: The returned value can be a combination of:
+ * @arg HAL_FLASH_ERROR_NONE: FLASH Programming Sequence error flag
+ * @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
+ * @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
+ * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
+ * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
+ * @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag
+ */
+uint32_t HAL_FLASH_GetError(void)
{
return pFlash.ErrorCode;
}
@@ -556,36 +553,48 @@ FLASH_ErrorTypeDef HAL_FLASH_GetError(void)
/**
* @brief Wait for a FLASH operation to complete.
* @param Timeout: maximum flash operationtimeout
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
+ uint32_t tickstart = 0;
+
+ /* Clear Error Code */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
-
- uint32_t timeout = HAL_GetTick() + Timeout;
-
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET)
{
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
return HAL_TIMEOUT;
}
}
}
+
+ /* Check FLASH End of Operation flag */
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ }
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
- FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
+ FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET)
{
/*Save the error code*/
FLASH_SetErrorCode();
return HAL_ERROR;
}
- /* If there is an error flag set */
+ /* If there is no error flag set */
return HAL_OK;
}
@@ -608,7 +617,7 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
FLASH->CR |= FLASH_CR_PG;
@@ -634,7 +643,7 @@ static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
FLASH->CR |= FLASH_PSIZE_WORD;
FLASH->CR |= FLASH_CR_PG;
@@ -659,7 +668,7 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
FLASH->CR |= FLASH_PSIZE_HALF_WORD;
FLASH->CR |= FLASH_CR_PG;
@@ -684,7 +693,7 @@ static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
FLASH->CR |= FLASH_PSIZE_BYTE;
FLASH->CR |= FLASH_CR_PG;
@@ -693,39 +702,48 @@ static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
/**
* @brief Set the specific FLASH error flag.
- * @param None
* @retval None
*/
static void FLASH_SetErrorCode(void)
{
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
{
- pFlash.ErrorCode = FLASH_ERROR_WRP;
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
+
+ /* Clear FLASH write protection error pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR);
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
{
- pFlash.ErrorCode |= FLASH_ERROR_PGA;
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
+
+ /* Clear FLASH Programming alignment error pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR);
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
{
- pFlash.ErrorCode |= FLASH_ERROR_PGP;
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;
+
+ /* Clear FLASH Programming parallelism error pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGPERR);
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET)
{
- pFlash.ErrorCode |= FLASH_ERROR_PGS;
- }
-
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
- {
- pFlash.ErrorCode |= FLASH_ERROR_RD;
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS;
+
+ /* Clear FLASH Programming sequence error pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR);
}
-
+
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
{
- pFlash.ErrorCode |= FLASH_ERROR_OPERATION;
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
+
+ /* Clear FLASH Operation error pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR);
}
}
diff --git a/f2/src/stm32f2xx_hal_flash_ex.c b/f2/src/stm32f2xx_hal_flash_ex.c
index 0767bf0dd5502b2c8b2e15fd75395139533ec90f..372ffa7ae4e10c3b66ef7729988efb6ccc19948c 100755
--- a/f2/src/stm32f2xx_hal_flash_ex.c
+++ b/f2/src/stm32f2xx_hal_flash_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_flash_ex.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Extended FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the FLASH extension peripheral:
@@ -22,7 +22,7 @@
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
HAL_FLASH_Lock() functions
(++) Erase function: Erase sector, erase all sectors
- (++) There is two mode of erase :
+ (++) There are two modes of erase :
(+++) Polling Mode using HAL_FLASHEx_Erase()
(+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
@@ -36,7 +36,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -70,7 +70,7 @@
* @{
*/
-/** @defgroup FLASHEx
+/** @defgroup FLASHEx FLASHEx
* @brief FLASH HAL Extension module driver
* @{
*/
@@ -79,43 +79,60 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-#define SECTOR_MASK ((uint32_t)0xFFFFFF07)
-
-#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
+/** @addtogroup FLASHEx_Private_Constants
+ * @{
+ */
+#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
+/**
+ * @}
+ */
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Variables
+ * @{
+ */
extern FLASH_ProcessTypeDef pFlash;
+/**
+ * @}
+ */
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Functions
+ * @{
+ */
/* Option bytes control */
-static void FLASH_MassErase(uint8_t VoltageRange);
-static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector);
-static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector);
+static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks);
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level);
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby);
static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);
static uint8_t FLASH_OB_GetUser(void);
static uint16_t FLASH_OB_GetWRP(void);
-static FlagStatus FLASH_OB_GetRDP(void);
+static uint8_t FLASH_OB_GetRDP(void);
static uint8_t FLASH_OB_GetBOR(void);
-/* Private functions ---------------------------------------------------------*/
extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+ * @}
+ */
-/** @defgroup FLASHEx_Private_Functions Extended FLASH Private functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
* @{
*/
-/** @defgroup FLASHEx_Group1 Extended IO operation functions
- * @brief Extended IO operation functions
- *
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
+ * @brief Extended IO operation functions
+ *
@verbatim
===============================================================================
##### Extended programming operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the Extension FLASH
- programming operations Operations.
+ programming operations.
@endverbatim
* @{
@@ -129,7 +146,7 @@ extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
* contains the configuration information on faulty sector in case of error
* (0xFFFFFFFF means that all the sectors have been correctly erased)
*
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
{
@@ -140,31 +157,31 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
__HAL_LOCK(&pFlash);
/* Check the parameters */
- assert_param(IS_TYPEERASE(pEraseInit->TypeErase));
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- if (status == HAL_OK)
+ if(status == HAL_OK)
{
/*Initialization of SectorError variable*/
*SectorError = 0xFFFFFFFF;
- if (pEraseInit->TypeErase == TYPEERASE_MASSERASE)
+ if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
{
/*Mass erase to be done*/
- FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
+ FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* if the erase operation is completed, disable the MER Bit */
- FLASH->CR &= (~FLASH_CR_MER);
+ FLASH->CR &= (~FLASH_MER_BIT);
}
else
{
/* Check the parameters */
- assert_param(IS_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
+ assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
/* Erase by sector by sector to be done*/
for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
@@ -172,13 +189,12 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- /* If the erase operation is completed, disable the SER Bit */
- FLASH->CR &= (~FLASH_CR_SER);
- FLASH->CR &= SECTOR_MASK;
+ /* If the erase operation is completed, disable the SER and SNB Bits */
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));
- if (status != HAL_OK)
+ if(status != HAL_OK)
{
/* In case of error, stop erase procedure and return the faulty sector*/
*SectorError = index;
@@ -186,6 +202,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
}
}
}
+ /* Flush the caches to be sure of the data consistency */
+ FLASH_FlushCaches();
}
/* Process Unlocked */
@@ -199,7 +217,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
* @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
* contains the configuration information for the erasing.
*
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
{
@@ -209,7 +227,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
__HAL_LOCK(&pFlash);
/* Check the parameters */
- assert_param(IS_TYPEERASE(pEraseInit->TypeErase));
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
/* Enable End of FLASH Operation interrupt */
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
@@ -221,18 +239,19 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR);
- if (pEraseInit->TypeErase == TYPEERASE_MASSERASE)
+ if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
{
/*Mass erase to be done*/
pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
- FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
+ pFlash.Bank = pEraseInit->Banks;
+ FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
}
else
{
/* Erase by sector to be done*/
/* Check the parameters */
- assert_param(IS_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
+ assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
pFlash.NbSectorsToErase = pEraseInit->NbSectors;
@@ -251,7 +270,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
* @param pOBInit: pointer to an FLASH_OBInitStruct structure that
* contains the configuration information for the programming.
*
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
{
@@ -267,15 +286,15 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
{
assert_param(IS_WRPSTATE(pOBInit->WRPState));
- if (pOBInit->WRPState == WRPSTATE_ENABLE)
+ if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
{
/*Enable of Write protection on the selected Sector*/
- status = FLASH_OB_EnableWRP(pOBInit->WRPSector);
+ status = FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks);
}
else
{
/*Disable of Write protection on the selected Sector*/
- status = FLASH_OB_DisableWRP(pOBInit->WRPSector);
+ status = FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
}
}
@@ -317,46 +336,21 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR;
/*Get WRP*/
- pOBInit->WRPSector = FLASH_OB_GetWRP();
+ pOBInit->WRPSector = (uint32_t)FLASH_OB_GetWRP();
/*Get RDP Level*/
- pOBInit->RDPLevel = FLASH_OB_GetRDP();
+ pOBInit->RDPLevel = (uint32_t)FLASH_OB_GetRDP();
/*Get USER*/
- pOBInit->USERConfig = FLASH_OB_GetUser();
+ pOBInit->USERConfig = (uint8_t)FLASH_OB_GetUser();
/*Get BOR Level*/
- pOBInit->BORLevel = FLASH_OB_GetBOR();
+ pOBInit->BORLevel = (uint32_t)FLASH_OB_GetBOR();
}
/**
- * @brief Mass erase of FLASH memory
- * @param VoltageRange: The device voltage range which defines the erase parallelism.
- * This parameter can be one of the following values:
- * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
- * the operation will be done by byte (8-bit)
- * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
- * the operation will be done by half word (16-bit)
- * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
- * the operation will be done by word (32-bit)
- * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
- * the operation will be done by double word (64-bit)
- *
- * @retval None
+ * @}
*/
-static void FLASH_MassErase(uint8_t VoltageRange)
-{
- uint32_t tmp_psize = 0;
-
- /* Check the parameters */
- assert_param(IS_VOLTAGERANGE(VoltageRange));
-
- /* if the previous operation is completed, proceed to erase all sectors */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= tmp_psize;
- FLASH->CR |= FLASH_CR_MER;
- FLASH->CR |= FLASH_CR_STRT;
-}
/**
* @brief Erase the specified FLASH memory sector
@@ -364,13 +358,13 @@ static void FLASH_MassErase(uint8_t VoltageRange)
* The value of this parameter depend on device used within the same series
* @param VoltageRange: The device voltage range which defines the erase parallelism.
* This parameter can be one of the following values:
- * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+ * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
* the operation will be done by byte (8-bit)
- * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+ * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
* the operation will be done by half word (16-bit)
- * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+ * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
* the operation will be done by word (32-bit)
- * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+ * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
* the operation will be done by double word (64-bit)
*
* @retval None
@@ -383,15 +377,15 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
assert_param(IS_FLASH_SECTOR(Sector));
assert_param(IS_VOLTAGERANGE(VoltageRange));
- if(VoltageRange == VOLTAGE_RANGE_1)
+ if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
{
tmp_psize = FLASH_PSIZE_BYTE;
}
- else if(VoltageRange == VOLTAGE_RANGE_2)
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
{
tmp_psize = FLASH_PSIZE_HALF_WORD;
}
- else if(VoltageRange == VOLTAGE_RANGE_3)
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
{
tmp_psize = FLASH_PSIZE_WORD;
}
@@ -400,21 +394,79 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
}
- /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
- if (Sector > FLASH_SECTOR_11)
- {
- Sector += 4;
- }
/* If the previous operation is completed, proceed to erase the sector */
- FLASH->CR &= CR_PSIZE_MASK;
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
FLASH->CR |= tmp_psize;
- FLASH->CR &= SECTOR_MASK;
+ CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
FLASH->CR |= FLASH_CR_STRT;
}
/**
- * @brief Enable the write protection of the desired sectors
+ * @brief Flush the instruction and data caches
+ * @retval None
+ */
+void FLASH_FlushCaches(void)
+{
+ /* Flush instruction cache */
+ if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)
+ {
+ /* Disable instruction cache */
+ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+ /* Reset instruction cache */
+ __HAL_FLASH_INSTRUCTION_CACHE_RESET();
+ /* Enable instruction cache */
+ __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+ }
+
+ /* Flush data cache */
+ if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
+ {
+ /* Disable data cache */
+ __HAL_FLASH_DATA_CACHE_DISABLE();
+ /* Reset data cache */
+ __HAL_FLASH_DATA_CACHE_RESET();
+ /* Enable data cache */
+ __HAL_FLASH_DATA_CACHE_ENABLE();
+ }
+}
+
+/**
+ * @brief Mass erase of FLASH memory
+ * @param VoltageRange: The device voltage range which defines the erase parallelism.
+ * This parameter can be one of the following values:
+ * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+ * the operation will be done by byte (8-bit)
+ * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+ * the operation will be done by half word (16-bit)
+ * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+ * the operation will be done by word (32-bit)
+ * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+ * the operation will be done by double word (64-bit)
+ *
+ * @param Banks: Banks to be erased
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: Bank1 to be erased
+ *
+ * @retval None
+ */
+static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
+{
+ uint32_t tmp_psize = 0;
+
+ /* Check the parameters */
+ assert_param(IS_VOLTAGERANGE(VoltageRange));
+ assert_param(IS_FLASH_BANK(Banks));
+
+ /* If the previous operation is completed, proceed to erase all sectors */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+ FLASH->CR |= tmp_psize;
+ FLASH->CR |= FLASH_CR_MER;
+ FLASH->CR |= FLASH_CR_STRT;
+}
+
+/**
+ * @brief Enable the write protection of the desired bank 1 sectors
*
* @note When the memory read protection level is selected (RDP level = 1),
* it is not possible to program or erase the flash sector i if CortexM3
@@ -422,18 +474,23 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
*
* @param WRPSector: specifies the sector(s) to be write protected.
* The value of this parameter depend on device used within the same series
-
- * @retval HAL_StatusTypeDef HAL Status
+ *
+ * @param Banks: Enable write protection on all the sectors for the specific bank
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: WRP on all sectors of bank1
+ *
+ * @retval HAL Status
*/
-static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_OB_WRP_SECTOR(WRPSector));
+ assert_param(IS_FLASH_BANK(Banks));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
@@ -444,7 +501,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)
}
/**
- * @brief Disable the write protection of the desired sectors
+ * @brief Disable the write protection of the desired bank 1 sectors
*
* @note When the memory read protection level is selected (RDP level = 1),
* it is not possible to program or erase the flash sector if CortexM3
@@ -453,18 +510,22 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)
* @param WRPSector: specifies the sector(s) to be write protected.
* The value of this parameter depend on device used within the same series
*
+ * @param Banks: Enable write protection on all the sectors for the specific bank
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: WRP on all sectors of bank1
*
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
-static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_OB_WRP_SECTOR(WRPSector));
+ assert_param(IS_FLASH_BANK(Banks));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
@@ -484,7 +545,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)
*
* @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
*
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
{
@@ -494,7 +555,7 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
assert_param(IS_OB_RDP_LEVEL(Level));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
@@ -518,7 +579,7 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
* This parameter can be one of the following values:
* @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
* @arg OB_STDBY_RST: Reset generated when entering in STANDBY
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby)
{
@@ -531,7 +592,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t
assert_param(IS_OB_STDBY_SOURCE(Stdby));
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
@@ -543,7 +604,6 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t
}
return status;
-
}
/**
@@ -554,7 +614,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t
* @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
* @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
* @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
{
@@ -571,7 +631,6 @@ static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
/**
* @brief Return the FLASH User Option Byte value.
- * @param None
* @retval uint8_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
* and RST_STDBY(Bit2).
*/
@@ -583,7 +642,6 @@ static uint8_t FLASH_OB_GetUser(void)
/**
* @brief Return the FLASH Write Protection Option Bytes value.
- * @param None
* @retval uint16_t FLASH Write Protection Option Bytes value
*/
static uint16_t FLASH_OB_GetWRP(void)
@@ -594,26 +652,34 @@ static uint16_t FLASH_OB_GetWRP(void)
/**
* @brief Returns the FLASH Read Protection level.
- * @param None
- * @retval FlagStatus FLASH ReadOut Protection Status:
- * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
- * - RESET, when OB_RDP_Level_0 is set
+ * @retval FLASH ReadOut Protection Status:
+ * This parameter can be one of the following values:
+ * @arg OB_RDP_LEVEL_0: No protection
+ * @arg OB_RDP_LEVEL_1: Read protection of the memory
+ * @arg OB_RDP_LEVEL_2: Full chip protection
*/
-static FlagStatus FLASH_OB_GetRDP(void)
+static uint8_t FLASH_OB_GetRDP(void)
{
- FlagStatus readstatus = RESET;
+ uint8_t readstatus = OB_RDP_LEVEL_0;
- if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_LEVEL_0))
+ if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2))
{
- readstatus = SET;
+ readstatus = OB_RDP_LEVEL_2;
}
-
+ else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_1))
+ {
+ readstatus = OB_RDP_LEVEL_1;
+ }
+ else
+ {
+ readstatus = OB_RDP_LEVEL_0;
+ }
+
return readstatus;
}
/**
* @brief Returns the FLASH BOR level.
- * @param None
* @retval uint8_t The FLASH BOR level:
* - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
* - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
diff --git a/f2/src/stm32f2xx_hal_gpio.c b/f2/src/stm32f2xx_hal_gpio.c
index e3b755f510ebf3a5efd359679ebf35dfcfd1e471..23b7b5a550bb6acdd1e956d5b77226eae00df372 100755
--- a/f2/src/stm32f2xx_hal_gpio.c
+++ b/f2/src/stm32f2xx_hal_gpio.c
@@ -2,56 +2,57 @@
******************************************************************************
* @file stm32f2xx_hal_gpio.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- *
+ *
@verbatim
==============================================================================
##### GPIO Peripheral features #####
- ==============================================================================
+ ==============================================================================
[..]
- (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
- configured by software in several modes:
- (++) Input mode
- (++) Analog mode
- (++) Output mode
- (++) Alternate function mode
- (++) External interrupt/event lines
-
- (+) During and just after reset, the alternate functions and external interrupt
- lines are not active and the I/O ports are configured in input floating mode.
-
- (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
- activated or not.
-
- (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
- type and the IO speed can be selected depending on the VDD value.
+ Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
+ port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
+ in several modes:
+ (+) Input mode
+ (+) Analog mode
+ (+) Output mode
+ (+) Alternate function mode
+ (+) External interrupt/event lines
+
+ [..]
+ During and just after reset, the alternate functions and external interrupt
+ lines are not active and the I/O ports are configured in input floating mode.
- (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
- multiplexer that allows only one peripheral alternate function (AF) connected
- to an IO pin at a time. In this way, there can be no conflict between peripherals
- sharing the same IO pin.
-
- (+) All ports have external interrupt/event capability. To use external interrupt
- lines, the port must be configured in input mode. All available GPIO pins are
- connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
-
- (+) The external interrupt/event controller consists of up to 23 edge detectors
- (16 lines are connected to GPIO) for generating event/interrupt requests (each
- input line can be independently configured to select the type (interrupt or event)
- and the corresponding trigger event (rising or falling or both). Each line can
- also be masked independently.
+ [..]
+ All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+ activated or not.
+
+ [..]
+ In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+ type and the IO speed can be selected depending on the VDD value.
+
+ [..]
+ All ports have external interrupt/event capability. To use external interrupt
+ lines, the port must be configured in input mode. All available GPIO pins are
+ connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+ [..]
+ The external interrupt/event controller consists of up to 23 edge detectors
+ (16 lines are connected to GPIO) for generating event/interrupt requests (each
+ input line can be independently configured to select the type (interrupt or event)
+ and the corresponding trigger event (rising or falling or both). Each line can
+ also be masked independently.
+
##### How to use this driver #####
==============================================================================
- [..]
- (#) Enable the GPIO AHB clock using the following function: __GPIOx_CLK_ENABLE().
-
+ [..]
+ (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
+
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
@@ -65,7 +66,7 @@
(++) In case of external interrupt/event selection the "Mode" member from
GPIO_InitTypeDef structure select the type (interrupt or event) and
the corresponding trigger event (rising or falling or both).
-
+
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
HAL_NVIC_EnableIRQ().
@@ -74,6 +75,9 @@
(#) To set/reset the level of a pin configured in output mode use
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+ (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
(#) During and just after reset, the alternate functions are not
active and the GPIO pins are configured in input floating mode (except JTAG
@@ -91,7 +95,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -125,7 +129,7 @@
* @{
*/
-/** @defgroup GPIO
+/** @defgroup GPIO GPIO
* @brief GPIO HAL module driver
* @{
*/
@@ -134,19 +138,9 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-#define __HAL_GET_GPIO_SOURCE(__GPIOx__) \
-(((uint32_t)(__GPIOx__) == ((uint32_t)GPIOA_BASE))? (uint32_t)0 :\
- ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0400)))? (uint32_t)1 :\
- ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0800)))? (uint32_t)2 :\
- ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0C00)))? (uint32_t)3 :\
- ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x1000)))? (uint32_t)4 :\
- ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x1400)))? (uint32_t)5 :\
- ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x1800)))? (uint32_t)6 :\
- ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x1C00)))? (uint32_t)7 :\
- ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x2000)))? (uint32_t)8 :\
- ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x2400)))? (uint32_t)9 : (uint32_t)10)
-
+/** @addtogroup GPIO_Private_Constants GPIO Private Constants
+ * @{
+ */
#define GPIO_MODE ((uint32_t)0x00000003)
#define EXTI_MODE ((uint32_t)0x10000000)
#define GPIO_MODE_IT ((uint32_t)0x00010000)
@@ -156,26 +150,34 @@
#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
#define GPIO_NUMBER ((uint32_t)16)
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup GPIO_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
* @{
*/
-/** @defgroup GPIO_Group1 Initialization and de-initialization functions
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
-
+ [..]
+ This section provides functions allowing to initialize and de-initialize the GPIOs
+ to be ready for use.
+
@endverbatim
* @{
*/
+
/**
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
@@ -191,6 +193,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
uint32_t temp = 0x00;
/* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
@@ -212,14 +215,17 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
- temp = ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)) ;
- GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
- GPIOx->AFR[position >> 3] |= temp;
+ temp = GPIOx->AFR[position >> 3];
+ temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+ temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
+ GPIOx->AFR[position >> 3] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
- GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
- GPIOx->MODER |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+ temp = GPIOx->MODER;
+ temp &= ~(GPIO_MODER_MODER0 << (position * 2));
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+ GPIOx->MODER = temp;
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
@@ -228,55 +234,69 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
- GPIOx->OSPEEDR |= (GPIO_Init->Speed << (position * 2));
+ temp = GPIOx->OSPEEDR;
+ temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+ temp |= (GPIO_Init->Speed << (position * 2));
+ GPIOx->OSPEEDR = temp;
/* Configure the IO Output Type */
- GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
- GPIOx->OTYPER |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
+ temp = GPIOx->OTYPER;
+ temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
+ GPIOx->OTYPER = temp;
}
/* Activate the Pull-up or Pull down resistor for the current IO */
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
- GPIOx->PUPDR |= ((GPIO_Init->Pull) << (position * 2));
-
+ temp = GPIOx->PUPDR;
+ temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+ temp |= ((GPIO_Init->Pull) << (position * 2));
+ GPIOx->PUPDR = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
{
/* Enable SYSCFG Clock */
- __SYSCFG_CLK_ENABLE();
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
- temp = ((uint32_t)0x0F) << (4 * (position & 0x03));
- SYSCFG->EXTICR[position >> 2] &= ~temp;
- SYSCFG->EXTICR[position >> 2] |= ((uint32_t)(__HAL_GET_GPIO_SOURCE(GPIOx)) << (4 * (position & 0x03)));
-
- /* Clear EXTI line configuration */
- EXTI->IMR &= ~((uint32_t)iocurrent);
- EXTI->EMR &= ~((uint32_t)iocurrent);
+ temp = SYSCFG->EXTICR[position >> 2];
+ temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
+ temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
+ SYSCFG->EXTICR[position >> 2] = temp;
+ /* Clear EXTI line configuration */
+ temp = EXTI->IMR;
+ temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
{
- EXTI->IMR |= iocurrent;
+ temp |= iocurrent;
}
+ EXTI->IMR = temp;
+
+ temp = EXTI->EMR;
+ temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
{
- EXTI->EMR |= iocurrent;
+ temp |= iocurrent;
}
+ EXTI->EMR = temp;
/* Clear Rising Falling edge configuration */
- EXTI->RTSR &= ~((uint32_t)iocurrent);
- EXTI->FTSR &= ~((uint32_t)iocurrent);
-
+ temp = EXTI->RTSR;
+ temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
{
- EXTI->RTSR |= iocurrent;
+ temp |= iocurrent;
}
+ EXTI->RTSR = temp;
+
+ temp = EXTI->FTSR;
+ temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
{
- EXTI->FTSR |= iocurrent;
+ temp |= iocurrent;
}
+ EXTI->FTSR = temp;
}
}
}
@@ -296,6 +316,9 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
uint32_t iocurrent = 0x00;
uint32_t tmp = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
/* Configure the port pins */
for(position = 0; position < GPIO_NUMBER; position++)
{
@@ -307,7 +330,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
if(iocurrent == ioposition)
{
/*------------------------- GPIO Mode Configuration --------------------*/
- /* Configure IO Direction in Input Floting Mode */
+ /* Configure IO Direction in Input Floating Mode */
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
/* Configure the default Alternate Function in current IO */
@@ -319,22 +342,26 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
- /* Deactivate the Pull-up oand Pull-down resistor for the current IO */
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
-
/*------------------------- EXTI Mode Configuration --------------------*/
- /* Configure the External Interrupt or event for the current IO */
- tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
- SYSCFG->EXTICR[position >> 2] &= ~tmp;
-
- /* Clear EXTI line configuration */
- EXTI->IMR &= ~((uint32_t)iocurrent);
- EXTI->EMR &= ~((uint32_t)iocurrent);
+ tmp = SYSCFG->EXTICR[position >> 2];
+ tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
+ if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
+ {
+ /* Configure the External Interrupt or event for the current IO */
+ tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
+ SYSCFG->EXTICR[position >> 2] &= ~tmp;
- /* Clear Rising Falling edge configuration */
- EXTI->RTSR &= ~((uint32_t)iocurrent);
- EXTI->FTSR &= ~((uint32_t)iocurrent);
+ /* Clear EXTI line configuration */
+ EXTI->IMR &= ~((uint32_t)iocurrent);
+ EXTI->EMR &= ~((uint32_t)iocurrent);
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RTSR &= ~((uint32_t)iocurrent);
+ EXTI->FTSR &= ~((uint32_t)iocurrent);
+ }
}
}
}
@@ -343,7 +370,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
* @}
*/
-/** @defgroup GPIO_Group2 IO operation functions
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
* @brief GPIO Read and Write
*
@verbatim
@@ -367,7 +394,7 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
GPIO_PinState bitstatus;
/* Check the parameters */
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
{
@@ -392,23 +419,23 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @param PinState: specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
- * @arg GPIO_BIT_RESET: to clear the port pin
- * @arg GPIO_BIT_SET: to set the port pin
+ * @arg GPIO_PIN_RESET: to clear the port pin
+ * @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
/* Check the parameters */
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
{
- GPIOx->BSRRL = GPIO_Pin;
+ GPIOx->BSRR = GPIO_Pin;
}
else
{
- GPIOx->BSRRH = GPIO_Pin ;
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
}
}
@@ -421,11 +448,50 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
/* Check the parameters */
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
GPIOx->ODR ^= GPIO_Pin;
}
+/**
+ * @brief Locks GPIO Pins configuration registers.
+ * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+ * @note The configuration of the locked GPIO pins can no longer be modified
+ * until the next reset.
+ * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for STM32F2XX family
+ * @param GPIO_Pin: specifies the port bit to be locked.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Apply lock key write sequence */
+ tmp |= GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+
+ if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
+ {
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
/**
* @brief This function handles EXTI interrupt request.
* @param GPIO_Pin: Specifies the pins connected EXTI line
@@ -457,7 +523,6 @@ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
* @}
*/
-
/**
* @}
*/
diff --git a/f2/src/stm32f2xx_hal_hash.c b/f2/src/stm32f2xx_hal_hash.c
index 20e89669ea27d9fce2a0903ccdfda838226c71af..9163170544f9ac25a7a94b2b000660e1681d14ad 100755
--- a/f2/src/stm32f2xx_hal_hash.c
+++ b/f2/src/stm32f2xx_hal_hash.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_hash.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral:
@@ -20,7 +20,7 @@
[..]
The HASH HAL driver can be used as follows:
(#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
- (##) Enable the HASH interface clock using __HASH_CLK_ENABLE()
+ (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
(##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT())
(+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
@@ -68,7 +68,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -102,7 +102,7 @@
* @{
*/
-/** @defgroup HASH
+/** @defgroup HASH HASH
* @brief HASH HAL module driver.
* @{
*/
@@ -116,18 +116,198 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HASH_Private_Functions HASH Private Functions
+ * @{
+ */
static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
static void HASH_DMAError(DMA_HandleTypeDef *hdma);
static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);
-
+/**
+ * @}
+ */
+
/* Private functions ---------------------------------------------------------*/
+/** @addtogroup HASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief DMA HASH Input Data complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
+{
+ HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ uint32_t inputaddr = 0;
+ uint32_t buffersize = 0;
+
+ if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
+ {
+ /* Disable the DMA transfer */
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
+ }
+ else
+ {
+ /* Increment Interrupt counter */
+ hhash->HashInCount++;
+ /* Disable the DMA transfer before starting the next transfer */
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
+
+ if(hhash->HashInCount <= 2)
+ {
+ /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
+ if(hhash->HashInCount == 1)
+ {
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ buffersize = hhash->HashBuffSize;
+ }
+ /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
+ else if(hhash->HashInCount == 2)
+ {
+ inputaddr = (uint32_t)hhash->Init.pKey;
+ buffersize = hhash->Init.KeySize;
+ }
+ /* Configure the number of valid bits in last word of the message */
+ MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));
+
+ /* Set the HASH DMA transfer complete */
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));
+
+ /* Enable DMA requests */
+ HASH->CR |= (HASH_CR_DMAE);
+ }
+ else
+ {
+ /* Disable the DMA transfer */
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
+
+ /* Reset the InCount */
+ hhash->HashInCount = 0;
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
+ }
+ }
+}
+
+/**
+ * @brief DMA HASH communication error callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void HASH_DMAError(DMA_HandleTypeDef *hdma)
+{
+ HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hhash->State= HAL_HASH_STATE_READY;
+ HAL_HASH_ErrorCallback(hhash);
+}
-/** @defgroup HASH_Private_Functions
+/**
+ * @brief Writes the input buffer in data register.
+ * @param pInBuffer: Pointer to input buffer
+ * @param Size: The size of input buffer
+ * @retval None
+ */
+static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t buffercounter;
+ uint32_t inputaddr = (uint32_t) pInBuffer;
+
+ for(buffercounter = 0; buffercounter < Size; buffercounter+=4)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4;
+ }
+}
+
+/**
+ * @brief Provides the message digest result.
+ * @param pMsgDigest: Pointer to the message digest
+ * @param Size: The size of the message digest in bytes
+ * @retval None
+ */
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
+{
+ uint32_t msgdigest = (uint32_t)pMsgDigest;
+
+ switch(Size)
+ {
+ case 16:
+ /* Read the message digest */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest+=4;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest+=4;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest+=4;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+ break;
+ case 20:
+ /* Read the message digest */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest+=4;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest+=4;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest+=4;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+ msgdigest+=4;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+ break;
+ case 28:
+ /* Read the message digest */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest+=4;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest+=4;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest+=4;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+ msgdigest+=4;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+ break;
+ case 32:
+ /* Read the message digest */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest+=4;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest+=4;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest+=4;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+ msgdigest+=4;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HASH_Exported_Functions
* @{
*/
+
-/** @defgroup HASH_Group1 Initialization and de-initialization functions
+/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
@@ -148,7 +328,8 @@ static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);
/**
* @brief Initializes the HASH according to the specified parameters in the
HASH_HandleTypeDef and creates the associated handle.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
@@ -164,6 +345,8 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
if(hhash->State == HAL_HASH_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hhash->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_HASH_MspInit(hhash);
}
@@ -192,7 +375,8 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
/**
* @brief DeInitializes the HASH peripheral.
* @note This API must be called before starting a new processing.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
@@ -229,7 +413,8 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
/**
* @brief Initializes the HASH MSP.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @retval None
*/
__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
@@ -241,7 +426,8 @@ __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
/**
* @brief DeInitializes HASH MSP.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @retval None
*/
__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
@@ -253,7 +439,8 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
/**
* @brief Input data transfer complete callback.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @retval None
*/
__weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
@@ -265,7 +452,8 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
/**
* @brief Data transfer Error callback.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @retval None
*/
__weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
@@ -278,7 +466,8 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
/**
* @brief Digest computation complete callback. It is used only with interrupt.
* @note This callback is not relevant with DMA.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @retval None
*/
__weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
@@ -292,7 +481,7 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
* @}
*/
-/** @defgroup HASH_Group2 HASH processing functions using polling mode
+/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions using polling mode
* @brief processing functions using polling mode
*
@verbatim
@@ -311,9 +500,9 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
/**
* @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
The digest is available in pOutBuffer.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param pOutBuffer: Pointer to the Output buffer (hashed buffer).
* @param Size: Length of the input buffer in bytes.
* If the Size is multiple of 64 bytes, appending the input buffer is possible.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware
@@ -324,7 +513,7 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Process Locked */
__HAL_LOCK(hhash);
@@ -337,7 +526,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
{
/* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
the message digest of a new message */
- HASH->CR |= HASH_AlgoSelection_MD5 | HASH_CR_INIT;
+ HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
}
/* Set the phase */
@@ -352,20 +541,20 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
/* Start the digest calculation */
__HAL_HASH_START_DIGEST();
- /* Get timeout */
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Change state */
hhash->State = HAL_HASH_STATE_TIMEOUT;
- /* Process Unlocked */
+ /* Process Unlocked */
__HAL_UNLOCK(hhash);
return HAL_TIMEOUT;
@@ -388,7 +577,8 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
/**
* @brief Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is multiple of 64 bytes, appending the input buffer is possible.
@@ -409,7 +599,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pI
{
/* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
the message digest of a new message */
- HASH->CR |= HASH_AlgoSelection_MD5 | HASH_CR_INIT;
+ HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
}
/* Set the phase */
@@ -434,9 +624,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pI
/**
* @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
The digest is available in pOutBuffer.
- * @param hhash: HASH handle
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param pOutBuffer: Pointer to the Output buffer (hashed buffer).
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
@@ -445,7 +635,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pI
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Process Locked */
__HAL_LOCK(hhash);
@@ -458,7 +648,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
{
/* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
the message digest of a new message */
- HASH->CR |= HASH_AlgoSelection_SHA1 | HASH_CR_INIT;
+ HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
}
/* Set the phase */
@@ -473,20 +663,20 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
/* Start the digest calculation */
__HAL_HASH_START_DIGEST();
- /* Get timeout */
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Change state */
hhash->State = HAL_HASH_STATE_TIMEOUT;
- /* Process Unlocked */
+ /* Process Unlocked */
__HAL_UNLOCK(hhash);
return HAL_TIMEOUT;
@@ -509,16 +699,20 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
/**
* @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
- The digest is available in pOutBuffer.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+ * @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
+
+ /* Check the parameters */
+ assert_param(IS_HASH_SHA1_BUFFER_SIZE(Size));
+
/* Process Locked */
__HAL_LOCK(hhash);
@@ -530,7 +724,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p
{
/* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
the message digest of a new message */
- HASH->CR |= HASH_AlgoSelection_SHA1 | HASH_CR_INIT;
+ HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
}
/* Set the phase */
@@ -556,7 +750,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p
* @}
*/
-/** @defgroup HASH_Group3 HASH processing functions using interrupt mode
+/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions using interrupt mode
* @brief processing functions using interrupt mode.
*
@verbatim
@@ -575,9 +769,9 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p
/**
* @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
* The digest is available in pOutBuffer.
- * @param hhash: HASH handle
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param pOutBuffer: Pointer to the Output buffer (hashed buffer).
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
@@ -593,14 +787,6 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
/* Process Locked */
__HAL_LOCK(hhash);
- if(hhash->HashITCounter == 0)
- {
- hhash->HashITCounter = 1;
- }
- else
- {
- hhash->HashITCounter = 0;
- }
if(hhash->State == HAL_HASH_STATE_READY)
{
/* Change the HASH state */
@@ -614,11 +800,13 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
if(hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Select the SHA1 mode */
- HASH->CR |= HASH_AlgoSelection_MD5;
+ HASH->CR |= HASH_ALGOSELECTION_MD5;
/* Reset the HASH processor core, so that the HASH will be ready to compute
the message digest of a new message */
HASH->CR |= HASH_CR_INIT;
}
+ /* Reset interrupt counter */
+ hhash->HashITCounter = 0;
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
@@ -652,11 +840,17 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
hhash->State = HAL_HASH_STATE_READY;
/* Call digest computation complete callback */
HAL_HASH_DgstCpltCallback(hhash);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
}
}
if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
- if(hhash->HashInCount > 64)
+ if(hhash->HashInCount >= 68)
{
inputaddr = (uint32_t)hhash->pHashInBuffPtr;
/* Write the Input block in the Data IN register */
@@ -677,8 +871,11 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
}
else
{
- hhash->HashInCount -= 64;
+ hhash->HashInCount = 0;
+ hhash->pHashInBuffPtr+= hhash->HashInCount;
}
+ /* Set Interrupt counter */
+ hhash->HashITCounter = 1;
}
else
{
@@ -702,7 +899,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
{
inputcounter = (inputcounter+4-inputcounter%4);
}
-
+ else if ((inputcounter < 4) && (inputcounter != 0))
+ {
+ inputcounter = 4;
+ }
/* Write the Input block in the Data IN register */
for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
{
@@ -713,11 +913,12 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
__HAL_HASH_START_DIGEST();
/* Reset buffer counter */
hhash->HashInCount = 0;
+
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
}
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
}
-
+
/* Process Unlocked */
__HAL_UNLOCK(hhash);
@@ -728,9 +929,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
/**
* @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
* The digest is available in pOutBuffer.
- * @param hhash: HASH handle
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param pOutBuffer: Pointer to the Output buffer (hashed buffer).
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
@@ -746,14 +947,6 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
/* Process Locked */
__HAL_LOCK(hhash);
- if(hhash->HashITCounter == 0)
- {
- hhash->HashITCounter = 1;
- }
- else
- {
- hhash->HashITCounter = 0;
- }
if(hhash->State == HAL_HASH_STATE_READY)
{
/* Change the HASH state */
@@ -767,12 +960,15 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
if(hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Select the SHA1 mode */
- HASH->CR |= HASH_AlgoSelection_SHA1;
+ HASH->CR |= HASH_ALGOSELECTION_SHA1;
/* Reset the HASH processor core, so that the HASH will be ready to compute
the message digest of a new message */
HASH->CR |= HASH_CR_INIT;
}
+ /* Reset interrupt counter */
+ hhash->HashITCounter = 0;
+
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
@@ -806,11 +1002,17 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
hhash->State = HAL_HASH_STATE_READY;
/* Call digest computation complete callback */
HAL_HASH_DgstCpltCallback(hhash);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
}
}
if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
- if(hhash->HashInCount > 64)
+ if(hhash->HashInCount >= 68)
{
inputaddr = (uint32_t)hhash->pHashInBuffPtr;
/* Write the Input block in the Data IN register */
@@ -822,7 +1024,6 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
if(hhash->HashITCounter == 0)
{
HASH->DIN = *(uint32_t*)inputaddr;
-
if(hhash->HashInCount >= 68)
{
/* Decrement buffer counter */
@@ -831,8 +1032,11 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
}
else
{
- hhash->HashInCount -= 64;
+ hhash->HashInCount = 0;
+ hhash->pHashInBuffPtr+= hhash->HashInCount;
}
+ /* Set Interrupt counter */
+ hhash->HashITCounter = 1;
}
else
{
@@ -856,7 +1060,10 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
{
inputcounter = (inputcounter+4-inputcounter%4);
}
-
+ else if ((inputcounter < 4) && (inputcounter != 0))
+ {
+ inputcounter = 4;
+ }
/* Write the Input block in the Data IN register */
for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
{
@@ -867,9 +1074,10 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
__HAL_HASH_START_DIGEST();
/* Reset buffer counter */
hhash->HashInCount = 0;
+
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
}
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
}
/* Process Unlocked */
@@ -881,18 +1089,19 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
/**
* @brief This function handles HASH interrupt request.
- * @param hhash: hash handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @retval None
*/
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
{
switch(HASH->CR & HASH_CR_ALGO)
{
- case HASH_AlgoSelection_MD5:
+ case HASH_ALGOSELECTION_MD5:
HAL_HASH_MD5_Start_IT(hhash, NULL, 0, NULL);
break;
- case HASH_AlgoSelection_SHA1:
+ case HASH_ALGOSELECTION_SHA1:
HAL_HASH_SHA1_Start_IT(hhash, NULL, 0, NULL);
break;
@@ -905,7 +1114,7 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
* @}
*/
-/** @defgroup HASH_Group4 HASH processing functions using DMA mode
+/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions using DMA mode
* @brief processing functions using DMA mode.
*
@verbatim
@@ -924,11 +1133,11 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
/**
* @brief Initializes the HASH peripheral in MD5 mode then enables DMA to
control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -946,7 +1155,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
{
/* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
the message digest of a new message */
- HASH->CR |= HASH_AlgoSelection_MD5 | HASH_CR_INIT;
+ HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
}
/* Configure the number of valid bits in last word of the message */
@@ -975,14 +1184,15 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
/**
* @brief Returns the computed digest in MD5 mode
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
* @param Timeout: Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Process Locked */
__HAL_LOCK(hhash);
@@ -990,20 +1200,20 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu
/* Change HASH peripheral state */
hhash->State = HAL_HASH_STATE_BUSY;
- /* Get timeout */
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Change state */
hhash->State = HAL_HASH_STATE_TIMEOUT;
- /* Process Unlocked */
+ /* Process Unlocked */
__HAL_UNLOCK(hhash);
return HAL_TIMEOUT;
@@ -1027,11 +1237,11 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu
/**
* @brief Initializes the HASH peripheral in SHA1 mode then enables DMA to
control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -1049,7 +1259,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI
{
/* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
the message digest of a new message */
- HASH->CR |= HASH_AlgoSelection_SHA1;
+ HASH->CR |= HASH_ALGOSELECTION_SHA1;
HASH->CR |= HASH_CR_INIT;
}
@@ -1079,14 +1289,15 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI
/**
* @brief Returns the computed digest in SHA1 mode.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
* @param Timeout: Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Process Locked */
__HAL_LOCK(hhash);
@@ -1094,19 +1305,19 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB
/* Change HASH peripheral state */
hhash->State = HAL_HASH_STATE_BUSY;
- /* Get timeout */
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Change state */
hhash->State = HAL_HASH_STATE_TIMEOUT;
- /* Process Unlocked */
+ /* Process Unlocked */
__HAL_UNLOCK(hhash);
return HAL_TIMEOUT;
@@ -1132,7 +1343,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB
* @}
*/
-/** @defgroup HASH_Group5 HASH-MAC (HMAC) processing functions using polling mode
+/** @defgroup HASH_Exported_Functions_Group5 HASH-MAC (HMAC) processing functions using polling mode
* @brief HMAC processing functions using polling mode .
*
@verbatim
@@ -1151,7 +1362,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB
/**
* @brief Initializes the HASH peripheral in HMAC MD5 mode
* then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@@ -1161,7 +1373,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB
*/
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Process Locked */
__HAL_LOCK(hhash);
@@ -1176,12 +1388,12 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
if(hhash->Init.KeySize > 64)
{
/* Select the HMAC MD5 mode */
- HASH->CR |= (HASH_AlgoSelection_MD5 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey | HASH_CR_INIT);
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
}
else
{
/* Select the HMAC MD5 mode */
- HASH->CR |= (HASH_AlgoSelection_MD5 | HASH_AlgoMode_HMAC | HASH_CR_INIT);
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
}
}
@@ -1198,20 +1410,20 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
/* Start the digest calculation */
__HAL_HASH_START_DIGEST();
- /* Get timeout */
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Change state */
hhash->State = HAL_HASH_STATE_TIMEOUT;
- /* Process Unlocked */
+ /* Process Unlocked */
__HAL_UNLOCK(hhash);
return HAL_TIMEOUT;
@@ -1228,20 +1440,20 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
/* Start the digest calculation */
__HAL_HASH_START_DIGEST();
- /* Get timeout */
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > Timeout)
{
/* Change state */
hhash->State = HAL_HASH_STATE_TIMEOUT;
- /* Process Unlocked */
+ /* Process Unlocked */
__HAL_UNLOCK(hhash);
return HAL_TIMEOUT;
@@ -1258,20 +1470,20 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
/* Start the digest calculation */
__HAL_HASH_START_DIGEST();
- /* Get timeout */
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > Timeout)
{
/* Change state */
hhash->State = HAL_HASH_STATE_TIMEOUT;
- /* Process Unlocked */
+ /* Process Unlocked */
__HAL_UNLOCK(hhash);
return HAL_TIMEOUT;
@@ -1295,7 +1507,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
/**
* @brief Initializes the HASH peripheral in HMAC SHA1 mode
* then processes pInBuffer. The digest is available in pOutBuffer.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@@ -1305,7 +1518,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
*/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Process Locked */
__HAL_LOCK(hhash);
@@ -1320,12 +1533,12 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
if(hhash->Init.KeySize > 64)
{
/* Select the HMAC SHA1 mode */
- HASH->CR |= (HASH_AlgoSelection_SHA1 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey | HASH_CR_INIT);
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
}
else
{
/* Select the HMAC SHA1 mode */
- HASH->CR |= (HASH_AlgoSelection_SHA1 | HASH_AlgoMode_HMAC | HASH_CR_INIT);
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
}
}
@@ -1342,20 +1555,20 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
/* Start the digest calculation */
__HAL_HASH_START_DIGEST();
- /* Get timeout */
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Change state */
hhash->State = HAL_HASH_STATE_TIMEOUT;
- /* Process Unlocked */
+ /* Process Unlocked */
__HAL_UNLOCK(hhash);
return HAL_TIMEOUT;
@@ -1372,20 +1585,20 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
/* Start the digest calculation */
__HAL_HASH_START_DIGEST();
- /* Get timeout */
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > Timeout)
{
/* Change state */
hhash->State = HAL_HASH_STATE_TIMEOUT;
- /* Process Unlocked */
+ /* Process Unlocked */
__HAL_UNLOCK(hhash);
return HAL_TIMEOUT;
@@ -1402,20 +1615,20 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
/* Start the digest calculation */
__HAL_HASH_START_DIGEST();
- /* Get timeout */
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > Timeout)
{
/* Change state */
hhash->State = HAL_HASH_STATE_TIMEOUT;
- /* Process Unlocked */
+ /* Process Unlocked */
__HAL_UNLOCK(hhash);
return HAL_TIMEOUT;
@@ -1435,14 +1648,11 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
return HAL_OK;
}
-
-
-
/**
* @}
*/
-/** @defgroup HASH_Group6 HASH-MAC (HMAC) processing functions using DMA mode
+/** @defgroup HASH_Exported_Functions_Group6 HASH-MAC (HMAC) processing functions using DMA mode
* @brief HMAC processing functions using DMA mode .
*
@verbatim
@@ -1461,7 +1671,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
/**
* @brief Initializes the HASH peripheral in HMAC MD5 mode
* then enables DMA to control data transfer.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@@ -1489,12 +1700,12 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
if(hhash->Init.KeySize > 64)
{
/* Select the HMAC MD5 mode */
- HASH->CR |= (HASH_AlgoSelection_MD5 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey | HASH_CR_INIT);
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
}
else
{
/* Select the HMAC MD5 mode */
- HASH->CR |= (HASH_AlgoSelection_MD5 | HASH_AlgoMode_HMAC | HASH_CR_INIT);
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
}
}
@@ -1527,7 +1738,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
/**
* @brief Initializes the HASH peripheral in HMAC SHA1 mode
* then enables DMA to control data transfer.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@@ -1555,12 +1767,12 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI
if(hhash->Init.KeySize > 64)
{
/* Select the HMAC SHA1 mode */
- HASH->CR |= (HASH_AlgoSelection_SHA1 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey | HASH_CR_INIT);
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
}
else
{
/* Select the HMAC SHA1 mode */
- HASH->CR |= (HASH_AlgoSelection_SHA1 | HASH_AlgoMode_HMAC | HASH_CR_INIT);
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
}
}
@@ -1594,7 +1806,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI
* @}
*/
-/** @defgroup HASH_Group7 Peripheral State functions
+/** @defgroup HASH_Exported_Functions_Group7 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
@@ -1610,7 +1822,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI
/**
* @brief return the HASH state
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @retval HAL state
*/
HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
@@ -1622,147 +1835,6 @@ HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
* @}
*/
-/**
- * @brief DMA HASH Input Data complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
-{
- HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- uint32_t inputaddr = 0;
- uint32_t buffersize = 0;
-
- if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
- {
- /* Disable the DMA transfer */
- HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
- else
- {
- /* Increment Interrupt counter */
- hhash->HashInCount++;
- /* Disable the DMA transfer before starting the next transfer */
- HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
-
- if(hhash->HashInCount <= 2)
- {
- /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
- if(hhash->HashInCount == 1)
- {
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- buffersize = hhash->HashBuffSize;
- }
- /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
- else if(hhash->HashInCount == 2)
- {
- inputaddr = (uint32_t)hhash->Init.pKey;
- buffersize = hhash->Init.KeySize;
- }
- /* Configure the number of valid bits in last word of the message */
- HASH->STR |= 8 * (buffersize % 4);
-
- /* Set the HASH DMA transfer complete */
- hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));
-
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
- }
- else
- {
- /* Disable the DMA transfer */
- HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
-
- /* Reset the InCount */
- hhash->HashInCount = 0;
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
- }
-}
-
-/**
- * @brief DMA HASH communication error callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void HASH_DMAError(DMA_HandleTypeDef *hdma)
-{
- HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hhash->State= HAL_HASH_STATE_READY;
- HAL_HASH_ErrorCallback(hhash);
-}
-
-/**
- * @brief Writes the input buffer in data register.
- * @param pInBuffer: Pointer to input buffer
- * @param Size: The size of input buffer
- * @retval None
- */
-static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size)
-{
- uint32_t buffercounter;
- uint32_t inputaddr = (uint32_t) pInBuffer;
-
- for(buffercounter = 0; buffercounter < Size; buffercounter+=4)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- }
-}
-
-/**
- * @brief Provides the message digest result.
- * @param pMsgDigest: Pointer to the message digest
- * @param Size: The size of the message digest in bytes
- * @retval None
- */
-static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
-{
- uint32_t msgdigest = (uint32_t)pMsgDigest;
-
- switch(Size)
- {
- case 16:
- /* Read the message digest */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- break;
- case 20:
- /* Read the message digest */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
- break;
- default:
- break;
- }
-}
-
/**
* @}
*/
diff --git a/f2/src/stm32f2xx_hal_hcd.c b/f2/src/stm32f2xx_hal_hcd.c
index e625e979b7c0530b60463e4451d8978425e1242e..453ad53cf476a148b50c13d3a8c987d6f50177cd 100755
--- a/f2/src/stm32f2xx_hal_hcd.c
+++ b/f2/src/stm32f2xx_hal_hcd.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_hcd.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief HCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -25,9 +25,10 @@
(#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
(#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
- (##) Enable the HCD/USB Low Level interface clock using
- (+++) __OTGFS-OTG_CLK_ENABLE()/__OTGHS-OTG_CLK_ENABLE();
- (+++) __OTGHSULPI_CLK_ENABLE(); (For High Speed Mode)
+ (##) Enable the HCD/USB Low Level interface clock using the following macros
+ (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+ (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
+ (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode)
(##) Initialize the related GPIO clocks
(##) Configure HCD pin-out
@@ -43,7 +44,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -72,11 +73,12 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f2xx_hal.h"
+
/** @addtogroup STM32F2xx_HAL_Driver
* @{
*/
-/** @defgroup HCD
+/** @defgroup HCD HCD
* @brief HCD HAL module driver
* @{
*/
@@ -88,20 +90,26 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HCD_Private_Functions HCD Private Functions
+ * @{
+ */
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
-/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
-/** @defgroup HCD_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Functions HCD Exported Functions
* @{
*/
-/** @defgroup HCD_Group1 Initialization and de-initialization functions
+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
@@ -112,9 +120,9 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
*/
/**
- * @brief Initialize the host driver
- * @param hhcd : HCD handle
- * @retval HAL state
+ * @brief Initialize the host driver.
+ * @param hhcd: HCD handle
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
{
@@ -126,52 +134,52 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
/* Check the parameters */
assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
-
- hhcd->State = HCD_BUSY;
+
+ hhcd->State = HAL_HCD_STATE_BUSY;
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_HCD_MspInit(hhcd);
-
+
/* Disable the Interrupts */
- __HAL_HCD_DISABLE(hhcd);
-
- /*Init the Core (common init.) */
- USB_CoreInit(hhcd->Instance, hhcd->Init);
-
- /* Force Host Mode*/
- USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE);
-
- /* Init Host */
- USB_HostInit(hhcd->Instance, hhcd->Init);
-
- hhcd->State= HCD_READY;
-
- return HAL_OK;
+ __HAL_HCD_DISABLE(hhcd);
+
+ /* Init the Core (common init.) */
+ USB_CoreInit(hhcd->Instance, hhcd->Init);
+
+ /* Force Host Mode*/
+ USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE);
+
+ /* Init Host */
+ USB_HostInit(hhcd->Instance, hhcd->Init);
+
+ hhcd->State= HAL_HCD_STATE_READY;
+
+ return HAL_OK;
}
/**
- * @brief Initialize a host channel
- * @param hhcd : HCD handle
- * @param ch_num : Channel number
+ * @brief Initialize a host channel.
+ * @param hhcd: HCD handle
+ * @param ch_num: Channel number.
* This parameter can be a value from 1 to 15
- * @param epnum : Endpoint number
+ * @param epnum: Endpoint number.
* This parameter can be a value from 1 to 15
* @param dev_address : Current device address
* This parameter can be a value from 0 to 255
- * @param speed : Current device speed
- * This parameter can be one of the these values:
- * @arg HCD_SPEED_HIGH: High speed mode
- * @arg HCD_SPEED_FULL: Full speed mode
- * @arg HCD_SPEED_LOW: Low speed mode
- * @param ep_type : Endpoint Type
- * This parameter can be one of the these values:
- * @arg EP_TYPE_CTRL: Control type
- * @arg EP_TYPE_ISOC: Isochrounous type
- * @arg EP_TYPE_BULK: Bulk type
- * @arg EP_TYPE_INTR: Interrupt type
- * @param mps : Max Packet Size
+ * @param speed: Current device speed.
+ * This parameter can be one of these values:
+ * HCD_SPEED_HIGH: High speed mode,
+ * HCD_SPEED_FULL: Full speed mode,
+ * HCD_SPEED_LOW: Low speed mode
+ * @param ep_type: Endpoint Type.
+ * This parameter can be one of these values:
+ * EP_TYPE_CTRL: Control type,
+ * EP_TYPE_ISOC: Isochronous type,
+ * EP_TYPE_BULK: Bulk type,
+ * EP_TYPE_INTR: Interrupt type
+ * @param mps: Max Packet Size.
* This parameter can be a value from 0 to32K
- * @retval HAL state
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
uint8_t ch_num,
@@ -192,7 +200,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
hhcd->hc[ch_num].ep_num = epnum & 0x7F;
hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);
hhcd->hc[ch_num].speed = speed;
-
+
status = USB_HC_Init(hhcd->Instance,
ch_num,
epnum,
@@ -205,17 +213,14 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
return status;
}
-
-
/**
- * @brief Halt a host channel
- * @param hhcd : HCD handle
- * @param ch_num : Channel number
+ * @brief Halt a host channel.
+ * @param hhcd: HCD handle
+ * @param ch_num: Channel number.
* This parameter can be a value from 1 to 15
- * @retval HAL state
+ * @retval HAL status
*/
-HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num)
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -225,10 +230,11 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
return status;
}
+
/**
- * @brief DeInitialize the host driver
- * @param hhcd : HCD handle
- * @retval HAL state
+ * @brief DeInitialize the host driver.
+ * @param hhcd: HCD handle
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
{
@@ -238,39 +244,39 @@ HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
return HAL_ERROR;
}
- hhcd->State = HCD_BUSY;
+ hhcd->State = HAL_HCD_STATE_BUSY;
/* DeInit the low level hardware */
HAL_HCD_MspDeInit(hhcd);
- __HAL_HCD_DISABLE(hhcd);
+ __HAL_HCD_DISABLE(hhcd);
- hhcd->State = HCD_READY;
+ hhcd->State = HAL_HCD_STATE_RESET;
return HAL_OK;
}
/**
- * @brief Initializes the HCD MSP.
+ * @brief Initialize the HCD MSP.
* @param hhcd: HCD handle
* @retval None
*/
__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_MspInit could be implenetd in the user file
+ the HAL_PCD_MspInit could be implemented in the user file
*/
}
/**
- * @brief DeInitializes HCD MSP.
+ * @brief DeInitialize the HCD MSP.
* @param hhcd: HCD handle
* @retval None
*/
-__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhhcd)
+__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_MspDeInit could be implenetd in the user file
+ the HAL_PCD_MspDeInit could be implemented in the user file
*/
}
@@ -278,14 +284,14 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhhcd)
* @}
*/
-/** @defgroup HCD_Group2 IO operation functions
+/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions
* @brief HCD IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
- This subsection provides a set of functions allowing to manage the USB Host Data
+ [..] This subsection provides a set of functions allowing to manage the USB Host Data
Transfer
@endverbatim
@@ -293,40 +299,37 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhhcd)
*/
/**
- * @brief Submit a new URB for processing
- * @param hhcd : HCD handle
- * @param ch_num : Channel number
+ * @brief Submit a new URB for processing.
+ * @param hhcd: HCD handle
+ * @param ch_num: Channel number.
* This parameter can be a value from 1 to 15
- * @param direction : Channel number
- * This parameter can be one of the these values:
- * 0 : Output
- * 1 : Input
- * @param ep_type : Endpoint Type
- * This parameter can be one of the these values:
- * @arg EP_TYPE_CTRL: Control type
- * @arg EP_TYPE_ISOC: Isochrounous type
- * @arg EP_TYPE_BULK: Bulk type
- * @arg EP_TYPE_INTR: Interrupt type
- * @param token : Endpoint Type
- * This parameter can be one of the these values:
- * @arg 0: HC_PID_SETUP
- * @arg 1: HC_PID_DATA1
- * @param pbuff : pointer to URB data
- * @param length : Length of URB data
- * @param do_ping : activate do ping protocol (for high speed only)
- * This parameter can be one of the these values:
- * 0 : do ping inactive
- * 1 : do ping active
- * @retval HAL state
+ * @param direction: Channel number.
+ * This parameter can be one of these values:
+ * 0 : Output / 1 : Input
+ * @param ep_type: Endpoint Type.
+ * This parameter can be one of these values:
+ * EP_TYPE_CTRL: Control type/
+ * EP_TYPE_ISOC: Isochronous type/
+ * EP_TYPE_BULK: Bulk type/
+ * EP_TYPE_INTR: Interrupt type/
+ * @param token: Endpoint Type.
+ * This parameter can be one of these values:
+ * 0: HC_PID_SETUP / 1: HC_PID_DATA1
+ * @param pbuff: pointer to URB data
+ * @param length: Length of URB data
+ * @param do_ping: activate do ping protocol (for high speed only).
+ * This parameter can be one of these values:
+ * 0 : do ping inactive / 1 : do ping active
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t direction ,
- uint8_t ep_type,
- uint8_t token,
- uint8_t* pbuff,
- uint16_t length,
- uint8_t do_ping)
+ uint8_t ch_num,
+ uint8_t direction,
+ uint8_t ep_type,
+ uint8_t token,
+ uint8_t* pbuff,
+ uint16_t length,
+ uint8_t do_ping)
{
hhcd->hc[ch_num].ep_is_in = direction;
hhcd->hc[ch_num].ep_type = ep_type;
@@ -358,7 +361,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
}
else
{ /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)
{
@@ -377,7 +380,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
}
else
{ /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)
{
@@ -407,7 +410,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
}
else
{ /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
}
else
@@ -425,14 +428,13 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
case EP_TYPE_ISOC:
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- break;
-
+ break;
}
hhcd->hc[ch_num].xfer_buff = pbuff;
hhcd->hc[ch_num].xfer_len = length;
hhcd->hc[ch_num].urb_state = URB_IDLE;
- hhcd->hc[ch_num].xfer_count = 0 ;
+ hhcd->hc[ch_num].xfer_count = 0;
hhcd->hc[ch_num].ch_num = ch_num;
hhcd->hc[ch_num].state = HC_IDLE;
@@ -440,19 +442,19 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
}
/**
- * @brief This function handles HCD interrupt request.
+ * @brief Handle HCD interrupt request.
* @param hhcd: HCD handle
- * @retval none
+ * @retval None
*/
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t i = 0 , interrupt = 0;
- /* ensure that we are in device mode */
+ /* Ensure that we are in device mode */
if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
{
- /* avoid spurious interrupt */
+ /* Avoid spurious interrupt */
if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
{
return;
@@ -460,25 +462,25 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
{
- /* incorrect mode, acknowledge the interrupt */
+ /* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
}
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
{
- /* incorrect mode, acknowledge the interrupt */
+ /* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
}
-
+
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
{
- /* incorrect mode, acknowledge the interrupt */
+ /* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
}
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
{
- /* incorrect mode, acknowledge the interrupt */
+ /* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
}
@@ -489,10 +491,10 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
/* Cleanup HPRT */
USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-
+
/* Handle Host Port Interrupts */
HAL_HCD_Disconnect_Callback(hhcd);
- USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
+ USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
}
@@ -508,19 +510,18 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
HAL_HCD_SOF_Callback(hhcd);
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
}
-
+
/* Handle Host channel Interrupts */
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
{
-
interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
- for (i = 0; i < hhcd->Init.Host_channels ; i++)
+ for (i = 0; i < hhcd->Init.Host_channels; i++)
{
if (interrupt & (1 << i))
{
if ((USBx_HC(i)->HCCHAR) & USB_OTG_HCCHAR_EPDIR)
{
- HCD_HC_IN_IRQHandler (hhcd, i);
+ HCD_HC_IN_IRQHandler(hhcd, i);
}
else
{
@@ -531,7 +532,7 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
}
- /* Handle Rx Queue Level Interrupts */
+ /* Handle Rx Queue Level Interrupts */
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL))
{
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
@@ -540,7 +541,6 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
-
}
}
@@ -552,53 +552,53 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_SOF_Callback could be implenetd in the user file
+ the HAL_HCD_SOF_Callback could be implemented in the user file
*/
}
/**
- * @brief Connexion Event callback.
+ * @brief Connection Event callback.
* @param hhcd: HCD handle
* @retval None
*/
__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_Connect_Callback could be implenetd in the user file
+ the HAL_HCD_Connect_Callback could be implemented in the user file
*/
}
/**
- * @brief Disonnexion Event callback.
+ * @brief Disconnection Event callback.
* @param hhcd: HCD handle
* @retval None
*/
__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_Disconnect_Callback could be implenetd in the user file
+ the HAL_HCD_Disconnect_Callback could be implemented in the user file
*/
}
/**
* @brief Notify URB state change callback.
* @param hhcd: HCD handle
- * @param chnum : Channel number
+ * @param chnum: Channel number.
* This parameter can be a value from 1 to 15
* @param urb_state:
- * This parameter can be one of the these values:
- * @arg URB_IDLE
- * @arg URB_DONE
- * @arg URB_NOTREADY
- * @arg URB_NYET
- * @arg URB_ERROR
- * @arg URB_STALL
+ * This parameter can be one of these values:
+ * URB_IDLE/
+ * URB_DONE/
+ * URB_NOTREADY/
+ * URB_NYET/
+ * URB_ERROR/
+ * URB_STALL/
* @retval None
*/
__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_HC_NotifyURBChange_Callback could be implenetd in the user file
+ the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
*/
}
@@ -606,10 +606,10 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t
* @}
*/
-/** @defgroup HCD_Group3 Peripheral Control functions
- * @brief management functions
+/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Management functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
@@ -622,9 +622,9 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t
*/
/**
- * @brief Start the host driver
- * @param hhcd : HCD handle
- * @retval HAL state
+ * @brief Start the host driver.
+ * @param hhcd: HCD handle
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
{
@@ -636,9 +636,9 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
}
/**
- * @brief Stop the host driver
- * @param hhcd : HCD handle
- * @retval HAL state
+ * @brief Stop the host driver.
+ * @param hhcd: HCD handle
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
@@ -650,9 +650,9 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
}
/**
- * @brief Reset the host port
- * @param hhcd : HCD handle
- * @retval HAL state
+ * @brief Reset the host port.
+ * @param hhcd: HCD handle
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
{
@@ -663,15 +663,15 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
* @}
*/
-/** @defgroup HCD_Group4 Peripheral State functions
+/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -679,8 +679,8 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
*/
/**
- * @brief Return the HCD state
- * @param hhcd : HCD handle
+ * @brief Return the HCD handle state.
+ * @param hhcd: HCD handle
* @retval HAL state
*/
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
@@ -689,18 +689,18 @@ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
}
/**
- * @brief Return URB state for a channel
- * @param hhcd : HCD handle
- * @param chnum : Channel number
+ * @brief Return URB state for a channel.
+ * @param hhcd: HCD handle
+ * @param chnum: Channel number.
* This parameter can be a value from 1 to 15
- * @retval URB state
- * This parameter can be one of the these values:
- * @arg URB_IDLE
- * @arg URB_DONE
- * @arg URB_NOTREADY
- * @arg URB_NYET
- * @arg URB_ERROR
- * @arg URB_STALL
+ * @retval URB state.
+ * This parameter can be one of these values:
+ * URB_IDLE/
+ * URB_DONE/
+ * URB_NOTREADY/
+ * URB_NYET/
+ * URB_ERROR/
+ * URB_STALL
*/
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
@@ -709,9 +709,9 @@ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnu
/**
- * @brief Return the last host transfer size
- * @param hhcd : HCD handle
- * @param chnum : Channel number
+ * @brief Return the last host transfer size.
+ * @param hhcd: HCD handle
+ * @param chnum: Channel number.
* This parameter can be a value from 1 to 15
* @retval last transfer size in byte
*/
@@ -721,21 +721,21 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
}
/**
- * @brief Return the Host Channel state
- * @param hhcd : HCD handle
- * @param chnum : Channel number
+ * @brief Return the Host Channel state.
+ * @param hhcd: HCD handle
+ * @param chnum: Channel number.
* This parameter can be a value from 1 to 15
* @retval Host channel state
- * This parameter can be one of the these values:
- * @arg HC_IDLE
- * @arg HC_XFRC
- * @arg HC_HALTED
- * @arg HC_NYET
- * @arg HC_NAK
- * @arg HC_STALL
- * @arg HC_XACTERR
- * @arg HC_BBLERR
- * @arg HC_DATATGLERR
+ * This parameter can be one of these values:
+ * HC_IDLE/
+ * HC_XFRC/
+ * HC_HALTED/
+ * HC_NYET/
+ * HC_NAK/
+ * HC_STALL/
+ * HC_XACTERR/
+ * HC_BBLERR/
+ * HC_DATATGLERR
*/
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
@@ -743,9 +743,9 @@ HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
}
/**
- * @brief Return the current Host frame number
- * @param hhcd : HCD handle
- * @retval current Host frame number
+ * @brief Return the current Host frame number.
+ * @param hhcd: HCD handle
+ * @retval Current Host frame number
*/
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
{
@@ -753,8 +753,8 @@ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
}
/**
- * @brief Return the Host enumeration speed
- * @param hhcd : HCD handle
+ * @brief Return the Host enumeration speed.
+ * @param hhcd: HCD handle
* @retval Enumeration speed
*/
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
@@ -767,16 +767,24 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
*/
/**
- * @brief This function handles Host Channel IN interrupt requests.
+ * @}
+ */
+
+/** @addtogroup HCD_Private_Functions
+ * @{
+ */
+/**
+ * @brief Handle Host Channel IN interrupt requests.
* @param hhcd: HCD handle
- * @param chnum : Channel number
+ * @param chnum: Channel number.
* This parameter can be a value from 1 to 15
- * @retval none
+ * @retval None
*/
-static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
+static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
-
+ uint32_t tmpreg = 0;
+
if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
@@ -817,7 +825,7 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
if (hhcd->Init.dma_enable)
{
hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \
- (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
+ (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
}
hhcd->hc[chnum].state = HC_XFRC;
@@ -870,8 +878,10 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
}
/* re-activate the channel */
- USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
- USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ tmpreg = USBx_HC(chnum)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(chnum)->HCCHAR = tmpreg;
}
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
@@ -880,10 +890,10 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)
{
__HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- hhcd->hc[chnum].ErrCnt++;
- hhcd->hc[chnum].state = HC_XACTERR;
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
+ hhcd->hc[chnum].ErrCnt++;
+ hhcd->hc[chnum].state = HC_XACTERR;
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
}
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)
{
@@ -895,26 +905,28 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
{
- /* re-activate the channel */
- USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
- USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
-
+ /* re-activate the channel */
+ tmpreg = USBx_HC(chnum)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(chnum)->HCCHAR = tmpreg;
}
hhcd->hc[chnum].state = HC_NAK;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
}
}
/**
- * @brief This function handles Host Channel OUT interrupt requests.
+ * @brief Handle Host Channel OUT interrupt requests.
* @param hhcd: HCD handle
- * @param chnum : Channel number
+ * @param chnum: Channel number.
* This parameter can be a value from 1 to 15
- * @retval none
+ * @retval None
*/
static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ uint32_t tmpreg = 0;
if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
{
@@ -1038,8 +1050,10 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
}
/* re-activate the channel */
- USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
- USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ tmpreg = USBx_HC(chnum)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(chnum)->HCCHAR = tmpreg;
}
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
@@ -1048,23 +1062,24 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
}
/**
- * @brief This function handles Rx Queue Level interrupt requests.
+ * @brief Handle Rx Queue Level interrupt requests.
* @param hhcd: HCD handle
- * @retval none
+ * @retval None
*/
-static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
+static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- uint8_t channelnum =0;
- uint32_t pktsts;
- uint32_t pktcnt;
- uint32_t temp = 0;
+ uint8_t channelnum = 0;
+ uint32_t pktsts;
+ uint32_t pktcnt;
+ uint32_t temp = 0;
+ uint32_t tmpreg = 0;
- temp = hhcd->Instance->GRXSTSP ;
+ temp = hhcd->Instance->GRXSTSP;
channelnum = temp & USB_OTG_GRXSTSP_EPNUM;
pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17;
pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
-
+
switch (pktsts)
{
case GRXSTS_PKTSTS_IN:
@@ -1073,21 +1088,23 @@ static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
{
USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);
-
+
/*manage multiple Xfer */
hhcd->hc[channelnum].xfer_buff += pktcnt;
hhcd->hc[channelnum].xfer_count += pktcnt;
-
+
if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)
{
/* re-activate the channel when more packets are expected */
- USBx_HC(channelnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
- USBx_HC(channelnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ tmpreg = USBx_HC(channelnum)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(channelnum)->HCCHAR = tmpreg;
hhcd->hc[channelnum].toggle_in ^= 1;
}
}
break;
-
+
case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
break;
case GRXSTS_PKTSTS_IN_XFER_COMP:
@@ -1098,9 +1115,9 @@ static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
}
/**
- * @brief This function handles Host Port interrupt requests.
+ * @brief Handle Host Port interrupt requests.
* @param hhcd: HCD handle
- * @retval none
+ * @retval None
*/
static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
{
@@ -1114,9 +1131,9 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
- /* Check wether Port Connect Detected */
+ /* Check whether Port Connect Detected */
if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
- {
+ {
if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
{
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
@@ -1168,7 +1185,7 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
}
}
- /* Check For an overcurrent */
+ /* Check for an overcurrent */
if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
{
hprt0_dup |= USB_OTG_HPRT_POCCHNG;
@@ -1178,6 +1195,10 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
USBx_HPRT0 = hprt0_dup;
}
+/**
+ * @}
+ */
+
/**
* @}
*/
diff --git a/f2/src/stm32f2xx_hal_i2c.c b/f2/src/stm32f2xx_hal_i2c.c
index c484ba0548e5d41b93b330bb8910a79d155343b7..703ffa655fcd94485bd68f17db521b93563b755b 100755
--- a/f2/src/stm32f2xx_hal_i2c.c
+++ b/f2/src/stm32f2xx_hal_i2c.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_i2c.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
@@ -35,19 +35,19 @@
(+++) Enable the DMAx interface clock using
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx Stream
- (+++) Associate the initilalized DMA handle to the hi2c DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
+ (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+ the DMA Tx or Rx Stream
(#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
- (#) Initialize the I2C registers by calling the HAL_I2C_Init() API:
- (+++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_I2C_MspInit(&hi2c) API.
+ (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
+ (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
(#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
- (#) For I2C IO and IO MEM operations, three mode of operations are available within this driver :
+ (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -141,9 +141,9 @@
(+) __HAL_I2C_ENABLE: Enable the I2C peripheral
(+) __HAL_I2C_DISABLE: Disable the I2C peripheral
(+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
- (+) __HAL_I2C_CLEAR_FLAG : Clears the specified I2C pending flag
- (+) __HAL_I2C_ENABLE_IT: Enables the specified I2C interrupt
- (+) __HAL_I2C_DISABLE_IT: Disables the specified I2C interrupt
+ (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
+ (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+ (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
[..]
(@) You can refer to the I2C HAL driver header file for more useful macros
@@ -153,7 +153,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -187,7 +187,7 @@
* @{
*/
-/** @defgroup I2C
+/** @defgroup I2C I2C
* @brief I2C HAL module driver
* @{
*/
@@ -196,12 +196,22 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup I2C_Private_Constants
+ * @{
+ */
#define I2C_TIMEOUT_FLAG ((uint32_t)35) /* 35 ms */
#define I2C_TIMEOUT_ADDR_SLAVE ((uint32_t)10000) /* 10 s */
+#define I2C_TIMEOUT_BUSY_FLAG ((uint32_t)10000) /* 10 s */
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup I2C_Private_Functions
+ * @{
+ */
static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
@@ -229,14 +239,16 @@ static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c);
static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup I2C_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2C_Exported_Functions I2C Exported Functions
* @{
*/
-/** @defgroup I2C_Group1 Initialization and de-initialization functions
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -244,7 +256,7 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
- de-initialiaze the I2Cx peripheral:
+ de-initialize the I2Cx peripheral:
(+) User must Implement HAL_I2C_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
@@ -261,7 +273,7 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
(++) Nostretch mode
(+) Call the function HAL_I2C_DeInit() to restore the default configuration
- of the selected I2Cx periperal.
+ of the selected I2Cx peripheral.
@endverbatim
* @{
@@ -270,8 +282,8 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
/**
* @brief Initializes the I2C according to the specified parameters
* in the I2C_InitTypeDef and create the associated handle.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
@@ -298,20 +310,22 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
if(hi2c->State == HAL_I2C_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hi2c->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_I2C_MspInit(hi2c);
}
hi2c->State = HAL_I2C_STATE_BUSY;
- /* Disble the selected I2C peripheral */
+ /* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Get PCLK1 frequency */
pclk1 = HAL_RCC_GetPCLK1Freq();
/* Calculate frequency range */
- freqrange = __HAL_I2C_FREQRANGE(pclk1);
+ freqrange = I2C_FREQRANGE(pclk1);
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Frequency range */
@@ -319,11 +333,11 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
/*---------------------------- I2Cx TRISE Configuration --------------------*/
/* Configure I2Cx: Rise Time */
- hi2c->Instance->TRISE = __HAL_I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
+ hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
/*---------------------------- I2Cx CCR Configuration ----------------------*/
/* Configure I2Cx: Speed */
- hi2c->Instance->CCR = __HAL_I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
+ hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
@@ -348,8 +362,8 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
/**
* @brief DeInitializes the I2C peripheral.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
@@ -383,8 +397,8 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
/**
* @brief I2C MSP Init.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
@@ -396,8 +410,8 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
/**
* @brief I2C MSP DeInit
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
@@ -411,7 +425,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
* @}
*/
-/** @defgroup I2C_Group2 IO operation functions
+/** @defgroup I2C_Exported_Functions_Group2 IO operation functions
* @brief Data transfers functions
*
@verbatim
@@ -422,7 +436,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
This subsection provides a set of functions allowing to manage the I2C data
transfers.
- (#) There is two mode of transfer:
+ (#) There are two modes of transfer:
(++) Blocking mode : The communication is performed in the polling mode.
The status of all data processing is returned by the same function
after finishing transfer.
@@ -457,7 +471,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
(++) HAL_I2C_Mem_Write_DMA()
(++) HAL_I2C_Mem_Read_DMA()
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_I2C_MemTxCpltCallback()
(++) HAL_I2C_MemRxCpltCallback()
(++) HAL_I2C_MasterTxCpltCallback()
@@ -472,8 +486,8 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
/**
* @brief Transmits in master mode an amount of data in blocking mode.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@@ -489,13 +503,17 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -549,12 +567,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
/* Generate Stop */
hi2c->Instance->CR1 |= I2C_CR1_STOP;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
@@ -570,8 +582,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
/**
* @brief Receives in master mode an amount of data in blocking mode.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@@ -587,13 +599,17 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
-
+
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -738,15 +754,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
}
}
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
@@ -762,8 +769,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
/**
* @brief Transmits in slave mode an amount of data in blocking mode.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @param Timeout: Timeout duration
@@ -778,13 +785,17 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -846,12 +857,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
/* Disable Address Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
@@ -867,8 +872,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
/**
* @brief Receive in slave mode an amount of data in blocking mode
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @param Timeout: Timeout duration
@@ -883,13 +888,17 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -938,12 +947,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
/* Disable Address Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
@@ -959,8 +962,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
/**
* @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@@ -975,13 +978,17 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1030,8 +1037,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
/**
* @brief Receive in master mode an amount of data in no-blocking mode with Interrupt
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@@ -1046,13 +1053,17 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1129,8 +1140,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
/**
* @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -1144,13 +1155,17 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1182,8 +1197,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
/**
* @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -1197,13 +1212,17 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1235,8 +1254,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
/**
* @brief Transmit in master mode an amount of data in no-blocking mode with DMA
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@@ -1251,13 +1270,17 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1266,7 +1289,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
hi2c->XferSize = Size;
hi2c->XferCount = Size;
- /* Set the I2C DMA transfert complete callback */
+ /* Set the I2C DMA transfer complete callback */
hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
/* Set the DMA error callback */
@@ -1311,8 +1334,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
/**
* @brief Receive in master mode an amount of data in no-blocking mode with DMA
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@@ -1327,13 +1350,17 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1342,7 +1369,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
hi2c->XferSize = Size;
hi2c->XferCount = Size;
- /* Set the I2C DMA transfert complete callback */
+ /* Set the I2C DMA transfer complete callback */
hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
/* Set the DMA error callback */
@@ -1398,8 +1425,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
/**
* @brief Transmit in slave mode an amount of data in no-blocking mode with DMA
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -1413,13 +1440,17 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1428,7 +1459,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
hi2c->XferSize = Size;
hi2c->XferCount = Size;
- /* Set the I2C DMA transfert complete callback */
+ /* Set the I2C DMA transfer complete callback */
hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
/* Set the DMA error callback */
@@ -1483,8 +1514,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
/**
* @brief Receive in slave mode an amount of data in no-blocking mode with DMA
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -1498,13 +1529,17 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1513,7 +1548,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
hi2c->XferSize = Size;
hi2c->XferCount = Size;
- /* Set the I2C DMA transfert complete callback */
+ /* Set the I2C DMA transfer complete callback */
hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
/* Set the DMA error callback */
@@ -1549,8 +1584,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
}
/**
* @brief Write an amount of data in blocking mode to a specific memory address
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -1571,13 +1606,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1628,12 +1667,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
/* Generate Stop */
hi2c->Instance->CR1 |= I2C_CR1_STOP;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
@@ -1649,8 +1682,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
/**
* @brief Read an amount of data in blocking mode from a specific memory address
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -1671,13 +1704,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1819,15 +1856,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
}
}
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
@@ -1842,8 +1870,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
}
/**
* @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -1863,13 +1891,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1915,8 +1947,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
/**
* @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -1936,13 +1968,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2018,8 +2054,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
}
/**
* @brief Write an amount of data in no-blocking mode with DMA to a specific memory address
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -2039,13 +2075,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2054,7 +2094,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
hi2c->XferSize = Size;
hi2c->XferCount = Size;
- /* Set the I2C DMA transfert complete callback */
+ /* Set the I2C DMA transfer complete callback */
hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt;
/* Set the DMA error callback */
@@ -2096,8 +2136,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/**
* @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -2117,13 +2157,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2132,7 +2176,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
hi2c->XferSize = Size;
hi2c->XferCount = Size;
- /* Set the I2C DMA transfert complete callback */
+ /* Set the I2C DMA transfer complete callback */
hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt;
/* Set the DMA error callback */
@@ -2189,8 +2233,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
/**
* @brief Checks if target device is ready for communication.
* @note This function is used with Memory devices
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param Trials: Number of trials
* @param Timeout: Timeout duration
@@ -2198,17 +2242,21 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
*/
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
{
- uint32_t timeout = 0, tmp1 = 0, tmp2 = 0, tmp3 = 0, I2C_Trials = 1;
+ uint32_t tickstart = 0, tmp1 = 0, tmp2 = 0, tmp3 = 0, I2C_Trials = 1;
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2225,17 +2273,18 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
}
/* Send slave address */
- hi2c->Instance->DR = __HAL_I2C_7BIT_ADD_WRITE(DevAddress);
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
/* Wait until ADDR or AF flag are set */
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
tmp3 = hi2c->State;
while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT))
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
hi2c->State = HAL_I2C_STATE_TIMEOUT;
}
@@ -2256,7 +2305,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -2277,10 +2326,11 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_TIMEOUT;
}
+
}
}while(I2C_Trials++ < Trials);
@@ -2299,8 +2349,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/**
* @brief This function handles I2C event interrupt request.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
@@ -2404,8 +2454,8 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
/**
* @brief This function handles I2C error interrupt request.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
@@ -2468,14 +2518,17 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
{
hi2c->State = HAL_I2C_STATE_READY;
+ /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
HAL_I2C_ErrorCallback(hi2c);
}
}
/**
* @brief Master Tx Transfer completed callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
@@ -2487,8 +2540,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
/**
* @brief Master Rx Transfer completed callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
@@ -2499,8 +2552,8 @@ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
}
/** @brief Slave Tx Transfer completed callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
@@ -2512,8 +2565,8 @@ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
/**
* @brief Slave Rx Transfer completed callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
@@ -2525,8 +2578,8 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
/**
* @brief Memory Tx Transfer completed callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
@@ -2538,8 +2591,8 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
/**
* @brief Memory Rx Transfer completed callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
@@ -2551,8 +2604,8 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
/**
* @brief I2C error callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
@@ -2566,7 +2619,7 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
* @}
*/
-/** @defgroup I2C_Group3 Peripheral State and Errors functions
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral State and Errors functions
*
@verbatim
@@ -2574,7 +2627,7 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
##### Peripheral State and Errors functions #####
===============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -2583,7 +2636,8 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
/**
* @brief Returns the I2C state.
- * @param hi2c : I2C handle
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL state
*/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
@@ -2608,15 +2662,12 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
/**
* @brief Handle TXE flag for Master
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
{
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
/* Write data to DR */
hi2c->Instance->DR = (*hi2c->pBuffPtr++);
hi2c->XferCount--;
@@ -2627,31 +2678,22 @@ static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
}
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
return HAL_OK;
}
/**
* @brief Handle BTF flag for Master transmitter
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
{
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
if(hi2c->XferCount != 0)
{
/* Write data to DR */
hi2c->Instance->DR = (*hi2c->pBuffPtr++);
hi2c->XferCount--;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
}
else
{
@@ -2661,28 +2703,16 @@ static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
/* Generate Stop */
hi2c->Instance->CR1 |= I2C_CR1_STOP;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
{
hi2c->State = HAL_I2C_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
HAL_I2C_MemTxCpltCallback(hi2c);
}
else
{
hi2c->State = HAL_I2C_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
HAL_I2C_MasterTxCpltCallback(hi2c);
}
}
@@ -2691,34 +2721,25 @@ static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
/**
* @brief Handle RXNE flag for Master
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
{
uint32_t tmp = 0;
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
tmp = hi2c->XferCount;
if(tmp > 3)
{
/* Read data from DR */
(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
hi2c->XferCount--;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
}
else if((tmp == 2) || (tmp == 3))
{
/* Disable BUF interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
}
else
{
@@ -2729,28 +2750,16 @@ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
hi2c->XferCount--;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
HAL_I2C_MemRxCpltCallback(hi2c);
}
else
{
hi2c->State = HAL_I2C_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
HAL_I2C_MasterRxCpltCallback(hi2c);
}
}
@@ -2759,15 +2768,12 @@ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
/**
* @brief Handle BTF flag for Master receiver
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
{
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
if(hi2c->XferCount == 3)
{
/* Disable Acknowledge */
@@ -2776,9 +2782,6 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
/* Read data from DR */
(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
hi2c->XferCount--;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
}
else if(hi2c->XferCount == 2)
{
@@ -2796,28 +2799,16 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
/* Disable EVT and ERR interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
HAL_I2C_MemRxCpltCallback(hi2c);
}
else
{
hi2c->State = HAL_I2C_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
HAL_I2C_MasterRxCpltCallback(hi2c);
}
}
@@ -2826,135 +2817,100 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
/* Read data from DR */
(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
hi2c->XferCount--;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
}
return HAL_OK;
}
/**
* @brief Handle TXE flag for Slave
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
{
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- if(hi2c->XferCount != 0)
+ if(hi2c->XferCount != 0)
{
/* Write data to DR */
hi2c->Instance->DR = (*hi2c->pBuffPtr++);
hi2c->XferCount--;
}
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
return HAL_OK;
}
/**
* @brief Handle BTF flag for Slave transmitter
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
{
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- if(hi2c->XferCount != 0)
+ if(hi2c->XferCount != 0)
{
/* Write data to DR */
hi2c->Instance->DR = (*hi2c->pBuffPtr++);
hi2c->XferCount--;
}
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
return HAL_OK;
}
/**
* @brief Handle RXNE flag for Slave
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
{
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- if(hi2c->XferCount != 0)
+ if(hi2c->XferCount != 0)
{
/* Read data from DR */
(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
hi2c->XferCount--;
}
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
return HAL_OK;
}
/**
* @brief Handle BTF flag for Slave receiver
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
{
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- if(hi2c->XferCount != 0)
+ if(hi2c->XferCount != 0)
{
/* Read data from DR */
(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
hi2c->XferCount--;
}
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
return HAL_OK;
}
/**
* @brief Handle ADD flag for Slave
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
{
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
return HAL_OK;
}
/**
* @brief Handle STOPF flag for Slave
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
{
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
/* Disable EVT, BUF and ERR interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
@@ -2964,32 +2920,20 @@ static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
/* Disable Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
HAL_I2C_SlaveRxCpltCallback(hi2c);
return HAL_OK;
}
/**
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
{
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
/* Disable EVT, BUF and ERR interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
@@ -2999,26 +2943,18 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
/* Disable Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
HAL_I2C_SlaveTxCpltCallback(hi2c);
return HAL_OK;
}
/**
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
@@ -3035,12 +2971,12 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_
if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
{
/* Send slave address */
- hi2c->Instance->DR = __HAL_I2C_7BIT_ADD_WRITE(DevAddress);
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
}
else
{
/* Send header of slave address */
- hi2c->Instance->DR = __HAL_I2C_10BIT_HEADER_WRITE(DevAddress);
+ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
/* Wait until ADD10 flag is set */
if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK)
@@ -3056,7 +2992,7 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_
}
/* Send slave address */
- hi2c->Instance->DR = __HAL_I2C_10BIT_ADDRESS(DevAddress);
+ hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
}
/* Wait until ADDR flag is set */
@@ -3077,9 +3013,10 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_
/**
* @brief Master sends target device address for read request.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
@@ -3099,12 +3036,12 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
{
/* Send slave address */
- hi2c->Instance->DR = __HAL_I2C_7BIT_ADD_READ(DevAddress);
+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
}
else
{
/* Send header of slave address */
- hi2c->Instance->DR = __HAL_I2C_10BIT_HEADER_WRITE(DevAddress);
+ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
/* Wait until ADD10 flag is set */
if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK)
@@ -3120,7 +3057,7 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
}
/* Send slave address */
- hi2c->Instance->DR = __HAL_I2C_10BIT_ADDRESS(DevAddress);
+ hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
/* Wait until ADDR flag is set */
if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
@@ -3148,7 +3085,7 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
}
/* Send header of slave address */
- hi2c->Instance->DR = __HAL_I2C_10BIT_HEADER_READ(DevAddress);
+ hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
}
/* Wait until ADDR flag is set */
@@ -3169,11 +3106,12 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
/**
* @brief Master sends target device address followed by internal memory address for write request.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
@@ -3188,7 +3126,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
}
/* Send slave address */
- hi2c->Instance->DR = __HAL_I2C_7BIT_ADD_WRITE(DevAddress);
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
/* Wait until ADDR flag is set */
if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
@@ -3216,13 +3154,13 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
/* Send Memory Address */
- hi2c->Instance->DR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
- hi2c->Instance->DR = __HAL_I2C_MEM_ADD_MSB(MemAddress);
+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXE flag is set */
if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
@@ -3231,7 +3169,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
}
/* Send LSB of Memory Address */
- hi2c->Instance->DR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
}
return HAL_OK;
@@ -3239,11 +3177,12 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
/**
* @brief Master sends target device address followed by internal memory address for read request.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
@@ -3261,7 +3200,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
}
/* Send slave address */
- hi2c->Instance->DR = __HAL_I2C_7BIT_ADD_WRITE(DevAddress);
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
/* Wait until ADDR flag is set */
if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
@@ -3289,13 +3228,13 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
/* Send Memory Address */
- hi2c->Instance->DR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
- hi2c->Instance->DR = __HAL_I2C_MEM_ADD_MSB(MemAddress);
+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXE flag is set */
if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
@@ -3304,7 +3243,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
}
/* Send LSB of Memory Address */
- hi2c->Instance->DR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
}
/* Wait until TXE flag is set */
@@ -3323,7 +3262,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
}
/* Send slave address */
- hi2c->Instance->DR = __HAL_I2C_7BIT_ADD_READ(DevAddress);
+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
/* Wait until ADDR flag is set */
if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
@@ -3364,12 +3303,6 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
hi2c->XferCount = 0;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Check if Errors has been detected during transfer */
@@ -3409,12 +3342,6 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
hi2c->XferCount = 0;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Check if Errors has been detected during transfer */
@@ -3437,26 +3364,20 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
{
I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
/* Generate Stop */
hi2c->Instance->CR1 |= I2C_CR1_STOP;
/* Disable Last DMA */
hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
/* Disable DMA Request */
hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
hi2c->XferCount = 0;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Check if Errors has been detected during transfer */
@@ -3496,12 +3417,6 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
hi2c->XferCount = 0;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Check if Errors has been detected during transfer */
@@ -3538,12 +3453,6 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
hi2c->XferCount = 0;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Check if Errors has been detected during transfer */
@@ -3566,26 +3475,20 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
{
I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
/* Generate Stop */
hi2c->Instance->CR1 |= I2C_CR1_STOP;
/* Disable Last DMA */
hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
/* Disable DMA Request */
hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
hi2c->XferCount = 0;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Check if Errors has been detected during transfer */
@@ -3622,8 +3525,8 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
/**
* @brief This function handles I2C Communication Timeout.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param Flag: specifies the I2C flag to check.
* @param Status: The new Flag status (SET or RESET).
* @param Timeout: Timeout duration
@@ -3631,9 +3534,10 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
*/
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Wait until flag is set */
if(Status == RESET)
@@ -3643,7 +3547,7 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
hi2c->State= HAL_I2C_STATE_READY;
@@ -3662,7 +3566,7 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
hi2c->State= HAL_I2C_STATE_READY;
@@ -3679,17 +3583,18 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
/**
* @brief This function handles I2C Communication Timeout for Master addressing phase.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param Flag: specifies the I2C flag to check.
* @param Timeout: Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
{
@@ -3713,7 +3618,7 @@ static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeD
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
hi2c->State= HAL_I2C_STATE_READY;
diff --git a/f2/src/stm32f2xx_hal_i2s.c b/f2/src/stm32f2xx_hal_i2s.c
index e31edb92905e95283a9cde07422e3ff1814a1a4e..7080d1f2b4545439d892f999361758d40f98a61f 100755
--- a/f2/src/stm32f2xx_hal_i2s.c
+++ b/f2/src/stm32f2xx_hal_i2s.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_i2s.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
@@ -31,9 +31,9 @@
and HAL_I2S_Receive_DMA() APIs:
(+++) Declare a DMA handle structure for the Tx/Rx stream.
(+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx Stream.
- (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
+ (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
DMA Tx/Rx Stream.
@@ -48,7 +48,7 @@
(+@) External clock source is configured after setting correctly
the define constant EXTERNAL_CLOCK_VALUE in the stm32f2xx_hal_conf.h file.
- (#) Three mode of operations are available within this driver :
+ (#) Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -56,7 +56,7 @@
(+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
(+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
- *** Interrupt mode IO operation ***
+ *** Interrupt mode IO operation ***
===================================
[..]
(+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
@@ -68,11 +68,11 @@
(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2S_ErrorCallback
- *** DMA mode IO operation ***
+ *** DMA mode IO operation ***
==============================
[..]
(+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
@@ -84,32 +84,32 @@
(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2S_ErrorCallback
- (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
- (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
- (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
-
+ (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
+ (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
+ (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
+
*** I2S HAL driver macros list ***
- =============================================
+ =============================================
[..]
Below the list of most used macros in USART HAL driver.
(+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
- (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
+ (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
(+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
(+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
(+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
-
- [..]
+
+ [..]
(@) You can refer to the I2S HAL driver header file for more useful macros
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -143,7 +143,7 @@
* @{
*/
-/** @defgroup I2S
+/** @defgroup I2S I2S
* @brief I2S HAL module driver
* @{
*/
@@ -155,23 +155,35 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup I2S_Private_Functions
+ * @{
+ */
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup I2S_Private_Functions
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2S_Exported_Functions I2S Exported Functions
* @{
*/
-/** @defgroup I2S_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
+/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
- de-initialiaze the I2Sx peripheral in simplex mode:
+ de-initialize the I2Sx peripheral in simplex mode:
(+) User must Implement HAL_I2S_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
@@ -186,7 +198,7 @@ static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
(++) Polarity
(+) Call the function HAL_I2S_DeInit() to restore the default configuration
- of the selected I2Sx periperal.
+ of the selected I2Sx peripheral.
@endverbatim
* @{
*/
@@ -194,10 +206,11 @@ static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
/**
* @brief Initializes the I2S according to the specified parameters
* in the I2S_InitTypeDef and create the associated handle.
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
+__weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
{
uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
uint32_t tmp = 0, i2sclk = 0;
@@ -209,6 +222,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
}
/* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
assert_param(IS_I2S_MODE(hi2s->Init.Mode));
assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
@@ -219,6 +233,8 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
if(hi2s->State == HAL_I2S_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hi2s->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2S_MspInit(hi2s);
}
@@ -332,7 +348,6 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
/* Write to SPIx I2SCFGR */
hi2s->Instance->I2SCFGR = tmpreg;
-
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->State= HAL_I2S_STATE_READY;
@@ -341,7 +356,8 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
/**
* @brief DeInitializes the I2S peripheral
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
@@ -356,43 +372,48 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
HAL_I2S_MspDeInit(hi2s);
-
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->State = HAL_I2S_STATE_RESET;
-
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2s);
+
return HAL_OK;
}
/**
* @brief I2S MSP Init
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_MspInit could be implenetd in the user file
+ the HAL_I2S_MspInit could be implemented in the user file
*/
}
/**
* @brief I2S MSP DeInit
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_MspDeInit could be implenetd in the user file
+ the HAL_I2S_MspDeInit could be implemented in the user file
*/
}
-
/**
* @}
*/
-/** @defgroup I2S_Group2 IO operation functions
- * @brief Data transfers functions
- *
+/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -401,7 +422,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
This subsection provides a set of functions allowing to manage the I2S data
transfers.
- (#) There is two mode of transfer:
+ (#) There are two modes of transfer:
(++) Blocking mode : The communication is performed in the polling mode.
The status of all data processing is returned by the same function
after finishing transfer.
@@ -423,7 +444,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
(++) HAL_I2S_Transmit_DMA()
(++) HAL_I2S_Receive_DMA()
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_I2S_TxCpltCallback()
(++) HAL_I2S_RxCpltCallback()
(++) HAL_I2S_ErrorCallback()
@@ -434,7 +455,8 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
/**
* @brief Transmit an amount of data in blocking mode
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @param pData: a 16-bit pointer to data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
@@ -448,7 +470,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
*/
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tmp1 = 0, tmp2 = 0;
+ uint32_t tmp1 = 0;
if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
@@ -457,9 +479,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
if(hi2s->State == HAL_I2S_STATE_READY)
{
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- if((tmp1 == I2S_DATAFORMAT_24B)|| \
- (tmp2 == I2S_DATAFORMAT_32B))
+
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
{
hi2s->TxXferSize = Size*2;
hi2s->TxXferCount = Size*2;
@@ -491,12 +512,17 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
{
return HAL_TIMEOUT;
}
- }
- /* Wait until Busy flag is reset */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
+ }
+
+ /* Check if Slave mode is selected */
+ if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
{
- return HAL_TIMEOUT;
- }
+ /* Wait until Busy flag is reset */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
hi2s->State = HAL_I2S_STATE_READY;
@@ -513,7 +539,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
/**
* @brief Receive an amount of data in blocking mode
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @param pData: a 16-bit pointer to data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
@@ -524,12 +551,12 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
- * in continouse way and as the I2S is not disabled at the end of the I2S transaction.
+ * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tmp1 = 0, tmp2 = 0;
+ uint32_t tmp1 = 0;
if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
@@ -538,9 +565,8 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
if(hi2s->State == HAL_I2S_STATE_READY)
{
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- if((tmp1 == I2S_DATAFORMAT_24B)|| \
- (tmp2 == I2S_DATAFORMAT_32B))
+
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
{
hi2s->RxXferSize = Size*2;
hi2s->RxXferCount = Size*2;
@@ -598,7 +624,8 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
/**
* @brief Transmit an amount of data in non-blocking mode with Interrupt
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @param pData: a 16-bit pointer to data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
@@ -611,7 +638,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
*/
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- uint32_t tmp1 = 0, tmp2 = 0;
+ uint32_t tmp1 = 0;
if(hi2s->State == HAL_I2S_STATE_READY)
{
if((pData == NULL) || (Size == 0))
@@ -621,9 +648,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
hi2s->pTxBuffPtr = pData;
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- if((tmp1 == I2S_DATAFORMAT_24B)|| \
- (tmp2 == I2S_DATAFORMAT_32B))
+
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
{
hi2s->TxXferSize = Size*2;
hi2s->TxXferCount = Size*2;
@@ -663,7 +689,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
/**
* @brief Receive an amount of data in non-blocking mode with Interrupt
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @param pData: a 16-bit pointer to the Receive data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
@@ -678,7 +705,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
*/
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- uint32_t tmp1 = 0, tmp2 = 0;
+ uint32_t tmp1 = 0;
if(hi2s->State == HAL_I2S_STATE_READY)
{
if((pData == NULL) || (Size == 0))
@@ -688,9 +715,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
hi2s->pRxBuffPtr = pData;
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- if((tmp1 == I2S_DATAFORMAT_24B)||\
- (tmp2 == I2S_DATAFORMAT_32B))
+
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
{
hi2s->RxXferSize = Size*2;
hi2s->RxXferCount = Size*2;
@@ -730,7 +756,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
/**
* @brief Transmit an amount of data in non-blocking mode with DMA
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @param pData: a 16-bit pointer to the Transmit data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
@@ -744,7 +771,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
uint32_t *tmp;
- uint32_t tmp1 = 0, tmp2 = 0;
+ uint32_t tmp1 = 0;
if((pData == NULL) || (Size == 0))
{
@@ -755,9 +782,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
{
hi2s->pTxBuffPtr = pData;
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- if((tmp1 == I2S_DATAFORMAT_24B)|| \
- (tmp2 == I2S_DATAFORMAT_32B))
+
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
{
hi2s->TxXferSize = Size*2;
hi2s->TxXferCount = Size*2;
@@ -774,10 +800,10 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- /* Set the I2S Tx DMA Half transfert complete callback */
+ /* Set the I2S Tx DMA Half transfer complete callback */
hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
- /* Set the I2S Tx DMA transfert complete callback */
+ /* Set the I2S Tx DMA transfer complete callback */
hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
/* Set the DMA error callback */
@@ -814,7 +840,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
/**
* @brief Receive an amount of data in non-blocking mode with DMA
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @param pData: a 16-bit pointer to the Receive data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
@@ -828,7 +855,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
uint32_t *tmp;
- uint32_t tmp1 = 0, tmp2 = 0;
+ uint32_t tmp1 = 0;
if((pData == NULL) || (Size == 0))
{
@@ -839,9 +866,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
{
hi2s->pRxBuffPtr = pData;
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- if((tmp1 == I2S_DATAFORMAT_24B)|| \
- (tmp2 == I2S_DATAFORMAT_32B))
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
{
hi2s->RxXferSize = Size*2;
hi2s->RxXferCount = Size*2;
@@ -857,10 +882,10 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- /* Set the I2S Rx DMA Half transfert complete callback */
+ /* Set the I2S Rx DMA Half transfer complete callback */
hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
- /* Set the I2S Rx DMA transfert complete callback */
+ /* Set the I2S Rx DMA transfer complete callback */
hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
/* Set the DMA error callback */
@@ -905,10 +930,11 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
/**
* @brief Pauses the audio stream playing from the Media.
- * @param hi2s: I2S handle
- * @retval None
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
+__weak HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
{
/* Process Locked */
__HAL_LOCK(hi2s);
@@ -945,10 +971,11 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
/**
* @brief Resumes the audio stream playing from the Media.
- * @param hi2s: I2S handle
- * @retval None
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
+__weak HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
{
/* Process Locked */
__HAL_LOCK(hi2s);
@@ -992,10 +1019,11 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
/**
* @brief Resumes the audio stream playing from the Media.
- * @param hi2s: I2S handle
- * @retval None
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
+__weak HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
{
/* Process Locked */
__HAL_LOCK(hi2s);
@@ -1003,11 +1031,18 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
/* Disable the I2S Tx/Rx DMA requests */
hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
-
- /* Disable the I2S DMA Stream */
- __HAL_DMA_DISABLE(hi2s->hdmatx);
- __HAL_DMA_DISABLE(hi2s->hdmarx);
-
+
+ /* Abort the I2S DMA Stream tx */
+ if(hi2s->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hi2s->hdmatx);
+ }
+ /* Abort the I2S DMA Stream rx */
+ if(hi2s->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hi2s->hdmarx);
+ }
+
/* Disable I2S peripheral */
__HAL_I2S_DISABLE(hi2s);
@@ -1021,50 +1056,51 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
/**
* @brief This function handles I2S interrupt request.
- * @param hi2s: I2S handle
- * @retval HAL status
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
*/
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
{
- uint32_t tmp1 = 0, tmp2 = 0;
+ uint32_t tmp1 = 0, tmp2 = 0;
- if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
- {
- tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
- tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
- /* I2S in mode Receiver ------------------------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
+ if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
- I2S_Receive_IT(hi2s);
- }
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
+ /* I2S in mode Receiver ------------------------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ I2S_Receive_IT(hi2s);
+ }
- tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
- tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
- /* I2S Overrun error interrupt occured ---------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
- {
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
+ /* I2S Overrun error interrupt occurred ---------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ }
}
- }
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
- {
- tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
- tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
- /* I2S in mode Tramitter -----------------------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
{
- I2S_Transmit_IT(hi2s);
- }
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
+ /* I2S in mode Transmitter -----------------------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ I2S_Transmit_IT(hi2s);
+ }
- tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
- tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
- /* I2S Underrun error interrupt occured --------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
- {
- __HAL_I2S_CLEAR_UDRFLAG(hi2s);
- hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
+ /* I2S Underrun error interrupt occurred --------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
}
}
@@ -1079,61 +1115,66 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
/**
* @brief Tx Transfer Half completed callbacks
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_TxHalfCpltCallback could be implenetd in the user file
+ the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
*/
}
/**
* @brief Tx Transfer completed callbacks
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_TxCpltCallback could be implenetd in the user file
+ the HAL_I2S_TxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Rx Transfer half completed callbacks
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_RxCpltCallback could be implenetd in the user file
+ the HAL_I2S_RxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Rx Transfer completed callbacks
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_RxCpltCallback could be implenetd in the user file
+ the HAL_I2S_RxCpltCallback could be implemented in the user file
*/
}
/**
* @brief I2S error callbacks
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_ErrorCallback could be implenetd in the user file
+ the HAL_I2S_ErrorCallback could be implemented in the user file
*/
}
@@ -1141,15 +1182,14 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
* @}
*/
-/** @defgroup I2S_Group3 Peripheral State and Errors functions
- * @brief Peripheral State functions
- *
+/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State functions
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
===============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -1158,7 +1198,8 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
/**
* @brief Return the I2S state
- * @param hi2s : I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval HAL state
*/
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
@@ -1168,24 +1209,25 @@ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
/**
* @brief Return the I2S error code
- * @param hi2s : I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval I2S Error Code
*/
-HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
{
return hi2s->ErrorCode;
}
-
/**
* @}
*/
/**
* @brief DMA I2S transmit process complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
-void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
@@ -1195,7 +1237,7 @@ void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
/* Disable Tx DMA Request */
hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-
+
if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
{
if(hi2s->RxXferCount == 0)
@@ -1213,10 +1255,11 @@ void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA I2S transmit process half complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
-void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
@@ -1225,10 +1268,11 @@ void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA I2S receive process complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
-void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
@@ -1236,7 +1280,6 @@ void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
{
/* Disable Rx DMA Request */
hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-
hi2s->RxXferCount = 0;
if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
{
@@ -1255,10 +1298,11 @@ void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA I2S receive process half complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
-void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
@@ -1267,10 +1311,11 @@ void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA I2S communication error callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
-void I2S_DMAError(DMA_HandleTypeDef *hdma)
+static void I2S_DMAError(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
@@ -1285,7 +1330,8 @@ void I2S_DMAError(DMA_HandleTypeDef *hdma)
/**
* @brief Transmit an amount of data in non-blocking mode with Interrupt
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval HAL status
*/
static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
@@ -1328,7 +1374,8 @@ static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
/**
* @brief Receive an amount of data in non-blocking mode with Interrupt
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval HAL status
*/
static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
@@ -1379,17 +1426,19 @@ static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
/**
* @brief This function handles I2S Communication Timeout.
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @param Flag: Flag checked
- * @param State: Value of the flag expected
+ * @param Status: Value of the flag expected
* @param Timeout: Duration of the timeout
* @retval HAL status
*/
-HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Wait until flag is set */
if(Status == RESET)
@@ -1398,7 +1447,7 @@ HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_
{
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Set the I2S State ready */
hi2s->State= HAL_I2S_STATE_READY;
@@ -1417,7 +1466,7 @@ HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_
{
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Set the I2S State ready */
hi2s->State= HAL_I2S_STATE_READY;
diff --git a/f2/src/stm32f2xx_hal_irda.c b/f2/src/stm32f2xx_hal_irda.c
index dc7e896d451a8d951a6a1b55d1f178e5caf02da1..86f291ad11f9661c348d204d203ef62195763f9b 100755
--- a/f2/src/stm32f2xx_hal_irda.c
+++ b/f2/src/stm32f2xx_hal_irda.c
@@ -2,24 +2,24 @@
******************************************************************************
* @file stm32f2xx_hal_irda.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA SIR ENDEC block (IrDA):
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State and Errors functions
- *
- @verbatim
+ * + Initialization and de-initialization methods
+ * + IO operation methods
+ * + Peripheral Control methods
+ *
+ @verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
- The IRDA HAL driver can be used as follow:
+ The IRDA HAL driver can be used as follows:
(#) Declare a IRDA_HandleTypeDef handle structure.
- (#) Initialize the IRDA low level resources by implement the HAL_IRDA_MspInit() API:
+ (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
(##) Enable the USARTx interface clock.
(##) IRDA pins configuration:
(+++) Enable the clock for the IRDA GPIOs.
@@ -34,7 +34,7 @@
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx Stream.
- (+++) Associate the initilalized DMA handle to the IRDA DMA Tx/Rx handle.
+ (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
(#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
@@ -42,12 +42,12 @@
(#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_IRDA_MspInit() API.
+ by calling the customized HAL_IRDA_MspInit() API.
-@@- The specific IRDA interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
- (#) Three mode of operations are available within this driver :
+ (#) Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -97,7 +97,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -131,7 +131,7 @@
* @{
*/
-/** @defgroup IRDA
+/** @defgroup IRDA IRDA
* @brief HAL IRDA module driver
* @{
*/
@@ -140,25 +140,38 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup IRDA_Private_Constants
+ * @{
+ */
#define IRDA_TIMEOUT_VALUE 22000
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup IRDA_Private_Functions
+ * @{
+ */
static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup IRDA_Private_Functions
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Functions IrDA Exported Functions
* @{
*/
-/** @defgroup IRDA_Group1 IrDA Initialization and de-initialization functions
+/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -175,18 +188,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
(++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible IRDA frame formats are as listed in the following table:
- +-------------------------------------------------------------+
- | M bit | PCE bit | IRDA frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
+ please refer to Reference manual for possible IRDA frame formats.
(++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
specification specifies a minimum of 10 ms delay between transmission and
@@ -204,7 +206,8 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
/**
* @brief Initializes the IRDA mode according to the specified
* parameters in the IRDA_InitTypeDef and create the associated handle.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
@@ -222,6 +225,8 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
if(hirda->State == HAL_IRDA_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hirda->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_IRDA_MspInit(hirda);
}
@@ -229,7 +234,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
hirda->State = HAL_IRDA_STATE_BUSY;
/* Disable the IRDA peripheral */
- __IRDA_DISABLE(hirda);
+ __HAL_IRDA_DISABLE(hirda);
/* Set the IRDA communication parameters */
IRDA_SetConfig(hirda);
@@ -241,7 +246,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL);
/* Enable the IRDA peripheral */
- __IRDA_ENABLE(hirda);
+ __HAL_IRDA_ENABLE(hirda);
/* Set the prescaler */
MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
@@ -261,7 +266,8 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
/**
* @brief DeInitializes the IRDA peripheral
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
@@ -277,6 +283,9 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
hirda->State = HAL_IRDA_STATE_BUSY;
+ /* Disable the Peripheral */
+ __HAL_IRDA_DISABLE(hirda);
+
/* DeInit the low level hardware */
HAL_IRDA_MspDeInit(hirda);
@@ -292,25 +301,27 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
/**
* @brief IRDA MSP Init.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_IRDA_MspInit could be implenetd in the user file
+ the HAL_IRDA_MspInit could be implemented in the user file
*/
}
/**
* @brief IRDA MSP DeInit.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_IRDA_MspDeInit could be implenetd in the user file
+ the HAL_IRDA_MspDeInit could be implemented in the user file
*/
}
@@ -318,7 +329,7 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
* @}
*/
-/** @defgroup IRDA_Group2 IO operation functions
+/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
* @brief IRDA Transmit/Receive functions
*
@verbatim
@@ -333,33 +344,33 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
While receiving data, transmission should be avoided as the data to be transmitted
could be corrupted.
- (#) There are two mode of transfer:
+ (#) There are two modes of transfer:
(++) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
(++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These API's return the HAL status.
+ or DMA, These APIs return the HAL status.
The end of the data processing will be indicated through the
dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
- will be executed respectivelly at the end of the transmit or Receive process
- The HAL_IRDA_ErrorCallback()user callback will be executed when a communication error is detected
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
(#) Blocking mode API's are :
(++) HAL_IRDA_Transmit()
(++) HAL_IRDA_Receive()
- (#) Non-Blocking mode API's with Interrupt are :
+ (#) Non Blocking mode APIs with Interrupt are :
(++) HAL_IRDA_Transmit_IT()
(++) HAL_IRDA_Receive_IT()
(++) HAL_IRDA_IRQHandler()
- (#) No-Blocking mode functions with DMA are :
+ (#) Non Blocking mode functions with DMA are :
(++) HAL_IRDA_Transmit_DMA()
(++) HAL_IRDA_Receive_DMA()
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_IRDA_TxCpltCallback()
(++) HAL_IRDA_RxCpltCallback()
(++) HAL_IRDA_ErrorCallback()
@@ -370,7 +381,8 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
/**
* @brief Sends an amount of data in blocking mode.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @param Timeout: Specify timeout value
@@ -461,7 +473,8 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
/**
* @brief Receive an amount of data in blocking mode.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be received
* @param Timeout: Specify timeout value
@@ -554,7 +567,8 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
/**
* @brief Send an amount of data in non blocking mode.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -586,17 +600,14 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData
hirda->State = HAL_IRDA_STATE_BUSY_TX;
}
- /* Enable the IRDA Parity Error Interrupt */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
-
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
/* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Enable the IRDA Transmit Complete Interrupt */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
+
+ /* Enable the IRDA Transmit Data Register Empty Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE);
return HAL_OK;
}
@@ -608,7 +619,8 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData
/**
* @brief Receives an amount of data in non blocking mode.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be received
* @retval HAL status
@@ -641,18 +653,18 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
hirda->State = HAL_IRDA_STATE_BUSY_RX;
}
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
/* Enable the IRDA Data Register not empty Interrupt */
__HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE);
-
+
/* Enable the IRDA Parity Error Interrupt */
__HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
-
+
/* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
return HAL_OK;
}
else
@@ -663,7 +675,8 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
/**
* @brief Sends an amount of data in non blocking mode.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -698,9 +711,12 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
hirda->State = HAL_IRDA_STATE_BUSY_TX;
}
- /* Set the IRDA DMA transfert complete callback */
+ /* Set the IRDA DMA transfer complete callback */
hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
+ /* Set the IRDA DMA half transfer complete callback */
+ hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
+
/* Set the DMA error callback */
hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
@@ -708,6 +724,9 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size);
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC);
+
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
hirda->Instance->CR3 |= USART_CR3_DMAT;
@@ -725,7 +744,8 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
/**
* @brief Receives an amount of data in non blocking mode.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be received
* @note When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
@@ -759,9 +779,12 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
hirda->State = HAL_IRDA_STATE_BUSY_RX;
}
- /* Set the IRDA DMA transfert complete callback */
+ /* Set the IRDA DMA transfer complete callback */
hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
+ /* Set the IRDA DMA half transfer complete callback */
+ hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
+
/* Set the DMA error callback */
hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
@@ -783,10 +806,131 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
return HAL_BUSY;
}
}
+
+/**
+ * @brief Pauses the DMA Transfer.
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
+{
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ {
+ /* Disable the UART DMA Tx request */
+ hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+ }
+ else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+ {
+ /* Disable the UART DMA Rx request */
+ hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+ }
+ else if (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ /* Disable the UART DMA Tx & Rx requests */
+ hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+ hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_ERROR;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the DMA Transfer.
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
+{
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ {
+ /* Enable the UART DMA Tx request */
+ hirda->Instance->CR3 |= USART_CR3_DMAT;
+ }
+ else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+ {
+ /* Clear the Overrun flag before resuming the Rx transfer */
+ __HAL_IRDA_CLEAR_OREFLAG(hirda);
+ /* Enable the UART DMA Rx request */
+ hirda->Instance->CR3 |= USART_CR3_DMAR;
+ }
+ else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ /* Clear the Overrun flag before resuming the Rx transfer */
+ __HAL_IRDA_CLEAR_OREFLAG(hirda);
+ /* Enable the UART DMA Tx & Rx request */
+ hirda->Instance->CR3 |= USART_CR3_DMAT;
+ hirda->Instance->CR3 |= USART_CR3_DMAR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_ERROR;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the DMA Transfer.
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
+ */
+
+ /* Disable the UART Tx/Rx DMA requests */
+ hirda->Instance->CR3 &= ~USART_CR3_DMAT;
+ hirda->Instance->CR3 &= ~USART_CR3_DMAR;
+
+ /* Abort the UART DMA tx Stream */
+ if(hirda->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hirda->hdmatx);
+ }
+ /* Abort the UART DMA rx Stream */
+ if(hirda->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hirda->hdmarx);
+ }
+
+ hirda->State = HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
/**
* @brief This function handles IRDA interrupt request.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
@@ -795,37 +939,37 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_PE);
tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE);
- /* IRDA parity error interrupt occured -------------------------------------*/
+ /* IRDA parity error interrupt occurred -------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_PE);
+ __HAL_IRDA_CLEAR_PEFLAG(hirda);
hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
}
tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_FE);
tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
- /* IRDA frame error interrupt occured --------------------------------------*/
+ /* IRDA frame error interrupt occurred --------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_FE);
+ __HAL_IRDA_CLEAR_FEFLAG(hirda);
hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
}
tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_NE);
tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
- /* IRDA noise error interrupt occured --------------------------------------*/
+ /* IRDA noise error interrupt occurred --------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_NE);
+ __HAL_IRDA_CLEAR_NEFLAG(hirda);
hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
}
tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_ORE);
tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
- /* IRDA Over-Run interrupt occured -----------------------------------------*/
+ /* IRDA Over-Run interrupt occurred -----------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_ORE);
+ __HAL_IRDA_CLEAR_OREFLAG(hirda);
hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
}
@@ -843,22 +987,29 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
if((tmp1 != RESET) && (tmp2 != RESET))
{
IRDA_Receive_IT(hirda);
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_IT_RXNE);
}
- tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TC);
- tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC);
+ tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TXE);
+ tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE);
/* IRDA in mode Transmitter ------------------------------------------------*/
if((tmp1 != RESET) &&(tmp2 != RESET))
{
IRDA_Transmit_IT(hirda);
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_IT_TC);
}
+
+ tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TC);
+ tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC);
+ /* IRDA in mode Transmitter (transmission end) -----------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ IRDA_EndTransmit_IT(hirda);
+ }
}
/**
* @brief Tx Transfer complete callbacks.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
@@ -868,21 +1019,49 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
*/
}
+/**
+ * @brief Tx Half Transfer completed callbacks.
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+ __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_IRDA_TxHalfCpltCallback could be implemented in the user file
+ */
+}
+
/**
* @brief Rx Transfer complete callbacks.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_IRDA_TxCpltCallback could be implemented in the user file
+ the HAL_IRDA_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer complete callbacks.
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_IRDA_RxHalfCpltCallback could be implemented in the user file
*/
}
/**
* @brief IRDA error callbacks.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
@@ -896,7 +1075,7 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
* @}
*/
-/** @defgroup IRDA_Group3 Peripheral State and Errors functions
+/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief IRDA State and Errors functions
*
@verbatim
@@ -905,9 +1084,9 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
==============================================================================
[..]
This subsection provides a set of functions allowing to return the State of IrDA
- communication process, return Peripheral Errors occured during communication process
+ communication process and also return Peripheral Errors occurred during communication process
(+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IrDA peripheral.
- (+) HAL_IRDA_GetError() check in run-time errors that could be occured durung communication.
+ (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during communication.
@endverbatim
* @{
@@ -915,7 +1094,8 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
/**
* @brief Returns the IRDA state.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL state
*/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
@@ -946,32 +1126,38 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* DMA Normal mode */
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ {
+ hirda->TxXferCount = 0;
- hirda->TxXferCount = 0;
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit
+ in the IRDA CR3 register */
+ hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT);
- /* Wait for IRDA TC Flag */
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, IRDA_TIMEOUT_VALUE) != HAL_OK)
- {
- /* Timeout Occured */
- hirda->State = HAL_IRDA_STATE_TIMEOUT;
- HAL_IRDA_ErrorCallback(hirda);
+ /* Enable the IRDA Transmit Complete Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
}
+ /* DMA Circular mode */
else
{
- /* No Timeout */
- /* Check if a receive process is ongoing or not */
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_RX;
- }
- else
- {
- hirda->State = HAL_IRDA_STATE_READY;
- }
HAL_IRDA_TxCpltCallback(hirda);
}
}
+/**
+ * @brief DMA IRDA receive process half complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_IRDA_TxHalfCpltCallback(hirda);
+}
+
/**
* @brief DMA IRDA receive process complete callback.
* @param hdma: DMA handle
@@ -980,21 +1166,41 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- hirda->RxXferCount = 0;
-
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_TX;
- }
- else
+ /* DMA Normal mode */
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
{
- hirda->State = HAL_IRDA_STATE_READY;
+ hirda->RxXferCount = 0;
+
+ /* Disable the DMA transfer for the receiver request by setting the DMAR bit
+ in the IRDA CR3 register */
+ hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR);
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
}
-
+
HAL_IRDA_RxCpltCallback(hirda);
}
+/**
+ * @brief DMA IRDA receive process half complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_IRDA_RxHalfCpltCallback(hirda);
+}
+
/**
* @brief DMA IRDA communication error callback.
* @param hdma: DMA handle
@@ -1014,7 +1220,8 @@ static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
/**
* @brief This function handles IRDA Communication Timeout.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @param Flag: specifies the IRDA flag to check.
* @param Status: The new Flag status (SET or RESET).
* @param Timeout: Timeout duration
@@ -1022,9 +1229,10 @@ static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
*/
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Wait until flag is set */
if(Status == RESET)
@@ -1034,7 +1242,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
@@ -1059,7 +1267,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
@@ -1082,7 +1290,8 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
/**
* @brief Send an amount of data in non blocking mode.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
@@ -1093,9 +1302,6 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
tmp1 = hirda->State;
if((tmp1 == HAL_IRDA_STATE_BUSY_TX) || (tmp1 == HAL_IRDA_STATE_BUSY_TX_RX))
{
- /* Process Locked */
- __HAL_LOCK(hirda);
-
if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
{
tmp = (uint16_t*) hirda->pTxBuffPtr;
@@ -1116,45 +1322,54 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
if(--hirda->TxXferCount == 0)
{
- /* Disable the IRDA Transmit Complete Interrupt */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
+ /* Disable the IRDA Transmit Data Register Empty Interrupt */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_RX;
- }
- else
- {
- /* Disable the IRDA Parity Error Interrupt */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
-
- /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
- hirda->State = HAL_IRDA_STATE_READY;
- }
- /* Call the Process Unlocked before calling the Tx call back API to give the possibiity to
- start again the Transmission under the Tx call back API */
- __HAL_UNLOCK(hirda);
-
- HAL_IRDA_TxCpltCallback(hirda);
-
- return HAL_OK;
+ /* Enable the IRDA Transmit Complete Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
}
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
+/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable the IRDA Transmit Complete Interrupt */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
+
+ /* Check if a receive process is ongoing or not */
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ HAL_IRDA_TxCpltCallback(hirda);
+
+ return HAL_OK;
+}
+
/**
* @brief Receives an amount of data in non blocking mode.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
@@ -1165,9 +1380,6 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
tmp1 = hirda->State;
if((tmp1 == HAL_IRDA_STATE_BUSY_RX) || (tmp1 == HAL_IRDA_STATE_BUSY_TX_RX))
{
- /* Process Locked */
- __HAL_LOCK(hirda);
-
if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
{
tmp = (uint16_t*) hirda->pRxBuffPtr;
@@ -1196,9 +1408,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
if(--hirda->RxXferCount == 0)
{
- while(HAL_IS_BIT_SET(hirda->Instance->SR, IRDA_FLAG_RXNE))
- {
- }
+
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
@@ -1215,18 +1425,10 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
hirda->State = HAL_IRDA_STATE_READY;
}
- /* Call the Process Unlocked before calling the Rx call back API to give the possibiity to
- start again the receiption under the Rx call back API */
- __HAL_UNLOCK(hirda);
-
HAL_IRDA_RxCpltCallback(hirda);
return HAL_OK;
}
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
return HAL_OK;
}
else
@@ -1237,7 +1439,8 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
/**
* @brief Configures the IRDA peripheral.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
@@ -1278,23 +1481,22 @@ static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
/*-------------------------- USART BRR Configuration -----------------------*/
if((hirda->Instance == USART1) || (hirda->Instance == USART6))
{
- hirda->Instance->BRR = __IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate);
+ hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate);
}
else
{
- hirda->Instance->BRR = __IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate);
+ hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate);
}
}
/**
* @}
*/
+#endif /* HAL_IRDA_MODULE_ENABLED */
/**
* @}
*/
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
/**
* @}
*/
diff --git a/f2/src/stm32f2xx_hal_iwdg.c b/f2/src/stm32f2xx_hal_iwdg.c
index c56c16134da1dd0a7bca91f4193e67c1a7b71a39..3d433a5b6ababcb85f5113fce8fd8bc3aef3cd68 100755
--- a/f2/src/stm32f2xx_hal_iwdg.c
+++ b/f2/src/stm32f2xx_hal_iwdg.c
@@ -2,18 +2,18 @@
******************************************************************************
* @file stm32f2xx_hal_iwdg.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
- * + Initialization and de-initialization functions
+ * + Initialization and Configuration functions
* + IO operation functions
* + Peripheral State functions
*
@verbatim
==============================================================================
- ##### IWDG Generic features #####
+ ##### IWDG Specific features #####
==============================================================================
[..]
(+) The IWDG can be started by either software or hardware (configurable
@@ -43,13 +43,28 @@
##### How to use this driver #####
==============================================================================
+ [..]
+ If Window option is disabled
+ (+) Use IWDG using HAL_IWDG_Init() function to :
+ (++) Enable write access to IWDG_PR, IWDG_RLR.
+ (++) Configure the IWDG prescaler, counter reload value.
+ This reload value will be loaded in the IWDG counter each time the counter
+ is reloaded, then the IWDG will start counting down from this value.
[..]
(+) Use IWDG using HAL_IWDG_Start() function to:
- (++) Enable write access to IWDG_PR and IWDG_RLR registers.
- (++) Configure the IWDG prescaler and counter reload values.
(++) Reload IWDG counter with value defined in the IWDG_RLR register.
(++) Start the IWDG, when the IWDG is used in software mode (no need
to enable the LSI, it will be enabled by hardware).
+ (+) Then the application program must refresh the IWDG counter at regular
+ intervals during normal operation to prevent an MCU reset, using
+ HAL_IWDG_Refresh() function.
+ [..]
+ if Window option is enabled:
+
+ (+) Use IWDG using HAL_IWDG_Start() function to enable IWDG downcounter
+ (+) Use IWDG using HAL_IWDG_Init() function to :
+ (++) Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+ (++) Configure the IWDG prescaler, reload value and window value.
(+) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_IWDG_Refresh() function.
@@ -61,16 +76,13 @@
(+) __HAL_IWDG_START: Enable the IWDG peripheral
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register
- (+) __HAL_IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers
- (+) __HAL_IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers
(+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
- (+) __HAL_IWDG_CLEAR_FLAG: Clear the IWDG's pending flags
-
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -104,7 +116,7 @@
* @{
*/
-/** @defgroup IWDG
+/** @defgroup IWDG IWDG
* @brief IWDG HAL module driver.
* @{
*/
@@ -113,16 +125,23 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+ /** @addtogroup IWDG_Private_Constants
+ * @{
+ */
+#define IWDG_TIMEOUT_FLAG ((uint32_t)1000) /* 1 s */
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup IWDG_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
* @{
*/
-/** @defgroup IWDG_Group1 Initialization and de-initialization functions
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
@@ -142,13 +161,12 @@
/**
* @brief Initializes the IWDG according to the specified
* parameters in the IWDG_InitTypeDef and creates the associated handle.
- * @param hiwdg: IWDG handle
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
{
- uint32_t tmp;
-
/* Check the IWDG handle allocation */
if(hiwdg == NULL)
{
@@ -156,11 +174,14 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
}
/* Check the parameters */
+ assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
if(hiwdg->State == HAL_IWDG_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hiwdg->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_IWDG_MspInit(hiwdg);
}
@@ -168,34 +189,12 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_BUSY;
- /* Set IWDG counter clock prescaler */
- /* Get the PR register value */
- tmp = hiwdg->Instance->PR;
-
- /* Clear PR[2:0] bits */
- tmp &= ((uint32_t)~(IWDG_PR_PR));
-
- /* Prepare the IWDG Prescaler parameter */
- tmp |= hiwdg->Init.Prescaler;
-
/* Enable write access to IWDG_PR and IWDG_RLR registers */
- __HAL_IWDG_ENABLE_WRITE_ACCESS(hiwdg);
+ IWDG_ENABLE_WRITE_ACCESS(hiwdg);
- /* Write to IWDG PR */
- hiwdg->Instance->PR = tmp;
-
- /* Set IWDG counter reload value */
- /* Get the RLR register value */
- tmp = hiwdg->Instance->RLR;
-
- /* Clear RL[11:0] bits */
- tmp &= ((uint32_t)~(IWDG_RLR_RL));
-
- /* Prepare the IWDG Prescaler parameter */
- tmp |= hiwdg->Init.Reload;
-
- /* Write to IWDG RLR */
- hiwdg->Instance->RLR = tmp;
+ /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
+ MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler);
+ MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload);
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_READY;
@@ -206,7 +205,8 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
/**
* @brief Initializes the IWDG MSP.
- * @param hiwdg: IWDG handle
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
* @retval None
*/
__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
@@ -220,7 +220,7 @@ __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
* @}
*/
-/** @defgroup IWDG_Group2 IO operation functions
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
@@ -237,7 +237,8 @@ __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
/**
* @brief Starts the IWDG.
- * @param hiwdg: IWDG handle
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
@@ -266,19 +267,36 @@ HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
/**
* @brief Refreshes the IWDG.
- * @param hiwdg: IWDG handle
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
{
+ uint32_t tickstart = 0;
+
/* Process Locked */
- __HAL_LOCK(hiwdg);
-
+ __HAL_LOCK(hiwdg);
+
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_BUSY;
-
- /* Clear the RVU flag */
- __HAL_IWDG_CLEAR_FLAG(hiwdg, IWDG_FLAG_RVU);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait until RVU flag is RESET */
+ while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > IWDG_TIMEOUT_FLAG)
+ {
+ /* Set IWDG state */
+ hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hiwdg);
+
+ return HAL_TIMEOUT;
+ }
+ }
/* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
@@ -297,7 +315,7 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
* @}
*/
-/** @defgroup IWDG_Group3 Peripheral State functions
+/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
@@ -314,7 +332,8 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
/**
* @brief Returns the IWDG state.
- * @param hiwdg: IWDG handle
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
* @retval HAL state
*/
HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
diff --git a/f2/src/stm32f2xx_hal_nand.c b/f2/src/stm32f2xx_hal_nand.c
index 7bc9bc7c31352c678b6fd393d153a4323f81a328..525a4a8b92930aacc57efc030079180774cb018e 100755
--- a/f2/src/stm32f2xx_hal_nand.c
+++ b/f2/src/stm32f2xx_hal_nand.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_nand.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief NAND HAL module driver.
* This file provides a generic firmware to drive NAND memories mounted
* as external device.
@@ -11,10 +11,10 @@
@verbatim
==============================================================================
##### How to use this driver #####
- ==============================================================================
+ ==============================================================================
[..]
This driver is a generic layered driver which contains a set of APIs used to
- control NAND flash memories. It uses the FMC/FSMC layer functions to interface
+ control NAND flash memories. It uses the FSMC layer functions to interface
with NAND devices. This driver is used as follows:
(+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
@@ -55,7 +55,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -89,23 +89,41 @@
* @{
*/
-/** @defgroup NAND
- * @brief NAND driver modules
+
+#ifdef HAL_NAND_MODULE_ENABLED
+
+
+/** @defgroup NAND NAND
+ * @brief NAND HAL module driver
* @{
*/
-#ifdef HAL_NAND_MODULE_ENABLED
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @defgroup NAND_Private_Constants NAND Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/* Private macro -------------------------------------------------------------*/
+/** @defgroup NAND_Private_Macros NAND Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup NAND_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup NAND_Exported_Functions NAND Exported Functions
* @{
*/
-/** @defgroup NAND_Group1 Initialization and de-initialization functions
+/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -122,12 +140,13 @@
/**
* @brief Perform NAND memory Initialization sequence
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @param ComSpace_Timing: pointer to Common space timing structure
* @param AttSpace_Timing: pointer to Attribute space timing structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
{
/* Check the NAND handle state */
if(hnand == NULL)
@@ -137,21 +156,23 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT
if(hnand->State == HAL_NAND_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hnand->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_NAND_MspInit(hnand);
}
/* Initialize NAND control Interface */
- FMC_NAND_Init(hnand->Instance, &(hnand->Init));
+ FSMC_NAND_Init(hnand->Instance, &(hnand->Init));
/* Initialize NAND common space timing Interface */
- FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
+ FSMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
/* Initialize NAND attribute space timing Interface */
- FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
+ FSMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
/* Enable the NAND device */
- __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
+ __FSMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
@@ -161,7 +182,8 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT
/**
* @brief Perform NAND memory De-Initialization sequence
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
@@ -170,7 +192,7 @@ HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
HAL_NAND_MspDeInit(hnand);
/* Configure the NAND registers with their reset values */
- FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
+ FSMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
/* Reset the NAND controller state */
hnand->State = HAL_NAND_STATE_RESET;
@@ -183,7 +205,8 @@ HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
/**
* @brief NAND MSP Init
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval None
*/
__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
@@ -195,7 +218,8 @@ __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
/**
* @brief NAND MSP DeInit
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval None
*/
__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
@@ -208,56 +232,58 @@ __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
/**
* @brief This function handles NAND device interrupt request.
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval HAL status
*/
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
{
/* Check NAND interrupt Rising edge flag */
- if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
+ if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE))
{
/* NAND interrupt callback*/
HAL_NAND_ITCallback(hnand);
/* Clear NAND interrupt Rising edge pending bit */
- __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
+ __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE);
}
/* Check NAND interrupt Level flag */
- if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
+ if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL))
{
/* NAND interrupt callback*/
HAL_NAND_ITCallback(hnand);
/* Clear NAND interrupt Level pending bit */
- __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
+ __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL);
}
/* Check NAND interrupt Falling edge flag */
- if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
+ if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE))
{
/* NAND interrupt callback*/
HAL_NAND_ITCallback(hnand);
/* Clear NAND interrupt Falling edge pending bit */
- __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
+ __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE);
}
/* Check NAND interrupt FIFO empty flag */
- if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
+ if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT))
{
/* NAND interrupt callback*/
HAL_NAND_ITCallback(hnand);
/* Clear NAND interrupt FIFO empty pending bit */
- __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
+ __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT);
}
}
/**
* @brief NAND interrupt feature callback
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval None
*/
__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
@@ -271,7 +297,10 @@ __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
* @}
*/
-/** @defgroup NAND_Group2 Input and Output functions
+
+
+
+/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
* @brief Input Output and memory control functions
*
@verbatim
@@ -288,14 +317,15 @@ __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
/**
* @brief Read the NAND memory electronic signature
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @param pNAND_ID: NAND ID structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
{
__IO uint32_t data = 0;
- uint32_t deviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -307,98 +337,101 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN
}
/* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
{
- deviceAddress = NAND_DEVICE1;
+ deviceaddress = NAND_DEVICE1;
}
else
{
- deviceAddress = NAND_DEVICE2;
+ deviceaddress = NAND_DEVICE2;
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
- /* Send Read ID command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x90;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
+ /* Send Read ID command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- /* Read the electronic signature from NAND flash */
- data = *(__IO uint32_t *)deviceAddress;
+ /* Read the electronic signature from NAND flash */
+ data = *(__IO uint32_t *)deviceaddress;
/* Return the data read */
- pNAND_ID->Maker_Id = ADDR_1st_CYCLE(data);
- pNAND_ID->Device_Id = ADDR_2nd_CYCLE(data);
- pNAND_ID->Third_Id = ADDR_3rd_CYCLE(data);
- pNAND_ID->Fourth_Id = ADDR_4th_CYCLE(data);
+ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
+ pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
+ pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
+ pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
+ __HAL_UNLOCK(hnand);
return HAL_OK;
}
/**
* @brief NAND memory reset
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
{
- uint32_t deviceAddress = 0;
-
+ uint32_t deviceaddress = 0;
+
/* Process Locked */
__HAL_LOCK(hnand);
-
+
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
- /* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
{
- deviceAddress = NAND_DEVICE1;
+ deviceaddress = NAND_DEVICE1;
}
else
{
- deviceAddress = NAND_DEVICE2;
+ deviceaddress = NAND_DEVICE2;
}
- /* Update the NAND controller state */
+ /* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Send NAND reset command */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;
-
-
- /* Update the NAND controller state */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
+
+
+ /* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
-
+ __HAL_UNLOCK(hnand);
+
return HAL_OK;
-
-}
+}
/**
* @brief Read Page(s) from NAND memory block
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
* @param pBuffer : pointer to destination read buffer
* @param NumPageToRead : number of pages to read from block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
+HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
{
__IO uint32_t index = 0;
- uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
+ uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS;
+ NAND_AddressTypeDef nandaddress;
+ uint32_t addressoffset = 0;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -410,83 +443,90 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType
}
/* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
{
- deviceAddress = NAND_DEVICE1;
+ deviceaddress = NAND_DEVICE1;
}
else
{
- deviceAddress = NAND_DEVICE2;
+ deviceaddress = NAND_DEVICE2;
}
- /* Update the NAND controller state */
+ /* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
- /* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
-
+ /* Save the content of pAddress as it will be modified */
+ nandaddress.Block = pAddress->Block;
+ nandaddress.Page = pAddress->Page;
+ nandaddress.Zone = pAddress->Zone;
+
/* Page(s) read loop */
- while((NumPageToRead != 0) && (nandAddress < (hnand->Info.BlockSize) * (hnand->Info.PageSize)))
- {
+ while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ {
/* update the buffer size */
- size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead);
+ size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
+
+ /* Get the address offset */
+ addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
/* Send read page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
- /* for 512 and 1 GB devices, 4th cycle is required */
+ /* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x30;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
/* Get Data into Buffer */
- for(; index < size; index++)
+ for(index = size; index != 0; index--)
{
- *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
+ *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
}
/* Increment read pages number */
- numPagesRead++;
+ numpagesread++;
/* Decrement pages to read */
NumPageToRead--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
-
+ addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
}
- /* Update the NAND controller state */
+ /* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
-
+ __HAL_UNLOCK(hnand);
+
return HAL_OK;
}
/**
* @brief Write Page(s) to NAND memory block
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
* @param pBuffer : pointer to source buffer to write
* @param NumPageToWrite : number of pages to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
+HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
{
__IO uint32_t index = 0;
- uint32_t timeout = 0;
- uint32_t deviceAddress = 0, size = 0 , numPagesWritten = 0, nandAddress = 0;
+ uint32_t tickstart = 0;
+ uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS;
+ NAND_AddressTypeDef nandaddress;
+ uint32_t addressoffset = 0;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -498,95 +538,101 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp
}
/* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
{
- deviceAddress = NAND_DEVICE1;
+ deviceaddress = NAND_DEVICE1;
}
else
{
- deviceAddress = NAND_DEVICE2;
+ deviceaddress = NAND_DEVICE2;
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
- /* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
-
+ /* Save the content of pAddress as it will be modified */
+ nandaddress.Block = pAddress->Block;
+ nandaddress.Page = pAddress->Page;
+ nandaddress.Zone = pAddress->Zone;
+
/* Page(s) write loop */
- while((NumPageToWrite != 0) && (nandAddress < (hnand->Info.BlockSize) * (hnand->Info.PageSize)))
- {
+ while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ {
/* update the buffer size */
- size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten);
-
+ size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
+
+ /* Get the address offset */
+ addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
+
/* Send write page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x80;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
}
/* Write data to memory */
- for(; index < size; index++)
+ for(index = size; index != 0; index--)
{
- *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
+ *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x10;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
{
- /* Check for timeout value */
- timeout = HAL_GetTick() + NAND_WRITE_TIMEOUT;
-
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
- }
- }
+ }
+ }
/* Increment written pages number */
- numPagesWritten++;
+ numpageswritten++;
/* Decrement pages to write */
NumPageToWrite--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
-
+ addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
+ __HAL_UNLOCK(hnand);
return HAL_OK;
}
-
/**
* @brief Read Spare area(s) from NAND memory
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
* @param pBuffer: pointer to source buffer to write
* @param NumSpareAreaToRead: Number of spare area to read
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
{
__IO uint32_t index = 0;
- uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0;
+ uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS;
+ NAND_AddressTypeDef nandaddress;
+ uint32_t addressoffset = 0;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -598,82 +644,89 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres
}
/* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
{
- deviceAddress = NAND_DEVICE1;
+ deviceaddress = NAND_DEVICE1;
}
else
{
- deviceAddress = NAND_DEVICE2;
+ deviceaddress = NAND_DEVICE2;
}
/* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
+ hnand->State = HAL_NAND_STATE_BUSY;
- /* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ /* Save the content of pAddress as it will be modified */
+ nandaddress.Block = pAddress->Block;
+ nandaddress.Page = pAddress->Page;
+ nandaddress.Zone = pAddress->Zone;
/* Spare area(s) read loop */
- while((NumSpareAreaToRead != 0) && (nandAddress < (hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize)))
+ while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
{
-
/* update the buffer size */
- size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numSpareAreaRead);
+ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
+
+ /* Get the address offset */
+ addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
/* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x30;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
/* Get Data into Buffer */
- for ( ;index < size; index++)
+ for (index = size ;index != 0; index--)
{
- *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
+ *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
}
/* Increment read spare areas number */
- numSpareAreaRead++;
+ num_spare_area_read++;
/* Decrement spare areas to read */
NumSpareAreaToRead--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize));
+ addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
+ __HAL_UNLOCK(hnand);
return HAL_OK;
}
/**
* @brief Write Spare area(s) to NAND memory
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
* @param pBuffer : pointer to source buffer to write
* @param NumSpareAreaTowrite : number of spare areas to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
__IO uint32_t index = 0;
- uint32_t timeout = 0;
- uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0;
+ uint32_t tickstart = 0;
+ uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS;
+ NAND_AddressTypeDef nandaddress;
+ uint32_t addressoffset = 0;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -685,72 +738,75 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre
}
/* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
{
- deviceAddress = NAND_DEVICE1;
+ deviceaddress = NAND_DEVICE1;
}
else
{
- deviceAddress = NAND_DEVICE2;
+ deviceaddress = NAND_DEVICE2;
}
- /* Update the FMC_NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ /* Update the FSMC_NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Save the content of pAddress as it will be modified */
+ nandaddress.Block = pAddress->Block;
+ nandaddress.Page = pAddress->Page;
+ nandaddress.Zone = pAddress->Zone;
/* Spare area(s) write loop */
- while((NumSpareAreaTowrite != 0) && (nandAddress < (hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize)))
- {
+ while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ {
/* update the buffer size */
- size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numSpareAreaWritten);
+ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
+ /* Get the address offset */
+ addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
+
/* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x80;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
}
/* Write data to memory */
for(; index < size; index++)
{
- *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
+ *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x10;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
-
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
{
- /* Check for timeout value */
- timeout = HAL_GetTick() + NAND_WRITE_TIMEOUT;
-
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
- }
+ }
}
/* Increment written spare areas number */
- numSpareAreaWritten++;
+ num_spare_area_written++;
/* Decrement spare areas to write */
NumSpareAreaTowrite--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize));
-
+ addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
}
/* Update the NAND controller state */
@@ -759,18 +815,20 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre
/* Process unlocked */
__HAL_UNLOCK(hnand);
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief NAND memory Block erase
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress)
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
{
- uint32_t DeviceAddress = 0;
+ uint32_t deviceaddress = 0;
+ uint32_t tickstart = 0;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -782,68 +840,83 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy
}
/* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
{
- DeviceAddress = NAND_DEVICE1;
+ deviceaddress = NAND_DEVICE1;
}
else
{
- DeviceAddress = NAND_DEVICE2;
+ deviceaddress = NAND_DEVICE2;
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Send Erase block command sequence */
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = 0x60;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
}
-
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = 0xD0;
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_OK;
}
-
/**
* @brief NAND memory read status
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval NAND status
*/
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
{
uint32_t data = 0;
- uint32_t DeviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
{
- DeviceAddress = NAND_DEVICE1;
+ deviceaddress = NAND_DEVICE1;
}
else
{
- DeviceAddress = NAND_DEVICE2;
+ deviceaddress = NAND_DEVICE2;
}
/* Send Read status operation command */
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = 0x70;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
/* Read status register data */
- data = *(__IO uint8_t *)DeviceAddress;
+ data = *(__IO uint8_t *)deviceaddress;
/* Return the status */
if((data & NAND_ERROR) == NAND_ERROR)
@@ -856,18 +929,18 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
}
return NAND_BUSY;
-
}
/**
* @brief Increment the NAND memory address
- * @param hnand: pointer to NAND handle
- * @param pAddress: pointer to NAND adress structure
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress: pointer to NAND address structure
* @retval The new status of the increment address operation. It can be:
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
*/
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress)
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
{
uint32_t status = NAND_VALID_ADDRESS;
@@ -894,13 +967,11 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pA
return (status);
}
-
-
/**
* @}
*/
-/** @defgroup NAND_Group3 Control functions
+/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
* @brief management functions
*
@verbatim
@@ -918,7 +989,8 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pA
/**
* @brief Enables dynamically NAND ECC feature.
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
@@ -933,21 +1005,21 @@ HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
hnand->State = HAL_NAND_STATE_BUSY;
/* Enable ECC feature */
- FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
+ FSMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
/* Update the NAND state */
hnand->State = HAL_NAND_STATE_READY;
- return HAL_OK;
+ return HAL_OK;
}
-
/**
- * @brief Disables dynamically FMC_NAND ECC feature.
- * @param hnand: pointer to NAND handle
+ * @brief Disables dynamically FSMC_NAND ECC feature.
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
{
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
@@ -959,7 +1031,7 @@ HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
hnand->State = HAL_NAND_STATE_BUSY;
/* Disable ECC feature */
- FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
+ FSMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
/* Update the NAND state */
hnand->State = HAL_NAND_STATE_READY;
@@ -969,7 +1041,8 @@ HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
/**
* @brief Disables dynamically NAND ECC feature.
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @param ECCval: pointer to ECC value
* @param Timeout: maximum timeout to wait
* @retval HAL status
@@ -988,20 +1061,20 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
hnand->State = HAL_NAND_STATE_BUSY;
/* Get NAND ECC value */
- status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
+ status = FSMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
/* Update the NAND state */
hnand->State = HAL_NAND_STATE_READY;
return status;
}
-
+
/**
* @}
*/
-/** @defgroup NAND_Group4 State functions
+/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
@@ -1009,7 +1082,7 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
##### NAND State functions #####
==============================================================================
[..]
- This subsection permit to get in run-time the status of the NAND controller
+ This subsection permits to get in run-time the status of the NAND controller
and the data flow.
@endverbatim
@@ -1018,7 +1091,8 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
/**
* @brief return the NAND state
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval HAL state
*/
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
@@ -1033,12 +1107,13 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
/**
* @}
*/
-#endif /* HAL_NAND_MODULE_ENABLED */
/**
* @}
*/
+#endif /* HAL_NAND_MODULE_ENABLED */
+
/**
* @}
*/
diff --git a/f2/src/stm32f2xx_hal_nor.c b/f2/src/stm32f2xx_hal_nor.c
index e9f040a14ddbb8ac29d04a0714fc402f125e8dd2..474511a9d22071a5ba116a286b7fd97f00963cc7 100755
--- a/f2/src/stm32f2xx_hal_nor.c
+++ b/f2/src/stm32f2xx_hal_nor.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_nor.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.
@@ -14,7 +14,7 @@
==============================================================================
[..]
This driver is a generic layered driver which contains a set of APIs used to
- control NOR flash memories. It uses the FMC/FSMC layer functions to interface
+ control NOR flash memories. It uses the FSMC layer functions to interface
with NOR devices. This driver is used as follows:
(+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
@@ -49,13 +49,13 @@
[..]
Below the list of most used macros in NOR HAL driver.
- (+) __NOR_WRITE : NOR memory write data to specified address
+ (+) NOR_WRITE : NOR memory write data to specified address
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -89,26 +89,60 @@
* @{
*/
-/** @defgroup NOR
+/** @defgroup NOR NOR
* @brief NOR driver modules
* @{
*/
#ifdef HAL_NOR_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup NOR_Private_Defines NOR Private Defines
+ * @{
+ */
+
+/* Constants to define address to set to write a command */
+#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
+#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
+
+/* Constants to define data to program a command */
+#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
+#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
+#define NOR_CMD_DATA_SECOND (uint16_t)0x0055
+#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
+#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
+#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
+#define NOR_CMD_DATA_CFI (uint16_t)0x0098
+
+#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
+#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
+#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
+
+/* Mask on NOR STATUS REGISTER */
+#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
+#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup NOR_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup NOR_Exported_Functions NOR Exported Functions
* @{
*/
-/** @defgroup NOR_Group1 Initialization and de-initialization functions
+/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -125,12 +159,12 @@
/**
* @brief Perform the NOR memory Initialization sequence
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to the NOR handle
* @param Timing: pointer to NOR control timing structure
* @param ExtTiming: pointer to NOR extended mode timing structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
{
/* Check the NOR handle parameter */
if(hnor == NULL)
@@ -140,21 +174,23 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
if(hnor->State == HAL_NOR_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hnor->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_NOR_MspInit(hnor);
}
-
+
/* Initialize NOR control Interface */
- FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
+ FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
/* Initialize NOR timing Interface */
- FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
+ FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
/* Initialize NOR extended mode timing Interface */
- FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
+ FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
/* Enable the NORSRAM device */
- __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
+ __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -164,7 +200,8 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
/**
* @brief Perform NOR memory De-Initialization sequence
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
@@ -173,7 +210,7 @@ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
HAL_NOR_MspDeInit(hnor);
/* Configure the NOR registers with their reset values */
- FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
+ FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_RESET;
@@ -186,7 +223,8 @@ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
/**
* @brief NOR MSP Init
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @retval None
*/
__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
@@ -198,7 +236,8 @@ __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
/**
* @brief NOR MSP DeInit
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @retval None
*/
__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
@@ -209,8 +248,9 @@ __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
}
/**
- * @brief NOR BSP Wait fro Ready/Busy signal
- * @param hnor: pointer to NOR handle
+ * @brief NOR BSP Wait for Ready/Busy signal
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @param Timeout: Maximum timeout value
* @retval None
*/
@@ -225,7 +265,7 @@ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
* @}
*/
-/** @defgroup NOR_Group2 Input and Output functions
+/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
* @brief Input Output and memory control functions
*
@verbatim
@@ -241,12 +281,14 @@ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
/**
* @brief Read NOR flash IDs
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to the NOR handle
* @param pNOR_ID : pointer to NOR ID structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
{
+ uint32_t deviceaddress = 0;
+
/* Process Locked */
__HAL_LOCK(hnor);
@@ -255,20 +297,38 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
{
return HAL_BUSY;
}
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FSMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send read ID command */
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA);
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055);
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x0090);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
/* Read the NOR IDs */
- pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) __NOR_ADDR_SHIFT(MC_ADDRESS);
- pNOR_ID->Device_Code1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(DEVICE_CODE1_ADDR);
- pNOR_ID->Device_Code2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(DEVICE_CODE2_ADDR);
- pNOR_ID->Device_Code3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(DEVICE_CODE3_ADDR);
+ pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, MC_ADDRESS);
+ pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);
+ pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);
+ pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -281,11 +341,13 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
/**
* @brief Returns the NOR memory to Read mode.
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to the NOR handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
{
+ uint32_t deviceaddress = 0;
+
/* Process Locked */
__HAL_LOCK(hnor);
@@ -295,7 +357,25 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
return HAL_BUSY;
}
- __NOR_WRITE(NOR_MEMORY_ADRESS, 0x00F0);
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FSMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -308,13 +388,15 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
/**
* @brief Read data from NOR memory
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to the NOR handle
* @param pAddress: pointer to Device address
* @param pData : pointer to read data
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
{
+ uint32_t deviceaddress = 0;
+
/* Process Locked */
__HAL_LOCK(hnor);
@@ -323,17 +405,35 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
{
return HAL_BUSY;
}
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FSMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send read data command */
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x00555), 0x00AA);
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x002AA), 0x0055);
- __NOR_WRITE(*pAddress, 0x00F0);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
/* Read the data */
- *pData = *(__IO uint32_t *)pAddress;
+ *pData = *(__IO uint32_t *)(uint32_t)pAddress;
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -346,13 +446,15 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
/**
* @brief Program data to NOR memory
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to the NOR handle
* @param pAddress: Device address
* @param pData : pointer to the data to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
{
+ uint32_t deviceaddress = 0;
+
/* Process Locked */
__HAL_LOCK(hnor);
@@ -361,17 +463,35 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
{
return HAL_BUSY;
}
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FSMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send program data command */
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA);
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055);
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00A0);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
/* Write the data */
- __NOR_WRITE(pAddress, *pData);
+ NOR_WRITE(pAddress, *pData);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -383,8 +503,8 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
}
/**
- * @brief Reads a block of data from the FMC NOR memory.
- * @param hnor: pointer to NOR handle
+ * @brief Reads a half-word buffer from the NOR memory.
+ * @param hnor: pointer to the NOR handle
* @param uwAddress: NOR memory internal address to read from.
* @param pData: pointer to the buffer that receives the data read from the
* NOR memory.
@@ -393,6 +513,8 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
*/
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
{
+ uint32_t deviceaddress = 0;
+
/* Process Locked */
__HAL_LOCK(hnor);
@@ -401,14 +523,32 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
{
return HAL_BUSY;
}
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FSMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send read data command */
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x00555), 0x00AA);
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x002AA), 0x0055);
- __NOR_WRITE(uwAddress, 0x00F0);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(uwAddress, 0x00F0);
/* Read buffer */
while( uwBufferSize > 0)
@@ -428,20 +568,20 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
}
/**
- * @brief Writes a half-word buffer to the FMC NOR memory. This function
- * must be used only with S29GL128P NOR memory.
- * @param hnor: pointer to NOR handle
- * @param uwAddress: NOR memory internal address from which the data
+ * @brief Writes a half-word buffer to the NOR memory. This function must be used
+ only with S29GL128P NOR memory.
+ * @param hnor: pointer to the NOR handle
+ * @param uwAddress: NOR memory internal start write address
* @param pData: pointer to source data buffer.
- * @param uwBufferSize: number of Half words to write. The maximum allowed
+ * @param uwBufferSize: Size of the buffer to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
{
- uint32_t lastloadedaddress = 0;
- uint32_t currentaddress = 0;
- uint32_t endaddress = 0;
-
+ uint16_t * p_currentaddress = (uint16_t *)NULL;
+ uint16_t * p_endaddress = (uint16_t *)NULL;
+ uint32_t lastloadedaddress = 0, deviceaddress = 0;
+
/* Process Locked */
__HAL_LOCK(hnor);
@@ -450,35 +590,53 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
{
return HAL_BUSY;
}
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FSMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Initialize variables */
- currentaddress = uwAddress;
- endaddress = uwAddress + uwBufferSize - 1;
- lastloadedaddress = uwAddress;
+ p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
+ p_endaddress = p_currentaddress + (uwBufferSize-1);
+ lastloadedaddress = (uint32_t)(uwAddress);
/* Issue unlock command sequence */
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA);
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
/* Write Buffer Load Command */
- __NOR_WRITE(__NOR_ADDR_SHIFT(uwAddress), 0x25);
- __NOR_WRITE(__NOR_ADDR_SHIFT(uwAddress), (uwBufferSize - 1));
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1));
/* Load Data into NOR Buffer */
- while(currentaddress <= endaddress)
+ while(p_currentaddress <= p_endaddress)
{
/* Store last loaded address & data value (for polling) */
- lastloadedaddress = currentaddress;
+ lastloadedaddress = (uint32_t)p_currentaddress;
- __NOR_WRITE(__NOR_ADDR_SHIFT(currentaddress), *pData++);
+ NOR_WRITE(p_currentaddress, *pData++);
- currentaddress += 1;
+ p_currentaddress ++;
}
- __NOR_WRITE(__NOR_ADDR_SHIFT(lastloadedaddress), 0x29);
+ NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -492,13 +650,15 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
/**
* @brief Erase the specified block of the NOR memory
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to the NOR handle
* @param BlockAddress : Block to erase address
* @param Address: Device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
{
+ uint32_t deviceaddress = 0;
+
/* Process Locked */
__HAL_LOCK(hnor);
@@ -507,17 +667,35 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
{
return HAL_BUSY;
}
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FSMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send block erase command sequence */
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA);
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055);
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x0080);
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA);
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055);
- __NOR_WRITE((uint32_t)(BlockAddress + Address), 0x30);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
/* Check the NOR memory status and update the controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -531,12 +709,14 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
/**
* @brief Erase the entire NOR chip.
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to the NOR handle
* @param Address : Device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
{
+ uint32_t deviceaddress = 0;
+
/* Process Locked */
__HAL_LOCK(hnor);
@@ -545,17 +725,35 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
{
return HAL_BUSY;
}
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FSMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send NOR chip erase command sequence */
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA);
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055);
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x0080);
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA);
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055);
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x0010);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
/* Check the NOR memory status and update the controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -568,12 +766,14 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
/**
* @brief Read NOR flash CFI IDs
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to the NOR handle
* @param pNOR_CFI : pointer to NOR CFI IDs structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
{
+ uint32_t deviceaddress = 0;
+
/* Process Locked */
__HAL_LOCK(hnor);
@@ -582,18 +782,36 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
{
return HAL_BUSY;
}
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FSMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send read CFI query command */
- __NOR_WRITE(__NOR_ADDR_SHIFT(0x0055), 0x0098);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
/* read the NOR CFI information */
- pNOR_CFI->CFI_1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(CFI1_ADDRESS);
- pNOR_CFI->CFI_2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(CFI2_ADDRESS);
- pNOR_CFI->CFI_3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(CFI3_ADDRESS);
- pNOR_CFI->CFI_4 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(CFI4_ADDRESS);
+ pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI1_ADDRESS);
+ pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI2_ADDRESS);
+ pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI3_ADDRESS);
+ pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI4_ADDRESS);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -608,7 +826,7 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
* @}
*/
-/** @defgroup NOR_Group3 Control functions
+/** @defgroup NOR_Exported_Functions_Group3 Control functions
* @brief management functions
*
@verbatim
@@ -625,7 +843,7 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
/**
* @brief Enables dynamically NOR write operation.
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to the NOR handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
@@ -634,7 +852,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
__HAL_LOCK(hnor);
/* Enable write operation */
- FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
+ FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -647,7 +865,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
/**
* @brief Disables dynamically NOR write operation.
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to the NOR handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
@@ -659,7 +877,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
hnor->State = HAL_NOR_STATE_BUSY;
/* Disable write operation */
- FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
+ FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_PROTECTED;
@@ -674,7 +892,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
* @}
*/
-/** @defgroup NOR_Group4 State functions
+/** @defgroup NOR_Exported_Functions_Group4 State functions
* @brief Peripheral State functions
*
@verbatim
@@ -682,7 +900,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
##### NOR State functions #####
==============================================================================
[..]
- This subsection permit to get in run-time the status of the NOR controller
+ This subsection permits to get in run-time the status of the NOR controller
and the data flow.
@endverbatim
@@ -691,7 +909,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
/**
* @brief return the NOR controller state
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to the NOR handle
* @retval NOR controller state
*/
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
@@ -701,59 +919,62 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
/**
* @brief Returns the NOR operation status.
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to the NOR handle
* @param Address: Device address
- * @param Timeout: NOR progamming Timeout
- * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
- * or NOR_TIMEOUT
+ * @param Timeout: NOR programming Timeout
+ * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
+ * or HAL_NOR_STATUS_TIMEOUT
*/
-NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
{
- NOR_StatusTypedef status = NOR_ONGOING;
+ HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
uint16_t tmpSR1 = 0, tmpSR2 = 0;
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Poll on NOR memory Ready/Busy signal ------------------------------------*/
- HAL_NOR_MspWait(hnor, timeout);
+ HAL_NOR_MspWait(hnor, Timeout);
/* Get the NOR memory operation status -------------------------------------*/
- while(status != NOR_SUCCESS)
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))
{
- /* Check for timeout value */
- timeout = HAL_GetTick() + Timeout;
-
- if(HAL_GetTick() >= timeout)
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- status = NOR_TIMEOUT;
- }
-
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ status = HAL_NOR_STATUS_TIMEOUT;
+ }
+ }
+
/* Read NOR status register (DQ6 and DQ5) */
tmpSR1 = *(__IO uint16_t *)Address;
tmpSR2 = *(__IO uint16_t *)Address;
- /* If DQ6 did not toggle between the two reads then return NOR_Success */
- if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040))
+ /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
+ if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
{
- return NOR_SUCCESS;
+ return HAL_NOR_STATUS_SUCCESS ;
}
- if((tmpSR1 & 0x0020) == 0x0020)
+ if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
{
- return NOR_ONGOING;
+ status = HAL_NOR_STATUS_ONGOING;
}
tmpSR1 = *(__IO uint16_t *)Address;
tmpSR2 = *(__IO uint16_t *)Address;
- /* If DQ6 did not toggle between the two reads then return NOR_Success */
- if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040))
+ /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
+ if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
{
- return NOR_SUCCESS;
+ return HAL_NOR_STATUS_SUCCESS;
}
-
- if((tmpSR1 & 0x0020) == 0x0020)
+ if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
{
- return NOR_ERROR;
+ return HAL_NOR_STATUS_ERROR;
}
}
@@ -764,10 +985,12 @@ NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, u
/**
* @}
*/
+
/**
* @}
*/
+
#endif /* HAL_NOR_MODULE_ENABLED */
/**
* @}
diff --git a/f2/src/stm32f2xx_hal_pccard.c b/f2/src/stm32f2xx_hal_pccard.c
index 4b5e10ca71eb634aab08f1664966765889010acf..5e819cf6fd5a155668bc901d6079ff37ba4d4f9c 100755
--- a/f2/src/stm32f2xx_hal_pccard.c
+++ b/f2/src/stm32f2xx_hal_pccard.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_pccard.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief PCCARD HAL module driver.
* This file provides a generic firmware to drive PCCARD memories mounted
* as external device.
@@ -14,40 +14,43 @@
===============================================================================
[..]
This driver is a generic layered driver which contains a set of APIs used to
- control PCCARD/compact flash memories. It uses the FMC/FSMC layer functions
+ control PCCARD/compact flash memories. It uses the FSMC layer functions
to interface with PCCARD devices. This driver is used for:
- (+) PCCARD/compact flash memory configuration sequence using the function
- HAL_PCCARD_Init() with control and timing parameters for both common and
- attribute spaces.
+ (+) PCCARD/Compact Flash memory configuration sequence using the function
+ HAL_PCCARD_Init()/HAL_CF_Init() with control and timing parameters for
+ both common and attribute spaces.
- (+) Read PCCARD/compact flash memory maker and device IDs using the function
- HAL_CF_Read_ID(). The read information is stored in the CompactFlash_ID
- structure declared by the function caller.
+ (+) Read PCCARD/Compact Flash memory maker and device IDs using the function
+ HAL_PCCARD_Read_ID()/HAL_CF_Read_ID(). The read information is stored in
+ the CompactFlash_ID structure declared by the function caller.
- (+) Access PCCARD/compact flash memory by read/write operations using the functions
+ (+) Access PCCARD/Compact Flash memory by read/write operations using the functions
+ HAL_PCCARD_Read_Sector()/ HAL_PCCARD_Write_Sector() -
HAL_CF_Read_Sector()/HAL_CF_Write_Sector(), to read/write sector.
- (+) Perform PCCARD/compact flash Reset chip operation using the function HAL_CF_Reset().
+ (+) Perform PCCARD/Compact Flash Reset chip operation using the function
+ HAL_PCCARD_Reset()/HAL_CF_Reset.
- (+) Perform PCCARD/compact flash erase sector operation using the function
- HAL_CF_Erase_Sector().
+ (+) Perform PCCARD/Compact Flash erase sector operation using the function
+ HAL_PCCARD_Erase_Sector()/HAL_CF_Erase_Sector.
- (+) Read the PCCARD/compact flash status operation using the function HAL_CF_ReadStatus().
+ (+) Read the PCCARD/Compact Flash status operation using the function
+ HAL_PCCARD_ReadStatus()/HAL_CF_ReadStatus().
- (+) You can monitor the PCCARD/compact flash device HAL state by calling the function
- HAL_PCCARD_GetState()
+ (+) You can monitor the PCCARD/Compact Flash device HAL state by calling
+ the function HAL_PCCARD_GetState()/HAL_CF_GetState()
[..]
(@) This driver is a set of generic APIs which handle standard PCCARD/compact flash
- operations. If a PCCARD/compact flash device contains different operations
+ operations. If a PCCARD/Compact Flash device contains different operations
and/or implementations, it should be implemented separately.
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -81,24 +84,37 @@
* @{
*/
-/** @defgroup PCCARD
- * @brief PCCARD driver modules
+#ifdef HAL_PCCARD_MODULE_ENABLED
+/** @defgroup PCCARD PCCARD
+ * @brief PCCARD HAL module driver
* @{
*/
-#ifdef HAL_PCCARD_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PCCARD_Private_Defines PCCARD Private Defines
+ * @{
+ */
+#define PCCARD_TIMEOUT_READ_ID (uint32_t)0x0000FFFF
+#define PCCARD_TIMEOUT_READ_WRITE_SECTOR (uint32_t)0x0000FFFF
+#define PCCARD_TIMEOUT_ERASE_SECTOR (uint32_t)0x00000400
+#define PCCARD_TIMEOUT_STATUS (uint32_t)0x01000000
-/** @defgroup PCCARD_Private_Functions
+#define PCCARD_STATUS_OK (uint8_t)0x58
+#define PCCARD_STATUS_WRITE_OK (uint8_t)0x50
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function ----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PCCARD_Exported_Functions PCCARD Exported Functions
* @{
*/
-/** @defgroup PCCARD_Group1 Initialization and de-initialization functions
+/** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -115,13 +131,14 @@
/**
* @brief Perform the PCCARD memory Initialization sequence
- * @param hpccard : pointer to PCCARD handle
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
* @param ComSpaceTiming: Common space timing structure
* @param AttSpaceTiming: Attribute space timing structure
* @param IOSpaceTiming: IO space timing structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
+HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
{
/* Check the PCCARD controller state */
if(hpccard == NULL)
@@ -131,6 +148,8 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_Ti
if(hpccard->State == HAL_PCCARD_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hpccard->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_PCCARD_MspInit(hpccard);
}
@@ -139,19 +158,19 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_Ti
hpccard->State = HAL_PCCARD_STATE_BUSY;
/* Initialize PCCARD control Interface */
- FMC_PCCARD_Init(hpccard->Instance, &(hpccard->Init));
+ FSMC_PCCARD_Init(hpccard->Instance, &(hpccard->Init));
/* Init PCCARD common space timing Interface */
- FMC_PCCARD_CommonSpace_Timing_Init(hpccard->Instance, ComSpaceTiming);
+ FSMC_PCCARD_CommonSpace_Timing_Init(hpccard->Instance, ComSpaceTiming);
/* Init PCCARD attribute space timing Interface */
- FMC_PCCARD_AttributeSpace_Timing_Init(hpccard->Instance, AttSpaceTiming);
+ FSMC_PCCARD_AttributeSpace_Timing_Init(hpccard->Instance, AttSpaceTiming);
/* Init PCCARD IO space timing Interface */
- FMC_PCCARD_IOSpace_Timing_Init(hpccard->Instance, IOSpaceTiming);
+ FSMC_PCCARD_IOSpace_Timing_Init(hpccard->Instance, IOSpaceTiming);
/* Enable the PCCARD device */
- __FMC_PCCARD_ENABLE(hpccard->Instance);
+ __FSMC_PCCARD_ENABLE(hpccard->Instance);
/* Update the PCCARD state */
hpccard->State = HAL_PCCARD_STATE_READY;
@@ -162,29 +181,31 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_Ti
/**
* @brief Perform the PCCARD memory De-initialization sequence
- * @param hpccard : pointer to PCCARD handle
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
{
- /* Update the PCCARD controller state */
- hpccard->State = HAL_PCCARD_STATE_BUSY;
-
/* De-Initialize the low level hardware (MSP) */
- HAL_PCCARD_MspDeInit(hpccard);
+ HAL_PCCARD_MspDeInit(hpccard);
/* Configure the PCCARD registers with their reset values */
- FMC_PCCARD_DeInit(hpccard->Instance);
+ FSMC_PCCARD_DeInit(hpccard->Instance);
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_RESET;
-
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpccard);
+
return HAL_OK;
}
/**
* @brief PCCARD MSP Init
- * @param hpccard : pointer to PCCARD handle
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
* @retval None
*/
__weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard)
@@ -196,7 +217,8 @@ __weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard)
/**
* @brief PCCARD MSP DeInit
- * @param hpccard : pointer to PCCARD handle
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
* @retval None
*/
__weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
@@ -210,7 +232,7 @@ __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
* @}
*/
-/** @defgroup PCCARD_Group2 Input and Output functions
+/** @defgroup PCCARD_Exported_Functions_Group2 Input and Output functions
* @brief Input Output and memory control functions
*
@verbatim
@@ -226,16 +248,17 @@ __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
/**
* @brief Read Compact Flash's ID.
- * @param hpccard : pointer to PCCARD handle
- * @param CF_ID: Compact flash ID structure.
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param CompactFlash_ID: Compact flash ID structure.
* @param pStatus: pointer to compact flash status
* @retval HAL status
*
*/
-HAL_StatusTypeDef HAL_CF_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
+HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
{
- uint32_t timeout = 0xFFFF, index;
- uint8_t status;
+ uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0;
+ uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -248,32 +271,34 @@ HAL_StatusTypeDef HAL_CF_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactF
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
-
- /* Initialize the CF status */
- *pStatus = CF_READY;
+
+
+
+ /* Initialize the PCCARD status */
+ *pStatus = PCCARD_READY;
/* Send the Identify Command */
- *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD) = 0xECEC;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = 0xECEC;
- /* Read CF IDs and timeout treatment */
+ /* Read PCCARD IDs and timeout treatment */
do
{
- /* Read the CF status */
- status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ /* Read the PCCARD status */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
- }while((status != 0x58) && timeout);
+ }while((status != PCCARD_STATUS_OK) && timeout);
if(timeout == 0)
{
- *pStatus = CF_TIMEOUT_ERROR;
+ *pStatus = PCCARD_TIMEOUT_ERROR;
}
else
{
- /* Read CF ID bytes */
+ /* Read PCCARD ID bytes */
for(index = 0; index < 16; index++)
{
- CompactFlash_ID[index] = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_DATA);
+ CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA);
}
}
@@ -288,16 +313,17 @@ HAL_StatusTypeDef HAL_CF_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactF
/**
* @brief Read sector from PCCARD memory
- * @param hpccard : pointer to PCCARD handle
- * @param pBuffer : pointer to destination read buffer
- * @param SectorAddress : Sector address to read
- * @param pStatus : pointer to CF status
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param pBuffer: pointer to destination read buffer
+ * @param SectorAddress: Sector address to read
+ * @param pStatus: pointer to PCCARD status
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CF_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
+HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
{
- uint32_t timeout = 0xFFFF, index = 0;
- uint8_t status;
+ uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0;
+ uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -311,44 +337,44 @@ HAL_StatusTypeDef HAL_CF_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pB
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
- /* Initialize CF status */
- *pStatus = CF_READY;
+ /* Initialize PCCARD status */
+ *pStatus = PCCARD_READY;
/* Set the parameters to write a sector */
- *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_HIGH) = (uint16_t)0x00;
- *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
- *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD) = (uint16_t)0xE4A0;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0;
do
{
/* wait till the Status = 0x80 */
- status = *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}while((status == 0x80) && timeout);
if(timeout == 0)
{
- *pStatus = CF_TIMEOUT_ERROR;
+ *pStatus = PCCARD_TIMEOUT_ERROR;
}
- timeout = 0xFFFF;
+ timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR;
do
{
- /* wait till the Status = 0x58 */
- status = *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ /* wait till the Status = PCCARD_STATUS_OK */
+ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
- }while((status != 0x58) && timeout);
+ }while((status != PCCARD_STATUS_OK) && timeout);
if(timeout == 0)
{
- *pStatus = CF_TIMEOUT_ERROR;
+ *pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Read bytes */
- for(; index < CF_SECTOR_SIZE; index++)
+ for(; index < PCCARD_SECTOR_SIZE; index++)
{
- *(uint16_t *)pBuffer++ = *(uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR);
+ *(uint16_t *)pBuffer++ = *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR);
}
/* Update the PCCARD controller state */
@@ -363,16 +389,17 @@ HAL_StatusTypeDef HAL_CF_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pB
/**
* @brief Write sector to PCCARD memory
- * @param hpccard : pointer to PCCARD handle
- * @param pBuffer : pointer to source write buffer
- * @param SectorAddress : Sector address to write
- * @param pStatus : pointer to CF status
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param pBuffer: pointer to source write buffer
+ * @param SectorAddress: Sector address to write
+ * @param pStatus: pointer to PCCARD status
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CF_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
+HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
{
- uint32_t timeout = 0xFFFF, index = 0;
- uint8_t status;
+ uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0;
+ uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -386,42 +413,42 @@ HAL_StatusTypeDef HAL_CF_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *p
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
- /* Initialize CF status */
- *pStatus = CF_READY;
+ /* Initialize PCCARD status */
+ *pStatus = PCCARD_READY;
/* Set the parameters to write a sector */
- *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_HIGH) = (uint16_t)0x00;
- *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
- *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD) = (uint16_t)0x30A0;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0x30A0;
do
{
- /* Wait till the Status = 0x58 */
- status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ /* Wait till the Status = PCCARD_STATUS_OK */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
- }while((status != 0x58) && timeout);
+ }while((status != PCCARD_STATUS_OK) && timeout);
if(timeout == 0)
{
- *pStatus = CF_TIMEOUT_ERROR;
+ *pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Write bytes */
- for(; index < CF_SECTOR_SIZE; index++)
+ for(; index < PCCARD_SECTOR_SIZE; index++)
{
- *(uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
+ *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
}
do
{
- /* Wait till the Status = 0x50 */
- status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ /* Wait till the Status = PCCARD_STATUS_WRITE_OK */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
- }while((status != 0x50) && timeout);
+ }while((status != PCCARD_STATUS_WRITE_OK) && timeout);
if(timeout == 0)
{
- *pStatus = CF_TIMEOUT_ERROR;
+ *pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Update the PCCARD controller state */
@@ -436,15 +463,16 @@ HAL_StatusTypeDef HAL_CF_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *p
/**
* @brief Erase sector from PCCARD memory
- * @param hpccard : pointer to PCCARD handle
- * @param SectorAddress : Sector address to erase
- * @param pStatus : pointer to CF status
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param SectorAddress: Sector address to erase
+ * @param pStatus: pointer to PCCARD status
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CF_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
+HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
{
- uint32_t timeout = 0x400;
- uint8_t status;
+ uint32_t timeout = PCCARD_TIMEOUT_ERASE_SECTOR;
+ uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -458,29 +486,29 @@ HAL_StatusTypeDef HAL_CF_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t S
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
- /* Initialize CF status */
- *pStatus = CF_READY;
+ /* Initialize PCCARD status */
+ *pStatus = PCCARD_READY;
/* Set the parameters to write a sector */
- *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_LOW) = 0x00;
- *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_HIGH) = 0x00;
- *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_NUMBER) = SectorAddress;
- *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_COUNT) = 0x01;
- *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CARD_HEAD) = 0xA0;
- *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD) = CF_ERASE_SECTOR_CMD;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_LOW) = 0x00;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = 0x00;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_NUMBER) = SectorAddress;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = 0x01;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CARD_HEAD) = 0xA0;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = ATA_ERASE_SECTOR_CMD;
- /* wait till the CF is ready */
- status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ /* wait till the PCCARD is ready */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
- while((status != 0x50) && timeout)
+ while((status != PCCARD_STATUS_WRITE_OK) && timeout)
{
- status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}
if(timeout == 0)
{
- *pStatus = CF_TIMEOUT_ERROR;
+ *pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Check the PCCARD controller state */
@@ -494,12 +522,12 @@ HAL_StatusTypeDef HAL_CF_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t S
/**
* @brief Reset the PCCARD memory
- * @param hpccard : pointer to PCCARD handle
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CF_Reset(PCCARD_HandleTypeDef *hpccard)
+HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
{
-
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -509,17 +537,17 @@ HAL_StatusTypeDef HAL_CF_Reset(PCCARD_HandleTypeDef *hpccard)
return HAL_BUSY;
}
- /* Provide an SW reset and Read and verify the:
- - CF Configuration Option Register at address 0x98000200 --> 0x80
- - Card Configuration and Status Register at address 0x98000202 --> 0x00
- - Pin Replacement Register at address 0x98000204 --> 0x0C
+ /* Provide a SW reset and Read and verify the:
+ - PCCard Configuration Option Register at address 0x98000200 --> 0x80
+ - Card Configuration and Status Register at address 0x98000202 --> 0x00
+ - Pin Replacement Register at address 0x98000204 --> 0x0C
- Socket and Copy Register at address 0x98000206 --> 0x00
*/
/* Check the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
- *(__IO uint8_t *)(0x98000202) = 0x01;
+ *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION ) = 0x01;
/* Check the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_READY;
@@ -532,56 +560,57 @@ HAL_StatusTypeDef HAL_CF_Reset(PCCARD_HandleTypeDef *hpccard)
/**
* @brief This function handles PCCARD device interrupt request.
- * @param hpccard : pointer to PCCARD handle
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
* @retval HAL status
*/
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
{
/* Check PCCARD interrupt Rising edge flag */
- if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE))
+ if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE))
{
/* PCCARD interrupt callback*/
HAL_PCCARD_ITCallback(hpccard);
/* Clear PCCARD interrupt Rising edge pending bit */
- __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE);
+ __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE);
}
/* Check PCCARD interrupt Level flag */
- if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_LEVEL))
+ if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL))
{
/* PCCARD interrupt callback*/
HAL_PCCARD_ITCallback(hpccard);
/* Clear PCCARD interrupt Level pending bit */
- __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_LEVEL);
+ __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL);
}
/* Check PCCARD interrupt Falling edge flag */
- if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE))
+ if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE))
{
/* PCCARD interrupt callback*/
HAL_PCCARD_ITCallback(hpccard);
/* Clear PCCARD interrupt Falling edge pending bit */
- __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE);
+ __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE);
}
/* Check PCCARD interrupt FIFO empty flag */
- if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FEMPT))
+ if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT))
{
/* PCCARD interrupt callback*/
HAL_PCCARD_ITCallback(hpccard);
/* Clear PCCARD interrupt FIFO empty pending bit */
- __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FEMPT);
+ __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT);
}
-
}
/**
* @brief PCCARD interrupt feature callback
- * @param hpccard : pointer to PCCARD handle
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
* @retval None
*/
__weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
@@ -595,7 +624,7 @@ __weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
* @}
*/
-/** @defgroup PCCARD_Group4 State functions
+/** @defgroup PCCARD_Exported_Functions_Group3 State functions
* @brief Peripheral State functions
*
@verbatim
@@ -603,7 +632,7 @@ __weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
##### PCCARD State functions #####
==============================================================================
[..]
- This subsection permit to get in run-time the status of the PCCARD controller
+ This subsection permits to get in run-time the status of the PCCARD controller
and the data flow.
@endverbatim
@@ -612,8 +641,9 @@ __weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
/**
* @brief return the PCCARD controller state
- * @param hpccard : pointer to PCCARD handle
- * @retval PCCARD controller state
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval HAL state
*/
HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
{
@@ -622,71 +652,72 @@ HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
/**
* @brief Get the compact flash memory status
- * @param hpccard: PCCARD handle
- * @retval New status of the CF operation. This parameter can be:
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval New status of the PCCARD operation. This parameter can be:
* - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
* a Timeout error
- * - CompactFlash_READY: when memory is ready for the next operation
- *
+ * - CompactFlash_READY: when memory is ready for the next operation
*/
-CF_StatusTypedef HAL_CF_GetStatus(PCCARD_HandleTypeDef *hpccard)
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
{
- uint32_t timeout = 0x1000000, status_CF;
+ uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_pccard = 0;
/* Check the PCCARD controller state */
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
{
- return CF_ONGOING;
+ return HAL_PCCARD_STATUS_ONGOING;
}
- status_CF = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ status_pccard = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
- while((status_CF == CF_BUSY) && timeout)
+ while((status_pccard == PCCARD_BUSY) && timeout)
{
- status_CF = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ status_pccard = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}
if(timeout == 0)
{
- status_CF = CF_TIMEOUT_ERROR;
+ status_pccard = PCCARD_TIMEOUT_ERROR;
}
/* Return the operation status */
- return (CF_StatusTypedef) status_CF;
+ return (HAL_PCCARD_StatusTypeDef) status_pccard;
}
/**
* @brief Reads the Compact Flash memory status using the Read status command
- * @param hpccard : pointer to PCCARD handle
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
* @retval The status of the Compact Flash memory. This parameter can be:
* - CompactFlash_BUSY: when memory is busy
* - CompactFlash_READY: when memory is ready for the next operation
- * - CompactFlash_ERROR: when the previous operation gererates error
+ * - CompactFlash_ERROR: when the previous operation generates error
*/
-CF_StatusTypedef HAL_CF_ReadStatus(PCCARD_HandleTypeDef *hpccard)
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
{
- uint8_t data = 0, status_CF = CF_BUSY;
+ uint8_t data = 0, status_pccard = PCCARD_BUSY;
/* Check the PCCARD controller state */
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
{
- return CF_ONGOING;
+ return HAL_PCCARD_STATUS_ONGOING;
}
/* Read status operation */
- data = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+ data = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
- if((data & CF_TIMEOUT_ERROR) == CF_TIMEOUT_ERROR)
+ if((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR)
{
- status_CF = CF_TIMEOUT_ERROR;
+ status_pccard = PCCARD_TIMEOUT_ERROR;
}
- else if((data & CF_READY) == CF_READY)
+ else if((data & PCCARD_READY) == PCCARD_READY)
{
- status_CF = CF_READY;
+ status_pccard = PCCARD_READY;
}
- return (CF_StatusTypedef) status_CF;
+ return (HAL_PCCARD_StatusTypeDef) status_pccard;
}
/**
@@ -696,7 +727,8 @@ CF_StatusTypedef HAL_CF_ReadStatus(PCCARD_HandleTypeDef *hpccard)
/**
* @}
*/
-#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#endif /* HAL_PCCARD_MODULE_ENABLED */
/**
* @}
diff --git a/f2/src/stm32f2xx_hal_pcd.c b/f2/src/stm32f2xx_hal_pcd.c
index a948814b1ad95fd62d5a286c7ad3a9b022ff52d6..875140eca18783fa8e3b722f477e7b62534f92d6 100755
--- a/f2/src/stm32f2xx_hal_pcd.c
+++ b/f2/src/stm32f2xx_hal_pcd.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_pcd.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -24,12 +24,12 @@
(#) Fill parameters of Init structure in HCD handle
- (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...)
+ (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
(#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
(##) Enable the PCD/USB Low Level interface clock using
- (+++) __OTGFS-OTG_CLK_ENABLE()/__OTGHS-OTG_CLK_ENABLE();
- (+++) __OTGHSULPI_CLK_ENABLE(); (For High Speed Mode)
+ (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+ (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
(##) Initialize the related GPIO clocks
(##) Configure PCD pin-out
@@ -38,14 +38,14 @@
(#)Associate the Upper USB device stack to the HAL PCD Driver:
(##) hpcd.pData = pdev;
- (#)Enable HCD transmission and reception:
+ (#)Enable PCD transmission and reception:
(##) HAL_PCD_Start();
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -79,31 +79,44 @@
* @{
*/
-/** @defgroup PCD
+/** @defgroup PCD PCD
* @brief PCD HAL module driver
* @{
*/
#ifdef HAL_PCD_MODULE_ENABLED
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup PCD_Private_Functions PCD Private Functions
+ * @{
+ */
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
-/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
-/** @defgroup PCD_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Functions PCD Exported Functions
* @{
*/
-/** @defgroup PCD_Group1 Initialization and de-initialization functions
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
@@ -115,7 +128,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
/**
* @brief Initializes the PCD according to the specified
- * parameters in the PCD_InitTypeDef and create the associated handle.
+ * parameters in the PCD_InitTypeDef and initialize the associated handle.
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -132,7 +145,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
- hpcd->State = PCD_BUSY;
+ hpcd->State = HAL_PCD_STATE_BUSY;
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
@@ -153,7 +166,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->IN_ep[i].is_in = 1;
hpcd->IN_ep[i].num = i;
hpcd->IN_ep[i].tx_fifo_num = i;
- /* Control until ep is actvated */
+ /* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
hpcd->IN_ep[i].maxpacket = 0;
hpcd->IN_ep[i].xfer_buff = 0;
@@ -177,14 +190,14 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
/* Init Device */
USB_DevInit(hpcd->Instance, hpcd->Init);
- hpcd->State= PCD_READY;
+ hpcd->State= HAL_PCD_STATE_READY;
USB_DevDisconnect (hpcd->Instance);
return HAL_OK;
}
/**
- * @brief DeInitializes the PCD peripheral
+ * @brief DeInitializes the PCD peripheral.
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -196,7 +209,7 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
return HAL_ERROR;
}
- hpcd->State = PCD_BUSY;
+ hpcd->State = HAL_PCD_STATE_BUSY;
/* Stop Device */
HAL_PCD_Stop(hpcd);
@@ -204,7 +217,7 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
/* DeInit the low level hardware */
HAL_PCD_MspDeInit(hpcd);
- hpcd->State = PCD_READY;
+ hpcd->State = HAL_PCD_STATE_RESET;
return HAL_OK;
}
@@ -217,7 +230,7 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_MspInit could be implenetd in the user file
+ the HAL_PCD_MspInit could be implemented in the user file
*/
}
@@ -229,7 +242,7 @@ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_MspDeInit could be implenetd in the user file
+ the HAL_PCD_MspDeInit could be implemented in the user file
*/
}
@@ -237,10 +250,10 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
* @}
*/
-/** @defgroup PCD_Group2 IO operation functions
+/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
* @brief Data transfers functions
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@@ -276,13 +289,13 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
__HAL_LOCK(hpcd);
__HAL_PCD_DISABLE(hpcd);
USB_StopDevice(hpcd->Instance);
- USB_DevDisconnect (hpcd->Instance);
+ USB_DevDisconnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
- * @brief This function handles PCD interrupt request.
+ * @brief Handles PCD interrupt request.
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -297,18 +310,18 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
{
/* avoid spurious interrupt */
- if(__HAL_IS_INVALID_INTERRUPT(hpcd))
+ if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
{
return;
}
- if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
{
/* incorrect mode, acknowledge the interrupt */
- __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
}
- if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
{
epnum = 0;
@@ -359,7 +372,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
}
- if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
{
/* Read in the device interrupt bits */
ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
@@ -375,7 +388,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
{
fifoemptymsk = 0x1 << epnum;
- USBx_DEVICE->DIEPEMPMSK = ~fifoemptymsk;
+ USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
@@ -423,29 +436,29 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
/* Handle Resume Interrupt */
- if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
{
- /* Clear the Remote Wake-up Signaling */
+ /* Clear the Remote Wake-up Signaling */
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
-
- HAL_PCD_ResumeCallback(hpcd);
- __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
+ HAL_PCD_ResumeCallback(hpcd);
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
}
/* Handle Suspend Interrupt */
- if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
{
-
if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
- {
+ {
+
HAL_PCD_SuspendCallback(hpcd);
}
- __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
}
-
+
/* Handle Reset Interrupt */
- if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
{
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
USB_FlushTxFifo(hpcd->Instance , 0 );
@@ -475,11 +488,11 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/* setup EP0 to receive SETUP packets */
USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
- __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
}
/* Handle Enumeration done Interrupt */
- if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
{
USB_ActivateSetup(hpcd->Instance);
hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
@@ -488,26 +501,27 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
hpcd->Init.speed = USB_OTG_SPEED_HIGH;
hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE ;
- hpcd->Instance->GUSBCFG |= (USB_OTG_GUSBCFG_TRDT_0 | USB_OTG_GUSBCFG_TRDT_3);
+ hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);
}
else
{
hpcd->Init.speed = USB_OTG_SPEED_FULL;
hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ;
- hpcd->Instance->GUSBCFG |= (USB_OTG_GUSBCFG_TRDT_0 | USB_OTG_GUSBCFG_TRDT_2);
+ hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);
}
HAL_PCD_ResetCallback(hpcd);
- __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
}
-
-
+
/* Handle RxQLevel Interrupt */
- if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
{
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+
temp = USBx->GRXSTSP;
+
ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
@@ -528,35 +542,35 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
/* Handle SOF Interrupt */
- if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
{
HAL_PCD_SOFCallback(hpcd);
- __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
}
/* Handle Incomplete ISO IN Interrupt */
- if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
{
HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);
- __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
}
/* Handle Incomplete ISO OUT Interrupt */
- if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
{
HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);
- __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
}
/* Handle Connection event Interrupt */
- if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
{
HAL_PCD_ConnectCallback(hpcd);
- __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
}
/* Handle Disconnection event Interrupt */
- if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
{
temp = hpcd->Instance->GOTGINT;
@@ -570,144 +584,148 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
/**
- * @brief Data out stage callbacks
+ * @brief Data OUT stage callback.
* @param hpcd: PCD handle
+ * @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file
*/
}
/**
- * @brief Data IN stage callbacks
+ * @brief Data IN stage callback.
* @param hpcd: PCD handle
+ * @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_DataInStageCallback could be implemented in the user file
*/
}
/**
- * @brief Setup stage callback
- * @param hpcd: ppp handle
+ * @brief Setup stage callback.
+ * @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_SetupStageCallback could be implemented in the user file
*/
}
/**
- * @brief USB Start Of Frame callbacks
+ * @brief USB Start Of Frame callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_SOFCallback could be implemented in the user file
*/
}
/**
- * @brief USB Reset callbacks
+ * @brief USB Reset callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_ResetCallback could be implemented in the user file
*/
}
/**
- * @brief Suspend event callbacks
+ * @brief Suspend event callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_SuspendCallback could be implemented in the user file
*/
}
/**
- * @brief Resume event callbacks
+ * @brief Resume event callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_ResumeCallback could be implemented in the user file
*/
}
/**
- * @brief Incomplete ISO OUT callbacks
+ * @brief Incomplete ISO OUT callback.
* @param hpcd: PCD handle
+ * @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
*/
}
/**
- * @brief Incomplete ISO IN callbacks
+ * @brief Incomplete ISO IN callback.
* @param hpcd: PCD handle
+ * @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
*/
}
/**
- * @brief Connection event callbacks
+ * @brief Connection event callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_ConnectCallback could be implemented in the user file
*/
}
/**
- * @brief Disconnection event callbacks
- * @param hpcd: ppp handle
+ * @brief Disconnection event callback.
+ * @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_DisconnectCallback could be implemented in the user file
*/
}
/**
* @}
*/
-
-/** @defgroup PCD_Group3 Peripheral Control functions
- * @brief management functions
+
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
@@ -720,10 +738,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
*/
/**
- * @brief Send an amount of data in blocking mode
+ * @brief Connect the USB device.
* @param hpcd: PCD handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
@@ -735,10 +751,8 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
}
/**
- * @brief Send an amount of data in blocking mode
+ * @brief Disconnect the USB device.
* @param hpcd: PCD handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
@@ -750,7 +764,7 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
}
/**
- * @brief Set the USB Device address
+ * @brief Set the USB Device address.
* @param hpcd: PCD handle
* @param address: new device address
* @retval HAL status
@@ -763,10 +777,10 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
return HAL_OK;
}
/**
- * @brief Open and configure an endpoint
+ * @brief Open and configure an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
- * @param ep_mps: endpoint max packert size
+ * @param ep_mps: endpoint max packet size
* @param ep_type: endpoint type
* @retval HAL status
*/
@@ -807,7 +821,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
/**
- * @brief Deactivate an endpoint
+ * @brief Deactivate an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval HAL status
@@ -836,7 +850,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
/**
- * @brief Receive an amount of data
+ * @brief Receive an amount of data.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @param pBuf: pointer to the reception buffer
@@ -845,7 +859,6 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
*/
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
-
USB_OTG_EPTypeDef *ep;
ep = &hpcd->OUT_ep[ep_addr & 0x7F];
@@ -878,7 +891,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
}
/**
- * @brief Get Received Data Size
+ * @brief Get Received Data Size.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval Data Size
@@ -888,7 +901,7 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
}
/**
- * @brief Send an amount of data
+ * @brief Send an amount of data.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @param pBuf: pointer to the transmission buffer
@@ -930,7 +943,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
}
/**
- * @brief Set a STALL condition over an endpoint
+ * @brief Set a STALL condition over an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval HAL status
@@ -965,7 +978,7 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
/**
- * @brief Clear a STALL condition over in an endpoint
+ * @brief Clear a STALL condition over in an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval HAL status
@@ -995,7 +1008,7 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
/**
- * @brief Flush an endpoint
+ * @brief Flush an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval HAL status
@@ -1019,105 +1032,48 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
/**
- * @brief Update FIFO configuration
- * @param hpcd: PCD handle
- * @retval status
- */
-HAL_StatusTypeDef HAL_PCD_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
-{
- uint8_t i = 0;
- uint32_t Tx_Offset = 0;
-
-
- /* TXn min size = 16 words. (n : Transmit FIFO index)
- * When a TxFIFO is not used, the Configuration should be as follows:
- * case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
- * --> Txm can use the space allocated for Txn.
- * case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
- * --> Txn should be configured with the minimum space of 16 words
- * The FIFO is used optimally when used TxFIFOs are allocated in the top
- * of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
- * When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
-
- Tx_Offset = hpcd->Instance->GRXFSIZ;
-
- if(fifo == 0)
- {
- hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset;
- }
- else
- {
- Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
- for (i = 0; i < (fifo - 1); i++)
- {
- Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
- }
-
- /* Multiply Tx_Size by 2 to get higher performance */
- hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset;
-
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Update FIFO configuration
+ * @brief Activate remote wakeup signalling.
* @param hpcd: PCD handle
- * @retval status
- */
-HAL_StatusTypeDef HAL_PCD_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
-{
-
- hpcd->Instance->GRXFSIZ = size;
-
- return HAL_OK;
-}
-
-
-/**
- * @brief HAL_PCD_ActiveRemoteWakeup : active remote wakeup signalling
- * @param hpcd: PCD handle
- * @retval status
+ * @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
{
- /* active Remote wakeup signaling */
+ /* Activate Remote wakeup signaling */
USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
}
return HAL_OK;
}
/**
- * @brief HAL_PCD_DeActiveRemoteWakeup : de-active remote wakeup signalling
+ * @brief De-activate remote wakeup signalling.
* @param hpcd: PCD handle
- * @retval status
+ * @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
- /* active Remote wakeup signaling */
- USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
+ /* De-activate Remote wakeup signaling */
+ USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
return HAL_OK;
}
/**
* @}
*/
-/** @defgroup PCD_Group4 Peripheral State functions
- * @brief Peripheral State functions
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -1125,8 +1081,8 @@ HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
*/
/**
- * @brief Return the PCD state
- * @param hpcd : PCD handle
+ * @brief Return the PCD handle state.
+ * @param hpcd: PCD handle
* @retval HAL state
*/
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
@@ -1138,10 +1094,19 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
*/
/**
- * @brief DCD_WriteEmptyTxFifo
- * check FIFO for the next packet to be loaded
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup PCD_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Check FIFO for the next packet to be loaded.
* @param hpcd: PCD handle
- * @retval status
+ * @param epnum : endpoint number
+ * @retval HAL status
*/
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
@@ -1159,6 +1124,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
len = ep->maxpacket;
}
+
len32b = (len + 3) / 4;
while ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
@@ -1183,7 +1149,8 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
if(len <= 0)
{
fifoemptymsk = 0x1 << epnum;
- USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
+ USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
+
}
return HAL_OK;
diff --git a/f2/src/stm32f2xx_hal_pcd_ex.c b/f2/src/stm32f2xx_hal_pcd_ex.c
new file mode 100644
index 0000000000000000000000000000000000000000..b1ff6559471b1dccc58adc1de37ab873a0c565d4
--- /dev/null
+++ b/f2/src/stm32f2xx_hal_pcd_ex.c
@@ -0,0 +1,153 @@
+/**
+ ******************************************************************************
+ * @file stm32f2xx_hal_pcd_ex.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 09-October-2015
+ * @brief PCD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Extended features functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f2xx_hal.h"
+
+/** @addtogroup STM32F2xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PCDEx PCDEx
+ * @brief PCD Extended HAL module driver
+ * @{
+ */
+#ifdef HAL_PCD_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PCDEx_Exported_Functions PCD Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+ * @brief PCDEx control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Update FIFO configuration
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set Tx FIFO
+ * @param hpcd: PCD handle
+ * @param fifo: The number of Tx fifo
+ * @param size: Fifo size
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
+{
+ uint8_t i = 0;
+ uint32_t Tx_Offset = 0;
+
+ /* TXn min size = 16 words. (n : Transmit FIFO index)
+ When a TxFIFO is not used, the Configuration should be as follows:
+ case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
+ --> Txm can use the space allocated for Txn.
+ case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
+ --> Txn should be configured with the minimum space of 16 words
+ The FIFO is used optimally when used TxFIFOs are allocated in the top
+ of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
+ When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
+
+ Tx_Offset = hpcd->Instance->GRXFSIZ;
+
+ if(fifo == 0)
+ {
+ hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
+ }
+ else
+ {
+ Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
+ for (i = 0; i < (fifo - 1); i++)
+ {
+ Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
+ }
+
+ /* Multiply Tx_Size by 2 to get higher performance */
+ hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set Rx FIFO
+ * @param hpcd: PCD handle
+ * @param size: Size of Rx fifo
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
+{
+ hpcd->Instance->GRXFSIZ = size;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_PCD_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f2/src/stm32f2xx_hal_pwr.c b/f2/src/stm32f2xx_hal_pwr.c
index 8fa3850bdce7404ae7397a451724ad2b24d35587..682dbbfd08cd2e7a23c9d003c99899706506bf3d 100755
--- a/f2/src/stm32f2xx_hal_pwr.c
+++ b/f2/src/stm32f2xx_hal_pwr.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_pwr.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -47,7 +47,7 @@
* @{
*/
-/** @defgroup PWR
+/** @defgroup PWR PWR
* @brief PWR HAL module driver
* @{
*/
@@ -56,16 +56,34 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup PWR_Private_Constants
+ * @{
+ */
+
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+ * @{
+ */
+#define PVD_MODE_IT ((uint32_t)0x00010000)
+#define PVD_MODE_EVT ((uint32_t)0x00020000)
+#define PVD_RISING_EDGE ((uint32_t)0x00000001)
+#define PVD_FALLING_EDGE ((uint32_t)0x00000002)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup PWR_Private_Functions
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
-/** @defgroup PWR_Group1 Initialization and de-initialization functions
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
*
@verbatim
@@ -78,7 +96,7 @@
write accesses.
To enable access to the RTC Domain and RTC registers, proceed as follows:
(+) Enable the Power Controller (PWR) APB1 interface clock using the
- __PWR_CLK_ENABLE() macro.
+ __HAL_RCC_PWR_CLK_ENABLE() macro.
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
@endverbatim
@@ -87,13 +105,12 @@
/**
* @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
- * @param None
* @retval None
*/
void HAL_PWR_DeInit(void)
{
- __PWR_FORCE_RESET();
- __PWR_RELEASE_RESET();
+ __HAL_RCC_PWR_FORCE_RESET();
+ __HAL_RCC_PWR_RELEASE_RESET();
}
/**
@@ -101,7 +118,6 @@ void HAL_PWR_DeInit(void)
* backup data registers and backup SRAM).
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
- * @param None
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
@@ -114,7 +130,6 @@ void HAL_PWR_EnableBkUpAccess(void)
* backup data registers and backup SRAM).
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
- * @param None
* @retval None
*/
void HAL_PWR_DisableBkUpAccess(void)
@@ -126,7 +141,7 @@ void HAL_PWR_DisableBkUpAccess(void)
* @}
*/
-/** @defgroup PWR_Group2 Peripheral Control functions
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @brief Low Power modes configuration functions
*
@verbatim
@@ -143,15 +158,15 @@ void HAL_PWR_DisableBkUpAccess(void)
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
than the PVD threshold. This event is internally connected to the EXTI
line16 and can generate an interrupt if enabled. This is done through
- __HAL_PVD_EXTI_ENABLE_IT() macro.
+ __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
(+) The PVD is stopped in Standby mode.
- *** WakeUp pin configuration ***
+ *** Wake-up pin configuration ***
================================
[..]
- (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
+ (+) Wake-up pin is used to wake up the system from Standby mode. This pin is
forced in input pull-down configuration and is active on rising edges.
- (+) There is only one WakeUp pin: WakeUp Pin 1 on PA.00.
+ (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
*** Low Power modes configuration ***
=====================================
@@ -186,9 +201,9 @@ void HAL_PWR_DisableBkUpAccess(void)
are preserved.
The voltage regulator can be configured either in normal or low-power mode.
To minimize the consumption In Stop mode, FLASH can be powered off before
- entering the Stop mode using the HAL_PWR_EnableFlashPowerDown() function.
+ entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
It can be switched on again by software after exiting the Stop mode using
- the HAL_PWR_DisableFlashPowerDown() function.
+ the HAL_PWREx_DisableFlashPowerDown() function.
(+) Entry:
The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
@@ -214,18 +229,18 @@ void HAL_PWR_DisableBkUpAccess(void)
(++) Entry:
(+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
(++) Exit:
- (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
+ (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
- *** Auto-wakeup (AWU) from low-power mode ***
+ *** Auto-wake-up (AWU) from low-power mode ***
=============================================
[..]
(+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
- Wakeup event, a tamper event or a time-stamp event, without depending on
- an external interrupt (Auto-wakeup mode).
+ Wake-up event, a tamper event or a time-stamp event, without depending on
+ an external interrupt (Auto-wake-up mode).
- (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
+ (+) RTC auto-wake-up (AWU) from the Stop and Standby modes
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
@@ -234,8 +249,8 @@ void HAL_PWR_DisableBkUpAccess(void)
is necessary to configure the RTC to detect the tamper or time stamp event using the
HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
- (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
- configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+ (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
+ configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
@endverbatim
* @{
@@ -250,52 +265,47 @@ void HAL_PWR_DisableBkUpAccess(void)
* detection level.
* @retval None
*/
-void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD)
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
{
- uint32_t tmpreg = 0;
-
/* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
- tmpreg = PWR->CR;
-
- /* Clear PLS[7:5] bits */
- tmpreg &= ~ (uint32_t)PWR_CR_PLS;
-
/* Set PLS[7:5] bits according to PVDLevel value */
- tmpreg |= sConfigPVD->PVDLevel;
+ MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
- /* Store the new value */
- PWR->CR = tmpreg;
+ /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+ __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
+ __HAL_PWR_PVD_EXTI_DISABLE_IT();
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+
+ /* Configure interrupt mode */
+ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_IT();
+ }
- /* Configure the EXTI 16 interrupt */
- if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\
- (sConfigPVD->Mode == PWR_MODE_IT_FALLING) ||\
- (sConfigPVD->Mode == PWR_MODE_IT_RISING))
+ /* Configure event mode */
+ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
{
- __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD);
+ __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
}
- /* Clear the edge trigger for the EXTI Line 16 (PVD) */
- EXTI->RTSR &= ~EXTI_RTSR_TR16;
- EXTI->FTSR &= ~EXTI_FTSR_TR16;
- /* Configure the rising edge */
- if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\
- (sConfigPVD->Mode == PWR_MODE_IT_RISING))
+
+ /* Configure the edge */
+ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
{
- EXTI->RTSR |= PWR_EXTI_LINE_PVD;
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
}
- /* Configure the falling edge */
- if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\
- (sConfigPVD->Mode == PWR_MODE_IT_FALLING))
+
+ if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
{
- EXTI->FTSR |= PWR_EXTI_LINE_PVD;
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
}
}
/**
* @brief Enables the Power Voltage Detector(PVD).
- * @param None
* @retval None
*/
void HAL_PWR_EnablePVD(void)
@@ -305,7 +315,6 @@ void HAL_PWR_EnablePVD(void)
/**
* @brief Disables the Power Voltage Detector(PVD).
- * @param None
* @retval None
*/
void HAL_PWR_DisablePVD(void)
@@ -314,8 +323,8 @@ void HAL_PWR_DisablePVD(void)
}
/**
- * @brief Enables the WakeUp PINx functionality.
- * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable
+ * @brief Enables the Wake-up PINx functionality.
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1
* @retval None
@@ -324,12 +333,14 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
{
/* Check the parameter */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
- *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)ENABLE;
+
+ /* Enable the wake up pin */
+ SET_BIT(PWR->CSR, WakeUpPinx);
}
/**
- * @brief Disables the WakeUp PINx functionality.
- * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable
+ * @brief Disables the Wake-up PINx functionality.
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1
* @retval None
@@ -338,7 +349,9 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
{
/* Check the parameter */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
- *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)DISABLE;
+
+ /* Disable the wake up pin */
+ CLEAR_BIT(PWR->CSR, WakeUpPinx);
}
/**
@@ -366,10 +379,10 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
-
- /* Disable SysTick Timer */
- SysTick->CTRL &= 0xFE;
-
+
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
/* Select SLEEP mode entry -------------------------------------------------*/
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
{
@@ -379,17 +392,16 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
else
{
/* Request Wait For Event */
+ __SEV();
+ __WFE();
__WFE();
}
-
- /* Enable SysTick Timer */
- SysTick->CTRL |= 0x01;
}
/**
* @brief Enters Stop mode.
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
- * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
+ * @note When exiting Stop mode by issuing an interrupt or a wake-up event,
* the HSI RC oscillator is selected as system clock.
* @note When the voltage regulator operates in low power mode, an additional
* startup delay is incurred when waking up from Stop mode.
@@ -407,25 +419,15 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
*/
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
{
- uint32_t tmpreg = 0;
-
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
- /* Select the regulator state in Stop mode ---------------------------------*/
- tmpreg = PWR->CR;
- /* Clear PDDS and LPDS bits */
- tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
-
- /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */
- tmpreg |= Regulator;
-
- /* Store the new value */
- PWR->CR = tmpreg;
+ /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */
+ MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);
/* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* Select Stop mode entry --------------------------------------------------*/
if(STOPEntry == PWR_STOPENTRY_WFI)
@@ -436,10 +438,12 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
else
{
/* Request Wait For Event */
+ __SEV();
+ __WFE();
__WFE();
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
@@ -450,19 +454,15 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
* Alarm out, or RTC clock calibration out.
* - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
* - WKUP pin 1 (PA0) if enabled.
- * @param None
* @retval None
*/
void HAL_PWR_EnterSTANDBYMode(void)
{
- /* Clear Wakeup flag */
- PWR->CR |= PWR_CR_CWUF;
-
/* Select Standby mode */
- PWR->CR |= PWR_CR_PDDS;
-
+ SET_BIT(PWR->CR, PWR_CR_PDDS);
+
/* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM)
@@ -475,26 +475,24 @@ void HAL_PWR_EnterSTANDBYMode(void)
/**
* @brief This function handles the PWR PVD interrupt request.
* @note This API should be called under the PVD_IRQHandler().
- * @param None
* @retval None
*/
void HAL_PWR_PVD_IRQHandler(void)
{
- /* Check PWR exti flag */
- if(__HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) != RESET)
+ /* Check PWR Exti flag */
+ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
{
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback();
/* Clear PWR Exti pending bit */
- __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD);
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
}
}
/**
* @brief PWR PVD interrupt callback
- * @param none
- * @retval none
+ * @retval None
*/
__weak void HAL_PWR_PVDCallback(void)
{
@@ -503,6 +501,56 @@ __weak void HAL_PWR_PVDCallback(void)
*/
}
+/**
+ * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ * re-enters SLEEP mode when an interruption handling is over.
+ * Setting this bit is useful when the processor is expected to run only on
+ * interruptions handling.
+ * @retval None
+ */
+void HAL_PWR_EnableSleepOnExit(void)
+{
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
+ * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ * re-enters SLEEP mode when an interruption handling is over.
+ * @retval None
+ */
+void HAL_PWR_DisableSleepOnExit(void)
+{
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Enables CORTEX M3 SEVONPEND bit.
+ * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_EnableSEVOnPend(void)
+{
+ /* Set SEVONPEND bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @brief Disables CORTEX M3 SEVONPEND bit.
+ * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_DisableSEVOnPend(void)
+{
+ /* Clear SEVONPEND bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
/**
* @}
*/
diff --git a/f2/src/stm32f2xx_hal_pwr_ex.c b/f2/src/stm32f2xx_hal_pwr_ex.c
index 53d68d5ceed202549a718a287f2b98e9722275b3..c1229652567ab698a8aabae8d5b9295fd47b331f 100755
--- a/f2/src/stm32f2xx_hal_pwr_ex.c
+++ b/f2/src/stm32f2xx_hal_pwr_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_pwr_ex.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of PWR extension peripheral:
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -46,7 +46,7 @@
* @{
*/
-/** @defgroup PWREx
+/** @defgroup PWREx PWREx
* @brief PWR HAL module driver
* @{
*/
@@ -55,17 +55,24 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup PWREx_Private_Constants
+ * @{
+ */
#define PWR_BKPREG_TIMEOUT_VALUE 1000
+/**
+ * @}
+ */
+
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PWREx_Private_Functions
- * @{
+/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
+ * @{
*/
-/** @defgroup PWREx_Group1 Peripheral Extended features functions
+/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
* @brief Peripheral Extended features functions
*
@verbatim
@@ -81,7 +88,7 @@
the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
retained even in Standby or VBAT mode when the low power backup regulator
is enabled. It can be considered as an internal EEPROM when VBAT is
- always present. You can use the HAL_PWR_EnableBkUpReg() function to
+ always present. You can use the HAL_PWREx_EnableBkUpReg() function to
enable the low power backup regulator.
(+) When the backup domain is supplied by VDD (analog switch connected to VDD)
@@ -102,7 +109,7 @@
=======================================
[..]
(+) By setting the FPDS bit in the PWR_CR register by using the
- HAL_PWR_EnableFlashPowerDown() function, the Flash memory also enters power
+ HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
down mode when the device enters Stop mode. When the Flash memory
is in power down mode, an additional startup delay is incurred when
waking up from Stop mode.
@@ -113,21 +120,21 @@
/**
* @brief Enables the Backup Regulator.
- * @param None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
*(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE;
- /* Get timeout */
- timeout = HAL_GetTick() + PWR_BKPREG_TIMEOUT_VALUE;
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait till Backup regulator ready flag is set */
while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -137,21 +144,21 @@ HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
/**
* @brief Disables the Backup Regulator.
- * @param None
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
*(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE;
- /* Get timeout */
- timeout = HAL_GetTick() + PWR_BKPREG_TIMEOUT_VALUE;
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait till Backup regulator ready flag is set */
while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -161,7 +168,6 @@ HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
/**
* @brief Enables the Flash Power Down in Stop mode.
- * @param None
* @retval None
*/
void HAL_PWREx_EnableFlashPowerDown(void)
@@ -171,7 +177,6 @@ void HAL_PWREx_EnableFlashPowerDown(void)
/**
* @brief Disables the Flash Power Down in Stop mode.
- * @param None
* @retval None
*/
void HAL_PWREx_DisableFlashPowerDown(void)
@@ -186,7 +191,6 @@ void HAL_PWREx_DisableFlashPowerDown(void)
/**
* @}
*/
-
#endif /* HAL_PWR_MODULE_ENABLED */
/**
* @}
diff --git a/f2/src/stm32f2xx_hal_rcc.c b/f2/src/stm32f2xx_hal_rcc.c
index cc1f0fed7aa4b437667dbef9207fac0bfaba973e..ee5d9ef7b588b57fe8473fff6dd6ff0b33638bf2 100755
--- a/f2/src/stm32f2xx_hal_rcc.c
+++ b/f2/src/stm32f2xx_hal_rcc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_rcc.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -35,11 +35,30 @@
(+) Configure the clock source(s) for peripherals which clocks are not
derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
+ ##### RCC Limitations #####
+ ==============================================================================
+ [..]
+ A delay between an RCC peripheral clock enable and the effective peripheral
+ enabling should be taken into account in order to manage the peripheral read/write
+ from/to registers.
+ (+) This delay depends on the peripheral mapping.
+ (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
+ after the clock enable bit is set on the hardware register
+ (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
+ after the clock enable bit is set on the hardware register
+
+ [..]
+ Possible Workarounds:
+ (#) Enable the peripheral clock sometimes before the peripheral read/write
+ register is required.
+ (#) For AHB peripheral, insert two dummy read to the peripheral register.
+ (#) For APB peripheral, insert a dummy read to the peripheral register.
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -73,7 +92,7 @@
* @{
*/
-/** @defgroup RCC
+/** @defgroup RCC RCC
* @brief RCC HAL module driver
* @{
*/
@@ -82,32 +101,40 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+/** @addtogroup RCC_Private_Constants
+ * @{
+ */
#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
/* Private macro -------------------------------------------------------------*/
-#define __MCO1_CLK_ENABLE() __GPIOA_CLK_ENABLE()
+#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define MCO1_GPIO_PORT GPIOA
#define MCO1_PIN GPIO_PIN_8
-#define __MCO2_CLK_ENABLE() __GPIOC_CLK_ENABLE()
+#define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define MCO2_GPIO_PORT GPIOC
#define MCO2_PIN GPIO_PIN_9
+/**
+ * @}
+ */
/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Variables RCC Private Variables
+ * @{
+ */
const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+ * @}
+ */
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup RCC_Private_Functions
- * @{
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+ * @{
*/
-/** @defgroup RCC_Group1 Initialization and de-initialization functions
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -115,7 +142,7 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7,
##### Initialization and de-initialization functions #####
===============================================================================
[..]
- This section provide functions allowing to configure the internal/external oscillators
+ This section provides functions allowing to configure the internal/external oscillators
(HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
and APB2).
@@ -138,7 +165,7 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7,
(#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
and if a HSE clock failure occurs(HSE used directly or through PLL as System
- clock source), the System clockis automatically switched to HSI and an interrupt
+ clock source), the System clocks automatically switched to HSI and an interrupt
is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
(Non-Maskable Interrupt) exception vector.
@@ -211,7 +238,6 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7,
* @note This function doesn't modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
- * @param None
* @retval None
*/
void HAL_RCC_DeInit(void)
@@ -250,8 +276,7 @@ void HAL_RCC_DeInit(void)
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
-
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
@@ -261,9 +286,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
{
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON))
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
{
return HAL_ERROR;
}
@@ -273,48 +299,48 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
__HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
- /* Get timeout */
- timeout = HAL_GetTick() + HSE_TIMEOUT_VALUE;
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
/* Check the HSE State */
- if((RCC_OscInitStruct->HSEState) == RCC_HSE_ON)
+ if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
{
- /* Get timeout */
- timeout = HAL_GetTick() + HSE_TIMEOUT_VALUE;
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else
{
- /* Get timeout */
- timeout = HAL_GetTick() + HSE_TIMEOUT_VALUE;
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
}
@@ -326,13 +352,21 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
- /* When the HSI is used as system clock it will not disabled */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
{
+ /* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
{
return HAL_ERROR;
}
+ /* Otherwise, just the calibration is allowed */
+ else
+ {
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
}
else
{
@@ -342,16 +376,16 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
- /* Get timeout */
- timeout = HAL_GetTick() + HSI_TIMEOUT_VALUE;
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
@@ -362,16 +396,16 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
- /* Get timeout */
- timeout = HAL_GetTick() + HSI_TIMEOUT_VALUE;
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
}
@@ -387,34 +421,34 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
-
- /* Get timeout */
- timeout = HAL_GetTick() + LSI_TIMEOUT_VALUE;
-
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
-
- /* Get timeout */
- timeout = HAL_GetTick() + LSI_TIMEOUT_VALUE;
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
}
@@ -425,65 +459,66 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Enable Power Clock*/
- __PWR_CLK_ENABLE();
+ __HAL_RCC_PWR_CLK_ENABLE();
/* Enable write access to Backup domain */
PWR->CR |= PWR_CR_DBP;
/* Wait for Backup domain Write protection disable */
- timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE;
+ tickstart = HAL_GetTick();
while((PWR->CR & PWR_CR_DBP) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
+
/* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
__HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
- /* Get timeout */
- timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE;
-
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
/* Check the LSE State */
- if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
+ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
{
- /* Get timeout */
- timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE;
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else
{
- /* Get timeout */
- timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE;
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
}
@@ -503,57 +538,58 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
-
+
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
-
- /* Get timeout */
- timeout = HAL_GetTick() + PLL_TIMEOUT_VALUE;
-
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
/* Configure the main PLL clock source, multiplication and division factors. */
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- RCC_OscInitStruct->PLL.PLLM,
- RCC_OscInitStruct->PLL.PLLN,
- RCC_OscInitStruct->PLL.PLLP,
- RCC_OscInitStruct->PLL.PLLQ);
+ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
+ RCC_OscInitStruct->PLL.PLLM | \
+ (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
+ (((RCC_OscInitStruct->PLL.PLLP >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
+ (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
- /* Get timeout */
- timeout = HAL_GetTick() + PLL_TIMEOUT_VALUE;
-
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
- /* Get timeout */
- timeout = HAL_GetTick() + PLL_TIMEOUT_VALUE;
-
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
}
@@ -592,8 +628,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
-
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
@@ -638,7 +673,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
}
/* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK))
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
@@ -655,36 +690,36 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
return HAL_ERROR;
}
}
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
-
- /* Get timeout */
- timeout = HAL_GetTick() + CLOCKSWITCH_TIMEOUT_VALUE;
+
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else
{
- while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
+ while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -717,7 +752,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
}
/* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK))
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
@@ -734,16 +769,15 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
return HAL_ERROR;
}
}
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
-
- /* Get timeout */
- timeout = HAL_GetTick() + CLOCKSWITCH_TIMEOUT_VALUE;
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -751,9 +785,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -761,12 +795,12 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
else
{
- while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
+ while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
}
@@ -796,16 +830,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
}
- /* Setup SysTick Timer for 1 msec interrupts.
- ------------------------------------------
- The SysTick_Config() function is a CMSIS function which configure:
- - The SysTick Reload register with value passed as function parameter.
- - Configure the SysTick IRQ priority to the lowest value (0x0F).
- - Reset the SysTick Counter register.
- - Configure the SysTick Counter clock source to be Core Clock Source (HCLK).
- - Enable the SysTick Interrupt.
- - Start the SysTick Counter.*/
- SysTick_Config(HAL_RCC_GetHCLKFreq() / 1000);
+ /* Configure the source of time base considering new system clocks settings*/
+ HAL_InitTick (TICK_INT_PRIORITY);
return HAL_OK;
}
@@ -814,7 +840,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
* @}
*/
-/** @defgroup RCC_Group2 Peripheral Control functions
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
* @brief RCC clocks control functions
*
@verbatim
@@ -869,10 +895,10 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
/* MCO1 Clock Enable */
__MCO1_CLK_ENABLE();
- /* Configue the MCO1 pin in alternate function mode */
+ /* Configure the MCO1 pin in alternate function mode */
GPIO_InitStruct.Pin = MCO1_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
@@ -887,10 +913,10 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
/* MCO2 Clock Enable */
__MCO2_CLK_ENABLE();
- /* Configue the MCO2 pin in alternate function mode */
+ /* Configure the MCO2 pin in alternate function mode */
GPIO_InitStruct.Pin = MCO2_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
@@ -907,22 +933,20 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
* software about the failure (Clock Security System Interrupt, CSSI),
* allowing the MCU to perform rescue operations. The CSSI is linked to
* the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
- * @param None
* @retval None
*/
void HAL_RCC_EnableCSS(void)
{
- *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)ENABLE;
+ *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
}
/**
* @brief Disables the Clock Security System.
- * @param None
* @retval None
*/
void HAL_RCC_DisableCSS(void)
{
- *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)DISABLE;
+ *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
}
/**
@@ -953,7 +977,6 @@ void HAL_RCC_DisableCSS(void)
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
*
- * @param None
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
@@ -979,7 +1002,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
- if (__RCC_PLLSRC() != 0)
+ if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
{
/* HSE used as PLL clock source */
pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
@@ -1010,7 +1033,6 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
- * @param None
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
@@ -1023,7 +1045,6 @@ uint32_t HAL_RCC_GetHCLKFreq(void)
* @brief Returns the PCLK1 frequency
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
- * @param None
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
@@ -1036,7 +1057,6 @@ uint32_t HAL_RCC_GetPCLK1Freq(void)
* @brief Returns the PCLK2 frequency
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
- * @param None
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
@@ -1126,7 +1146,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/**
* @brief Configures the RCC_ClkInitStruct according to the internal
* RCC configuration registers.
- * @param RCC_OscInitStruct: pointer to an RCC_ClkInitTypeDef structure that
+ * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
* will be configured.
* @param pFLatency: Pointer on the Flash Latency.
* @retval None
@@ -1155,7 +1175,6 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF
/**
* @brief This function handles the RCC CSS interrupt request.
* @note This API should be called under the NMI_Handler().
- * @param None
* @retval None
*/
void HAL_RCC_NMI_IRQHandler(void)
@@ -1164,7 +1183,7 @@ void HAL_RCC_NMI_IRQHandler(void)
if(__HAL_RCC_GET_IT(RCC_IT_CSS))
{
/* RCC Clock Security System interrupt user callback */
- HAL_RCC_CCSCallback();
+ HAL_RCC_CSSCallback();
/* Clear RCC CSS pending bit */
__HAL_RCC_CLEAR_IT(RCC_IT_CSS);
@@ -1173,13 +1192,12 @@ void HAL_RCC_NMI_IRQHandler(void)
/**
* @brief RCC Clock Security System interrupt callback
- * @param none
- * @retval none
+ * @retval None
*/
-__weak void HAL_RCC_CCSCallback(void)
+__weak void HAL_RCC_CSSCallback(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RCC_CCSCallback could be implemented in the user file
+ the HAL_RCC_CSSCallback could be implemented in the user file
*/
}
diff --git a/f2/src/stm32f2xx_hal_rcc_ex.c b/f2/src/stm32f2xx_hal_rcc_ex.c
index 6cd97c80b329f4b43730d8dfeb65afb7b325139e..6adc6b139473184833310d9befecce539a794da3 100755
--- a/f2/src/stm32f2xx_hal_rcc_ex.c
+++ b/f2/src/stm32f2xx_hal_rcc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_rcc_ex.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief Extension RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -46,8 +46,8 @@
* @{
*/
-/** @defgroup RCC
- * @brief RCC HAL module driver
+/** @defgroup RCCEx RCCEx
+ * @brief RCCEx HAL module driver
* @{
*/
@@ -55,17 +55,21 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-#define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
+/** @addtogroup RCCEx_Private_Constants
+ * @{
+ */
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCCEx_Private_Functions
- * @{
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+ * @{
*/
-/** @defgroup RCCEx_Group1 Extended Peripheral Control functions
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
* @brief Extended Peripheral Control functions
*
@verbatim
@@ -76,9 +80,10 @@
This subsection provides a set of functions allowing to control the RCC Clocks
frequencies.
[..]
- (@) Important note: A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock source, in this case
- * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
- * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset.
+ (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+ select the RTC clock source; in this case the Backup domain will be reset in
+ order to modify the RTC Clock source, as consequence RTC registers (including
+ the backup registers) and RCC_BDCR register are set to their reset values.
@endverbatim
* @{
@@ -90,7 +95,7 @@
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
* contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
*
- * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock source, in this case
+ * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
* the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
* domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
*
@@ -98,109 +103,110 @@
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
- uint32_t timeout = 0;
- uint32_t tmpreg = 0;
+ uint32_t tickstart = 0;
+ uint32_t tmpreg1 = 0;
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
- /*---------------------------- I2S configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+ /*---------------------------- I2S configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))|| \
+ (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
/* Disable the PLLI2S */
- __HAL_RCC_PLLI2S_DISABLE();
- /* Get new Timeout value */
- timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE;
+ __HAL_RCC_PLLI2S_DISABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Wait till PLLI2S is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
{
- /* return in case of Timeout detected */
+ /* return in case of Timeout detected */
return HAL_TIMEOUT;
}
}
/* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
- /* Get new Timeout value */
- timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE;
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
{
- /* return in case of Timeout detected */
+ /* return in case of Timeout detected */
return HAL_TIMEOUT;
}
}
}
+ /*--------------------------------------------------------------------------*/
- /*---------------------------- RTC configuration -------------------------------*/
+ /*----------------------------- RTC configuration --------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
- {
+ {
/* Enable Power Clock*/
- __PWR_CLK_ENABLE();
+ __HAL_RCC_PWR_CLK_ENABLE();
/* Enable write access to Backup domain */
PWR->CR |= PWR_CR_DBP;
- /* Wait for Backup domain Write protection disable */
- timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE;
+ /* Get tick */
+ tickstart = HAL_GetTick();
while((PWR->CR & PWR_CR_DBP) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
-
- /* Reset the Backup domain only if the RTC Clock source selction is modified */
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */
if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
{
/* Store the content of BDCR register before the reset of Backup Domain */
- tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
__HAL_RCC_BACKUPRESET_RELEASE();
/* Restore the Content of BDCR register */
- RCC->BDCR = tmpreg;
- }
-
- /* If LSE is selected as RTC clock source, wait for LSE reactivation */
- if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
- {
- /* Get timeout */
- timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE;
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ RCC->BDCR = tmpreg1;
+ /* Wait for LSERDY if LSE was enabled */
+ if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
{
- if(HAL_GetTick() >= timeout)
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
- return HAL_TIMEOUT;
- }
- }
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
-
+ /*--------------------------------------------------------------------------*/
+
return HAL_OK;
}
/**
* @brief Configures the RCC_OscInitStruct according to the internal
* RCC configuration registers.
- * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
* will be configured.
* @retval None
*/
diff --git a/f2/src/stm32f2xx_hal_rng.c b/f2/src/stm32f2xx_hal_rng.c
index 8f11564270d085500cb70cb7e1a8671794a07096..4135ad54de07c023ca53ffdc8091b5ab4249a780 100755
--- a/f2/src/stm32f2xx_hal_rng.c
+++ b/f2/src/stm32f2xx_hal_rng.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_rng.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
@@ -15,20 +15,21 @@
==============================================================================
##### How to use this driver #####
==============================================================================
- [..]
+ [..]
The RNG HAL driver can be used as follows:
- (#) Enable the RNG controller clock using __RNG_CLK_ENABLE() macro.
- (#) Activate the RNG peripheral using __HAL_RNG_ENABLE() macro.
- (#) Wait until the 32 bit Random Number Generator contains a valid
- random data using (polling/interrupt) mode.
- (#) Get the 32 bit random number using HAL_RNG_GetRandomNumber() function.
+ (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
+ in HAL_RNG_MspInit().
+ (#) Activate the RNG peripheral using HAL_RNG_Init() function.
+ (#) Wait until the 32 bit Random Number Generator contains a valid
+ random data using (polling/interrupt) mode.
+ (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -62,29 +63,37 @@
* @{
*/
-/** @defgroup RNG
- * @brief RNG HAL module driver.
+/** @addtogroup RNG
* @{
*/
#ifdef HAL_RNG_MODULE_ENABLED
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define RNG_TIMEOUT_VALUE 1000
-/* Private macro -------------------------------------------------------------*/
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup RNG_Private_Constants
+ * @{
+ */
+#define RNG_TIMEOUT_VALUE 2
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions prototypes ----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
-/** @defgroup RNG_Private_Functions
+/** @addtogroup RNG_Exported_Functions
* @{
*/
-/** @defgroup RNG_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
+/** @addtogroup RNG_Exported_Functions_Group1
+ * @brief Initialization and de-initialization functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
@@ -94,15 +103,15 @@
(+) DeInitialize the RNG peripheral
(+) Initialize the RNG MSP
(+) DeInitialize RNG MSP
-
+
@endverbatim
* @{
*/
/**
- * @brief Initializes the RNG according to the specified
- * parameters in the RNG_InitTypeDef and creates the associated handle.
- * @param hrng: RNG handle
+ * @brief Initializes the RNG peripheral and creates the associated handle.
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
@@ -112,46 +121,50 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
{
return HAL_ERROR;
}
-
+
+ __HAL_LOCK(hrng);
+
if(hrng->State == HAL_RNG_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hrng->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_RNG_MspInit(hrng);
}
+
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
/* Enable the RNG Peripheral */
__HAL_RNG_ENABLE(hrng);
-
+
/* Initialize the RNG state */
hrng->State = HAL_RNG_STATE_READY;
+ __HAL_UNLOCK(hrng);
+
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitializes the RNG peripheral.
- * @param hrng: RNG handle
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
{
- /* Check the RNG peripheral state */
- if(hrng->State == HAL_RNG_STATE_BUSY)
+ /* Check the RNG handle allocation */
+ if(hrng == NULL)
{
- return HAL_BUSY;
+ return HAL_ERROR;
}
-
- /* Update the RNG state */
- hrng->State = HAL_RNG_STATE_BUSY;
-
/* Disable the RNG Peripheral */
- __HAL_RNG_DISABLE(hrng);
+ CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
- /* Set the RNG registers to their reset values */
- hrng->Instance->CR &= 0xFFFFFFF3;
- hrng->Instance->SR &= 0xFFFFFF98;
- hrng->Instance->DR &= 0x0;
+ /* Clear RNG interrupt status flags */
+ CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
/* DeInit the low level hardware */
HAL_RNG_MspDeInit(hrng);
@@ -168,25 +181,27 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
/**
* @brief Initializes the RNG MSP.
- * @param hrng: RNG handle
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
* @retval None
*/
__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RNG_MspInit could be implemented in the user file
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_RNG_MspInit must be implemented in the user file.
*/
}
/**
* @brief DeInitializes the RNG MSP.
- * @param hrng: RNG handle
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
* @retval None
*/
__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RNG_MspDeInit could be implemented in the user file
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_RNG_MspDeInit must be implemented in the user file.
*/
}
@@ -194,8 +209,8 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
* @}
*/
-/** @defgroup RNG_Group2 Peripheral Control functions
- * @brief management functions.
+/** @addtogroup RNG_Exported_Functions_Group2
+ * @brief Peripheral Control functions
*
@verbatim
===============================================================================
@@ -206,70 +221,102 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
(+) Get the 32 bit Random number with interrupt enabled
(+) Handle RNG interrupt request
-
@endverbatim
* @{
*/
/**
- * @brief Returns a 32-bit random number.
+ * @brief Generates a 32-bit random number.
* @note Each time the random number data is read the RNG_FLAG_DRDY flag
* is automatically cleared.
- * @param hrng: RNG handle
- * @retval 32-bit random number
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @param random32bit: pointer to generated random number variable if successful.
+ * @retval HAL status
*/
-uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
+
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
{
- uint32_t random32bit = 0;
- uint32_t timeout = 0;
-
+ uint32_t tickstart = 0;
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Process Locked */
__HAL_LOCK(hrng);
- timeout = HAL_GetTick() + RNG_TIMEOUT_VALUE;
+ /* Check RNG peripheral state */
+ if(hrng->State == HAL_RNG_STATE_READY)
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check if data register contains valid random data */
+ while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
+ {
+ hrng->State = HAL_RNG_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+
+ return HAL_TIMEOUT;
+ }
+ }
- /* Check if data register contains valid random data */
- while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+ /* Get a 32bit Random number */
+ hrng->RandomNumber = hrng->Instance->DR;
+ *random32bit = hrng->RandomNumber;
+
+ hrng->State = HAL_RNG_STATE_READY;
+ }
+ else
{
- if(HAL_GetTick() >= timeout)
- {
- return HAL_TIMEOUT;
- }
+ status = HAL_ERROR;
}
- /* Get a 32bit Random number */
- random32bit = hrng->Instance->DR;
-
/* Process Unlocked */
__HAL_UNLOCK(hrng);
- /* Return the 32 bit random number */
- return random32bit;
+ return status;
}
/**
- * @brief Returns a 32-bit random number with interrupt enabled.
- * @param hrng: RNG handle
- * @retval 32-bit random number
+ * @brief Generates a 32-bit random number in interrupt mode.
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval HAL status
*/
-uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
{
- uint32_t random32bit = 0;
+ HAL_StatusTypeDef status = HAL_OK;
/* Process Locked */
__HAL_LOCK(hrng);
- /* Change RNG peripheral state */
- hrng->State = HAL_RNG_STATE_BUSY;
-
- /* Get a 32bit Random number */
- random32bit = hrng->Instance->DR;
+ /* Check RNG peripheral state */
+ if(hrng->State == HAL_RNG_STATE_READY)
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
- /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
- __HAL_RNG_ENABLE_IT(hrng);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+
+ /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
+ __HAL_RNG_ENABLE_IT(hrng);
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+
+ status = HAL_ERROR;
+ }
- /* Return the 32 bit random number */
- return random32bit;
+ return status;
}
/**
@@ -277,99 +324,147 @@ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
* @note In the case of a clock error, the RNG is no more able to generate
* random numbers because the PLL48CLK clock is not correct. User has
* to check that the clock controller is correctly configured to provide
- * the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_FLAG().
+ * the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
* The clock error has no impact on the previously generated
* random numbers, and the RNG_DR register contents can be used.
* @note In the case of a seed error, the generation of random numbers is
* interrupted as long as the SECS bit is '1'. If a number is
* available in the RNG_DR register, it must not be used because it may
* not have enough entropy. In this case, it is recommended to clear the
- * SEIS bit using __HAL_RNG_CLEAR_FLAG(), then disable and enable
+ * SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
* the RNG peripheral to reinitialize and restart the RNG.
- * @param hrng: RNG handle
+ * @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
+ * or CEIS are set.
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
* @retval None
*/
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
{
- /* RNG clock error interrupt occured */
- if(__HAL_RNG_GET_FLAG(hrng, RNG_IT_CEI) != RESET)
+ /* RNG clock error interrupt occurred */
+ if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) || (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
{
- HAL_RNG_ErrorCallback(hrng);
-
- /* Clear the clock error flag */
- __HAL_RNG_CLEAR_FLAG(hrng, RNG_IT_CEI);
-
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrng);
- }
- /* RNG seed error interrupt occured */
- if(__HAL_RNG_GET_FLAG(hrng, RNG_IT_SEI) != RESET)
- {
HAL_RNG_ErrorCallback(hrng);
- /* Clear the seed error flag */
- __HAL_RNG_CLEAR_FLAG(hrng, RNG_IT_SEI);
+ /* Clear the clock error flag */
+ __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
- /* Change RNG peripheral state */
- hrng->State = HAL_RNG_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrng);
}
- /* Check RNG data ready flag */
- if(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != RESET)
+ /* Check RNG data ready interrupt occurred */
+ if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
{
- /* Data Ready callback */
- HAL_RNG_ReadyCallback(hrng);
+ /* Generate random number once, so disable the IT */
+ __HAL_RNG_DISABLE_IT(hrng);
- /* Change RNG peripheral state */
- hrng->State = HAL_RNG_STATE_READY;
-
- /* Clear the RNG Data Ready flag */
- __HAL_RNG_CLEAR_FLAG(hrng, RNG_FLAG_DRDY);
+ /* Get the 32bit Random number (DRDY flag automatically cleared) */
+ hrng->RandomNumber = hrng->Instance->DR;
- /* Process Unlocked */
- __HAL_UNLOCK(hrng);
+ if(hrng->State != HAL_RNG_STATE_ERROR)
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_READY;
+
+ /* Data Ready callback */
+ HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
+ }
}
}
+/**
+ * @brief Returns generated random number in polling mode (Obsolete)
+ * Use HAL_RNG_GenerateRandomNumber() API instead.
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval Random value
+ */
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
+{
+ if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
+ {
+ return hrng->RandomNumber;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Returns a 32-bit random number with interrupt enabled (Obsolete),
+ * Use HAL_RNG_GenerateRandomNumber_IT() API instead.
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval 32-bit random number
+ */
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
+{
+ uint32_t random32bit = 0;
+
+ /* Process locked */
+ __HAL_LOCK(hrng);
+
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
+
+ /* Get a 32bit Random number */
+ random32bit = hrng->Instance->DR;
+
+ /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
+ __HAL_RNG_ENABLE_IT(hrng);
+
+ /* Return the 32 bit random number */
+ return random32bit;
+}
+
+/**
+ * @brief Read latest generated random number.
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval random value
+ */
+uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
+{
+ return(hrng->RandomNumber);
+}
+
/**
* @brief Data Ready callback in non-blocking mode.
- * @param hrng: RNG handle
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @param random32bit: generated random number.
* @retval None
*/
-
-__weak void HAL_RNG_ReadyCallback(RNG_HandleTypeDef* hrng)
+__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RNG_ReadyCallback could be implemented in the user file
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_RNG_ReadyDataCallback must be implemented in the user file.
*/
}
/**
* @brief RNG error callbacks.
- * @param hrng: RNG handle
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
* @retval None
*/
__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RNG_ErrorCallback could be implemented in the user file
- */
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_RNG_ErrorCallback must be implemented in the user file.
+ */
}
-
/**
* @}
*/
-/** @defgroup RNG_Group3 Peripheral State functions
- * @brief Peripheral State functions.
+
+/** @addtogroup RNG_Exported_Functions_Group3
+ * @brief Peripheral State functions
*
@verbatim
===============================================================================
@@ -385,7 +480,8 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
/**
* @brief Returns the RNG state.
- * @param hrng: RNG handle
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
* @retval HAL state
*/
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
@@ -411,4 +507,3 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/f2/src/stm32f2xx_hal_rtc.c b/f2/src/stm32f2xx_hal_rtc.c
index 502198450beabe9ed136786723961f5af0bda6ca..4836cc52355890d14ba5618e13cc748ba4a98d0c 100755
--- a/f2/src/stm32f2xx_hal_rtc.c
+++ b/f2/src/stm32f2xx_hal_rtc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_rtc.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
@@ -24,7 +24,7 @@
the RTC when VDD is turned off, VBAT pin can be connected to an optional
standby voltage supplied by a battery or by another source.
- [..] To allow the RTC to operate even when the main digital supply (VDD) is turned
+ [..] To allow the RTC operating even when the main digital supply (VDD) is turned
off, the VBAT pin powers the following blocks:
(#) The RTC
(#) The LSE oscillator
@@ -32,13 +32,13 @@
(#) PC13 to PC15 I/Os, plus PI8 I/O (when available)
[..] When the backup domain is supplied by VDD (analog switch connected to VDD),
- the following functions are available:
+ the following pins are available:
(#) PC14 and PC15 can be used as either GPIO or LSE pins
(#) PC13 can be used as a GPIO or as the RTC_AF1 pin
(#) PI8 can be used as a GPIO or as the RTC_AF2 pin
[..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
- because VDD is not present), the following functions are available:
+ because VDD is not present), the following pins are available:
(#) PC14 and PC15 can be used as LSE pins only
(#) PC13 can be used as the RTC_AF1 pin
(#) PI8 can be used as the RTC_AF2 pin
@@ -47,7 +47,7 @@
==================================================================
[..] The backup domain reset sets all RTC registers and the RCC_BDCR register
to their reset values. The BKPSRAM is not affected by this reset. The only
- way of resetting the BKPSRAM is through the Flash interface by requesting
+ way to reset the BKPSRAM is through the Flash interface by requesting
a protection level change from 1 to 0.
[..] A backup domain reset is generated when one of the following events occurs:
(#) Software reset, triggered by setting the BDRST bit in the
@@ -61,7 +61,7 @@
accesses.
[..] To enable access to the RTC Domain and RTC registers, proceed as follows:
(+) Enable the Power Controller (PWR) APB1 interface clock using the
- __PWR_CLK_ENABLE() function.
+ __HAL_RCC_PWR_CLK_ENABLE() function.
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
(+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
(+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
@@ -93,22 +93,22 @@
[..] The MCU can be woken up from a low power mode by an RTC alternate
function.
[..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
- RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
+ RTC wake-up, RTC tamper event detection and RTC time stamp event detection.
These RTC alternate functions can wake up the system from the Stop and
Standby low power modes.
[..] The system can also wake up from low power modes without depending
- on an external interrupt (Auto-wakeup mode), by using the RTC alarm
- or the RTC wakeup events.
+ on an external interrupt (Auto-wake-up mode), by using the RTC alarm
+ or the RTC wake-up events.
[..] The RTC provides a programmable time base for waking up from the
Stop or Standby mode at regular intervals.
- Wakeup from STOP and Standby modes is possible only when the RTC clock source
+ Wake-up from STOP and STANDBY modes is possible only when the RTC clock source
is LSE or LSI.
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -142,7 +142,7 @@
* @{
*/
-/** @defgroup RTC
+/** @defgroup RTC RTC
* @brief RTC HAL module driver
* @{
*/
@@ -156,34 +156,34 @@
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup RTC_Private_Functions
+/** @defgroup RTC_Exported_Functions RTC Exported Functions
* @{
*/
-
-/** @defgroup RTC_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+
+/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
- [..] This section provide functions allowing to initialize and configure the
+ [..] This section provides functions allowing to initialize and configure the
RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
RTC registers Write protection, enter and exit the RTC initialization mode,
RTC registers synchronization check and reference clock detection enable.
(#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
It is split into 2 programmable prescalers to minimize power consumption.
- (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
+ (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.
(++) When both prescalers are used, it is recommended to configure the
- asynchronous prescaler to a high value to minimize consumption.
+ asynchronous prescaler to a high value to minimize power consumption.
(#) All RTC registers are Write protected. Writing to the RTC registers
is enabled by writing a key into the Write Protection register, RTC_WPR.
- (#) To Configure the RTC Calendar, user application should enter
+ (#) To configure the RTC Calendar, user application should enter
initialization mode. In this mode, the calendar counter is stopped
and its value can be updated. When the initialization sequence is
complete, the calendar restarts counting after 4 RTCCLK cycles.
(#) To read the calendar through the shadow registers after Calendar
- initialization, calendar update or after wakeup from low power modes
+ initialization, calendar update or after wake-up from low power modes
the software must first clear the RSF flag. The software must then
wait until it is set again before reading the calendar, which means
that the calendar registers have been correctly copied into the
@@ -196,7 +196,8 @@
/**
* @brief Initializes the RTC peripheral
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
@@ -217,6 +218,8 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
if(hrtc->State == HAL_RTC_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hrtc->Lock = HAL_UNLOCKED;
/* Initialize RTC MSP */
HAL_RTC_MspInit(hrtc);
}
@@ -267,13 +270,14 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
/**
* @brief DeInitializes the RTC peripheral
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @note This function doesn't reset the RTC Backup Data registers.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
@@ -299,13 +303,14 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
hrtc->Instance->DR = (uint32_t)0x00002101;
/* Reset All CR bits except CR[2:0] */
hrtc->Instance->CR &= (uint32_t)0x00000007;
-
- timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
-
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait till WUTWF flag is set and if Time out is reached exit */
while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -358,25 +363,27 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
/**
* @brief Initializes the RTC MSP.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RTC_MspInit could be implenetd in the user file
+ the HAL_RTC_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes the RTC MSP.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RTC_MspDeInit could be implenetd in the user file
+ the HAL_RTC_MspDeInit could be implemented in the user file
*/
}
@@ -384,7 +391,7 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
* @}
*/
-/** @defgroup RTC_Group2 RTC Time and Date functions
+/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
* @brief RTC Time and Date functions
*
@verbatim
@@ -392,7 +399,7 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
##### RTC Time and Date functions #####
===============================================================================
- [..] This section provide functions allowing to configure Time and Date features
+ [..] This section provides functions allowing to configure Time and Date features
@endverbatim
* @{
@@ -400,12 +407,13 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
/**
* @brief Sets RTC current time.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTime: Pointer to Time structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
@@ -422,7 +430,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
hrtc->State = HAL_RTC_STATE_BUSY;
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
@@ -520,14 +528,16 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
/**
* @brief Gets RTC current time.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTime: Pointer to Time structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
- * @note Call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
- * in the higher-order calendar shadow registers.
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
@@ -547,7 +557,7 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
/* Check the input parameters format */
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
/* Convert the time structure parameters to Binary format */
sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
@@ -560,12 +570,13 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
/**
* @brief Sets RTC current date.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sDate: Pointer to date structure
* @param Format: specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
@@ -580,14 +591,14 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
hrtc->State = HAL_RTC_STATE_BUSY;
- if((Format == FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
+ if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
{
sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A);
}
assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
assert_param(IS_RTC_YEAR(sDate->Year));
assert_param(IS_RTC_MONTH(sDate->Month));
@@ -664,12 +675,16 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
/**
* @brief Gets RTC current date.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sDate: Pointer to Date structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN : Binary data format
- * @arg Format_BCD : BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
@@ -689,7 +704,7 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13);
/* Check the input parameters format */
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
/* Convert the date structure parameters to Binary format */
sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
@@ -703,7 +718,7 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
* @}
*/
-/** @defgroup RTC_Group3 RTC Alarm functions
+/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
* @brief RTC Alarm functions
*
@verbatim
@@ -711,30 +726,31 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
##### RTC Alarm functions #####
===============================================================================
- [..] This section provide functions allowing to configure Alarm feature
+ [..] This section provides functions allowing to configure Alarm feature
@endverbatim
* @{
*/
/**
* @brief Sets the specified RTC Alarm.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sAlarm: Pointer to Alarm structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_ALARM(sAlarm->Alarm));
- assert_param(IS_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
/* Process Locked */
@@ -742,7 +758,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
hrtc->State = HAL_RTC_STATE_BUSY;
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
@@ -822,12 +838,14 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
- timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -852,12 +870,14 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
-
- timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -890,23 +910,24 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
/**
* @brief Sets the specified RTC Alarm with Interrupt
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sAlarm: Pointer to Alarm structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_ALARM(sAlarm->Alarm));
- assert_param(IS_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
/* Process Locked */
@@ -914,7 +935,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
hrtc->State = HAL_RTC_STATE_BUSY;
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
@@ -993,11 +1014,13 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
/* Clear flag alarm A */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
- timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1025,11 +1048,13 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
/* Clear flag alarm B */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
- timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1051,7 +1076,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
}
/* RTC Alarm Interrupt Configuration: EXTI configuration */
- __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT);
+ __HAL_RTC_ALARM_EXTI_ENABLE_IT();
EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT;
@@ -1067,20 +1092,21 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
}
/**
- * @brief Deactive the specified RTC Alarm
- * @param hrtc: RTC handle
+ * @brief Deactivate the specified RTC Alarm
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Alarm: Specifies the Alarm.
* This parameter can be one of the following values:
- * @arg ALARM_A : AlarmA
- * @arg ALARM_B : AlarmB
+ * @arg RTC_ALARM_A: AlarmA
+ * @arg RTC_ALARM_B: AlarmB
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Check the parameters */
- assert_param(IS_ALARM(Alarm));
+ assert_param(IS_RTC_ALARM(Alarm));
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -1097,13 +1123,14 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
- timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
-
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1124,13 +1151,14 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
-
- timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
-
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1157,16 +1185,17 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
/**
* @brief Gets the RTC Alarm value and masks.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sAlarm: Pointer to Date structure
- * @param Alarm: Specifies the Alarm
+ * @param Alarm: Specifies the Alarm.
* This parameter can be one of the following values:
- * @arg ALARM_A: AlarmA
- * @arg ALARM_B: AlarmB
+ * @arg RTC_ALARM_A: AlarmA
+ * @arg RTC_ALARM_B: AlarmB
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
@@ -1175,7 +1204,7 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_ALARM(Alarm));
+ assert_param(IS_RTC_ALARM(Alarm));
if(Alarm == RTC_ALARM_A)
{
@@ -1200,7 +1229,7 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
@@ -1213,7 +1242,8 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
/**
* @brief This function handles Alarm interrupt request.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
@@ -1245,7 +1275,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
}
/* Clear the EXTI's line Flag for RTC Alarm */
- __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT);
+ __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@@ -1253,7 +1283,8 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
/**
* @brief Alarm A callback.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
@@ -1265,23 +1296,23 @@ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
/**
* @brief This function handles AlarmA Polling request.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
+{
+ uint32_t tickstart = 0;
- uint32_t timeout = 0;
+ /* Get tick */
+ tickstart = HAL_GetTick();
- /* Get Timeout value */
- timeout = HAL_GetTick() + Timeout;
-
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
{
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
@@ -1302,7 +1333,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T
* @}
*/
-/** @defgroup RTC_Group4 Peripheral Control functions
+/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
@@ -1323,27 +1354,29 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T
* @note The RTC Resynchronization mode is write protected, use the
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
* @note To read the calendar through the shadow registers after Calendar
- * initialization, calendar update or after wakeup from low power modes
+ * initialization, calendar update or after wake-up from low power modes
* the software must first clear the RSF flag.
* The software must then wait until it is set again before reading
* the calendar, which means that the calendar registers have been
* correctly copied into the RTC_TR and RTC_DR shadow registers.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Clear RSF flag */
hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
-
- timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Wait the registers to be synchronised */
while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -1352,7 +1385,11 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
return HAL_OK;
}
-/** @defgroup RTC_Group5 Peripheral State functions
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
@@ -1367,8 +1404,9 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
* @{
*/
/**
- * @brief Returns the Alarm state.
- * @param hrtc: RTC handle
+ * @brief Returns the RTC state.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL state
*/
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
@@ -1384,24 +1422,27 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
* @brief Enters the RTC Initialization mode.
* @note The RTC Initialization mode is write protected, use the
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Check if the Initialization mode is set */
if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
{
/* Set the Initialization mode */
hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
-
- timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait till RTC is in INIT state and if Time out is reached exit */
while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
diff --git a/f2/src/stm32f2xx_hal_rtc_ex.c b/f2/src/stm32f2xx_hal_rtc_ex.c
index 32710d9c24d56c079df37e0f31ba18822362717d..bb11dea3f8b44feb725ee4a43e9665b01fa7781f 100755
--- a/f2/src/stm32f2xx_hal_rtc_ex.c
+++ b/f2/src/stm32f2xx_hal_rtc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_rtc_ex.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extension peripheral:
@@ -22,19 +22,19 @@
(+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
format using the HAL_RTC_Init() function.
- *** RTC Wakeup configuration ***
+ *** RTC Wake-up configuration ***
================================
[..]
- (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
- function. You can also configure the RTC Wakeup timer with interrupt mode
+ (+) To configure the RTC Wake-up Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
+ function. You can also configure the RTC Wake-up timer in interrupt mode
using the HAL_RTC_SetWakeUpTimer_IT() function.
- (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer()
+ (+) To read the RTC Wake-up Counter register, use the HAL_RTC_GetWakeUpTimer()
function.
*** TimeStamp configuration ***
===============================
[..]
- (+) Configure the RTC_AFx trigger and enables the RTC TimeStamp using the
+ (+) Configure the RTC_AFx trigger and enable the RTC TimeStamp using the
HAL_RTC_SetTimeStamp() function. You can also configure the RTC TimeStamp with
interrupt mode using the HAL_RTC_SetTimeStamp_IT() function.
(+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
@@ -47,10 +47,10 @@
*** Tamper configuration ***
============================
[..]
- (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge
+ (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
or Level according to the Tamper filter (if equal to 0 Edge else Level)
value, sampling frequency, precharge or discharge and Pull-UP using the
- HAL_RTC_SetTamper() function. You can configure RTC Tamper with interrupt
+ HAL_RTC_SetTamper() function. You can configure RTC Tamper in interrupt
mode using HAL_RTC_SetTamper_IT() function.
(+) The TAMPER1 alternate function can be mapped either to RTC_AF1 (PC13)
or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in
@@ -69,7 +69,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -103,7 +103,7 @@
* @{
*/
-/** @defgroup RTCEx
+/** @defgroup RTCEx RTCEx
* @brief RTC HAL module driver
* @{
*/
@@ -117,20 +117,19 @@
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Functions
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
* @{
- */
-
+ */
-/** @defgroup RTCEx_Group1 RTC TimeStamp and Tamper functions
- * @brief RTC TimeStamp and Tamper functions
- *
+/** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions
+ * @brief RTC TimeStamp and Tamper functions
+ *
@verbatim
===============================================================================
##### RTC TimeStamp and Tamper functions #####
===============================================================================
- [..] This section provide functions allowing to configure TimeStamp feature
+ [..] This section provides functions allowing to configure TimeStamp feature
@endverbatim
* @{
@@ -139,18 +138,19 @@
/**
* @brief Sets TimeStamp.
* @note This API must be called before enabling the TimeStamp feature.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
* activated.
- * This parameter can be one of the following:
- * @arg TimeStampEdge_Rising: the Time stamp event occurs on the
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
* rising edge of the related pin.
- * @arg TimeStampEdge_Falling: the Time stamp event occurs on the
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
* falling edge of the related pin.
* @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
- * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPPIN_POS1: PI8 is selected as RTC TimeStamp Pin.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
@@ -196,19 +196,20 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS
/**
* @brief Sets TimeStamp with Interrupt.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @note This API must be called before enabling the TimeStamp feature.
* @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
* activated.
- * This parameter can be one of the following:
- * @arg TimeStampEdge_Rising: the Time stamp event occurs on the
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
* rising edge of the related pin.
- * @arg TimeStampEdge_Falling: the Time stamp event occurs on the
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
* falling edge of the related pin.
* @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
- * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPPIN_POS1: PI8 is selected as RTC TimeStamp Pin.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
@@ -244,7 +245,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti
__HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
/* RTC timestamp Interrupt Configuration: EXTI configuration */
- __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
@@ -261,7 +262,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti
/**
* @brief Deactivates TimeStamp.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
@@ -298,13 +300,14 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
/**
* @brief Gets the RTC TimeStamp value.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTimeStamp: Pointer to Time structure
* @param sTimeStampDate: Pointer to Date structure
* @param Format: specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
+ * RTC_FORMAT_BIN: Binary data format
+ * RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
@@ -331,7 +334,7 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe
sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
/* Check the input parameters format */
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
/* Convert the TimeStamp structure parameters to Binary format */
sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
@@ -353,7 +356,8 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe
/**
* @brief Sets Tamper
* @note By calling this API we disable the tamper interrupt for all tampers.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTamper: Pointer to Tamper Structure.
* @retval HAL status
*/
@@ -388,7 +392,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef
/**
* @brief Sets Tamper with interrupt.
* @note By calling this API we force the tamper interrupt for all tampers.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTamper: Pointer to RTC Tamper.
* @retval HAL status
*/
@@ -416,7 +421,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE;
/* RTC Tamper Interrupt Configuration: EXTI configuration */
- __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
@@ -430,14 +435,15 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
/**
* @brief Deactivates Tamper.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Tamper: Selected tamper pin.
* This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
{
- assert_param(IS_TAMPER(Tamper));
+ assert_param(IS_RTC_TAMPER(Tamper));
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -457,7 +463,8 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T
/**
* @brief This function handles TimeStamp interrupt request.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
@@ -490,7 +497,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
}
/* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
- __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@@ -498,7 +505,8 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
/**
* @brief TimeStamp callback.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
@@ -510,7 +518,8 @@ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
/**
* @brief Tamper 1 callback.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
@@ -522,22 +531,23 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
/**
* @brief This function handles TimeStamp polling request.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
- /* Get Timeout value */
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
{
if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
{
- /* Clear the TIMESTAMP OverRun Flag */
+ /* Clear the TIMESTAMP Overrun Flag */
__HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
/* Change TIMESTAMP state */
@@ -548,7 +558,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
@@ -564,23 +574,24 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3
/**
* @brief This function handles Tamper1 Polling.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
- /* Get Timeout value */
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Get the status of the Interrupt */
while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET)
{
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
@@ -601,15 +612,15 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_
* @}
*/
-/** @defgroup RTCEx_Group2 RTC Wake-up functions
- * @brief RTC Wake-up functions
- *
+/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions
+ * @brief RTC Wake-up functions
+ *
@verbatim
===============================================================================
##### RTC Wake-up functions #####
===============================================================================
- [..] This section provide functions allowing to configure Wake-up feature
+ [..] This section provides functions allowing to configure Wake-up feature
@endverbatim
* @{
@@ -617,18 +628,19 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_
/**
* @brief Sets wake up timer.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param WakeUpCounter: Wake up counter
* @param WakeUpClock: Wake up clock
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Check the parameters */
- assert_param(IS_WAKEUP_CLOCK(WakeUpClock));
- assert_param(IS_WAKEUP_COUNTER(WakeUpCounter));
+ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
+ assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -637,15 +649,39 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
+
+ /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
+ if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
+ {
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
- timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -659,16 +695,16 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
}
}
- /* Clear the Wakeup Timer clock source bits in CR register */
+ /* Clear the Wake-up Timer clock source bits in CR register */
hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
/* Configure the clock source */
hrtc->Instance->CR |= (uint32_t)WakeUpClock;
- /* Configure the Wakeup Timer counter */
+ /* Configure the Wake-up Timer counter */
hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
- /* Enable the Wakeup Timer */
+ /* Enable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
/* Enable the write protection for RTC registers */
@@ -684,18 +720,19 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
/**
* @brief Sets wake up timer with interrupt
- * @param hrtc: RTC handle
- * @param WakeUpCounter: wake up counter
- * @param WakeUpClock: wake up clock
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param WakeUpCounter: Wake up counter
+ * @param WakeUpClock: Wake up clock
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Check the parameters */
- assert_param(IS_WAKEUP_CLOCK(WakeUpClock));
- assert_param(IS_WAKEUP_COUNTER(WakeUpCounter));
+ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
+ assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -704,15 +741,39 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
+
+ /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
+ if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
+ {
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
- timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
-
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -726,24 +787,24 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
}
}
- /* Configure the Wakeup Timer counter */
+ /* Configure the Wake-up Timer counter */
hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
- /* Clear the Wakeup Timer clock source bits in CR register */
+ /* Clear the Wake-up Timer clock source bits in CR register */
hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
/* Configure the clock source */
hrtc->Instance->CR |= (uint32_t)WakeUpClock;
/* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
- __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;
/* Configure the Interrupt in the RTC_CR register */
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
- /* Enable the Wakeup Timer */
+ /* Enable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
/* Enable the write protection for RTC registers */
@@ -759,12 +820,13 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
/**
* @brief Deactivates wake up timer counter.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -774,17 +836,19 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Disable the Wakeup Timer */
+ /* Disable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
-
- timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -811,7 +875,8 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
/**
* @brief Gets wake up timer counter.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval Counter value
*/
uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
@@ -822,7 +887,8 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
/**
* @brief This function handles Wake Up Timer interrupt request.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
@@ -841,15 +907,16 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
}
/* Clear the EXTI's line Flag for RTC WakeUpTimer */
- __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
-
+ __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
+
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
/**
* @brief Wake Up Timer callback.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
@@ -861,22 +928,23 @@ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
/**
* @brief This function handles Wake Up Timer Polling.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
- /* Get Timeout value */
- timeout = HAL_GetTick() + Timeout;
-
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
{
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
@@ -898,28 +966,27 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin
* @}
*/
-
-/** @defgroup RTCEx_Group3 Extension Peripheral Control functions
- * @brief Extension Peripheral Control functions
- *
+/** @defgroup RTCEx_Exported_Functions_Group3 Extension Peripheral Control functions
+ * @brief Extension Peripheral Control functions
+ *
@verbatim
===============================================================================
##### Extension Peripheral Control functions #####
===============================================================================
[..]
This subsection provides functions allowing to
- (+) Writes a data in a specified RTC Backup data register
+ (+) Write a data in a specified RTC Backup data register
(+) Read a data in a specified RTC Backup data register
- (+) Sets the Coarse calibration parameters.
- (+) Deactivates the Coarse calibration parameters
- (+) Sets the Smooth calibration parameters.
- (+) Configures the Synchronization Shift Control Settings.
- (+) Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- (+) Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- (+) Enables the RTC reference clock detection.
+ (+) Set the Coarse calibration parameters.
+ (+) Deactivate the Coarse calibration parameters
+ (+) Set the Smooth calibration parameters.
+ (+) Configure the Synchronization Shift Control Settings.
+ (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Enable the RTC reference clock detection.
(+) Disable the RTC reference clock detection.
- (+) Enables the Bypass Shadow feature.
- (+) Disables the Bypass Shadow feature.
+ (+) Enable the Bypass Shadow feature.
+ (+) Disable the Bypass Shadow feature.
@endverbatim
* @{
@@ -927,11 +994,12 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin
/**
* @brief Writes a data in a specified RTC Backup data register.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param BackupRegister: RTC Backup data Register number.
* This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
* specify the register.
- * @param Data: Data to be written in the specified RTC Backup data register.
+ * @param Data: Data to be written in the specified RTC Backup data register.
* @retval None
*/
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
@@ -950,10 +1018,11 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3
/**
* @brief Reads data from the specified RTC Backup data Register.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param BackupRegister: RTC Backup data Register number.
* This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
- * specify the register.
+ * specify the register.
* @retval Read value
*/
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
@@ -972,7 +1041,8 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
/**
* @brief Sets the Coarse calibration parameters.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param CalibSign: Specifies the sign of the coarse calibration value.
* This parameter can be one of the following values :
* @arg RTC_CALIBSIGN_POSITIVE: The value sign is positive
@@ -1040,7 +1110,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef* hrtc, uint32_t Cal
/**
* @brief Deactivates the Coarse calibration parameters.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc)
@@ -1119,7 +1190,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc)
/**
* @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
@@ -1148,7 +1220,8 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
/**
* @brief Enables the RTC reference clock detection.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
@@ -1197,7 +1270,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
/**
* @brief Disable the RTC reference clock detection.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
@@ -1248,15 +1322,15 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
* @}
*/
- /** @defgroup RTCEx_Group4 Extended features functions
- * @brief Extended features functions
- *
+/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
+ * @brief Extended features functions
+ *
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
- (+) RTC Alram B callback
+ (+) RTC Alarm B callback
(+) RTC Poll for Alarm B request
@endverbatim
@@ -1265,7 +1339,8 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
/**
* @brief Alarm B callback.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
@@ -1277,22 +1352,23 @@ __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
/**
* @brief This function handles AlarmB Polling request.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
- /* Get Timeout value */
- timeout = HAL_GetTick() + Timeout;
-
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
{
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
diff --git a/f2/src/stm32f2xx_hal_sd.c b/f2/src/stm32f2xx_hal_sd.c
index c1ce9d0712c3730c2ab1c0b3ae3e8ab6c60944bb..39363762875ab7d15096cb1dd45d360fb4458c38 100755
--- a/f2/src/stm32f2xx_hal_sd.c
+++ b/f2/src/stm32f2xx_hal_sd.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_sd.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief SD card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:
@@ -30,14 +30,14 @@
It is used as follows:
(#)Initialize the SDIO low level resources by implement the HAL_SD_MspInit() API:
- (##) Enable the SDIO interface clock using __SDIO_CLK_ENABLE();
+ (##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE();
(##) SDIO pins configuration for SD card
- (+++) Enable the clock for the SDIO GPIOs using the functions __GPIOx_CLK_ENABLE();
+ (+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init()
and according to your pin assignment;
(##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
and HAL_SD_WriteBlocks_DMA() APIs).
- (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE();
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
(+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
(##) NVIC configuration if you need to use interrupt process when using DMA transfer.
(+++) Configure the SDIO and DMA interrupt priorities using functions
@@ -54,7 +54,7 @@
================================================
[..]
To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
- the SD Card and put it into StandBy State (Ready for data transfer).
+ the SD Card and put it into Standby State (Ready for data transfer).
This function provide the following operations:
(#) Apply the SD Card initialization process at 400KHz and check the SD Card
@@ -76,10 +76,6 @@
(#) Configure the SD Card Data transfer frequency. By Default, the card transfer
frequency is set to 24MHz. You can change or adapt this frequency by adjusting
the "ClockDiv" field.
- The SD Card frequency (SDIO_CK) is computed as follows:
-
- SDIO_CK = SDIOCLK / (ClockDiv + 2)
-
In transfer mode and according to the SD Card standard, make sure that the
SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
To be able to use a frequency higher than 24MHz, you should use the SDIO
@@ -94,14 +90,14 @@
==============================
[..]
(+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
- This function support only 512-byte block length (the block size should be
- chosen as 512 byte).
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
(+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
- This function support only 512-byte block length (the block size should be
- chosen as 512 byte).
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to call the function HAL_SD_CheckReadOperation(), to insure
@@ -111,13 +107,13 @@
===============================
[..]
(+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
- This function support only 512-byte block length (the block size should be
- chosen as 512 byte).
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
(+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
- This function support only 512-byte block length (the block size should be
+ This function support only 512-bytes block length (the block size should be
chosen as 512 byte).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
@@ -137,7 +133,7 @@
==================================
[..]
Below the list of most used macros in SD HAL driver.
-
+
(+) __HAL_SD_SDIO_ENABLE : Enable the SD device
(+) __HAL_SD_SDIO_DISABLE : Disable the SD device
(+) __HAL_SD_SDIO_DMA_ENABLE: Enable the SDIO DMA transfer
@@ -153,7 +149,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -183,24 +179,33 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f2xx_hal.h"
+#ifdef HAL_SD_MODULE_ENABLED
+
/** @addtogroup STM32F2xx_HAL_Driver
* @{
*/
-/** @defgroup SD
- * @brief SD HAL module driver
+/** @addtogroup SD
* @{
*/
-#ifdef HAL_SD_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-
+/** @addtogroup SD_Private_Defines
+ * @{
+ */
/**
- * @brief SDIO Static flags, TimeOut, FIFO Address
+ * @brief SDIO Data block size
+ */
+#define DATA_BLOCK_SIZE ((uint32_t)(9 << 4))
+/**
+ * @brief SDIO Static flags, Timeout, FIFO Address
*/
-#define SDIO_STATIC_FLAGS ((uint32_t)0x000005FF)
+#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
+ SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\
+ SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\
+ SDIO_FLAG_DBCKEND))
+
#define SDIO_CMD0TIMEOUT ((uint32_t)0x00010000)
/**
@@ -220,7 +225,7 @@
#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000)
#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000)
#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000)
-#define SD_OCR_CID_CSD_OVERWRIETE ((uint32_t)0x00010000)
+#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000)
#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000)
#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000)
#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000)
@@ -269,11 +274,16 @@
*/
#define SD_SDIO_SEND_IF_COND ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/** @addtogroup SD_Private_Functions_Prototypes
+ * @{
+ */
static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd);
static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr);
static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd);
@@ -294,15 +304,18 @@ static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma);
static void SD_DMA_RxError(DMA_HandleTypeDef *hdma);
static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma);
static void SD_DMA_TxError(DMA_HandleTypeDef *hdma);
-
-/** @defgroup SD_Private_Functions
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SD_Exported_Functions
* @{
*/
-/** @defgroup SD_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @addtogroup SD_Exported_Functions_Group1
+ * @brief Initialization and de-initialization functions
*
-@verbatim
+@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
@@ -324,52 +337,54 @@ static void SD_DMA_TxError(DMA_HandleTypeDef *hdma);
*/
HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)
{
- __IO HAL_SD_ErrorTypedef errorState = SD_OK;
- SD_InitTypeDef tmpInit;
+ __IO HAL_SD_ErrorTypedef errorstate = SD_OK;
+ SD_InitTypeDef tmpinit;
+ /* Allocate lock resource and initialize it */
+ hsd->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_SD_MspInit(hsd);
/* Default SDIO peripheral configuration for SD card initialization */
- tmpInit.ClockEdge = SDIO_CLOCK_EDGE_RISING;
- tmpInit.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
- tmpInit.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
- tmpInit.BusWide = SDIO_BUS_WIDE_1B;
- tmpInit.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
- tmpInit.ClockDiv = SDIO_INIT_CLK_DIV;
+ tmpinit.ClockEdge = SDIO_CLOCK_EDGE_RISING;
+ tmpinit.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
+ tmpinit.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
+ tmpinit.BusWide = SDIO_BUS_WIDE_1B;
+ tmpinit.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
+ tmpinit.ClockDiv = SDIO_INIT_CLK_DIV;
/* Initialize SDIO peripheral interface with default configuration */
- SDIO_Init(hsd->Instance, tmpInit);
+ SDIO_Init(hsd->Instance, tmpinit);
/* Identify card operating voltage */
- errorState = SD_PowerON(hsd);
+ errorstate = SD_PowerON(hsd);
- if(errorState != SD_OK)
+ if(errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Initialize the present SDIO card(s) and put them in idle state */
- errorState = SD_Initialize_Cards(hsd);
+ errorstate = SD_Initialize_Cards(hsd);
- if (errorState != SD_OK)
+ if (errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Read CSD/CID MSD registers */
- errorState = HAL_SD_Get_CardInfo(hsd, SDCardInfo);
+ errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo);
- if (errorState == SD_OK)
+ if (errorstate == SD_OK)
{
/* Select the Card */
- errorState = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16));
+ errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16));
}
/* Configure SDIO peripheral interface */
SDIO_Init(hsd->Instance, hsd->Init);
- return errorState;
+ return errorstate;
}
/**
@@ -418,7 +433,7 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
* @}
*/
-/** @defgroup SD_Group2 IO operation functions
+/** @addtogroup SD_Exported_Functions_Group2
* @brief Data transfer functions
*
@verbatim
@@ -440,15 +455,15 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
* @param pReadBuffer: pointer to the buffer that will contain the received data
* @param ReadAddr: Address from where data is to be read
* @param BlockSize: SD card Data block size
- * This parameter should be 512
+ * @note BlockSize must be 512 bytes.
* @param NumberOfBlocks: Number of SD blocks to read
* @retval SD Card error state
*/
HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
{
- SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
- SDIO_DataInitTypeDef SDIO_DataInitStructure;
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure;
+ SDIO_DataInitTypeDef sdio_datainitstructure;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
uint32_t count = 0, *tempbuff = (uint32_t *)pReadBuffer;
/* Initialize data control register */
@@ -461,53 +476,53 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff
}
/* Set Block Size for Card */
- SDIO_CmdInitStructure.Argument = (uint32_t) BlockSize;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
- SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = (uint32_t) BlockSize;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
- if (errorState != SD_OK)
+ if (errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Configure the SD DPSM (Data Path State Machine) */
- SDIO_DataInitStructure.DataTimeOut = SD_DATATIMEOUT;
- SDIO_DataInitStructure.DataLength = NumberOfBlocks * BlockSize;
- SDIO_DataInitStructure.DataBlockSize = (uint32_t)(9 << 4);
- SDIO_DataInitStructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- SDIO_DataInitStructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- SDIO_DataInitStructure.DPSM = SDIO_DPSM_ENABLE;
- SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure);
+ sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
+ sdio_datainitstructure.DataLength = NumberOfBlocks * BlockSize;
+ sdio_datainitstructure.DataBlockSize = DATA_BLOCK_SIZE;
+ sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
if(NumberOfBlocks > 1)
{
/* Send CMD18 READ_MULT_BLOCK with argument data address */
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
}
else
{
/* Send CMD17 READ_SINGLE_BLOCK */
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
}
- SDIO_CmdInitStructure.Argument = (uint32_t)ReadAddr;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Read block(s) in polling mode */
if(NumberOfBlocks > 1)
{
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
- if (errorState != SD_OK)
+ if (errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Poll on SDIO flags */
@@ -528,11 +543,11 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff
else
{
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
- if (errorState != SD_OK)
+ if (errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* In case of single block transfer, no need of stop transfer at all */
@@ -548,7 +563,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff
tempbuff += 8;
}
- }
+ }
}
/* Send stop transmission command in case of multiblock read */
@@ -559,7 +574,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff
(hsd->CardType == HIGH_CAPACITY_SD_CARD))
{
/* Send stop transmission command */
- errorState = HAL_SD_StopTransfer(hsd);
+ errorstate = HAL_SD_StopTransfer(hsd);
}
}
@@ -568,33 +583,37 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
- errorState = SD_DATA_TIMEOUT;
+ errorstate = SD_DATA_TIMEOUT;
- return errorState;
+ return errorstate;
}
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
- errorState = SD_DATA_CRC_FAIL;
+ errorstate = SD_DATA_CRC_FAIL;
- return errorState;
+ return errorstate;
}
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
- errorState = SD_RX_OVERRUN;
+ errorstate = SD_RX_OVERRUN;
- return errorState;
+ return errorstate;
}
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
- errorState = SD_START_BIT_ERR;
+ errorstate = SD_START_BIT_ERR;
- return errorState;
+ return errorstate;
+ }
+ else
+ {
+ /* No error flag set */
}
count = SD_DATATIMEOUT;
@@ -610,7 +629,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff
/* Clear all the static flags */
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- return errorState;
+ return errorstate;
}
/**
@@ -620,16 +639,16 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff
* @param pWriteBuffer: pointer to the buffer that will contain the data to transmit
* @param WriteAddr: Address from where data is to be written
* @param BlockSize: SD card Data block size
- * This parameter should be 512.
+ * @note BlockSize must be 512 bytes.
* @param NumberOfBlocks: Number of SD blocks to write
* @retval SD Card error state
*/
HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
{
- SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
- SDIO_DataInitTypeDef SDIO_DataInitStructure;
- HAL_SD_ErrorTypedef errorState = SD_OK;
- uint32_t TotalNumberOfBytes = 0, bytestransferred = 0, count = 0, restwords = 0;
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure;
+ SDIO_DataInitTypeDef sdio_datainitstructure;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ uint32_t totalnumberofbytes = 0, bytestransferred = 0, count = 0, restwords = 0;
uint32_t *tempbuff = (uint32_t *)pWriteBuffer;
uint8_t cardstate = 0;
@@ -643,61 +662,61 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu
}
/* Set Block Size for Card */
- SDIO_CmdInitStructure.Argument = (uint32_t)BlockSize;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
- SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = (uint32_t)BlockSize;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
- if (errorState != SD_OK)
+ if (errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
if(NumberOfBlocks > 1)
{
/* Send CMD25 WRITE_MULT_BLOCK with argument data address */
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
}
else
{
/* Send CMD24 WRITE_SINGLE_BLOCK */
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
}
- SDIO_CmdInitStructure.Argument = (uint32_t)WriteAddr;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = (uint32_t)WriteAddr;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
if(NumberOfBlocks > 1)
{
- errorState = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
}
else
{
- errorState = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
}
- if (errorState != SD_OK)
+ if (errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Set total number of bytes to write */
- TotalNumberOfBytes = NumberOfBlocks * BlockSize;
+ totalnumberofbytes = NumberOfBlocks * BlockSize;
/* Configure the SD DPSM (Data Path State Machine) */
- SDIO_DataInitStructure.DataTimeOut = SD_DATATIMEOUT;
- SDIO_DataInitStructure.DataLength = NumberOfBlocks * BlockSize;
- SDIO_DataInitStructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- SDIO_DataInitStructure.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
- SDIO_DataInitStructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- SDIO_DataInitStructure.DPSM = SDIO_DPSM_ENABLE;
- SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure);
+ sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
+ sdio_datainitstructure.DataLength = NumberOfBlocks * BlockSize;
+ sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
+ sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
/* Write block(s) in polling mode */
if(NumberOfBlocks > 1)
@@ -706,9 +725,9 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
{
- if ((TotalNumberOfBytes - bytestransferred) < 32)
+ if ((totalnumberofbytes - bytestransferred) < 32)
{
- restwords = ((TotalNumberOfBytes - bytestransferred) % 4 == 0) ? ((TotalNumberOfBytes - bytestransferred) / 4) : (( TotalNumberOfBytes - bytestransferred) / 4 + 1);
+ restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1);
/* Write data to SDIO Tx FIFO */
for (count = 0; count < restwords; count++)
@@ -734,14 +753,14 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu
}
else
{
- /* In case of single data block transfer no need of stop command at all */
+ /* In case of single data block transfer no need of stop command at all */
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
{
- if ((TotalNumberOfBytes - bytestransferred) < 32)
+ if ((totalnumberofbytes - bytestransferred) < 32)
{
- restwords = ((TotalNumberOfBytes - bytestransferred) % 4 == 0) ? ((TotalNumberOfBytes - bytestransferred) / 4) : (( TotalNumberOfBytes - bytestransferred) / 4 + 1);
+ restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1);
/* Write data to SDIO Tx FIFO */
for (count = 0; count < restwords; count++)
@@ -773,7 +792,7 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu
(hsd->CardType == HIGH_CAPACITY_SD_CARD))
{
/* Send stop transmission command */
- errorState = HAL_SD_StopTransfer(hsd);
+ errorstate = HAL_SD_StopTransfer(hsd);
}
}
@@ -782,47 +801,51 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
- errorState = SD_DATA_TIMEOUT;
+ errorstate = SD_DATA_TIMEOUT;
- return errorState;
+ return errorstate;
}
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
- errorState = SD_DATA_CRC_FAIL;
+ errorstate = SD_DATA_CRC_FAIL;
- return errorState;
+ return errorstate;
}
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR);
- errorState = SD_TX_UNDERRUN;
+ errorstate = SD_TX_UNDERRUN;
- return errorState;
+ return errorstate;
}
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
- errorState = SD_START_BIT_ERR;
+ errorstate = SD_START_BIT_ERR;
- return errorState;
+ return errorstate;
+ }
+ else
+ {
+ /* No error flag set */
}
/* Clear all the static flags */
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
/* Wait till the card is in programming state */
- errorState = SD_IsCardProgramming(hsd, &cardstate);
+ errorstate = SD_IsCardProgramming(hsd, &cardstate);
- while ((errorState == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
+ while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
{
- errorState = SD_IsCardProgramming(hsd, &cardstate);
+ errorstate = SD_IsCardProgramming(hsd, &cardstate);
}
- return errorState;
+ return errorstate;
}
/**
@@ -834,15 +857,15 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu
* @param pReadBuffer: Pointer to the buffer that will contain the received data
* @param ReadAddr: Address from where data is to be read
* @param BlockSize: SD card Data block size
- * This paramater should be 512.
+ * @note BlockSize must be 512 bytes.
* @param NumberOfBlocks: Number of blocks to read.
* @retval SD Card error state
*/
HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
{
- SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
- SDIO_DataInitTypeDef SDIO_DataInitStructure;
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure;
+ SDIO_DataInitTypeDef sdio_datainitstructure;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
/* Initialize data control register */
hsd->Instance->DCTRL = 0;
@@ -877,7 +900,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pRead
hsd->hdmarx->XferErrorCallback = SD_DMA_RxError;
/* Enable the DMA Stream */
- HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)SDIO_FIFO_ADDRESS, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks));
+ HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4);
if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
{
@@ -886,59 +909,59 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pRead
}
/* Set Block Size for Card */
- SDIO_CmdInitStructure.Argument = (uint32_t)BlockSize;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
- SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = (uint32_t)BlockSize;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
- if (errorState != SD_OK)
+ if (errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Configure the SD DPSM (Data Path State Machine) */
- SDIO_DataInitStructure.DataTimeOut = SD_DATATIMEOUT;
- SDIO_DataInitStructure.DataLength = BlockSize * NumberOfBlocks;
- SDIO_DataInitStructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- SDIO_DataInitStructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- SDIO_DataInitStructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- SDIO_DataInitStructure.DPSM = SDIO_DPSM_ENABLE;
- SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure);
+ sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
+ sdio_datainitstructure.DataLength = BlockSize * NumberOfBlocks;
+ sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
/* Check number of blocks command */
if(NumberOfBlocks > 1)
{
/* Send CMD18 READ_MULT_BLOCK with argument data address */
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
}
else
{
/* Send CMD17 READ_SINGLE_BLOCK */
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
}
- SDIO_CmdInitStructure.Argument = (uint32_t)ReadAddr;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
if(NumberOfBlocks > 1)
{
- errorState = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
}
else
{
- errorState = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
}
/* Update the SD transfer error in SD handle */
- hsd->SdTransferErr = errorState;
+ hsd->SdTransferErr = errorstate;
- return errorState;
+ return errorstate;
}
@@ -951,15 +974,15 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pRead
* @param pWriteBuffer: pointer to the buffer that will contain the data to transmit
* @param WriteAddr: Address from where data is to be read
* @param BlockSize: the SD card Data block size
- * This parameter should be 512.
+ * @note BlockSize must be 512 bytes.
* @param NumberOfBlocks: Number of blocks to write
* @retval SD Card error state
*/
HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
{
- SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
- SDIO_DataInitTypeDef SDIO_DataInitStructure;
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure;
+ SDIO_DataInitTypeDef sdio_datainitstructure;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
/* Initialize data control register */
hsd->Instance->DCTRL = 0;
@@ -984,14 +1007,14 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWri
SDIO_IT_DTIMEOUT |\
SDIO_IT_DATAEND |\
SDIO_IT_TXUNDERR |\
- SDIO_IT_STBITERR));
+ SDIO_IT_STBITERR));
/* Configure DMA user callbacks */
hsd->hdmatx->XferCpltCallback = SD_DMA_TxCplt;
hsd->hdmatx->XferErrorCallback = SD_DMA_TxError;
/* Enable the DMA Stream */
- HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)SDIO_FIFO_ADDRESS, (uint32_t)(BlockSize * NumberOfBlocks));
+ HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)/4);
/* Enable SDIO DMA transfer */
__HAL_SD_SDIO_DMA_ENABLE();
@@ -1003,63 +1026,63 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWri
}
/* Set Block Size for Card */
- SDIO_CmdInitStructure.Argument = (uint32_t)BlockSize;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
- SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = (uint32_t)BlockSize;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
- if (errorState != SD_OK)
+ if (errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Check number of blocks command */
if(NumberOfBlocks <= 1)
{
/* Send CMD24 WRITE_SINGLE_BLOCK */
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
}
else
{
/* Send CMD25 WRITE_MULT_BLOCK with argument data address */
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
}
- SDIO_CmdInitStructure.Argument = (uint32_t)WriteAddr;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = (uint32_t)WriteAddr;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
if(NumberOfBlocks > 1)
{
- errorState = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
}
else
{
- errorState = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
}
- if (errorState != SD_OK)
+ if (errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Configure the SD DPSM (Data Path State Machine) */
- SDIO_DataInitStructure.DataTimeOut = SD_DATATIMEOUT;
- SDIO_DataInitStructure.DataLength = BlockSize * NumberOfBlocks;
- SDIO_DataInitStructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- SDIO_DataInitStructure.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
- SDIO_DataInitStructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- SDIO_DataInitStructure.DPSM = SDIO_DPSM_ENABLE;
- SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure);
+ sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
+ sdio_datainitstructure.DataLength = BlockSize * NumberOfBlocks;
+ sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
+ sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
- hsd->SdTransferErr = errorState;
+ hsd->SdTransferErr = errorstate;
- return errorState;
+ return errorstate;
}
/**
@@ -1073,7 +1096,7 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWri
*/
HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
{
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
uint32_t timeout = Timeout;
uint32_t tmp1, tmp2;
HAL_SD_ErrorTypedef tmp3;
@@ -1102,12 +1125,12 @@ HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Ti
/* Send stop command in multiblock read */
if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK)
{
- errorState = HAL_SD_StopTransfer(hsd);
+ errorstate = HAL_SD_StopTransfer(hsd);
}
- if ((timeout == 0) && (errorState == SD_OK))
+ if ((timeout == 0) && (errorstate == SD_OK))
{
- errorState = SD_DATA_TIMEOUT;
+ errorstate = SD_DATA_TIMEOUT;
}
/* Clear all the static flags */
@@ -1119,7 +1142,7 @@ HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Ti
return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
}
- return errorState;
+ return errorstate;
}
/**
@@ -1133,7 +1156,7 @@ HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Ti
*/
HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
{
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
uint32_t timeout = Timeout;
uint32_t tmp1, tmp2;
HAL_SD_ErrorTypedef tmp3;
@@ -1162,12 +1185,12 @@ HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t T
/* Send stop command in multiblock write */
if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK)
{
- errorState = HAL_SD_StopTransfer(hsd);
+ errorstate = HAL_SD_StopTransfer(hsd);
}
- if ((timeout == 0) && (errorState == SD_OK))
+ if ((timeout == 0) && (errorstate == SD_OK))
{
- errorState = SD_DATA_TIMEOUT;
+ errorstate = SD_DATA_TIMEOUT;
}
/* Clear all the static flags */
@@ -1184,7 +1207,7 @@ HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t T
{
}
- return errorState;
+ return errorstate;
}
/**
@@ -1196,8 +1219,8 @@ HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t T
*/
HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr)
{
- HAL_SD_ErrorTypedef errorState = SD_OK;
- SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure;
uint32_t delay = 0;
__IO uint32_t maxdelay = 0;
@@ -1206,9 +1229,9 @@ HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint
/* Check if the card command class supports erase command */
if (((hsd->CSD[1] >> 20) & SD_CCCC_ERASE) == 0)
{
- errorState = SD_REQUEST_NOT_APPLICABLE;
+ errorstate = SD_REQUEST_NOT_APPLICABLE;
- return errorState;
+ return errorstate;
}
/* Get max delay value */
@@ -1216,9 +1239,9 @@ HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint
if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
{
- errorState = SD_LOCK_UNLOCK_FAILED;
+ errorstate = SD_LOCK_UNLOCK_FAILED;
- return errorState;
+ return errorstate;
}
/* Get start and end block for high capacity cards */
@@ -1233,64 +1256,64 @@ HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint
(hsd->CardType == HIGH_CAPACITY_SD_CARD))
{
/* Send CMD32 SD_ERASE_GRP_START with argument as addr */
- SDIO_CmdInitStructure.Argument =(uint32_t)startaddr;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_SD_ERASE_GRP_START;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
- SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument =(uint32_t)startaddr;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_START;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START);
- if (errorState != SD_OK)
+ if (errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Send CMD33 SD_ERASE_GRP_END with argument as addr */
- SDIO_CmdInitStructure.Argument = (uint32_t)endaddr;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_SD_ERASE_GRP_END;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = (uint32_t)endaddr;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_END;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END);
- if (errorState != SD_OK)
+ if (errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
}
/* Send CMD38 ERASE */
- SDIO_CmdInitStructure.Argument = 0;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_ERASE;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = 0;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_ERASE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_ERASE);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE);
- if (errorState != SD_OK)
+ if (errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
for (; delay < maxdelay; delay++)
{
}
- /* Wait untill the card is in programming state */
- errorState = SD_IsCardProgramming(hsd, &cardstate);
+ /* Wait until the card is in programming state */
+ errorstate = SD_IsCardProgramming(hsd, &cardstate);
delay = SD_DATATIMEOUT;
- while ((delay > 0) && (errorState == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
+ while ((delay > 0) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
{
- errorState = SD_IsCardProgramming(hsd, &cardstate);
+ errorstate = SD_IsCardProgramming(hsd, &cardstate);
delay--;
}
- return errorState;
+ return errorstate;
}
/**
@@ -1354,6 +1377,10 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
HAL_SD_XferErrorCallback(hsd);
}
+ else
+ {
+ /* No error flag set */
+ }
/* Disable all SDIO peripheral interrupt sources */
__HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND |\
@@ -1388,7 +1415,8 @@ __weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd)
/**
* @brief SD Transfer complete Rx callback in non blocking mode.
- * @param hdma: DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)
@@ -1400,7 +1428,8 @@ __weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)
/**
* @brief SD DMA transfer complete Rx error callback.
- * @param hdma: DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)
@@ -1412,7 +1441,8 @@ __weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)
/**
* @brief SD Transfer complete Tx callback in non blocking mode.
- * @param hdma: DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)
@@ -1424,7 +1454,8 @@ __weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)
/**
* @brief SD DMA transfer complete error Tx callback.
- * @param hdma: DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)
@@ -1438,7 +1469,7 @@ __weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)
* @}
*/
-/** @defgroup SD_Group3 Peripheral Control functions
+/** @addtogroup SD_Exported_Functions_Group3
* @brief management functions
*
@verbatim
@@ -1462,7 +1493,7 @@ __weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)
*/
HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)
{
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
uint32_t tmp = 0;
pCardInfo->CardType = (uint8_t)(hsd->CardType);
@@ -1551,9 +1582,14 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
/* Byte 10 */
tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
- pCardInfo->CardCapacity = ((pCardInfo->SD_csd.DeviceSize + 1)) * 512 * 1024;
+ pCardInfo->CardCapacity = (uint64_t)((((uint64_t)pCardInfo->SD_csd.DeviceSize + 1)) * 512 * 1024);
pCardInfo->CardBlockSize = 512;
}
+ else
+ {
+ /* Not supported card type */
+ errorstate = SD_ERROR;
+ }
pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6;
pCardInfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1;
@@ -1657,7 +1693,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
pCardInfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1;
pCardInfo->SD_cid.Reserved2 = 1;
- return errorState;
+ return errorstate;
}
/**
@@ -1673,64 +1709,51 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
*/
HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode)
{
- HAL_SD_ErrorTypedef errorState = SD_OK;
- SDIO_InitTypeDef Init;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ SDIO_InitTypeDef tmpinit;
/* MMC Card does not support this feature */
if (hsd->CardType == MULTIMEDIA_CARD)
{
- errorState = SD_UNSUPPORTED_FEATURE;
+ errorstate = SD_UNSUPPORTED_FEATURE;
- return errorState;
+ return errorstate;
}
else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
(hsd->CardType == HIGH_CAPACITY_SD_CARD))
{
if (WideMode == SDIO_BUS_WIDE_8B)
{
- errorState = SD_UNSUPPORTED_FEATURE;
-
- return errorState;
+ errorstate = SD_UNSUPPORTED_FEATURE;
}
else if (WideMode == SDIO_BUS_WIDE_4B)
{
- errorState = SD_WideBus_Enable(hsd);
-
- if (errorState == SD_OK)
- {
- /* Configure the SDIO peripheral */
- Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
- Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
- Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
- Init.BusWide = SDIO_BUS_WIDE_4B;
- Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
- Init.ClockDiv = SDIO_TRANSFER_CLK_DIV;
-
- /* Configure SDIO peripheral interface */
- SDIO_Init(hsd->Instance, Init);
- }
+ errorstate = SD_WideBus_Enable(hsd);
+ }
+ else if (WideMode == SDIO_BUS_WIDE_1B)
+ {
+ errorstate = SD_WideBus_Disable(hsd);
}
else
{
- errorState = SD_WideBus_Disable(hsd);
+ /* WideMode is not a valid argument*/
+ errorstate = SD_INVALID_PARAMETER;
+ }
- if (errorState == SD_OK)
- {
- /* Configure the SDIO peripheral */
- Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
- Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
- Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
- Init.BusWide = SDIO_BUS_WIDE_1B;
- Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
- Init.ClockDiv = SDIO_TRANSFER_CLK_DIV;
-
- /* Configure SDIO peripheral interface */
- SDIO_Init(hsd->Instance, Init);
- }
+ if (errorstate == SD_OK)
+ {
+ /* Configure the SDIO peripheral */
+ tmpinit.ClockEdge = hsd->Init.ClockEdge;
+ tmpinit.ClockBypass = hsd->Init.ClockBypass;
+ tmpinit.ClockPowerSave = hsd->Init.ClockPowerSave;
+ tmpinit.BusWide = WideMode;
+ tmpinit.HardwareFlowControl = hsd->Init.HardwareFlowControl;
+ tmpinit.ClockDiv = hsd->Init.ClockDiv;
+ SDIO_Init(hsd->Instance, tmpinit);
}
}
- return errorState;
+ return errorstate;
}
/**
@@ -1740,21 +1763,21 @@ HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32
*/
HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd)
{
- SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
/* Send CMD12 STOP_TRANSMISSION */
- SDIO_CmdInitStructure.Argument = 0;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_STOP_TRANSMISSION;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
- SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = 0;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_STOP_TRANSMISSION;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION);
- return errorState;
+ return errorstate;
}
/**
@@ -1767,9 +1790,9 @@ HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd)
*/
HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
{
- HAL_SD_ErrorTypedef errorState = SD_OK;
- SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
- SDIO_DataInitTypeDef SDIO_DataInitStructure;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure;
+ SDIO_DataInitTypeDef sdio_datainitstructure;
uint8_t SD_hs[64] = {0};
uint32_t SD_scr[2] = {0, 0};
@@ -1780,11 +1803,11 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
hsd->Instance->DCTRL = 0;
/* Get SCR Register */
- errorState = SD_FindSCR(hsd, SD_scr);
+ errorstate = SD_FindSCR(hsd, SD_scr);
- if (errorState != SD_OK)
+ if (errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Test the Version supported by the card*/
@@ -1793,43 +1816,43 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
if (SD_SPEC != SD_ALLZERO)
{
/* Set Block Size for Card */
- SDIO_CmdInitStructure.Argument = (uint32_t)64;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
- SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = (uint32_t)64;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
- if (errorState != SD_OK)
+ if (errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Configure the SD DPSM (Data Path State Machine) */
- SDIO_DataInitStructure.DataTimeOut = SD_DATATIMEOUT;
- SDIO_DataInitStructure.DataLength = 64;
- SDIO_DataInitStructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B ;
- SDIO_DataInitStructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- SDIO_DataInitStructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- SDIO_DataInitStructure.DPSM = SDIO_DPSM_ENABLE;
- SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure);
+ sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
+ sdio_datainitstructure.DataLength = 64;
+ sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B ;
+ sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
/* Send CMD6 switch mode */
- SDIO_CmdInitStructure.Argument = 0x80FFFF01;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_HS_SWITCH;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = 0x80FFFF01;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_HS_SWITCH;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH);
- if (errorState != SD_OK)
+ if (errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
-
+
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
@@ -1847,33 +1870,37 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
- errorState = SD_DATA_TIMEOUT;
+ errorstate = SD_DATA_TIMEOUT;
- return errorState;
+ return errorstate;
}
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
- errorState = SD_DATA_CRC_FAIL;
+ errorstate = SD_DATA_CRC_FAIL;
- return errorState;
+ return errorstate;
}
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
- errorState = SD_RX_OVERRUN;
+ errorstate = SD_RX_OVERRUN;
- return errorState;
+ return errorstate;
}
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
- errorState = SD_START_BIT_ERR;
+ errorstate = SD_START_BIT_ERR;
- return errorState;
+ return errorstate;
+ }
+ else
+ {
+ /* No error flag set */
}
count = SD_DATATIMEOUT;
@@ -1891,18 +1918,18 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
/* Test if the switch mode HS is ok */
if ((SD_hs[13]& 2) != 2)
{
- errorState = SD_UNSUPPORTED_FEATURE;
+ errorstate = SD_UNSUPPORTED_FEATURE;
}
}
- return errorState;
+ return errorstate;
}
/**
* @}
*/
-/** @defgroup SD_Group4 Peripheral State functions
+/** @addtogroup SD_Exported_Functions_Group4
* @brief Peripheral State functions
*
@verbatim
@@ -1926,68 +1953,68 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
*/
HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
{
- SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
- SDIO_DataInitTypeDef SDIO_DataInitStructure;
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure;
+ SDIO_DataInitTypeDef sdio_datainitstructure;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
uint32_t count = 0;
/* Check SD response */
if ((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
{
- errorState = SD_LOCK_UNLOCK_FAILED;
+ errorstate = SD_LOCK_UNLOCK_FAILED;
- return errorState;
+ return errorstate;
}
/* Set block size for card if it is not equal to current block size for card */
- SDIO_CmdInitStructure.Argument = 64;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
- SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = 64;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
- if (errorState != SD_OK)
+ if (errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Send CMD55 */
- SDIO_CmdInitStructure.Argument = (uint32_t)(hsd->RCA << 16);
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_APP_CMD;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
- if (errorState != SD_OK)
+ if (errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Configure the SD DPSM (Data Path State Machine) */
- SDIO_DataInitStructure.DataTimeOut = SD_DATATIMEOUT;
- SDIO_DataInitStructure.DataLength = 64;
- SDIO_DataInitStructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B;
- SDIO_DataInitStructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- SDIO_DataInitStructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- SDIO_DataInitStructure.DPSM = SDIO_DPSM_ENABLE;
- SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure);
-
- /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */
- SDIO_CmdInitStructure.Argument = 0;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_SD_APP_STAUS;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
+ sdio_datainitstructure.DataLength = 64;
+ sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B;
+ sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
+
+ /* Send ACMD13 (SD_APP_STATUS) with argument as card's RCA */
+ sdio_cmdinitstructure.Argument = 0;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_STATUS;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STAUS);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STATUS);
- if (errorState != SD_OK)
+ if (errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Get status data */
@@ -2008,34 +2035,38 @@ HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstat
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
- errorState = SD_DATA_TIMEOUT;
+ errorstate = SD_DATA_TIMEOUT;
- return errorState;
+ return errorstate;
}
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
- errorState = SD_DATA_CRC_FAIL;
+ errorstate = SD_DATA_CRC_FAIL;
- return errorState;
+ return errorstate;
}
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
- errorState = SD_RX_OVERRUN;
+ errorstate = SD_RX_OVERRUN;
- return errorState;
+ return errorstate;
}
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
- errorState = SD_START_BIT_ERR;
+ errorstate = SD_START_BIT_ERR;
- return errorState;
+ return errorstate;
}
+ else
+ {
+ /* No error flag set */
+ }
count = SD_DATATIMEOUT;
while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0))
@@ -2048,7 +2079,7 @@ HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstat
/* Clear all the static status flags*/
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- return errorState;
+ return errorstate;
}
/**
@@ -2087,87 +2118,97 @@ HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd)
*/
HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)
{
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
uint32_t tmp = 0;
- uint32_t SD_STATUS[16];
+ uint32_t sd_status[16];
- errorState = HAL_SD_SendSDStatus(hsd, SD_STATUS);
+ errorstate = HAL_SD_SendSDStatus(hsd, sd_status);
- if (errorState != SD_OK)
+ if (errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Byte 0 */
- tmp = (SD_STATUS[0] & 0xC0) >> 6;
+ tmp = (sd_status[0] & 0xC0) >> 6;
pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp;
/* Byte 0 */
- tmp = (SD_STATUS[0] & 0x20) >> 5;
+ tmp = (sd_status[0] & 0x20) >> 5;
pCardStatus->SECURED_MODE = (uint8_t)tmp;
/* Byte 2 */
- tmp = (SD_STATUS[2] & 0xFF);
+ tmp = (sd_status[2] & 0xFF);
pCardStatus->SD_CARD_TYPE = (uint8_t)(tmp << 8);
/* Byte 3 */
- tmp = (SD_STATUS[3] & 0xFF);
+ tmp = (sd_status[3] & 0xFF);
pCardStatus->SD_CARD_TYPE |= (uint8_t)tmp;
/* Byte 4 */
- tmp = (SD_STATUS[4] & 0xFF);
+ tmp = (sd_status[4] & 0xFF);
pCardStatus->SIZE_OF_PROTECTED_AREA = (uint8_t)(tmp << 24);
/* Byte 5 */
- tmp = (SD_STATUS[5] & 0xFF);
+ tmp = (sd_status[5] & 0xFF);
pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 16);
/* Byte 6 */
- tmp = (SD_STATUS[6] & 0xFF);
+ tmp = (sd_status[6] & 0xFF);
pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 8);
/* Byte 7 */
- tmp = (SD_STATUS[7] & 0xFF);
+ tmp = (sd_status[7] & 0xFF);
pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)tmp;
/* Byte 8 */
- tmp = (SD_STATUS[8] & 0xFF);
+ tmp = (sd_status[8] & 0xFF);
pCardStatus->SPEED_CLASS = (uint8_t)tmp;
/* Byte 9 */
- tmp = (SD_STATUS[9] & 0xFF);
+ tmp = (sd_status[9] & 0xFF);
pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp;
/* Byte 10 */
- tmp = (SD_STATUS[10] & 0xF0) >> 4;
+ tmp = (sd_status[10] & 0xF0) >> 4;
pCardStatus->AU_SIZE = (uint8_t)tmp;
/* Byte 11 */
- tmp = (SD_STATUS[11] & 0xFF);
+ tmp = (sd_status[11] & 0xFF);
pCardStatus->ERASE_SIZE = (uint8_t)(tmp << 8);
/* Byte 12 */
- tmp = (SD_STATUS[12] & 0xFF);
+ tmp = (sd_status[12] & 0xFF);
pCardStatus->ERASE_SIZE |= (uint8_t)tmp;
/* Byte 13 */
- tmp = (SD_STATUS[13] & 0xFC) >> 2;
+ tmp = (sd_status[13] & 0xFC) >> 2;
pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp;
/* Byte 13 */
- tmp = (SD_STATUS[13] & 0x3);
+ tmp = (sd_status[13] & 0x3);
pCardStatus->ERASE_OFFSET = (uint8_t)tmp;
- return errorState;
+ return errorstate;
}
+/**
+ * @}
+ */
+
/**
* @}
*/
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup SD_Private_Functions
+ * @{
+ */
+
/**
* @brief SD DMA transfer complete Rx callback.
- * @param hdma: DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma)
@@ -2182,13 +2223,17 @@ static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma)
{
}
+ /* Disable the DMA channel */
+ HAL_DMA_Abort(hdma);
+
/* Transfer complete user callback */
HAL_SD_DMA_RxCpltCallback(hsd->hdmarx);
}
/**
* @brief SD DMA transfer Error Rx callback.
- * @param hdma: DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SD_DMA_RxError(DMA_HandleTypeDef *hdma)
@@ -2201,7 +2246,8 @@ static void SD_DMA_RxError(DMA_HandleTypeDef *hdma)
/**
* @brief SD DMA transfer complete Tx callback.
- * @param hdma: DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma)
@@ -2215,14 +2261,18 @@ static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma)
while(hsd->SdTransferCplt == 0)
{
}
-
+
+ /* Disable the DMA channel */
+ HAL_DMA_Abort(hdma);
+
/* Transfer complete user callback */
HAL_SD_DMA_TxCpltCallback(hsd->hdmatx);
}
/**
* @brief SD DMA transfer Error Tx callback.
- * @param hdma: DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SD_DMA_TxError(DMA_HandleTypeDef *hdma)
@@ -2260,33 +2310,33 @@ static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd)
*/
static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd)
{
- SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
uint16_t sd_rca = 1;
if(SDIO_GetPowerState(hsd->Instance) == 0) /* Power off */
{
- errorState = SD_REQUEST_NOT_APPLICABLE;
+ errorstate = SD_REQUEST_NOT_APPLICABLE;
- return errorState;
+ return errorstate;
}
if(hsd->CardType != SECURE_DIGITAL_IO_CARD)
{
/* Send CMD2 ALL_SEND_CID */
- SDIO_CmdInitStructure.Argument = 0;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_ALL_SEND_CID;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_LONG;
- SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
- SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = 0;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_ALL_SEND_CID;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_LONG;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp2Error(hsd);
+ errorstate = SD_CmdResp2Error(hsd);
- if(errorState != SD_OK)
+ if(errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Get Card identification number data */
@@ -2301,16 +2351,16 @@ static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd)
{
/* Send CMD3 SET_REL_ADDR with argument 0 */
/* SD Card publishes its RCA. */
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_SET_REL_ADDR;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_REL_ADDR;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca);
+ errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca);
- if(errorState != SD_OK)
+ if(errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
}
@@ -2320,17 +2370,17 @@ static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd)
hsd->RCA = sd_rca;
/* Send CMD9 SEND_CSD with argument as card's RCA */
- SDIO_CmdInitStructure.Argument = (uint32_t)(hsd->RCA << 16);
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_SEND_CSD;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_LONG;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_CSD;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_LONG;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp2Error(hsd);
+ errorstate = SD_CmdResp2Error(hsd);
- if(errorState != SD_OK)
+ if(errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Get Card Specific Data */
@@ -2341,32 +2391,32 @@ static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd)
}
/* All cards are initialized */
- return errorState;
+ return errorstate;
}
/**
- * @brief Selects od Deselects the corresponding card.
+ * @brief Selects of Deselects the corresponding card.
* @param hsd: SD handle
* @param addr: Address of the card to be selected
* @retval SD Card error state
*/
static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr)
{
- SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
/* Send CMD7 SDIO_SEL_DESEL_CARD */
- SDIO_CmdInitStructure.Argument = (uint32_t)addr;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_SEL_DESEL_CARD;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
- SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = (uint32_t)addr;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SEL_DESEL_CARD;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD);
- return errorState;
+ return errorstate;
}
/**
@@ -2378,10 +2428,10 @@ static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t ad
*/
static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
{
- SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
- __IO HAL_SD_ErrorTypedef errorState = SD_OK;
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure;
+ __IO HAL_SD_ErrorTypedef errorstate = SD_OK;
uint32_t response = 0, count = 0, validvoltage = 0;
- uint32_t SDType = SD_STD_CAPACITY;
+ uint32_t sdtype = SD_STD_CAPACITY;
/* Power ON Sequence -------------------------------------------------------*/
/* Disable SDIO Clock */
@@ -2390,25 +2440,29 @@ static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
/* Set Power State to ON */
SDIO_PowerState_ON(hsd->Instance);
+ /* 1ms: required power up waiting time before starting the SD initialization
+ sequence */
+ HAL_Delay(1);
+
/* Enable SDIO Clock */
__HAL_SD_SDIO_ENABLE();
/* CMD0: GO_IDLE_STATE -----------------------------------------------------*/
/* No CMD response required */
- SDIO_CmdInitStructure.Argument = 0;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_GO_IDLE_STATE;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_NO;
- SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
- SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = 0;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_GO_IDLE_STATE;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_NO;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdError(hsd);
+ errorstate = SD_CmdError(hsd);
- if(errorState != SD_OK)
+ if(errorstate != SD_OK)
{
- /* CMD Response TimeOut (wait for CMDSENT flag) */
- return errorState;
+ /* CMD Response Timeout (wait for CMDSENT flag) */
+ return errorstate;
}
/* CMD8: SEND_IF_COND ------------------------------------------------------*/
@@ -2417,33 +2471,33 @@ static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
- [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
- [7:0]: Check Pattern (recommended 0xAA) */
/* CMD Response: R7 */
- SDIO_CmdInitStructure.Argument = SD_CHECK_PATTERN;
- SDIO_CmdInitStructure.CmdIndex = SD_SDIO_SEND_IF_COND;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = SD_CHECK_PATTERN;
+ sdio_cmdinitstructure.CmdIndex = SD_SDIO_SEND_IF_COND;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp7Error(hsd);
+ errorstate = SD_CmdResp7Error(hsd);
- if (errorState == SD_OK)
+ if (errorstate == SD_OK)
{
/* SD Card 2.0 */
hsd->CardType = STD_CAPACITY_SD_CARD_V2_0;
- SDType = SD_HIGH_CAPACITY;
+ sdtype = SD_HIGH_CAPACITY;
}
/* Send CMD55 */
- SDIO_CmdInitStructure.Argument = 0;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_APP_CMD;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = 0;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
- /* If errorState is Command TimeOut, it is a MMC card */
- /* If errorState is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)
+ /* If errorstate is Command Timeout, it is a MMC card */
+ /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)
or SD card 1.x */
- if(errorState == SD_OK)
+ if(errorstate == SD_OK)
{
/* SD CARD */
/* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
@@ -2451,35 +2505,35 @@ static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
{
/* SEND CMD55 APP_CMD with RCA as 0 */
- SDIO_CmdInitStructure.Argument = 0;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_APP_CMD;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
- SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = 0;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
- if(errorState != SD_OK)
+ if(errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Send CMD41 */
- SDIO_CmdInitStructure.Argument = SD_VOLTAGE_WINDOW_SD | SDType;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_SD_APP_OP_COND;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
- SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = SD_VOLTAGE_WINDOW_SD | sdtype;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_OP_COND;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp3Error(hsd);
+ errorstate = SD_CmdResp3Error(hsd);
- if(errorState != SD_OK)
+ if(errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Get command response */
@@ -2493,9 +2547,9 @@ static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
if(count >= SD_MAX_VOLT_TRIAL)
{
- errorState = SD_INVALID_VOLTRANGE;
+ errorstate = SD_INVALID_VOLTRANGE;
- return errorState;
+ return errorstate;
}
if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
@@ -2505,7 +2559,7 @@ static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
} /* else MMC Card */
- return errorState;
+ return errorstate;
}
/**
@@ -2515,12 +2569,12 @@ static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
*/
static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd)
{
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
/* Set Power State to OFF */
SDIO_PowerState_OFF(hsd->Instance);
- return errorState;
+ return errorstate;
}
/**
@@ -2532,36 +2586,36 @@ static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd)
*/
static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
{
- SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
if(pCardStatus == NULL)
{
- errorState = SD_INVALID_PARAMETER;
+ errorstate = SD_INVALID_PARAMETER;
- return errorState;
+ return errorstate;
}
/* Send Status command */
- SDIO_CmdInitStructure.Argument = (uint32_t)(hsd->RCA << 16);
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_SEND_STATUS;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
- SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS);
- if(errorState != SD_OK)
+ if(errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Get SD card status */
*pCardStatus = SDIO_GetResponse(SDIO_RESP1);
- return errorState;
+ return errorstate;
}
/**
@@ -2571,7 +2625,7 @@ static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardS
*/
static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd)
{
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
uint32_t timeout, tmp;
timeout = SDIO_CMD0TIMEOUT;
@@ -2586,14 +2640,14 @@ static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd)
if(timeout == 0)
{
- errorState = SD_CMD_RSP_TIMEOUT;
- return errorState;
+ errorstate = SD_CMD_RSP_TIMEOUT;
+ return errorstate;
}
/* Clear all the static flags */
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- return errorState;
+ return errorstate;
}
/**
@@ -2603,7 +2657,7 @@ static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd)
*/
static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd)
{
- HAL_SD_ErrorTypedef errorState = SD_ERROR;
+ HAL_SD_ErrorTypedef errorstate = SD_ERROR;
uint32_t timeout = SDIO_CMD0TIMEOUT, tmp;
tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT);
@@ -2619,24 +2673,24 @@ static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd)
if((timeout == 0) || tmp)
{
/* Card is not V2.0 compliant or card does not support the set voltage range */
- errorState = SD_CMD_RSP_TIMEOUT;
+ errorstate = SD_CMD_RSP_TIMEOUT;
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
- return errorState;
+ return errorstate;
}
if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDREND))
{
/* Card is SD V2.0 compliant */
- errorState = SD_OK;
+ errorstate = SD_OK;
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CMDREND);
- return errorState;
+ return errorstate;
}
- return errorState;
+ return errorstate;
}
/**
@@ -2647,8 +2701,8 @@ static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd)
*/
static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD)
{
- HAL_SD_ErrorTypedef errorState = SD_OK;
- uint32_t response_R1;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ uint32_t response_r1;
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
{
@@ -2656,136 +2710,136 @@ static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CM
if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
{
- errorState = SD_CMD_RSP_TIMEOUT;
+ errorstate = SD_CMD_RSP_TIMEOUT;
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
- return errorState;
+ return errorstate;
}
else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
{
- errorState = SD_CMD_CRC_FAIL;
+ errorstate = SD_CMD_CRC_FAIL;
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
- return errorState;
+ return errorstate;
}
/* Check response received is of desired command */
if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD)
{
- errorState = SD_ILLEGAL_CMD;
+ errorstate = SD_ILLEGAL_CMD;
- return errorState;
+ return errorstate;
}
/* Clear all the static flags */
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
/* We have received response, retrieve it for analysis */
- response_R1 = SDIO_GetResponse(SDIO_RESP1);
+ response_r1 = SDIO_GetResponse(SDIO_RESP1);
- if((response_R1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
+ if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
{
- return errorState;
+ return errorstate;
}
- if((response_R1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
+ if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
{
return(SD_ADDR_OUT_OF_RANGE);
}
- if((response_R1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
+ if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
{
return(SD_ADDR_MISALIGNED);
}
- if((response_R1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
+ if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
{
return(SD_BLOCK_LEN_ERR);
}
- if((response_R1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
+ if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
{
return(SD_ERASE_SEQ_ERR);
}
- if((response_R1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
+ if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
{
return(SD_BAD_ERASE_PARAM);
}
- if((response_R1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
+ if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
{
return(SD_WRITE_PROT_VIOLATION);
}
- if((response_R1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
+ if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
{
return(SD_LOCK_UNLOCK_FAILED);
}
- if((response_R1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
+ if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
{
return(SD_COM_CRC_FAILED);
}
- if((response_R1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
+ if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
{
return(SD_ILLEGAL_CMD);
}
- if((response_R1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
+ if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
{
return(SD_CARD_ECC_FAILED);
}
- if((response_R1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
+ if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
{
return(SD_CC_ERROR);
}
- if((response_R1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
+ if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
{
return(SD_GENERAL_UNKNOWN_ERROR);
}
- if((response_R1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
+ if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
{
return(SD_STREAM_READ_UNDERRUN);
}
- if((response_R1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
+ if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
{
return(SD_STREAM_WRITE_OVERRUN);
}
- if((response_R1 & SD_OCR_CID_CSD_OVERWRIETE) == SD_OCR_CID_CSD_OVERWRIETE)
+ if((response_r1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
{
return(SD_CID_CSD_OVERWRITE);
}
- if((response_R1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
+ if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
{
return(SD_WP_ERASE_SKIP);
}
- if((response_R1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
+ if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
{
return(SD_CARD_ECC_DISABLED);
}
- if((response_R1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
+ if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
{
return(SD_ERASE_RESET);
}
- if((response_R1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
+ if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
{
return(SD_AKE_SEQ_ERROR);
}
- return errorState;
+ return errorstate;
}
/**
@@ -2795,7 +2849,7 @@ static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CM
*/
static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd)
{
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
{
@@ -2803,17 +2857,17 @@ static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd)
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
{
- errorState = SD_CMD_RSP_TIMEOUT;
+ errorstate = SD_CMD_RSP_TIMEOUT;
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
- return errorState;
+ return errorstate;
}
/* Clear all the static flags */
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- return errorState;
+ return errorstate;
}
/**
@@ -2823,7 +2877,7 @@ static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd)
*/
static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd)
{
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
{
@@ -2831,25 +2885,29 @@ static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd)
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
{
- errorState = SD_CMD_RSP_TIMEOUT;
+ errorstate = SD_CMD_RSP_TIMEOUT;
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
- return errorState;
+ return errorstate;
}
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
{
- errorState = SD_CMD_CRC_FAIL;
+ errorstate = SD_CMD_CRC_FAIL;
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
- return errorState;
+ return errorstate;
+ }
+ else
+ {
+ /* No error flag set */
}
/* Clear all the static flags */
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- return errorState;
+ return errorstate;
}
/**
@@ -2862,8 +2920,8 @@ static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd)
*/
static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA)
{
- HAL_SD_ErrorTypedef errorState = SD_OK;
- uint32_t response_R1;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ uint32_t response_r1;
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
{
@@ -2871,58 +2929,62 @@ static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CM
if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
{
- errorState = SD_CMD_RSP_TIMEOUT;
+ errorstate = SD_CMD_RSP_TIMEOUT;
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
- return errorState;
+ return errorstate;
}
else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
{
- errorState = SD_CMD_CRC_FAIL;
+ errorstate = SD_CMD_CRC_FAIL;
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
- return errorState;
+ return errorstate;
+ }
+ else
+ {
+ /* No error flag set */
}
/* Check response received is of desired command */
if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD)
{
- errorState = SD_ILLEGAL_CMD;
+ errorstate = SD_ILLEGAL_CMD;
- return errorState;
+ return errorstate;
}
/* Clear all the static flags */
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
/* We have received response, retrieve it. */
- response_R1 = SDIO_GetResponse(SDIO_RESP1);
+ response_r1 = SDIO_GetResponse(SDIO_RESP1);
- if((response_R1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO)
+ if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO)
{
- *pRCA = (uint16_t) (response_R1 >> 16);
+ *pRCA = (uint16_t) (response_r1 >> 16);
- return errorState;
+ return errorstate;
}
- if((response_R1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR)
+ if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR)
{
return(SD_GENERAL_UNKNOWN_ERROR);
}
- if((response_R1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD)
+ if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD)
{
return(SD_ILLEGAL_CMD);
}
- if((response_R1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED)
+ if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED)
{
return(SD_COM_CRC_FAILED);
}
- return errorState;
+ return errorstate;
}
/**
@@ -2932,65 +2994,65 @@ static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CM
*/
static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd)
{
- SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
uint32_t scr[2] = {0, 0};
if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
{
- errorState = SD_LOCK_UNLOCK_FAILED;
+ errorstate = SD_LOCK_UNLOCK_FAILED;
- return errorState;
+ return errorstate;
}
/* Get SCR Register */
- errorState = SD_FindSCR(hsd, scr);
+ errorstate = SD_FindSCR(hsd, scr);
- if(errorState != SD_OK)
+ if(errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* If requested card supports wide bus operation */
if((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO)
{
/* Send CMD55 APP_CMD with argument as card's RCA.*/
- SDIO_CmdInitStructure.Argument = (uint32_t)(hsd->RCA << 16);
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_APP_CMD;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
- SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
- if(errorState != SD_OK)
+ if(errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
- SDIO_CmdInitStructure.Argument = 2;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = 2;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
- if(errorState != SD_OK)
+ if(errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
- return errorState;
+ return errorstate;
}
else
{
- errorState = SD_REQUEST_NOT_APPLICABLE;
+ errorstate = SD_REQUEST_NOT_APPLICABLE;
- return errorState;
+ return errorstate;
}
}
@@ -3001,65 +3063,65 @@ static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd)
*/
static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd)
{
- SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
uint32_t scr[2] = {0, 0};
if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
{
- errorState = SD_LOCK_UNLOCK_FAILED;
+ errorstate = SD_LOCK_UNLOCK_FAILED;
- return errorState;
+ return errorstate;
}
/* Get SCR Register */
- errorState = SD_FindSCR(hsd, scr);
+ errorstate = SD_FindSCR(hsd, scr);
- if(errorState != SD_OK)
+ if(errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* If requested card supports 1 bit mode operation */
if((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO)
{
/* Send CMD55 APP_CMD with argument as card's RCA */
- SDIO_CmdInitStructure.Argument = (uint32_t)(hsd->RCA << 16);
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_APP_CMD;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
- SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
- if(errorState != SD_OK)
+ if(errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
- SDIO_CmdInitStructure.Argument = 0;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = 0;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
- if(errorState != SD_OK)
+ if(errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
- return errorState;
+ return errorstate;
}
else
{
- errorState = SD_REQUEST_NOT_APPLICABLE;
+ errorstate = SD_REQUEST_NOT_APPLICABLE;
- return errorState;
+ return errorstate;
}
}
@@ -3072,62 +3134,62 @@ static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd)
*/
static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
{
- SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
- SDIO_DataInitTypeDef SDIO_DataInitStructure;
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure;
+ SDIO_DataInitTypeDef sdio_datainitstructure;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
uint32_t index = 0;
uint32_t tempscr[2] = {0, 0};
/* Set Block Size To 8 Bytes */
/* Send CMD55 APP_CMD with argument as card's RCA */
- SDIO_CmdInitStructure.Argument = (uint32_t)8;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
- SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = (uint32_t)8;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
- if(errorState != SD_OK)
+ if(errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
/* Send CMD55 APP_CMD with argument as card's RCA */
- SDIO_CmdInitStructure.Argument = (uint32_t)((hsd->RCA) << 16);
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_APP_CMD;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = (uint32_t)((hsd->RCA) << 16);
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
- if(errorState != SD_OK)
+ if(errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
- SDIO_DataInitStructure.DataTimeOut = SD_DATATIMEOUT;
- SDIO_DataInitStructure.DataLength = 8;
- SDIO_DataInitStructure.DataBlockSize = SDIO_DATABLOCK_SIZE_8B;
- SDIO_DataInitStructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- SDIO_DataInitStructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- SDIO_DataInitStructure.DPSM = SDIO_DPSM_ENABLE;
- SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure);
+ sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
+ sdio_datainitstructure.DataLength = 8;
+ sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_8B;
+ sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
/* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
- SDIO_CmdInitStructure.Argument = 0;
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_SD_APP_SEND_SCR;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = 0;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_SEND_SCR;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
/* Check for error conditions */
- errorState = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR);
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR);
- if(errorState != SD_OK)
+ if(errorstate != SD_OK)
{
- return errorState;
+ return errorstate;
}
-
+
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
{
if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
@@ -3141,33 +3203,37 @@ static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
- errorState = SD_DATA_TIMEOUT;
+ errorstate = SD_DATA_TIMEOUT;
- return errorState;
+ return errorstate;
}
else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
- errorState = SD_DATA_CRC_FAIL;
+ errorstate = SD_DATA_CRC_FAIL;
- return errorState;
+ return errorstate;
}
else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
- errorState = SD_RX_OVERRUN;
+ errorstate = SD_RX_OVERRUN;
- return errorState;
+ return errorstate;
}
else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
- errorState = SD_START_BIT_ERR;
+ errorstate = SD_START_BIT_ERR;
- return errorState;
+ return errorstate;
+ }
+ else
+ {
+ /* No error flag set */
}
/* Clear all the static flags */
@@ -3179,7 +3245,7 @@ static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
*(pSCR) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) |\
((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24);
- return errorState;
+ return errorstate;
}
/**
@@ -3190,16 +3256,16 @@ static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
*/
static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus)
{
- SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
- HAL_SD_ErrorTypedef errorState = SD_OK;
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure;
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
__IO uint32_t responseR1 = 0;
- SDIO_CmdInitStructure.Argument = (uint32_t)(hsd->RCA << 16);
- SDIO_CmdInitStructure.CmdIndex = SD_CMD_SEND_STATUS;
- SDIO_CmdInitStructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
- SDIO_CmdInitStructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+ sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
{
@@ -3207,27 +3273,31 @@ static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *
if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
{
- errorState = SD_CMD_RSP_TIMEOUT;
+ errorstate = SD_CMD_RSP_TIMEOUT;
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
- return errorState;
+ return errorstate;
}
else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
{
- errorState = SD_CMD_CRC_FAIL;
+ errorstate = SD_CMD_CRC_FAIL;
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
- return errorState;
+ return errorstate;
+ }
+ else
+ {
+ /* No error flag set */
}
/* Check response received is of desired command */
if((uint32_t)SDIO_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS)
{
- errorState = SD_ILLEGAL_CMD;
+ errorstate = SD_ILLEGAL_CMD;
- return errorState;
+ return errorstate;
}
/* Clear all the static flags */
@@ -3242,7 +3312,7 @@ static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *
if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
{
- return errorState;
+ return errorstate;
}
if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
@@ -3315,7 +3385,7 @@ static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *
return(SD_STREAM_WRITE_OVERRUN);
}
- if((responseR1 & SD_OCR_CID_CSD_OVERWRIETE) == SD_OCR_CID_CSD_OVERWRIETE)
+ if((responseR1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
{
return(SD_CID_CSD_OVERWRITE);
}
@@ -3340,7 +3410,7 @@ static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *
return(SD_AKE_SEQ_ERROR);
}
- return errorState;
+ return errorstate;
}
/**
@@ -3348,6 +3418,7 @@ static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *
*/
#endif /* HAL_SD_MODULE_ENABLED */
+
/**
* @}
*/
diff --git a/f2/src/stm32f2xx_hal_smartcard.c b/f2/src/stm32f2xx_hal_smartcard.c
index 264704e5814538546b391cc4a76c8732465b7820..4ec71cc74c9b5024b1b7ba7d0d9b5a9fec9a9a98 100755
--- a/f2/src/stm32f2xx_hal_smartcard.c
+++ b/f2/src/stm32f2xx_hal_smartcard.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_smartcard.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief SMARTCARD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:
@@ -16,10 +16,10 @@
##### How to use this driver #####
==============================================================================
[..]
- The SMARTCARD HAL driver can be used as follow:
+ The SMARTCARD HAL driver can be used as follows:
(#) Declare a SMARTCARD_HandleTypeDef handle structure.
- (#) Initialize the SMARTCARD low level resources by implement the HAL_SMARTCARD_MspInit ()API:
+ (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
(##) Enable the USARTx interface clock.
(##) SMARTCARD pins configuration:
(+++) Enable the clock for the SMARTCARD GPIOs.
@@ -28,27 +28,28 @@
and HAL_SMARTCARD_Receive_IT() APIs):
(+++) Configure the USARTx interrupt priority.
(+++) Enable the NVIC USART IRQ handle.
-
- -@@- The specific SMARTCARD interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __SMARTCARD_ENABLE_IT() and __SMARTCARD_DISABLE_IT() inside the transmit and receive process.
(##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
and HAL_SMARTCARD_Receive_DMA() APIs):
(+++) Declare a DMA handle structure for the Tx/Rx stream.
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx Stream.
- (+++) Associate the initilalized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+ (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
(#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
- flow control and Mode(Receiver/Transmitter) in the hsc Init structure.
+ flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure.
(#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
- (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_SMARTCARD_MspInit(&hsc) API.
-
- (#) Three mode of operations are available within this driver :
+ (++) These APIs configure also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SMARTCARD_MspInit() API.
+ [..]
+ (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
+
+ [..]
+ Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -87,10 +88,10 @@
(+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral
(+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral
- (+) __HAL_SMARTCARD_GET_FLAG : Checks whether the specified SMARTCARD flag is set or not
- (+) __HAL_SMARTCARD_CLEAR_FLAG : Clears the specified SMARTCARD pending flag
- (+) __HAL_SMARTCARD_ENABLE_IT: Enables the specified SMARTCARD interrupt
- (+) __HAL_SMARTCARD_DISABLE_IT: Disables the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not
+ (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
+ (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
[..]
(@) You can refer to the SMARTCARD HAL driver header file for more useful macros
@@ -99,7 +100,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -133,74 +134,79 @@
* @{
*/
-/** @defgroup SMARTCARD
+/** @defgroup SMARTCARD SMARTCARD
* @brief HAL USART SMARTCARD module driver
* @{
*/
#ifdef HAL_SMARTCARD_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup SMARTCARD_Private_Constants
+ * @{
+ */
#define SMARTCARD_TIMEOUT_VALUE 22000
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMARTCARD_Private_Functions
+ * @{
+ */
static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc);
static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SMARTCARD_Private_Functions
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
* @{
*/
-/** @defgroup SMARTCARD_Group1 SmartCard Initialization and de-initialization functions
+/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USART
- in Smartcard mode.
- [..]
- The Smartcard interface is designed to support asynchronous protocol Smartcards as
- defined in the ISO 7816-3 standard.
- [..]
- The USART can provide a clock to the smartcard through the SCLK output.
- In smartcard mode, SCLK is not associated to the communication but is simply derived
- from the internal peripheral input clock through a 5-bit prescaler.
- [..]
- (+) For the asynchronous mode only these parameters can be configured:
- (++) Baud Rate
- (++) Word Length
- (++) Stop Bit
- (++) Parity: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible SmartCard frame formats are as listed in the following table:
- +-------------------------------------------------------------+
- | M bit | PCE bit | USART frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
- (++) USART polarity
- (++) USART phase
- (++) USART LastBit
- (++) Receiver/transmitter modes
- (++) Prescaler
- (++) GuardTime
- (++) NACKState: The Smartcard NACK state
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USART
+ in Smartcard mode.
+ [..]
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as
+ defined in the ISO 7816-3 standard.
+ [..]
+ The USART can provide a clock to the smartcard through the SCLK output.
+ In smartcard mode, SCLK is not associated to the communication but is simply derived
+ from the internal peripheral input clock through a 5-bit prescaler.
+ [..]
+ (+) For the Smartcard mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length => Should be 9 bits (8 bits + parity)
+ (++) Stop Bit
+ (++) Parity: => Should be enabled
+
+ (+++) +-------------------------------------------------------------+
+ (+++) | M bit | PCE bit | SMARTCARD frame |
+ (+++) |---------------------|---------------------------------------|
+ (+++) | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ (+++) +-------------------------------------------------------------+
+
+ (++) USART polarity
+ (++) USART phase
+ (++) USART LastBit
+ (++) Receiver/transmitter modes
+ (++) Prescaler
+ (++) GuardTime
+ (++) NACKState: The Smartcard NACK state
(+) Recommended SmartCard interface configuration to get the Answer to Reset from the Card:
(++) Word Length = 9 Bits
@@ -208,13 +214,13 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
(++) Even parity
(++) BaudRate = 12096 baud
(++) Tx and Rx enabled
- [..]
- Please refer to the ISO 7816-3 specification for more details.
+ [..]
+ Please refer to the ISO 7816-3 specification for more details.
- -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended
- to use 1.5 stop bits for both transmitting and receiving to avoid switching
- between the two configurations.
- [..]
+ -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended
+ to use 1.5 stop bits for both transmitting and receiving to avoid switching
+ between the two configurations.
+ [..]
The HAL_SMARTCARD_Init() function follows the USART SmartCard configuration
procedure (details for the procedure are available in reference manual (RM0329)).
@@ -225,7 +231,8 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
/**
* @brief Initializes the SmartCard mode according to the specified
* parameters in the SMARTCARD_InitTypeDef and create the associated handle .
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
@@ -242,6 +249,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
if(hsc->State == HAL_SMARTCARD_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hsc->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_SMARTCARD_MspInit(hsc);
}
@@ -264,13 +273,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
hsc->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_HDSEL);
/* Enable the SMARTCARD Parity Error Interrupt */
- __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
/* Enable the SMARTCARD Framing Error Interrupt */
- __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
- /* Enable the Peripharal */
- __SMARTCARD_ENABLE(hsc);
+ /* Enable the Peripheral */
+ __HAL_SMARTCARD_ENABLE(hsc);
/* Configure the Smartcard NACK state */
MODIFY_REG(hsc->Instance->CR3, USART_CR3_NACK, hsc->Init.NACKState);
@@ -287,7 +296,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
/**
* @brief DeInitializes the USART SmartCard peripheral
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
@@ -303,6 +313,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
hsc->State = HAL_SMARTCARD_STATE_BUSY;
+ /* Disable the Peripheral */
+ __HAL_SMARTCARD_DISABLE(hsc);
+
/* DeInit the low level hardware */
HAL_SMARTCARD_MspDeInit(hsc);
@@ -317,25 +330,27 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
/**
* @brief SMARTCARD MSP Init
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMARTCARD_MspInit could be implenetd in the user file
+ the HAL_SMARTCARD_MspInit could be implemented in the user file
*/
}
/**
* @brief SMARTCARD MSP DeInit
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMARTCARD_MspDeInit could be implenetd in the user file
+ the HAL_SMARTCARD_MspDeInit could be implemented in the user file
*/
}
@@ -343,7 +358,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
* @}
*/
-/** @defgroup SMARTCARD_Group2 IO operation functions
+/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
* @brief SMARTCARD Transmit and Receive functions
*
@verbatim
@@ -352,39 +367,39 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
===============================================================================
This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
[..]
- IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
- on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
- is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
- While receiving data, transmission should be avoided as the data to be transmitted
- could be corrupted.
+ Smartcard is a single wire half duplex communication protocol.
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as
+ defined in the ISO 7816-3 standard. The USART should be configured as:
+ (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
+ (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
- (#) There are two mode of transfer:
+ (#) There are two modes of transfer:
(++) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
- (++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These API's return the HAL status.
+ (++) Non Blocking mode: The communication is performed using Interrupts
+ or DMA, These APIs return the HAL status.
The end of the data processing will be indicated through the
dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
- will be executed respectivelly at the end of the transmit or Receive process
- The HAL_SMARTCARD_ErrorCallback()user callback will be executed when a communication error is detected
+ will be executed respectively at the end of the Transmit or Receive process
+ The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected
- (#) Blocking mode API's are :
+ (#) Blocking mode APIs are :
(++) HAL_SMARTCARD_Transmit()
(++) HAL_SMARTCARD_Receive()
- (#) Non-Blocking mode API's with Interrupt are :
+ (#) Non Blocking mode APIs with Interrupt are :
(++) HAL_SMARTCARD_Transmit_IT()
(++) HAL_SMARTCARD_Receive_IT()
(++) HAL_SMARTCARD_IRQHandler()
- (#) No-Blocking mode functions with DMA are :
+ (#) Non Blocking mode functions with DMA are :
(++) HAL_SMARTCARD_Transmit_DMA()
(++) HAL_SMARTCARD_Receive_DMA()
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_SMARTCARD_TxCpltCallback()
(++) HAL_SMARTCARD_RxCpltCallback()
(++) HAL_SMARTCARD_ErrorCallback()
@@ -395,16 +410,20 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
/**
* @brief Send an amount of data in blocking mode
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint16_t* tmp;
-
- if(hsc->State == HAL_SMARTCARD_STATE_READY)
+ uint32_t tmp1 = 0;
+
+ tmp1 = hsc->State;
+ if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
{
if((pData == NULL) || (Size == 0))
{
@@ -415,47 +434,44 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
__HAL_LOCK(hsc);
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
-
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+
hsc->TxXferSize = Size;
hsc->TxXferCount = Size;
while(hsc->TxXferCount > 0)
{
- hsc->TxXferCount--;
- if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
- {
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- tmp = (uint16_t*) pData;
- hsc->Instance->DR = (*tmp & (uint16_t)0x01FF);
- if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
- {
- pData +=2;
- }
- else
- {
- pData +=1;
- }
- }
- else
+ hsc->TxXferCount--;
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
{
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- hsc->Instance->DR = (*pData++ & (uint8_t)0xFF);
+ return HAL_TIMEOUT;
}
+ tmp = (uint16_t*) pData;
+ hsc->Instance->DR = (*tmp & (uint16_t)0x01FF);
+ pData +=1;
}
-
+
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- hsc->State = HAL_SMARTCARD_STATE_READY;
-
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_READY;
+ }
/* Process Unlocked */
__HAL_UNLOCK(hsc);
@@ -469,16 +485,20 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
/**
* @brief Receive an amount of data in blocking mode
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be received
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint16_t* tmp;
-
- if(hsc->State == HAL_SMARTCARD_STATE_READY)
+ uint32_t tmp1 = 0;
+
+ tmp1 = hsc->State;
+ if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
{
if((pData == NULL) || (Size == 0))
{
@@ -489,49 +509,42 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
__HAL_LOCK(hsc);
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
hsc->RxXferSize = Size;
hsc->RxXferCount = Size;
+
/* Check the remain data to be received */
while(hsc->RxXferCount > 0)
{
hsc->RxXferCount--;
- if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
- {
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- tmp = (uint16_t*) pData;
- if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
- {
- *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x01FF);
- pData +=2;
- }
- else
- {
- *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
- pData +=1;
- }
- }
- else
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
{
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
- {
- *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
- }
- else
- {
- *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x007F);
- }
+ return HAL_TIMEOUT;
}
+ tmp = (uint16_t*) pData;
+ *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
+ pData +=1;
+ }
+
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_READY;
}
- hsc->State = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsc);
@@ -546,14 +559,18 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
/**
* @brief Send an amount of data in non blocking mode
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
{
- if(hsc->State == HAL_SMARTCARD_STATE_READY)
+ uint32_t tmp1 = 0;
+
+ tmp1 = hsc->State;
+ if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
{
if((pData == NULL) || (Size == 0))
{
@@ -568,19 +585,27 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_
hsc->TxXferCount = Size;
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
-
- /* Enable the SMARTCARD Parity Error Interrupt */
- __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
-
- /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
/* Process Unlocked */
__HAL_UNLOCK(hsc);
+
+ /* Enable the SMARTCARD Parity Error Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
- /* Enable the SMARTCARD Transmit Complete Interrupt */
- __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
+
+ /* Enable the SMARTCARD Transmit data register empty Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TXE);
return HAL_OK;
}
@@ -592,14 +617,18 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_
/**
* @brief Receive an amount of data in non blocking mode
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
{
- if(hsc->State == HAL_SMARTCARD_STATE_READY)
+ uint32_t tmp1 = 0;
+
+ tmp1 = hsc->State;
+ if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
{
if((pData == NULL) || (Size == 0))
{
@@ -614,19 +643,26 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t
hsc->RxXferCount = Size;
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
-
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsc);
+
/* Enable the SMARTCARD Data Register not empty Interrupt */
- __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE);
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE);
/* Enable the SMARTCARD Parity Error Interrupt */
- __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
/* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
return HAL_OK;
}
@@ -638,7 +674,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t
/**
* @brief Send an amount of data in non blocking mode
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
* @retval HAL status
@@ -646,10 +683,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
{
uint32_t *tmp;
- uint32_t tmpstate;
+ uint32_t tmp1 = 0;
- tmpstate = hsc->State;
- if((tmpstate == HAL_SMARTCARD_STATE_READY) || (tmpstate == HAL_SMARTCARD_STATE_BUSY_RX))
+ tmp1 = hsc->State;
+ if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
{
if((pData == NULL) || (Size == 0))
{
@@ -664,9 +701,17 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8
hsc->TxXferCount = Size;
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
- /* Set the SMARTCARD DMA transfert complete callback */
+ /* Set the SMARTCARD DMA transfer complete callback */
hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
/* Set the DMA error callback */
@@ -676,6 +721,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size);
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC);
+
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the SMARTCARD CR3 register */
hsc->Instance->CR3 |= USART_CR3_DMAT;
@@ -693,7 +741,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8
/**
* @brief Receive an amount of data in non blocking mode
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be received
* @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.s
@@ -702,10 +751,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
{
uint32_t *tmp;
- uint32_t tmpstate;
+ uint32_t tmp1 = 0;
- tmpstate = hsc->State;
- if((tmpstate == HAL_SMARTCARD_STATE_READY) || (tmpstate == HAL_SMARTCARD_STATE_BUSY_TX))
+ tmp1 = hsc->State;
+ if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
{
if((pData == NULL) || (Size == 0))
{
@@ -719,9 +768,17 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_
hsc->RxXferSize = Size;
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
- /* Set the SMARTCARD DMA transfert complete callback */
+ /* Set the SMARTCARD DMA transfer complete callback */
hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
/* Set the DMA error callback */
@@ -748,65 +805,67 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_
/**
* @brief This function handles SMARTCARD interrupt request.
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
{
uint32_t tmp1 = 0, tmp2 = 0;
- tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_PE);
+ tmp1 = hsc->Instance->SR;
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE);
- /* SMARTCARD parity error interrupt occured --------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
+
+ /* SMARTCARD parity error interrupt occurred --------------------------------*/
+ if(((tmp1 & SMARTCARD_FLAG_PE) != RESET) && (tmp2 != RESET))
{
- __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_PE);
+ __HAL_SMARTCARD_CLEAR_PEFLAG(hsc);
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
}
- tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_FE);
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
- /* SMARTCARD frame error interrupt occured ---------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
+ /* SMARTCARD frame error interrupt occurred ---------------------------------*/
+ if(((tmp1 & SMARTCARD_FLAG_FE) != RESET) && (tmp2 != RESET))
{
- __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_FE);
+ __HAL_SMARTCARD_CLEAR_FEFLAG(hsc);
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
}
- tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_NE);
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
- /* SMARTCARD noise error interrupt occured ---------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
+ /* SMARTCARD noise error interrupt occurred ---------------------------------*/
+ if(((tmp1 & SMARTCARD_FLAG_NE) != RESET) && (tmp2 != RESET))
{
- __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_NE);
+ __HAL_SMARTCARD_CLEAR_NEFLAG(hsc);
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
}
-
- tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_ORE);
+
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
- /* SMARTCARD Over-Run interrupt occured ------------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
+ /* SMARTCARD Over-Run interrupt occurred ------------------------------------*/
+ if(((tmp1 & SMARTCARD_FLAG_ORE) != RESET) && (tmp2 != RESET))
{
- __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_ORE);
+ __HAL_SMARTCARD_CLEAR_OREFLAG(hsc);
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
}
- tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_RXNE);
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RXNE);
/* SMARTCARD in mode Receiver ----------------------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
+ if(((tmp1 & SMARTCARD_FLAG_RXNE) != RESET) && (tmp2 != RESET))
{
SMARTCARD_Receive_IT(hsc);
- __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_RXNE);
}
-
- tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_TC);
- tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC);
+
+ tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TXE);
/* SMARTCARD in mode Transmitter -------------------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
+ if(((tmp1 & SMARTCARD_FLAG_TXE) != RESET) && (tmp2 != RESET))
{
SMARTCARD_Transmit_IT(hsc);
- __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC);
+ }
+
+ tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC);
+ /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
+ if(((tmp1 & SMARTCARD_FLAG_TC) != RESET) && (tmp2 != RESET))
+ {
+ SMARTCARD_EndTransmit_IT(hsc);
}
/* Call the Error call Back in case of Errors */
@@ -820,7 +879,8 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
/**
* @brief Tx Transfer completed callbacks
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
@@ -832,7 +892,8 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
/**
* @brief Rx Transfer completed callbacks
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
@@ -844,7 +905,8 @@ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
/**
* @brief SMARTCARD error callbacks
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
@@ -858,7 +920,7 @@ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
* @}
*/
-/** @defgroup SMARTCARD_Group3 Peripheral State and Errors functions
+/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief SMARTCARD State and Errors functions
*
@verbatim
@@ -868,14 +930,15 @@ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
[..]
This subsection provides a set of functions allowing to control the SmartCard.
(+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SmartCard peripheral.
- (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occured durung communication.
+ (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during communication.
@endverbatim
* @{
*/
/**
* @brief return the SMARTCARD state
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval HAL state
*/
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc)
@@ -900,7 +963,8 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc)
/**
* @brief DMA SMARTCARD transmit process complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
@@ -913,24 +977,14 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
in the USART CR3 register */
hsc->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
- /* Wait for SMARTCARD TC Flag */
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, SMARTCARD_TIMEOUT_VALUE) != HAL_OK)
- {
- /* Timeout Occured */
- hsc->State = HAL_SMARTCARD_STATE_TIMEOUT;
- HAL_SMARTCARD_ErrorCallback(hsc);
- }
- else
- {
- /* No Timeout */
- hsc->State= HAL_SMARTCARD_STATE_READY;
- HAL_SMARTCARD_TxCpltCallback(hsc);
- }
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
}
/**
* @brief DMA SMARTCARD receive process complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
@@ -943,14 +997,23 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
in the USART CR3 register */
hsc->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
- hsc->State= HAL_SMARTCARD_STATE_READY;
-
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_READY;
+ }
+
HAL_SMARTCARD_RxCpltCallback(hsc);
}
/**
* @brief DMA SMARTCARD communication error callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
@@ -975,10 +1038,11 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
*/
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
{
- uint32_t timeout = 0;
-
- timeout = HAL_GetTick() + Timeout;
-
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait until flag is set */
if(Status == RESET)
{
@@ -987,11 +1051,11 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE and RXNE interrupts for the interrupt process */
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
hsc->State= HAL_SMARTCARD_STATE_READY;
@@ -1010,11 +1074,11 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE and RXNE interrupts for the interrupt process */
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
hsc->State= HAL_SMARTCARD_STATE_READY;
@@ -1031,136 +1095,110 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
/**
* @brief Send an amount of data in non blocking mode
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
{
uint16_t* tmp;
-
- if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ uint32_t tmp1 = 0;
+
+ tmp1 = hsc->State;
+ if((tmp1 == HAL_SMARTCARD_STATE_BUSY_TX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX))
{
- /* Process Locked */
- __HAL_LOCK(hsc);
-
- if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
- {
- tmp = (uint16_t*) hsc->pTxBuffPtr;
- hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
- if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
- {
- hsc->pTxBuffPtr += 2;
- }
- else
- {
- hsc->pTxBuffPtr += 1;
- }
- }
- else
- {
- hsc->Instance->DR = (uint8_t)(*hsc->pTxBuffPtr++ & (uint8_t)0x00FF);
- }
+ tmp = (uint16_t*) hsc->pTxBuffPtr;
+ hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
+ hsc->pTxBuffPtr += 1;
if(--hsc->TxXferCount == 0)
{
- /* Disable the SMARTCARD Transmit Complete Interrupt */
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TC);
-
- /* Disable the SMARTCARD Parity Error Interrupt */
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
+ /* Disable the SMARTCARD Transmit data register empty Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
- /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
-
- hsc->State = HAL_SMARTCARD_STATE_READY;
-
- /* Call the Process Unlocked before calling the Tx call back API to give the possibiity to
- start again the Transmission under the Tx call back API */
- __HAL_UNLOCK(hsc);
-
- HAL_SMARTCARD_TxCpltCallback(hsc);
-
- return HAL_OK;
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
}
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
-
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param hsmartcard: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+
+ /* Check if a receive process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
}
+
+ HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+
+ return HAL_OK;
}
/**
* @brief Receive an amount of data in non blocking mode
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
{
uint16_t* tmp;
-
- if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ uint32_t tmp1 = 0;
+
+ tmp1 = hsc->State;
+ if((tmp1 == HAL_SMARTCARD_STATE_BUSY_RX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX))
{
- /* Process Locked */
- __HAL_LOCK(hsc);
-
- if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
- {
- tmp = (uint16_t*) hsc->pRxBuffPtr;
- if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
- {
- *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x01FF);
- hsc->pRxBuffPtr += 2;
- }
- else
- {
- *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
- hsc->pRxBuffPtr += 1;
- }
- }
- else
- {
- if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
- {
- *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
- }
- else
- {
- *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x007F);
- }
- }
+ tmp = (uint16_t*) hsc->pRxBuffPtr;
+ *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
+ hsc->pRxBuffPtr += 1;
if(--hsc->RxXferCount == 0)
{
- while(HAL_IS_BIT_SET(hsc->Instance->SR, SMARTCARD_FLAG_RXNE))
- {
- }
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
/* Disable the SMARTCARD Parity Error Interrupt */
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
/* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
- hsc->State = HAL_SMARTCARD_STATE_READY;
-
- /* Call the Process Unlocked before calling the Rx call back API to give the possibiity to
- start again the receiption under the Rx call back API */
- __HAL_UNLOCK(hsc);
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_READY;
+ }
HAL_SMARTCARD_RxCpltCallback(hsc);
return HAL_OK;
}
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
-
return HAL_OK;
}
else
@@ -1171,7 +1209,8 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
/**
* @brief Configure the SMARTCARD peripheral
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
@@ -1242,11 +1281,11 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
/*-------------------------- USART BRR Configuration -----------------------*/
if((hsc->Instance == USART1) || (hsc->Instance == USART6))
{
- hsc->Instance->BRR = __SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate);
+ hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate);
}
else
{
- hsc->Instance->BRR = __SMARTCARD_BRR(HAL_RCC_GetPCLK1Freq(), hsc->Init.BaudRate);
+ hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK1Freq(), hsc->Init.BaudRate);
}
}
diff --git a/f2/src/stm32f2xx_hal_spi.c b/f2/src/stm32f2xx_hal_spi.c
index 2984706daec0a9da20ece8854ae1b22128c5c516..d501b819f6d8cc40a9a076bf1dc85c21f5f7afdb 100755
--- a/f2/src/stm32f2xx_hal_spi.c
+++ b/f2/src/stm32f2xx_hal_spi.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_spi.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief SPI HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -22,7 +22,7 @@
(#) Declare a SPI_HandleTypeDef handle structure, for example:
SPI_HandleTypeDef hspi;
- (#)Initialize the SPI low level resources by implement the HAL_SPI_MspInit ()API:
+ (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
(##) Enable the SPIx interface clock
(##) SPI pins configuration
(+++) Enable the clock for the SPI GPIOs
@@ -35,7 +35,7 @@
(+++) Enable the DMAx interface clock using
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx Stream
- (+++) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle
+ (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
(#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
@@ -43,13 +43,23 @@
(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_SPI_MspInit(&hspi) API.
+ by calling the customized HAL_SPI_MspInit() API.
+ [..]
+ Circular mode restriction:
+ (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
+ (##) Master 2Lines RxOnly
+ (##) Master 1Line Rx
+ (#) The CRC feature is not managed when the DMA circular mode is enabled
+ (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
+ the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
+
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -83,7 +93,7 @@
* @{
*/
-/** @defgroup SPI
+/** @defgroup SPI SPI
* @brief SPI HAL module driver
* @{
*/
@@ -96,24 +106,33 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SPI_Private_Functions
+ * @{
+ */
static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
static void SPI_TxISR(SPI_HandleTypeDef *hspi);
static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
static void SPI_RxISR(SPI_HandleTypeDef *hspi);
+static void SPI_DMAEndTransmitReceive(SPI_HandleTypeDef *hspi);
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAError(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SPI_Private_Functions
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_Exported_Functions SPI Exported Functions
* @{
*/
-/** @defgroup SPI_Group1 Initialization and de-initialization functions
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -121,9 +140,9 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin
##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
- de-initialiaze the SPIx peripheral:
+ de-initialize the SPIx peripheral:
- (+) User must Implement HAL_SPI_MspInit() function in which he configures
+ (+) User must implement HAL_SPI_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
(+) Call the function HAL_SPI_Init() to configure the selected device with
@@ -140,7 +159,7 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin
(++) CRC Polynomial if CRC enabled
(+) Call the function HAL_SPI_DeInit() to restore the default configuration
- of the selected SPIx periperal.
+ of the selected SPIx peripheral.
@endverbatim
* @{
@@ -149,7 +168,8 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin
/**
* @brief Initializes the SPI according to the specified parameters
* in the SPI_InitTypeDef and create the associated handle.
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
@@ -175,13 +195,15 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
if(hspi->State == HAL_SPI_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hspi->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
}
hspi->State = HAL_SPI_STATE_BUSY;
- /* Disble the selected SPI peripheral */
+ /* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
@@ -209,7 +231,8 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
/**
* @brief DeInitializes the SPI peripheral
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
@@ -237,25 +260,27 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
/**
* @brief SPI MSP Init
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_MspInit could be implenetd in the user file
+ the HAL_SPI_MspInit could be implemented in the user file
*/
}
/**
* @brief SPI MSP DeInit
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_MspDeInit could be implenetd in the user file
+ the HAL_SPI_MspDeInit could be implemented in the user file
*/
}
@@ -263,7 +288,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
* @}
*/
-/** @defgroup SPI_Group2 IO operation functions
+/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
* @brief Data transfers functions
*
@verbatim
@@ -275,40 +300,21 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
[..] The SPI supports master and slave mode :
- (#) There are two mode of transfer:
+ (#) There are two modes of transfer:
(++) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
(++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These API's return the HAL status.
+ or DMA, These APIs return the HAL status.
The end of the data processing will be indicated through the
dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
- will be executed respectivelly at the end of the transmit or Receive process
+ will be executed respectively at the end of the transmit or Receive process
The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
- (#) Blocking mode API's are :
- (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_TransmitReceive() in full duplex mode
-
- (#) Non-Blocking mode API's with Interrupt are :
- (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_TransmitReceive_IT()in full duplex mode
- (++) HAL_SPI_IRQHandler()
-
- (#) No-Blocking mode functions with DMA are :
- (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_TransmitReceie_DMA() in full duplex mode
-
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
- (++) HAL_SPI_TxCpltCallback()
- (++) HAL_SPI_RxCpltCallback()
- (++) HAL_SPI_ErrorCallback()
- (++) HAL_SPI_TxRxCpltCallback()
+ (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
+ exist for 1Line (simplex) and 2Lines (full duplex) modes.
@endverbatim
* @{
@@ -316,7 +322,8 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
/**
* @brief Transmit an amount of data in blocking mode
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
* @param Timeout: Timeout duration
@@ -353,15 +360,15 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
hspi->RxXferCount = 0;
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
/* Configure communication direction : 1Line */
- __HAL_SPI_1LINE_TX(hspi);
+ SPI_1LINE_TX(hspi);
}
/* Check if the SPI is already enabled */
@@ -374,10 +381,11 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Transmit data in 8 Bit mode */
if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
{
-
- hspi->Instance->DR = (*hspi->pTxBuffPtr++);
- hspi->TxXferCount--;
-
+ if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01))
+ {
+ hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+ }
while(hspi->TxXferCount > 0)
{
/* Wait until TXE flag is set to send data */
@@ -389,7 +397,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
hspi->TxXferCount--;
}
/* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@@ -397,10 +405,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Transmit data in 16 Bit mode */
else
{
- hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr+=2;
- hspi->TxXferCount--;
-
+ if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
+ {
+ hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr+=2;
+ hspi->TxXferCount--;
+ }
while(hspi->TxXferCount > 0)
{
/* Wait until TXE flag is set to send data */
@@ -413,7 +423,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
hspi->TxXferCount--;
}
/* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@@ -433,7 +443,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
return HAL_TIMEOUT;
}
- /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
+ /* Clear OVERRUN flag in 2 Lines communication mode because received is not read */
if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
@@ -454,7 +464,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/**
* @brief Receive an amount of data in blocking mode
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
* @param Timeout: Timeout duration
@@ -492,13 +503,13 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
- __HAL_SPI_1LINE_RX(hspi);
+ SPI_1LINE_RX(hspi);
}
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
@@ -532,7 +543,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
hspi->RxXferCount--;
}
/* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@@ -553,7 +564,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
hspi->RxXferCount--;
}
/* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@@ -579,7 +590,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
hspi->RxXferCount--;
/* Wait until RXNE flag is set: CRC Received */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
{
@@ -589,6 +600,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Read CRC to Flush RXNE flag */
tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
}
if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
@@ -601,12 +613,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
/* Check if CRC error occurred */
- if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
+ if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (tmp != RESET))
{
hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
/* Reset CRC Calculation */
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
/* Process Unlocked */
__HAL_UNLOCK(hspi);
@@ -627,7 +639,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/**
* @brief Transmit and Receive an amount of data in blocking mode
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param pTxData: pointer to transmission data buffer
* @param pRxData: pointer to reception data buffer to be
* @param Size: amount of data to be sent
@@ -637,10 +650,10 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
{
__IO uint16_t tmpreg;
- uint32_t tmp = 0;
+ uint32_t tmpstate = 0, tmp = 0;
- tmp = hspi->State;
- if((tmp == HAL_SPI_STATE_READY) || (tmp == HAL_SPI_STATE_BUSY_RX))
+ tmpstate = hspi->State;
+ if((tmpstate == HAL_SPI_STATE_READY) || (tmpstate == HAL_SPI_STATE_BUSY_RX))
{
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
{
@@ -675,9 +688,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
hspi->TxISR = 0;
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
/* Check if the SPI is already enabled */
@@ -690,14 +703,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/* Transmit and Receive data in 16 Bit mode */
if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
- hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr+=2;
- hspi->TxXferCount--;
-
+ if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
+ {
+ hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr+=2;
+ hspi->TxXferCount--;
+ }
if(hspi->TxXferCount == 0)
{
/* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@@ -727,7 +742,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
hspi->TxXferCount--;
/* Enable CRC Transmission */
- if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
+ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@@ -737,34 +752,38 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
return HAL_TIMEOUT;
}
-
+
*((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
hspi->pRxBuffPtr+=2;
hspi->RxXferCount--;
}
-
- /* Wait until RXNE flag is set */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ /* Receive the last byte */
+ if(hspi->Init.Mode == SPI_MODE_SLAVE)
{
- return HAL_TIMEOUT;
+ /* Wait until RXNE flag is set */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr+=2;
+ hspi->RxXferCount--;
}
-
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr+=2;
- hspi->RxXferCount--;
}
}
/* Transmit and Receive data in 8 Bit mode */
else
{
-
- hspi->Instance->DR = (*hspi->pTxBuffPtr++);
- hspi->TxXferCount--;
-
+ if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
+ {
+ hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+ }
if(hspi->TxXferCount == 0)
{
/* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
@@ -792,34 +811,36 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
hspi->TxXferCount--;
/* Enable CRC Transmission */
- if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
+ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
+ /* Wait until RXNE flag is set */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
+ hspi->RxXferCount--;
+ }
+ if(hspi->Init.Mode == SPI_MODE_SLAVE)
+ {
/* Wait until RXNE flag is set */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
-
+
(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
hspi->RxXferCount--;
}
-
- /* Wait until RXNE flag is set */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
- hspi->RxXferCount--;
}
}
/* Read CRC from DR to close CRC calculation process */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait until RXNE flag is set */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
@@ -829,6 +850,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
/* Read CRC */
tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
}
/* Wait until Busy flag is reset before disabling SPI */
@@ -842,14 +864,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
/* Check if CRC error occurred */
- if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
+ if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (tmp != RESET))
{
hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
/* Process Unlocked */
@@ -871,7 +893,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/**
* @brief Transmit an amount of data in no-blocking mode with Interrupt
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
* @retval HAL status
@@ -908,13 +931,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
- __HAL_SPI_1LINE_TX(hspi);
+ SPI_1LINE_TX(hspi);
}
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
@@ -945,7 +968,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/**
* @brief Receive an amount of data in no-blocking mode with Interrupt
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
* @retval HAL status
@@ -979,7 +1003,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
- __HAL_SPI_1LINE_RX(hspi);
+ SPI_1LINE_RX(hspi);
}
else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
@@ -991,9 +1015,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
}
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
/* Enable TXE and ERR interrupt */
@@ -1023,7 +1047,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
/**
* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param pTxData: pointer to transmission data buffer
* @param pRxData: pointer to reception data buffer to be
* @param Size: amount of data to be sent
@@ -1031,10 +1056,11 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
- uint32_t tmp = 0;
+ uint32_t tmpstate = 0;
- tmp = hspi->State;
- if((tmp == HAL_SPI_STATE_READY) || (tmp == HAL_SPI_STATE_BUSY_RX))
+ tmpstate = hspi->State;
+ if((tmpstate == HAL_SPI_STATE_READY) || \
+ ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmpstate == HAL_SPI_STATE_BUSY_RX)))
{
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
{
@@ -1048,7 +1074,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
__HAL_LOCK(hspi);
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if(hspi->State == HAL_SPI_STATE_READY)
+ if(hspi->State != HAL_SPI_STATE_BUSY_RX)
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
}
@@ -1067,9 +1093,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
hspi->RxXferCount = Size;
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
/* Enable TXE, RXNE and ERR interrupt */
@@ -1095,7 +1121,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
/**
* @brief Transmit an amount of data in no-blocking mode with DMA
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
* @retval HAL status
@@ -1132,15 +1159,18 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
- __HAL_SPI_1LINE_TX(hspi);
+ SPI_1LINE_TX(hspi);
}
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
+ /* Set the SPI TxDMA Half transfer complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
+
/* Set the SPI TxDMA transfer complete callback */
hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
@@ -1150,9 +1180,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
/* Enable the Tx DMA Stream */
HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
- /* Enable Tx DMA Request */
- hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
-
/* Process Unlocked */
__HAL_UNLOCK(hspi);
@@ -1163,6 +1190,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
__HAL_SPI_ENABLE(hspi);
}
+ /* Enable Tx DMA Request */
+ hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
+
return HAL_OK;
}
else
@@ -1173,7 +1203,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
/**
* @brief Receive an amount of data in no-blocking mode with DMA
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
* @note When the CRC feature is enabled the pData Length must be Size + 1.
* @param Size: amount of data to be sent
@@ -1208,7 +1239,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
- __HAL_SPI_1LINE_RX(hspi);
+ SPI_1LINE_RX(hspi);
}
else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
{
@@ -1220,11 +1251,14 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
}
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
+ /* Set the SPI RxDMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+
/* Set the SPI Rx DMA transfer complete callback */
hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
@@ -1234,9 +1268,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Enable the Rx DMA Stream */
HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
- /* Enable Rx DMA Request */
- hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
-
/* Process Unlocked */
__HAL_UNLOCK(hspi);
@@ -1247,6 +1278,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
__HAL_SPI_ENABLE(hspi);
}
+ /* Enable Rx DMA Request */
+ hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
+
return HAL_OK;
}
else
@@ -1257,7 +1291,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/**
* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param pTxData: pointer to transmission data buffer
* @param pRxData: pointer to reception data buffer
* @note When the CRC feature is enabled the pRxData Length must be Size + 1
@@ -1268,7 +1303,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
{
uint32_t tmpstate = 0;
tmpstate = hspi->State;
- if((tmpstate == HAL_SPI_STATE_READY) || (tmpstate == HAL_SPI_STATE_BUSY_RX))
+ if((tmpstate == HAL_SPI_STATE_READY) || ((hspi->Init.Mode == SPI_MODE_MASTER) && \
+ (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmpstate == HAL_SPI_STATE_BUSY_RX)))
{
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
{
@@ -1282,7 +1318,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
__HAL_LOCK(hspi);
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if(hspi->State == HAL_SPI_STATE_READY)
+ if(hspi->State != HAL_SPI_STATE_BUSY_RX)
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
}
@@ -1303,18 +1339,24 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
hspi->TxISR = 0;
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
if(hspi->State == HAL_SPI_STATE_BUSY_RX)
{
+ /* Set the SPI Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+
hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
}
else
{
+ /* Set the SPI Tx/Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
+
hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
}
@@ -1330,26 +1372,33 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
is performed in DMA reception complete callback */
hspi->hdmatx->XferCpltCallback = NULL;
-
- /* Set the DMA error callback */
- hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-
+
+ if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
+ {
+ /* Set the DMA error callback */
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+ }
+ else
+ {
+ hspi->hdmatx->XferErrorCallback = NULL;
+ }
+
/* Enable the Tx DMA Stream */
HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
- /* Enable Tx DMA Request */
- hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
-
/* Process Unlocked */
__HAL_UNLOCK(hspi);
- /* Check if the SPI is already enabled */
+ /* Check if the SPI is already enabled */
if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
+ /* Enable Tx DMA Request */
+ hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
+
return HAL_OK;
}
else
@@ -1358,9 +1407,86 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
}
}
+/**
+ * @brief Pauses the DMA Transfer.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Disable the SPI DMA Tx & Rx requests */
+ hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the DMA Transfer.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Enable the SPI DMA Tx & Rx requests */
+ hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
+ hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the DMA Transfer.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
+ */
+
+ /* Abort the SPI DMA tx Stream */
+ if(hspi->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hspi->hdmatx);
+ }
+ /* Abort the SPI DMA rx Stream */
+ if(hspi->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hspi->hdmarx);
+ }
+
+ /* Disable the SPI DMA Tx & Rx requests */
+ hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return HAL_OK;
+}
+
/**
* @brief This function handles SPI interrupt request.
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval HAL status
*/
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
@@ -1379,7 +1505,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE);
tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE);
- /* SPI in mode Tramitter ---------------------------------------------------*/
+ /* SPI in mode Transmitter ---------------------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
hspi->TxISR(hspi);
@@ -1388,20 +1514,20 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
{
- /* SPI CRC error interrupt occured ---------------------------------------*/
+ /* SPI CRC error interrupt occurred ---------------------------------------*/
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
- /* SPI Mode Fault error interrupt occured --------------------------------*/
+ /* SPI Mode Fault error interrupt occurred --------------------------------*/
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
{
hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
__HAL_SPI_CLEAR_MODFFLAG(hspi);
}
- /* SPI Overrun error interrupt occured -----------------------------------*/
+ /* SPI Overrun error interrupt occurred -----------------------------------*/
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
{
if(hspi->State != HAL_SPI_STATE_BUSY_TX)
@@ -1411,7 +1537,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
}
}
- /* SPI Frame error interrupt occured -------------------------------------*/
+ /* SPI Frame error interrupt occurred -------------------------------------*/
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
{
hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
@@ -1429,51 +1555,94 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
/**
* @brief Tx Transfer completed callbacks
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_TxCpltCallback could be implenetd in the user file
+ the HAL_SPI_TxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Rx Transfer completed callbacks
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_RxCpltCallback() could be implenetd in the user file
+ the HAL_SPI_RxCpltCallback() could be implemented in the user file
*/
}
/**
* @brief Tx and Rx Transfer completed callbacks
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
+ the HAL_SPI_TxRxCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callbacks
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_TxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callbacks
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_RxHalfCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Transfer completed callbacks
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxHalfCpltCallback() could be implemented in the user file
*/
}
/**
* @brief SPI error callbacks
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
{
/* NOTE : - This function Should not be modified, when the callback is needed,
- the HAL_SPI_ErrorCallback() could be implenetd in the user file.
+ the HAL_SPI_ErrorCallback() could be implemented in the user file.
- The ErrorCode parameter in the hspi handle is updated by the SPI processes
- and user can use HAL_SPI_GetError() API to check the latest error occured.
+ and user can use HAL_SPI_GetError() API to check the latest error occurred.
*/
}
@@ -1481,7 +1650,7 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
* @}
*/
-/** @defgroup SPI_Group3 Peripheral State and Errors functions
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief SPI control functions
*
@verbatim
@@ -1498,8 +1667,9 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
/**
* @brief Return the SPI state
- * @param hspi : SPI handle
- * @retval SPI state
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL state
*/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
{
@@ -1508,10 +1678,11 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
/**
* @brief Return the SPI error code
- * @param hspi : SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval SPI Error Code
*/
-HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
{
return hspi->ErrorCode;
}
@@ -1522,7 +1693,8 @@ HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
/**
* @brief Interrupt Handler to close Tx transfer
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval void
*/
static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
@@ -1547,7 +1719,7 @@ static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
}
- /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
+ /* Clear OVERRUN flag in 2 Lines communication mode because received is not read */
if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
@@ -1582,7 +1754,8 @@ static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
/**
* @brief Interrupt Handler to transmit amount of data in no-blocking mode
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval void
*/
static void SPI_TxISR(SPI_HandleTypeDef *hspi)
@@ -1602,7 +1775,7 @@ static void SPI_TxISR(SPI_HandleTypeDef *hspi)
if(hspi->TxXferCount == 0)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* calculate and transfer CRC on Tx line */
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
@@ -1613,14 +1786,15 @@ static void SPI_TxISR(SPI_HandleTypeDef *hspi)
/**
* @brief Interrupt Handler to close Rx transfer
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval void
*/
static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
{
__IO uint16_t tmpreg;
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait until RXNE flag is set to send data */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
@@ -1630,6 +1804,7 @@ static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
/* Read CRC to reset RXNE flag */
tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
/* Wait until RXNE flag is set to send data */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
@@ -1643,7 +1818,7 @@ static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
/* Reset CRC Calculation */
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
}
@@ -1671,7 +1846,8 @@ static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
/* Set state to READY before run the Callback Complete */
hspi->State = HAL_SPI_STATE_READY;
HAL_SPI_TxRxCpltCallback(hspi);
- }else
+ }
+ else
{
/* Set state to READY before run the Callback Complete */
hspi->State = HAL_SPI_STATE_READY;
@@ -1690,7 +1866,8 @@ static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
/**
* @brief Interrupt Handler to receive amount of data in 2Lines mode
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval void
*/
static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
@@ -1716,7 +1893,8 @@ static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
/**
* @brief Interrupt Handler to receive amount of data in no-blocking mode
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval void
*/
static void SPI_RxISR(SPI_HandleTypeDef *hspi)
@@ -1735,7 +1913,7 @@ static void SPI_RxISR(SPI_HandleTypeDef *hspi)
hspi->RxXferCount--;
/* Enable CRC Transmission */
- if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
+ if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
/* Set CRC Next to calculate CRC on Rx side */
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
@@ -1749,36 +1927,40 @@ static void SPI_RxISR(SPI_HandleTypeDef *hspi)
/**
* @brief DMA SPI transmit process complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* Wait until TXE flag is set to send data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ /* DMA Normal Mode */
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
- }
-
- /* Disable Tx DMA Request */
- hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ /* Wait until TXE flag is set to send data */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ }
+ /* Disable Tx DMA Request */
+ hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
- /* Wait until Busy flag is reset before disabling SPI */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
- }
+ /* Wait until Busy flag is reset before disabling SPI */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ }
- hspi->TxXferCount = 0;
+ hspi->TxXferCount = 0;
- hspi->State = HAL_SPI_STATE_READY;
+ hspi->State = HAL_SPI_STATE_READY;
+ }
- /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
+ /* Clear OVERRUN flag in 2 Lines communication mode because received is not read */
if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
}
/* Check if Errors has been detected during transfer */
@@ -1794,57 +1976,75 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA SPI receive process complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
__IO uint16_t tmpreg;
-
+
SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
- {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
- }
-
- /* Disable Rx DMA Request */
- hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ /* DMA Normal mode */
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
{
- /* Wait until RXNE flag is set to send data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ SPI_DMAEndTransmitReceive(hspi);
}
-
- /* Read CRC */
- tmpreg = hspi->Instance->DR;
-
- /* Wait until RXNE flag is set to send data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ /* SPI_DIRECTION_1LINE or SPI_DIRECTION_2LINES_RXONLY */
+ else
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Disable Rx DMA Request */
+ hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+
+ hspi->RxXferCount = 0;
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Wait until RXNE flag is set to send data */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Read CRC */
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+
+ /* Wait until RXNE flag is set */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+ }
}
- }
-
- hspi->RxXferCount = 0;
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
-
- /* Check if Errors has been detected during transfer */
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_ErrorCallback(hspi);
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+ HAL_SPI_RxCpltCallback(hspi);
+ }
}
else
{
@@ -1853,18 +2053,17 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
}
/**
- * @brief DMA SPI transmit receive process complete callback
- * @param hdma : DMA handle
+ * @brief End DMA SPI transmit receive process
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval None
*/
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+static void SPI_DMAEndTransmitReceive(SPI_HandleTypeDef *hspi)
{
__IO uint16_t tmpreg;
-
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
+
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Check if CRC is done on going (RXNE flag set) */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
@@ -1877,8 +2076,16 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
}
/* Read CRC */
tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
}
-
+
/* Wait until TXE flag is set to send data */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
{
@@ -1886,32 +2093,44 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
}
/* Disable Tx DMA Request */
hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-
+
/* Wait until Busy flag is reset before disabling SPI */
if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
{
hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
}
-
+
/* Disable Rx DMA Request */
hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-
+
hspi->TxXferCount = 0;
hspi->RxXferCount = 0;
+}
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
-
- /* Check if Errors has been detected during transfer */
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_ErrorCallback(hspi);
+/**
+ * @brief DMA SPI transmit receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ { /**/
+ SPI_DMAEndTransmitReceive(hspi);
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+ HAL_SPI_TxRxCpltCallback(hspi);
+ }
}
else
{
@@ -1919,9 +2138,49 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
}
}
+/**
+ * @brief DMA SPI half transmit process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_TxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI half receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_RxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI Half transmit receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_TxRxHalfCpltCallback(hspi);
+}
+
/**
* @brief DMA SPI communication error callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAError(DMA_HandleTypeDef *hdma)
@@ -1936,14 +2195,19 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma)
/**
* @brief This function handles SPI Communication Timeout.
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Flag: SPI flag to check
+ * @param Status: Flag status to check: RESET or set
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Wait until flag is set */
if(Status == RESET)
@@ -1952,7 +2216,7 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin
{
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
@@ -1965,9 +2229,9 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin
__HAL_SPI_DISABLE(hspi);
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
hspi->State= HAL_SPI_STATE_READY;
@@ -1986,7 +2250,7 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin
{
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
@@ -1999,9 +2263,9 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin
__HAL_SPI_DISABLE(hspi);
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
hspi->State= HAL_SPI_STATE_READY;
diff --git a/f2/src/stm32f2xx_hal_sram.c b/f2/src/stm32f2xx_hal_sram.c
index 64251456b8fb22a49f2ae671e3c403154bea432e..918d393234e6e9774d8dc8126ae629cb60529125 100755
--- a/f2/src/stm32f2xx_hal_sram.c
+++ b/f2/src/stm32f2xx_hal_sram.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_sram.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief SRAM HAL module driver.
* This file provides a generic firmware to drive SRAM memories
* mounted as external device.
@@ -14,9 +14,9 @@
==============================================================================
[..]
This driver is a generic layered driver which contains a set of APIs used to
- control SRAM memories. It uses the FMC layer functions to interface
+ control SRAM memories. It uses the FSMC layer functions to interface
with SRAM devices.
- The following sequence should be followed to configure the FMC/FSMC to interface
+ The following sequence should be followed to configure the FSMC to interface
with SRAM/PSRAM memories:
(#) Declare a SRAM_HandleTypeDef handle structure, for example:
@@ -31,22 +31,22 @@
(++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
base register instance for NOR or SRAM extended mode
- (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
+ (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
mode timings; for example:
- FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
+ FSMC_NORSRAM_TimingTypeDef Timing and FSMC_NORSRAM_TimingTypeDef ExTiming;
and fill its fields with the allowed values of the structure member.
(#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
performs the following sequence:
(##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
- (##) Control register configuration using the FMC NORSRAM interface function
- FMC_NORSRAM_Init()
- (##) Timing register configuration using the FMC NORSRAM interface function
- FMC_NORSRAM_Timing_Init()
- (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
- FMC_NORSRAM_Extended_Timing_Init()
- (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
+ (##) Control register configuration using the FSMC NORSRAM interface function
+ FSMC_NORSRAM_Init()
+ (##) Timing register configuration using the FSMC NORSRAM interface function
+ FSMC_NORSRAM_Timing_Init()
+ (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
+ FSMC_NORSRAM_Extended_Timing_Init()
+ (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()
(#) At this stage you can perform read/write accesses from/to the memory connected
to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
@@ -64,7 +64,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -98,7 +98,7 @@
* @{
*/
-/** @defgroup SRAM
+/** @defgroup SRAM SRAM
* @brief SRAM driver modules
* @{
*/
@@ -108,15 +108,13 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
/* Private functions ---------------------------------------------------------*/
-/** @defgroup SRAM_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
* @{
*/
-
-/** @defgroup SRAM_Group1 Initialization and de-initialization functions
+/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -132,12 +130,13 @@
/**
* @brief Performs the SRAM device initialization sequence
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @param Timing: Pointer to SRAM control timing structure
* @param ExtTiming: Pointer to SRAM extended mode timing structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
{
/* Check the SRAM handle parameter */
if(hsram == NULL)
@@ -147,28 +146,31 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp
if(hsram->State == HAL_SRAM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hsram->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_SRAM_MspInit(hsram);
}
/* Initialize SRAM control Interface */
- FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
+ FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
/* Initialize SRAM timing Interface */
- FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
+ FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
/* Initialize SRAM extended mode timing Interface */
- FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
+ FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
/* Enable the NORSRAM device */
- __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
+ __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
return HAL_OK;
}
/**
* @brief Performs the SRAM device De-initialization sequence.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
@@ -177,7 +179,7 @@ HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
HAL_SRAM_MspDeInit(hsram);
/* Configure the SRAM registers with their reset values */
- FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
+ FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
hsram->State = HAL_SRAM_STATE_RESET;
@@ -189,7 +191,8 @@ HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
/**
* @brief SRAM MSP Init.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @retval None
*/
__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
@@ -201,7 +204,8 @@ __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
/**
* @brief SRAM MSP DeInit.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @retval None
*/
__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
@@ -213,8 +217,9 @@ __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
/**
* @brief DMA transfer complete callback.
- * @param hsram: pointer to SRAM handle
- * @retval none
+ * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
*/
__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
{
@@ -225,8 +230,9 @@ __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
/**
* @brief DMA transfer complete error callback.
- * @param hsram: pointer to SRAM handle
- * @retval none
+ * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
*/
__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
{
@@ -239,7 +245,7 @@ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
* @}
*/
-/** @defgroup SRAM_Group2 Input and Output functions
+/** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions
* @brief Input Output and memory control functions
*
@verbatim
@@ -255,7 +261,8 @@ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
/**
* @brief Reads 8-bit buffer from SRAM memory.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
@@ -290,7 +297,8 @@ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress
/**
* @brief Writes 8-bit buffer to SRAM memory.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
@@ -331,7 +339,8 @@ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
/**
* @brief Reads 16-bit buffer from SRAM memory.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
@@ -366,7 +375,8 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
/**
* @brief Writes 16-bit buffer to SRAM memory.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
@@ -407,7 +417,8 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
/**
* @brief Reads 32-bit buffer from SRAM memory.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
@@ -440,7 +451,8 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
/**
* @brief Writes 32-bit buffer to SRAM memory.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
@@ -479,7 +491,8 @@ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
/**
* @brief Reads a Words data from the SRAM memory using DMA transfer.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
@@ -511,7 +524,8 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
/**
* @brief Writes a Words data buffer to SRAM memory using DMA transfer.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
@@ -551,7 +565,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
* @}
*/
-/** @defgroup SRAM_Group3 Control functions
+/** @defgroup SRAM_Exported_Functions_Group3 Control functions
* @brief management functions
*
@verbatim
@@ -568,7 +582,8 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
/**
* @brief Enables dynamically SRAM write operation.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
@@ -577,7 +592,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
__HAL_LOCK(hsram);
/* Enable write operation */
- FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
+ FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_READY;
@@ -590,7 +605,8 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
/**
* @brief Disables dynamically SRAM write operation.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
@@ -602,7 +618,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
hsram->State = HAL_SRAM_STATE_BUSY;
/* Disable write operation */
- FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
+ FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_PROTECTED;
@@ -617,7 +633,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
* @}
*/
-/** @defgroup SRAM_Group4 State functions
+/** @defgroup SRAM_Exported_Functions_Group4 State functions
* @brief Peripheral State functions
*
@verbatim
@@ -634,8 +650,9 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
/**
* @brief Returns the SRAM controller state
- * @param hsram: pointer to SRAM handle
- * @retval SRAM controller state
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL state
*/
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
{
diff --git a/f2/src/stm32f2xx_hal_tim.c b/f2/src/stm32f2xx_hal_tim.c
index 70c57ee3e17c1cc7d67556707289315ed50a25d8..3d94c34a4ab63198a745f2186201b87809451334 100755
--- a/f2/src/stm32f2xx_hal_tim.c
+++ b/f2/src/stm32f2xx_hal_tim.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_tim.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
@@ -98,7 +98,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -132,7 +132,7 @@
* @{
*/
-/** @defgroup TIM
+/** @defgroup TIM TIM
* @brief TIM HAL module driver
* @{
*/
@@ -143,6 +143,9 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+ * @{
+ */
/* Private function prototypes -----------------------------------------------*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
@@ -163,13 +166,18 @@ static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup TIM_Private_Functions
+static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
* @{
*/
-/** @defgroup TIM_Group1 Time Base functions
+/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
* @brief Time Base functions
*
@verbatim
@@ -193,7 +201,8 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
/**
* @brief Initializes the TIM Time base Unit according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: TIM Base handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
@@ -211,6 +220,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
if(htim->State == HAL_TIM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
}
@@ -229,7 +240,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes the TIM Base peripheral
- * @param htim: TIM Base handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
@@ -256,7 +268,8 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Base MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
@@ -268,7 +281,8 @@ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes TIM Base MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
@@ -280,7 +294,8 @@ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Base generation.
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
@@ -303,7 +318,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
/**
* @brief Stops the TIM Base generation.
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
@@ -326,7 +342,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Base generation in interrupt mode.
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
@@ -346,7 +363,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
/**
* @brief Stops the TIM Base generation in interrupt mode.
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
@@ -365,7 +383,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Base generation in DMA mode.
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param pData: The source Buffer address.
* @param Length: The length of data to be transferred from memory to peripheral.
* @retval HAL status
@@ -394,7 +413,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
@@ -411,7 +430,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
/**
* @brief Stops the TIM Base generation in DMA mode.
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
@@ -431,12 +451,11 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
/* Return function status */
return HAL_OK;
}
-
/**
* @}
*/
-/** @defgroup TIM_Group2 Time Output Compare functions
+/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
* @brief Time Output Compare functions
*
@verbatim
@@ -460,7 +479,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Output Compare according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: TIM Output Compare handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
@@ -477,7 +497,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OC_MspInit(htim);
}
@@ -496,7 +518,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
/**
* @brief DeInitializes the TIM peripheral
- * @param htim: TIM Output Compare handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
@@ -523,7 +546,8 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Output Compare MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
@@ -535,7 +559,8 @@ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes TIM Output Compare MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
@@ -547,8 +572,9 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Output Compare signal generation.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -579,8 +605,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the TIM Output Compare signal generation.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -598,7 +625,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -611,8 +638,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the TIM Output Compare signal generation in interrupt mode.
- * @param htim : TIM OC handle
- * @param Channel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -677,8 +705,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the TIM Output Compare signal generation in interrupt mode.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -730,7 +759,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -743,8 +772,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the TIM Output Compare signal generation in DMA mode.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -779,10 +809,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
@@ -795,10 +825,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
@@ -811,10 +841,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
@@ -827,10 +857,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
@@ -862,8 +892,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Stops the TIM Output Compare signal generation in DMA mode.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -915,7 +946,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -928,12 +959,11 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Return function status */
return HAL_OK;
}
-
/**
* @}
*/
-/** @defgroup TIM_Group3 Time PWM functions
+/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
* @brief Time PWM functions
*
@verbatim
@@ -957,7 +987,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Initializes the TIM PWM Time Base according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
@@ -975,6 +1006,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
if(htim->State == HAL_TIM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
}
@@ -993,7 +1026,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes the TIM peripheral
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
@@ -1020,7 +1054,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM PWM MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
@@ -1032,7 +1067,8 @@ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes TIM PWM MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
@@ -1044,8 +1080,9 @@ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
/**
* @brief Starts the PWM signal generation.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1076,8 +1113,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the PWM signal generation.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1095,7 +1133,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -1111,8 +1149,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the PWM signal generation in interrupt mode.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1177,8 +1216,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Stops the PWM signal generation in interrupt mode.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1230,7 +1270,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel
if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -1243,8 +1283,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Starts the TIM PWM signal generation in DMA mode.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1279,10 +1320,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
@@ -1295,10 +1336,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
@@ -1311,10 +1352,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
@@ -1327,10 +1368,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
@@ -1362,8 +1403,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
/**
* @brief Stops the TIM PWM signal generation in DMA mode.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1415,7 +1457,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -1428,12 +1470,11 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/* Return function status */
return HAL_OK;
}
-
/**
* @}
*/
-/** @defgroup TIM_Group4 Time Input Capture functions
+/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
* @brief Time Input Capture functions
*
@verbatim
@@ -1457,7 +1498,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Initializes the TIM Input Capture Time base according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: TIM Input Capture handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
@@ -1474,7 +1516,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_IC_MspInit(htim);
}
@@ -1493,7 +1537,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes the TIM peripheral
- * @param htim: TIM Input Capture handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
@@ -1520,7 +1565,8 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM INput Capture MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
@@ -1532,7 +1578,8 @@ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes TIM Input Capture MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
@@ -1544,8 +1591,9 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Input Capture measurement.
- * @param hdma : TIM Input Capture handle
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1570,8 +1618,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the TIM Input Capture measurement.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1596,8 +1645,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the TIM Input Capture measurement in interrupt mode.
- * @param hdma : TIM Input Capture handle
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1655,8 +1705,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Stops the TIM Input Capture measurement in interrupt mode.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1715,8 +1766,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the TIM Input Capture measurement on in DMA mode.
- * @param htim : TIM Input Capture handle
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1753,10 +1805,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
@@ -1769,10 +1821,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
@@ -1785,10 +1837,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
@@ -1801,10 +1853,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
@@ -1830,8 +1882,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Stops the TIM Input Capture measurement on in DMA mode.
- * @param htim : TIM Input Capture handle
- * @param Channel : TIM Channels to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1895,7 +1948,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
* @}
*/
-/** @defgroup TIM_Group5 Time One Pulse functions
+/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
* @brief Time One Pulse functions
*
@verbatim
@@ -1919,11 +1972,12 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Initializes the TIM One Pulse Time Base according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: TIM OnePulse handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param OnePulseMode: Select the One pulse mode.
* This parameter can be one of the following values:
* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
- * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
+ * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
@@ -1941,7 +1995,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul
assert_param(IS_TIM_OPM_MODE(OnePulseMode));
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OnePulse_MspInit(htim);
}
@@ -1966,7 +2022,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul
/**
* @brief DeInitializes the TIM One Pulse
- * @param htim: TIM One Pulse handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
@@ -1993,7 +2050,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM One Pulse MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
@@ -2005,7 +2063,8 @@ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes TIM One Pulse MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
@@ -2017,8 +2076,9 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM One Pulse signal generation.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel : TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2050,8 +2110,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu
/**
* @brief Stops the TIM One Pulse signal generation.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channels to be disable
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel : TIM Channels to be disable.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2070,7 +2131,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output
if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -2083,8 +2144,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel : TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2122,8 +2184,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel : TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2147,7 +2210,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -2157,12 +2220,11 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
/* Return function status */
return HAL_OK;
}
-
/**
* @}
*/
-/** @defgroup TIM_Group6 Time Encoder functions
+/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
* @brief Time Encoder functions
*
@verbatim
@@ -2185,7 +2247,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
*/
/**
* @brief Initializes the TIM Encoder Interface and create the associated handle.
- * @param htim: TIM Encoder Interface handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sConfig: TIM Encoder Interface configuration structure
* @retval HAL status
*/
@@ -2215,6 +2278,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
if(htim->State == HAL_TIM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_Encoder_MspInit(htim);
}
@@ -2244,7 +2309,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
- /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+ /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
@@ -2272,7 +2337,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
/**
* @brief DeInitializes the TIM Encoder interface
- * @param htim: TIM Encoder handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
@@ -2299,7 +2365,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Encoder Interface MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
@@ -2311,7 +2378,8 @@ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes TIM Encoder Interface MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
@@ -2323,11 +2391,13 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Encoder Interface.
- * @param htim : TIM Encoder Interface handle
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -2364,11 +2434,13 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe
/**
* @brief Stops the TIM Encoder Interface.
- * @param htim : TIM Encoder Interface handle
- * @param Channel : TIM Channels to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -2406,11 +2478,13 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Starts the TIM Encoder Interface in interrupt mode.
- * @param htim : TIM Encoder Interface handle
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -2453,11 +2527,13 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha
/**
* @brief Stops the TIM Encoder Interface in interrupt mode.
- * @param htim : TIM Encoder Interface handle
- * @param Channel : TIM Channels to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -2503,11 +2579,13 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan
/**
* @brief Starts the TIM Encoder Interface in DMA mode.
- * @param htim : TIM Encoder Interface handle
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @param pData1: The destination Buffer address for IC1.
* @param pData2: The destination Buffer address for IC2.
* @param Length: The length of data to be transferred from TIM peripheral to memory.
@@ -2539,10 +2617,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
@@ -2561,10 +2639,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
@@ -2582,19 +2660,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
case TIM_CHANNEL_ALL:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
@@ -2622,11 +2700,13 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
/**
* @brief Stops the TIM Encoder Interface in DMA mode.
- * @param htim : TIM Encoder Interface handle
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -2669,11 +2749,11 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Return function status */
return HAL_OK;
}
-
/**
* @}
*/
-/** @defgroup TIM_Group7 TIM IRQ handler management
+
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
* @brief IRQ handler management
*
@verbatim
@@ -2688,7 +2768,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
*/
/**
* @brief This function handles TIM interrupts requests.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
@@ -2696,7 +2777,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
/* Capture compare 1 event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
@@ -2720,7 +2801,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
/* Capture compare 2 event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
@@ -2741,12 +2822,12 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
/* Capture compare 3 event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
/* Input capture event */
- if((htim->Instance->CCMR1 & TIM_CCMR2_CC3S) != 0x00)
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
{
HAL_TIM_IC_CaptureCallback(htim);
}
@@ -2762,12 +2843,12 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
/* Capture compare 4 event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
/* Input capture event */
- if((htim->Instance->CCMR1 & TIM_CCMR2_CC4S) != 0x00)
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
{
HAL_TIM_IC_CaptureCallback(htim);
}
@@ -2783,7 +2864,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
/* TIM Update event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
HAL_TIM_PeriodElapsedCallback(htim);
@@ -2792,7 +2873,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
/* TIM Break input event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_BREAK) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
HAL_TIMEx_BreakCallback(htim);
@@ -2801,7 +2882,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
/* TIM Trigger detection event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
HAL_TIM_TriggerCallback(htim);
@@ -2810,19 +2891,18 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
/* TIM commutation event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_COM) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
HAL_TIMEx_CommutationCallback(htim);
}
}
}
-
/**
* @}
*/
-/** @defgroup TIM_Group8 Peripheral Control functions
+/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
@@ -2844,9 +2924,10 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Output Compare Channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
- * @param htim: TIM Output Compare handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sConfig: TIM Output Compare configuration structure
- * @param Channel : TIM Channels to be enabled
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2860,10 +2941,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
- assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
- assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
/* Check input state */
__HAL_LOCK(htim);
@@ -2917,9 +2994,10 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT
/**
* @brief Initializes the TIM Input Capture Channels according to the specified
* parameters in the TIM_IC_InitTypeDef.
- * @param htim: TIM IC handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sConfig: TIM Input Capture configuration structure
- * @param Channel : TIM Channels to be enabled
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3013,9 +3091,10 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
/**
* @brief Initializes the TIM PWM channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sConfig: TIM PWM configuration structure
- * @param Channel : TIM Channels to be enabled
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3031,10 +3110,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_Init
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
-
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
htim->State = HAL_TIM_STATE_BUSY;
switch (Channel)
@@ -3113,13 +3190,14 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_Init
/**
* @brief Initializes the TIM One Pulse Channels according to the specified
* parameters in the TIM_OnePulse_InitTypeDef.
- * @param htim: TIM One Pulse handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sConfig: TIM One Pulse configuration structure
- * @param OutputChannel : TIM Channels to be enabled
+ * @param OutputChannel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @param InputChannel : TIM Channels to be enabled
+ * @param InputChannel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3139,7 +3217,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
htim->State = HAL_TIM_STATE_BUSY;
- /* Extract the Ouput compare configuration from sConfig structure */
+ /* Extract the Output compare configuration from sConfig structure */
temp1.OCMode = sConfig->OCMode;
temp1.Pulse = sConfig->Pulse;
temp1.OCPolarity = sConfig->OCPolarity;
@@ -3225,29 +3303,30 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
/**
* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
- * @param htim: TIM handle
- * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
* This parameters can be on of the following values:
- * @arg TIM_DMABase_CR1
- * @arg TIM_DMABase_CR2
- * @arg TIM_DMABase_SMCR
- * @arg TIM_DMABase_DIER
- * @arg TIM_DMABase_SR
- * @arg TIM_DMABase_EGR
- * @arg TIM_DMABase_CCMR1
- * @arg TIM_DMABase_CCMR2
- * @arg TIM_DMABase_CCER
- * @arg TIM_DMABase_CNT
- * @arg TIM_DMABase_PSC
- * @arg TIM_DMABase_ARR
- * @arg TIM_DMABase_RCR
- * @arg TIM_DMABase_CCR1
- * @arg TIM_DMABase_CCR2
- * @arg TIM_DMABase_CCR3
- * @arg TIM_DMABase_CCR4
- * @arg TIM_DMABase_BDTR
- * @arg TIM_DMABase_DCR
- * @param BurstRequestSrc: TIM DMA Request sources
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
+ * @param BurstRequestSrc: TIM DMA Request sources.
* This parameters can be on of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
@@ -3258,7 +3337,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
* @param BurstBuffer: The Buffer address.
* @param BurstLength: DMA Burst length. This parameter can be one value
- * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+ * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
@@ -3293,7 +3372,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
@@ -3302,10 +3381,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
case TIM_DMA_CC1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
@@ -3314,10 +3393,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
case TIM_DMA_CC2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
@@ -3326,10 +3405,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
case TIM_DMA_CC3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
@@ -3338,10 +3417,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
case TIM_DMA_CC4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
@@ -3350,10 +3429,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
case TIM_DMA_COM:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
@@ -3365,7 +3444,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
@@ -3388,7 +3467,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
/**
* @brief Stops the TIM DMA Burst mode
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param BurstRequestSrc: TIM DMA Request sources to disable
* @retval HAL status
*/
@@ -3397,6 +3477,48 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ }
+ break;
+ default:
+ break;
+ }
+
/* Disable the TIM Update DMA request */
__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
@@ -3406,29 +3528,30 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
/**
* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
- * @param htim: TIM handle
- * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
* This parameters can be on of the following values:
- * @arg TIM_DMABase_CR1
- * @arg TIM_DMABase_CR2
- * @arg TIM_DMABase_SMCR
- * @arg TIM_DMABase_DIER
- * @arg TIM_DMABase_SR
- * @arg TIM_DMABase_EGR
- * @arg TIM_DMABase_CCMR1
- * @arg TIM_DMABase_CCMR2
- * @arg TIM_DMABase_CCER
- * @arg TIM_DMABase_CNT
- * @arg TIM_DMABase_PSC
- * @arg TIM_DMABase_ARR
- * @arg TIM_DMABase_RCR
- * @arg TIM_DMABase_CCR1
- * @arg TIM_DMABase_CCR2
- * @arg TIM_DMABase_CCR3
- * @arg TIM_DMABase_CCR4
- * @arg TIM_DMABase_BDTR
- * @arg TIM_DMABase_DCR
- * @param BurstRequestSrc: TIM DMA Request sources
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
+ * @param BurstRequestSrc: TIM DMA Request sources.
* This parameters can be on of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
@@ -3439,7 +3562,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
* @param BurstBuffer: The Buffer address.
* @param BurstLength: DMA Burst length. This parameter can be one value
- * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+ * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
@@ -3474,7 +3597,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
@@ -3483,10 +3606,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
case TIM_DMA_CC1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
@@ -3495,10 +3618,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
case TIM_DMA_CC2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
@@ -3507,10 +3630,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
case TIM_DMA_CC3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
@@ -3519,10 +3642,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
case TIM_DMA_CC4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
@@ -3531,10 +3654,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
case TIM_DMA_COM:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
@@ -3546,7 +3669,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
@@ -3570,7 +3693,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
/**
* @brief Stop the DMA burst reading
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param BurstRequestSrc: TIM DMA Request sources to disable.
* @retval HAL status
*/
@@ -3579,6 +3703,48 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ }
+ break;
+ default:
+ break;
+ }
+
/* Disable the TIM Update DMA request */
__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
@@ -3588,19 +3754,20 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu
/**
* @brief Generate a software event
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param EventSource: specifies the event source.
* This parameter can be one of the following values:
- * @arg TIM_EventSource_Update: Timer update Event source
- * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
- * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
- * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
- * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EventSource_COM: Timer COM event source
- * @arg TIM_EventSource_Trigger: Timer Trigger Event source
- * @arg TIM_EventSource_Break: Timer Break event source
+ * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+ * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+ * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+ * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+ * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+ * @arg TIM_EVENTSOURCE_COM: Timer COM event source
+ * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+ * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
* @note TIM6 and TIM7 can only generate an update event.
- * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
+ * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1 and TIM8.
* @retval HAL status
*/
@@ -3630,15 +3797,16 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS
/**
* @brief Configures the OCRef clear feature
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
* contains the OCREF clear feature and parameters for the TIM peripheral.
- * @param Channel: specifies the TIM Channel
+ * @param Channel: specifies the TIM Channel.
* This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
@@ -3738,7 +3906,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp
/**
* @brief Configures the clock source to be used
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
@@ -3871,7 +4040,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
/**
* @brief Selects the signal connected to the TI1 input: direct from CH1_input
* or a XOR combination between CH1_input, CH2_input & CH3_input
- * @param htim: TIM handle.
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param TI1_Selection: Indicate whether or not channel 1 is connected to the
* output of a XOR gate.
* This parameter can be one of the following values:
@@ -3894,7 +4064,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
/* Reset the TI1 selection */
tmpcr2 &= ~TIM_CR2_TI1S;
- /* Set the the TI1 selection */
+ /* Set the TI1 selection */
tmpcr2 |= TI1_Selection;
/* Write to TIMxCR2 */
@@ -3905,7 +4075,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
/**
* @brief Configures the TIM in Slave mode
- * @param htim: TIM handle.
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
* contains the selected trigger (internal trigger input, filtered
* timer input or external trigger input) and the ) and the Slave
@@ -3914,10 +4085,6 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
*/
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
{
- uint32_t tmpsmcr = 0;
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
-
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
@@ -3927,133 +4094,62 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI
htim->State = HAL_TIM_STATE_BUSY;
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* Reset the Trigger Selection Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- /* Set the Input Trigger source */
- tmpsmcr |= sSlaveConfig->InputTrigger;
-
- /* Reset the slave mode Bits */
- tmpsmcr &= ~TIM_SMCR_SMS;
- /* Set the slave mode */
- tmpsmcr |= sSlaveConfig->SlaveMode;
+ TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+
+ /* Disable Trigger Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
+/**
+ * @brief Configures the TIM in Slave mode in interrupt mode
+ * @param htim: TIM handle.
+ * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the ) and the Slave
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
- /* Configure the trigger prescaler, filter, and polarity */
- switch (sSlaveConfig->InputTrigger)
- {
- case TIM_TS_ETRF:
- {
- /* Check the parameters */
- assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
- /* Configure the ETR Trigger source */
- TIM_ETR_SetConfig(htim->Instance,
- sSlaveConfig->TriggerPrescaler,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- }
- break;
-
- case TIM_TS_TI1F_ED:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- tmpccer = htim->Instance->CCER;
- htim->Instance->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = htim->Instance->CCMR1;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
-
- /* Write to TIMx CCMR1 and CCER registers */
- htim->Instance->CCMR1 = tmpccmr1;
- htim->Instance->CCER = tmpccer;
-
- }
- break;
-
- case TIM_TS_TI1FP1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ __HAL_LOCK(htim);
- /* Configure TI1 Filter and Polarity */
- TIM_TI1_ConfigInputStage(htim->Instance,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- }
- break;
-
- case TIM_TS_TI2FP2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Configure TI2 Filter and Polarity */
- TIM_TI2_ConfigInputStage(htim->Instance,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- }
- break;
-
- case TIM_TS_ITR0:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- case TIM_TS_ITR1:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- case TIM_TS_ITR2:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- case TIM_TS_ITR3:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- default:
- break;
- }
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+
+ /* Enable Trigger Interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_OK;
-}
+}
/**
* @brief Read the captured value from Capture Compare unit
- * @param htim: TIM handle.
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -4119,12 +4215,11 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
__HAL_UNLOCK(htim);
return tmpreg;
}
-
/**
* @}
*/
-/** @defgroup TIM_Group9 TIM Callbacks functions
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
* @brief TIM Callbacks functions
*
@verbatim
@@ -4145,7 +4240,8 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Period elapsed callback in non blocking mode
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
@@ -4157,7 +4253,8 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
}
/**
* @brief Output Compare callback in non blocking mode
- * @param htim : TIM OC handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
@@ -4168,7 +4265,8 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
}
/**
* @brief Input Capture callback in non blocking mode
- * @param htim : TIM IC handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
@@ -4180,7 +4278,8 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
/**
* @brief PWM Pulse finished callback in non blocking mode
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
@@ -4192,7 +4291,8 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
/**
* @brief Hall Trigger detection callback in non blocking mode
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
@@ -4204,7 +4304,8 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
/**
* @brief Timer error callback in non blocking mode
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
@@ -4213,12 +4314,11 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
the HAL_TIM_ErrorCallback could be implemented in the user file
*/
}
-
/**
* @}
*/
-/** @defgroup TIM_Group10 Peripheral State functions
+/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
@@ -4226,7 +4326,7 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
##### Peripheral State functions #####
==============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -4235,7 +4335,8 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
/**
* @brief Return the TIM Base state
- * @param htim: TIM Base handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
@@ -4245,7 +4346,8 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
/**
* @brief Return the TIM OC state
- * @param htim: TIM Ouput Compare handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
@@ -4255,7 +4357,8 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
/**
* @brief Return the TIM PWM state
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
@@ -4265,7 +4368,8 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
/**
* @brief Return the TIM Input Capture state
- * @param htim: TIM IC handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
@@ -4275,7 +4379,8 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
/**
* @brief Return the TIM One Pulse Mode state
- * @param htim: TIM OPM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
@@ -4285,94 +4390,25 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
/**
* @brief Return the TIM Encoder Mode state
- * @param htim: TIM Encoder handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
{
return htim->State;
}
-
/**
* @}
*/
/**
- * @brief TIM DMA error callback
- * @param hdma : pointer to DMA handle.
+ * @brief Time Base configuration
+ * @param TIMx: TIM peripheral
+ * @param Structure: pointer on TIM Time Base required parameters
* @retval None
*/
-void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIM_ErrorCallback(htim);
-}
-
-/**
- * @brief TIM DMA Delay Pulse complete callback.
- * @param hdma : pointer to DMA handle.
- * @retval None
- */
-void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-}
-/**
- * @brief TIM DMA Capture complete callback.
- * @param hdma : pointer to DMA handle.
- * @retval None
- */
-void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIM_IC_CaptureCallback(htim);
-
-}
-
-/**
- * @brief TIM DMA Period Elapse complete callback.
- * @param hdma : pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIM_PeriodElapsedCallback(htim);
-}
-
-/**
- * @brief TIM DMA Trigger callback.
- * @param hdma : pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIM_TriggerCallback(htim);
-}
-
-/**
- * @brief Time Base configuration
- * @param TIMx: TIM periheral
- * @retval None
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
uint32_t tmpcr1 = 0;
tmpcr1 = TIMx->CR1;
@@ -4394,7 +4430,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
TIMx->CR1 = tmpcr1;
- /* Set the Autoreload value */
+ /* Set the Auto-reload value */
TIMx->ARR = (uint32_t)Structure->Period ;
/* Set the Prescaler value */
@@ -4407,26 +4443,79 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
}
/* Generate an update event to reload the Prescaler
- and the repetition counter(only for TIM1 and TIM8) value immediatly */
+ and the repetition counter(only for TIM1 and TIM8) value immediately */
TIMx->EGR = TIM_EGR_UG;
}
/**
- * @brief Time Ouput Compare 1 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config: The ouput configuration structure
+ * @brief Configure the TI1 as Input.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @arg TIM_ICPolarity_BothEdge
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
{
- uint32_t tmpccmrx = 0;
+ uint32_t tmpccmr1 = 0;
uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
-
+
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+ {
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;
+ tmpccmr1 |= TIM_ICSelection;
+ }
+ else
+ {
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;
+ tmpccmr1 |= TIM_CCMR1_CC1S_0;
+ }
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Output Compare 2 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config: The output configuration structure
+ * @retval None
+ */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0;
+ uint32_t tmpccer = 0;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
- /* Get the TIMx CCER register value */
+ /* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@@ -4434,34 +4523,36 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~TIM_CCMR1_OC1M;
- tmpccmrx &= ~TIM_CCMR1_CC1S;
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC2M;
+ tmpccmrx &= ~TIM_CCMR1_CC2S;
+
/* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
+ tmpccmrx |= (OC_Config->OCMode << 8);
/* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC1P;
+ tmpccer &= ~TIM_CCER_CC2P;
/* Set the Output Compare Polarity */
- tmpccer |= OC_Config->OCPolarity;
-
+ tmpccer |= (OC_Config->OCPolarity << 4);
if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
- {
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
/* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC1NP;
+ tmpccer &= ~TIM_CCER_CC2NP;
/* Set the Output N Polarity */
- tmpccer |= OC_Config->OCNPolarity;
+ tmpccer |= (OC_Config->OCNPolarity << 4);
/* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC1NE;
+ tmpccer &= ~TIM_CCER_CC2NE;
/* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS1;
- tmpcr2 &= ~TIM_CR2_OIS1N;
+ tmpcr2 &= ~TIM_CR2_OIS2;
+ tmpcr2 &= ~TIM_CR2_OIS2N;
/* Set the Output Idle state */
- tmpcr2 |= OC_Config->OCIdleState;
+ tmpcr2 |= (OC_Config->OCIdleState << 2);
/* Set the Output N Idle state */
- tmpcr2 |= OC_Config->OCNIdleState;
+ tmpcr2 |= (OC_Config->OCNIdleState << 2);
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
@@ -4469,29 +4560,172 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = OC_Config->Pulse;
+ /* Set the Capture Compare Register value */
+ TIMx->CCR2 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief TIM DMA Delay Pulse complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ if(hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA error callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_ErrorCallback(htim);
+}
+
+/**
+ * @brief TIM DMA Capture complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ if(hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+
+ HAL_TIM_IC_CaptureCallback(htim);
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel: specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @arg TIM_Channel_4: TIM Channel 4
+ * @param ChannelState: specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
+ * @retval None
+ */
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_TIM_CHANNELS(Channel));
+
+ tmp = TIM_CCER_CC1E << Channel;
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelState << Channel);
+}
+
+/**
+ * @brief TIM DMA Period Elapse complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_PeriodElapsedCallback(htim);
+}
+
+/**
+ * @brief TIM DMA Trigger callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
+ HAL_TIM_TriggerCallback(htim);
+}
/**
- * @brief Time Ouput Compare 2 configuration
+ * @brief Time Output Compare 1 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config: The ouput configuration structure
+ * @param OC_Config: The output configuration structure
* @retval None
*/
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
uint32_t tmpccmrx = 0;
uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
- /* Get the TIMx CCER register value */
+ /* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@@ -4499,38 +4733,34 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR1_OC2M;
- tmpccmrx &= ~TIM_CCMR1_CC2S;
-
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC1M;
+ tmpccmrx &= ~TIM_CCMR1_CC1S;
/* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8);
+ tmpccmrx |= OC_Config->OCMode;
/* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC2P;
+ tmpccer &= ~TIM_CCER_CC1P;
/* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 4);
+ tmpccer |= OC_Config->OCPolarity;
+
if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
+ {
/* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC2NP;
+ tmpccer &= ~TIM_CCER_CC1NP;
/* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 4);
+ tmpccer |= OC_Config->OCNPolarity;
/* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC2NE;
+ tmpccer &= ~TIM_CCER_CC1NE;
/* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS2;
- tmpcr2 &= ~TIM_CR2_OIS2N;
+ tmpcr2 &= ~TIM_CR2_OIS1;
+ tmpcr2 &= ~TIM_CR2_OIS1N;
/* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 2);
+ tmpcr2 |= OC_Config->OCIdleState;
/* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 2);
+ tmpcr2 |= OC_Config->OCNIdleState;
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
@@ -4539,16 +4769,16 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIMx->CCMR1 = tmpccmrx;
/* Set the Capture Compare Register value */
- TIMx->CCR2 = OC_Config->Pulse;
+ TIMx->CCR1 = OC_Config->Pulse;
/* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
+ TIMx->CCER = tmpccer;
+}
/**
- * @brief Time Ouput Compare 3 configuration
+ * @brief Time Output Compare 3 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config: The ouput configuration structure
+ * @param OC_Config: The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -4614,9 +4844,9 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
}
/**
- * @brief Time Ouput Compare 4 configuration
+ * @brief Time Output Compare 4 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config: The ouput configuration structure
+ * @param OC_Config: The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -4671,58 +4901,137 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
}
/**
- * @brief Configure the TI1 as Input.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
+ * @brief Time Output Compare 4 configuration
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param sSlaveConfig: The slave configuration structure
* @retval None
*/
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
+static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig)
{
+ uint32_t tmpsmcr = 0;
uint32_t tmpccmr1 = 0;
uint32_t tmpccer = 0;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
- /* Select the Input */
- if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
- {
- tmpccmr1 &= ~TIM_CCMR1_CC1S;
- tmpccmr1 |= TIM_ICSelection;
- }
- else
- {
- tmpccmr1 &= ~TIM_CCMR1_CC1S;
- tmpccmr1 |= TIM_CCMR1_CC1S_0;
- }
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= (TIM_ICFilter << 4);
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= TIM_ICPolarity;
+ /* Reset the Trigger Selection Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source */
+ tmpsmcr |= sSlaveConfig->InputTrigger;
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
+ /* Reset the slave mode Bits */
+ tmpsmcr &= ~TIM_SMCR_SMS;
+ /* Set the slave mode */
+ tmpsmcr |= sSlaveConfig->SlaveMode;
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Configure the trigger prescaler, filter, and polarity */
+ switch (sSlaveConfig->InputTrigger)
+ {
+ case TIM_TS_ETRF:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ /* Configure the ETR Trigger source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sSlaveConfig->TriggerPrescaler,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ }
+ break;
+
+ case TIM_TS_TI1F_ED:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = htim->Instance->CCER;
+ htim->Instance->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ htim->Instance->CCMR1 = tmpccmr1;
+ htim->Instance->CCER = tmpccer;
+
+ }
+ break;
+
+ case TIM_TS_TI1FP1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI1 Filter and Polarity */
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ }
+ break;
+
+ case TIM_TS_TI2FP2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI2 Filter and Polarity */
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ }
+ break;
+
+ case TIM_TS_ITR0:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ case TIM_TS_ITR1:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ case TIM_TS_ITR2:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ case TIM_TS_ITR3:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ default:
+ break;
+ }
}
+
/**
* @brief Configure the Polarity and Filter for TI1.
* @param TIMx to select the TIM peripheral.
@@ -4792,11 +5101,11 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= (TIM_ICFilter << 12);
+ tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (TIM_ICPolarity << 4);
+ tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
@@ -4872,11 +5181,11 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
/* Set the filter */
tmpccmr2 &= ~TIM_CCMR2_IC3F;
- tmpccmr2 |= (TIM_ICFilter << 4);
+ tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
/* Select the Polarity and set the CC3E Bit */
tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
- tmpccer |= (TIM_ICPolarity << 8);
+ tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
/* Write to TIMx CCMR2 and CCER registers */
TIMx->CCMR2 = tmpccmr2;
@@ -4917,11 +5226,11 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
/* Set the filter */
tmpccmr2 &= ~TIM_CCMR2_IC4F;
- tmpccmr2 |= (TIM_ICFilter << 12);
+ tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
/* Select the Polarity and set the CC4E Bit */
tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
- tmpccer |= (TIM_ICPolarity << 12);
+ tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
/* Write to TIMx CCMR2 and CCER registers */
TIMx->CCMR2 = tmpccmr2;
@@ -4931,7 +5240,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
/**
* @brief Selects the Input Trigger source
* @param TIMx to select the TIM peripheral
- * @param InputTriggerSource: The Input Trigger source.
+ * @param TIM_ITRx: The Input Trigger source.
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal Trigger 0
* @arg TIM_TS_ITR1: Internal Trigger 1
@@ -4956,6 +5265,7 @@ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
}
+
/**
* @brief Configures the TIMx External Trigger (ETR).
* @param TIMx to select the TIM peripheral
@@ -4990,37 +5300,6 @@ static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
TIMx->SMCR = tmpsmcr;
}
-/**
- * @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx to select the TIM peripheral
- * @param Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param ChannelState: specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
- * @retval None
- */
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_TIM_CHANNELS(Channel));
-
- tmp = TIM_CCER_CC1E << Channel;
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= ~tmp;
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint32_t)(ChannelState << Channel);
-}
-
-
/**
* @}
*/
diff --git a/f2/src/stm32f2xx_hal_tim_ex.c b/f2/src/stm32f2xx_hal_tim_ex.c
index f584f4c4111c699b836572b86e4cdf3d120fe19c..fe84a16e0eeb242141b055caab4199b535673e8b 100755
--- a/f2/src/stm32f2xx_hal_tim_ex.c
+++ b/f2/src/stm32f2xx_hal_tim_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_tim_ex.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer extension peripheral:
@@ -69,7 +69,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -103,7 +103,7 @@
* @{
*/
-/** @defgroup TIMEx
+/** @defgroup TIMEx TIMEx
* @brief TIM HAL module driver
* @{
*/
@@ -114,15 +114,21 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/** @addtogroup TIMEx_Private_Functions
+ * @{
+ */
/* Private function prototypes -----------------------------------------------*/
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup TIMEx_Private_Functions
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Exported Functions
* @{
*/
-/** @defgroup TIMEx_Group1 Timer Hall Sensor functions
+/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
* @brief Timer Hall Sensor functions
*
@verbatim
@@ -145,7 +151,8 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha
*/
/**
* @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
- * @param htim: TIM Encoder Interface handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sConfig: TIM Hall Sensor configuration structure
* @retval HAL status
*/
@@ -218,7 +225,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
/**
* @brief DeInitializes the TIM Hall Sensor interface
- * @param htim: TIM Hall Sensor handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
@@ -245,7 +253,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Hall Sensor MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
@@ -257,7 +266,8 @@ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes TIM Hall Sensor MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
@@ -269,7 +279,8 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Hall Sensor Interface.
- * @param htim : TIM Hall Sensor handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
@@ -290,7 +301,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
/**
* @brief Stops the TIM Hall sensor Interface.
- * @param htim : TIM Hall Sensor handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
@@ -311,7 +323,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Hall Sensor Interface in interrupt mode.
- * @param htim : TIM Hall Sensor handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
@@ -335,7 +348,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
/**
* @brief Stops the TIM Hall Sensor Interface in interrupt mode.
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
@@ -359,7 +373,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Hall Sensor Interface in DMA mode.
- * @param htim : TIM Hall Sensor handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param pData: The destination Buffer address.
* @param Length: The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
@@ -389,9 +404,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Set the DMA Input Capture 1 Callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream for Capture 1*/
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
@@ -408,7 +423,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
/**
* @brief Stops the TIM Hall Sensor Interface in DMA mode.
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
@@ -430,12 +446,11 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
/* Return function status */
return HAL_OK;
}
-
/**
* @}
*/
-/** @defgroup TIMEx_Group2 Timer Complementary Output Compare functions
+/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
* @brief Timer Complementary Output Compare functions
*
@verbatim
@@ -458,8 +473,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Output Compare signal generation on the complementary
* output.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -475,7 +491,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
+ /* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
@@ -488,8 +504,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the TIM Output Compare signal generation on the complementary
* output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -505,7 +522,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Disable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@@ -518,8 +535,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the TIM Output Compare signal generation in interrupt mode
* on the complementary output.
- * @param htim : TIM OC handle
- * @param Channel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -566,12 +584,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
break;
}
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
@@ -582,8 +603,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
/**
* @brief Stops the TIM Output Compare signal generation in interrupt mode
* on the complementary output.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -629,13 +651,19 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
default:
break;
}
-
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -646,8 +674,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
/**
* @brief Starts the TIM Output Compare signal generation in DMA mode
* on the complementary output.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -682,10 +711,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
@@ -698,10 +727,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
@@ -714,10 +743,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
@@ -730,10 +759,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
@@ -750,7 +779,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
+ /* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
@@ -763,8 +792,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/**
* @brief Stops the TIM Output Compare signal generation in DMA mode
* on the complementary output.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -814,7 +844,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
/* Disable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@@ -826,12 +856,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
/* Return function status */
return HAL_OK;
}
-
/**
* @}
*/
-/** @defgroup TIMEx_Group3 Timer Complementary PWM functions
+/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
* @brief Timer Complementary PWM functions
*
@verbatim
@@ -863,8 +892,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
/**
* @brief Starts the PWM signal generation on the complementary output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -880,7 +910,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
+ /* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
@@ -892,8 +922,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Stops the PWM signal generation on the complementary output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -909,7 +940,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Disable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@@ -922,8 +953,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the PWM signal generation in interrupt mode on the
* complementary output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -976,7 +1008,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
+ /* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
@@ -989,8 +1021,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
/**
* @brief Stops the PWM signal generation in interrupt mode on the
* complementary output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1037,13 +1070,16 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan
break;
}
- /* Disable the TIM Break interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
-
/* Disable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@@ -1056,8 +1092,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan
/**
* @brief Starts the TIM PWM signal generation in DMA mode on the
* complementary output
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1092,10 +1129,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
@@ -1108,10 +1145,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
@@ -1124,10 +1161,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
@@ -1140,10 +1177,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
@@ -1160,7 +1197,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
+ /* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
@@ -1173,8 +1210,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/**
* @brief Stops the TIM PWM signal generation in DMA mode on the complementary
* output
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1224,7 +1262,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Disable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@@ -1241,7 +1279,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
* @}
*/
-/** @defgroup TIMEx_Group4 Timer Complementary One Pulse functions
+/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
* @brief Timer Complementary One Pulse functions
*
@verbatim
@@ -1260,10 +1298,11 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
*/
/**
- * @brief Starts the TIM One Pulse signal generation on the complemetary
+ * @brief Starts the TIM One Pulse signal generation on the complementary
* output.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1277,7 +1316,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou
/* Enable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
+ /* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Return function status */
@@ -1287,8 +1326,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou
/**
* @brief Stops the TIM One Pulse signal generation on the complementary
* output.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1303,7 +1343,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
/* Disable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@@ -1316,8 +1356,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1337,7 +1378,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
/* Enable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
+ /* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Return function status */
@@ -1347,8 +1388,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1368,7 +1410,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
/* Disable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@@ -1377,11 +1419,11 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
/* Return function status */
return HAL_OK;
}
-
/**
* @}
*/
-/** @defgroup TIMEx_Group5 Peripheral Control functions
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
@@ -1402,21 +1444,22 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
*/
/**
* @brief Configure the TIM commutation event sequence.
- * @note: this function is mandatory to use the commutation event in order to
+ * @note This function is mandatory to use the commutation event in order to
* update the configuration at each commutation detection on the TRGI input of the Timer,
* the typical use of this feature is with the use of another Timer(interface Timer)
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim: TIM handle
- * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource : the Commutation Event source
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource: the Commutation Event source.
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
@@ -1451,21 +1494,22 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint
/**
* @brief Configure the TIM commutation event sequence with interrupt.
- * @note: this function is mandatory to use the commutation event in order to
+ * @note This function is mandatory to use the commutation event in order to
* update the configuration at each commutation detection on the TRGI input of the Timer,
* the typical use of this feature is with the use of another Timer(interface Timer)
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim: TIM handle
- * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource : the Commutation Event source
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource: the Commutation Event source.
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
@@ -1503,22 +1547,23 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u
/**
* @brief Configure the TIM commutation event sequence with DMA.
- * @note: this function is mandatory to use the commutation event in order to
+ * @note This function is mandatory to use the commutation event in order to
* update the configuration at each commutation detection on the TRGI input of the Timer,
* the typical use of this feature is with the use of another Timer(interface Timer)
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
* @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
- * @param htim: TIM handle
- * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource : the Commutation Event source
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource: the Commutation Event source.
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
@@ -1548,9 +1593,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim,
/* Enable the Commutation DMA Request */
/* Set the DMA Commutation Callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
/* Enable the Commutation DMA Request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
@@ -1562,7 +1607,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim,
/**
* @brief Configures the TIM in master mode.
- * @param htim: TIM handle.
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
* contains the selected trigger output (TRGO) and the Master/Slave
* mode.
@@ -1599,7 +1645,8 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
/**
* @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
* and the AOE(automatic output enable).
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
* contains the BDTR Register configuration information for the TIM peripheral.
* @retval HAL status
@@ -1615,6 +1662,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+ assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
/* Process Locked */
__HAL_LOCK(htim);
@@ -1641,11 +1689,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
/**
* @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
- * @param htim: TIM handle.
- * @param TIM_Remap: specifies the TIM input remapping source.
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Remap: specifies the TIM input remapping source.
* This parameter can be one of the following values:
* @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
- * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output.
+ * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.
* @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
* @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
* @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
@@ -1674,12 +1723,11 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
return HAL_OK;
}
-
/**
* @}
*/
-/** @defgroup TIMEx_Group6 Extension Callbacks functions
+/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
* @brief Extension Callbacks functions
*
@verbatim
@@ -1697,7 +1745,8 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
/**
* @brief Hall commutation changed callback in non blocking mode
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
@@ -1709,7 +1758,8 @@ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
/**
* @brief Hall Break detection callback in non blocking mode
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
@@ -1718,12 +1768,11 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
-
/**
* @}
*/
-/** @defgroup TIMEx_Group7 Extension Peripheral State functions
+/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
* @brief Extension Peripheral State functions
*
@verbatim
@@ -1731,7 +1780,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
##### Extension Peripheral State functions #####
==============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -1740,7 +1789,8 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
/**
* @brief Return the TIM Hall Sensor interface state
- * @param htim: TIM Hall Sensor handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
@@ -1754,10 +1804,11 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
/**
* @brief TIM DMA Commutation callback.
- * @param hdma : pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
-void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
@@ -1765,7 +1816,10 @@ void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
HAL_TIMEx_CommutationCallback(htim);
}
-
+/**
+ * @}
+ */
+
/**
* @brief Enables or disables the TIM Capture Compare Channel xN.
* @param TIMx to select the TIM peripheral
diff --git a/f2/src/stm32f2xx_hal_uart.c b/f2/src/stm32f2xx_hal_uart.c
index 86ff94b8be4ac443551110b30d5892fe39eedda0..330a9dd0736742efa3a2933fc4d650e4eb8402aa 100755
--- a/f2/src/stm32f2xx_hal_uart.c
+++ b/f2/src/stm32f2xx_hal_uart.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_uart.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
@@ -21,7 +21,7 @@
(#) Declare a UART_HandleTypeDef handle structure.
- (#) Initialize the UART low level resources by implement the HAL_UART_MspInit() API:
+ (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
(##) Enable the USARTx interface clock.
(##) UART pins configuration:
(+++) Enable the clock for the UART GPIOs.
@@ -42,7 +42,7 @@
interrupt on the DMA Tx/Rx Stream.
(#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
- flow control and Mode(Receiver/Transmitter) in the huart Init structure.
+ flow control and Mode(Receiver/Transmitter) in the Init structure.
(#) For the UART asynchronous mode, initialize the UART registers by calling
the HAL_UART_Init() API.
@@ -55,16 +55,19 @@
(#) For the Multi-Processor mode, initialize the UART registers by calling
the HAL_MultiProcessor_Init() API.
- -@- The specific UART interrupts (Transmission complete interrupt,
+ [..]
+ (@) The specific UART interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
and receive process.
- -@- These API's(HAL_UART_Init() and HAL_HalfDuplex_Init()) configures also the
- low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customed
+ [..]
+ (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
+ low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
HAL_UART_MspInit() API.
- (#) Three mode of operations are available within this driver :
+ [..]
+ Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -76,15 +79,11 @@
===================================
[..]
(+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
- (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
(+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_UART_TxCpltCallback
(+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
- (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
(+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_RxCpltCallback
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback
(+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_UART_ErrorCallback
@@ -100,7 +99,7 @@
(+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
(+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_RxCpltCallback
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback
(+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_UART_ErrorCallback
(+) Pause the DMA Transfer using HAL_UART_DMAPause()
@@ -114,10 +113,11 @@
(+) __HAL_UART_ENABLE: Enable the UART peripheral
(+) __HAL_UART_DISABLE: Disable the UART peripheral
- (+) __HAL_UART_GET_FLAG : Checks whether the specified UART flag is set or not
- (+) __HAL_UART_CLEAR_FLAG : Clears the specified UART pending flag
- (+) __HAL_UART_ENABLE_IT: Enables the specified UART interrupt
- (+) __HAL_UART_DISABLE_IT: Disables the specified UART interrupt
+ (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
+ (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
+ (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
+ (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
+ (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not
[..]
(@) You can refer to the UART HAL driver header file for more useful macros
@@ -126,7 +126,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -160,7 +160,7 @@
* @{
*/
-/** @defgroup UART
+/** @defgroup UART UART
* @brief HAL UART module driver
* @{
*/
@@ -168,12 +168,22 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup UART_Private_Constants
+ * @{
+ */
#define UART_TIMEOUT_VALUE 22000
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions UART Private Functions
+ * @{
+ */
static void UART_SetConfig (UART_HandleTypeDef *huart);
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
@@ -181,14 +191,16 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAError(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+/**
+ * @}
+ */
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup UART_Private_Functions
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup UART_Exported_Functions UART Exported Functions
* @{
*/
-/** @defgroup UART_Group1 Initialization and de-initialization functions
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -205,21 +217,10 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,
(++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible UART frame formats are as listed in the following table:
- +-------------------------------------------------------------+
- | M bit | PCE bit | UART frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
+ please refer to Reference manual for possible UART frame formats.
(++) Hardware flow control
(++) Receiver/transmitter modes
- (++) Over Sampling Methode
+ (++) Over Sampling Method
[..]
The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
@@ -232,7 +233,8 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,
/**
* @brief Initializes the UART mode according to the specified parameters in
* the UART_InitTypeDef and create the associated handle.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
@@ -242,20 +244,25 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
return HAL_ERROR;
}
-
+
+ /* Check the parameters */
if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
- {
- /* Check the parameters */
+ {
+ /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+ assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
}
else
{
- /* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
}
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
if(huart->State == HAL_UART_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
@@ -287,7 +294,8 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
/**
* @brief Initializes the half-duplex mode according to the specified
* parameters in the UART_InitTypeDef and create the associated handle.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
@@ -297,9 +305,16 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
{
return HAL_ERROR;
}
-
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
if(huart->State == HAL_UART_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
@@ -334,7 +349,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
/**
* @brief Initializes the LIN mode according to the specified
* parameters in the UART_InitTypeDef and create the associated handle.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @param BreakDetectLength: Specifies the LIN break detection length.
* This parameter can be one of the following values:
* @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
@@ -348,11 +364,17 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
{
return HAL_ERROR;
}
- /* Check the Break detection length parameter */
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
-
+ assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));
+
if(huart->State == HAL_UART_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
@@ -391,15 +413,16 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
/**
* @brief Initializes the Multi-Processor mode according to the specified
* parameters in the UART_InitTypeDef and create the associated handle.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @param Address: USART address
- * @param WakeUpMethode: specifies the USART wakeup method.
+ * @param WakeUpMethod: specifies the USART wake-up method.
* This parameter can be one of the following values:
- * @arg UART_WAKEUPMETHODE_IDLELINE: Wakeup by an idle line detection
- * @arg UART_WAKEUPMETHODE_ADDRESSMARK: Wakeup by an address mark
+ * @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection
+ * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethode)
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
{
/* Check the UART handle allocation */
if(huart == NULL)
@@ -407,12 +430,17 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
return HAL_ERROR;
}
- /* Check the Address & wake up method parameters */
- assert_param(IS_UART_WAKEUPMETHODE(WakeUpMethode));
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
assert_param(IS_UART_ADDRESS(Address));
-
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
if(huart->State == HAL_UART_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
@@ -436,9 +464,9 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
/* Set the USART address node */
huart->Instance->CR2 |= Address;
- /* Set the wake up methode by setting the WAKE bit in the CR1 register */
+ /* Set the wake up method by setting the WAKE bit in the CR1 register */
huart->Instance->CR1 &= ~(USART_CR1_WAKE);
- huart->Instance->CR1 |= WakeUpMethode;
+ huart->Instance->CR1 |= WakeUpMethod;
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
@@ -452,7 +480,8 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
/**
* @brief DeInitializes the UART peripheral.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
@@ -482,7 +511,8 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
/**
* @brief UART MSP Init.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
@@ -494,7 +524,8 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
/**
* @brief UART MSP DeInit.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
@@ -508,7 +539,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
* @}
*/
-/** @defgroup UART_Group2 IO operation functions
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
* @brief UART Transmit and Receive functions
*
@verbatim
@@ -523,30 +554,30 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
(++) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
- (++) Non-Blocking mode: The communication is performed using Interrupts
+ (++) Non blocking mode: The communication is performed using Interrupts
or DMA, these APIs return the HAL status.
The end of the data processing will be indicated through the
dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
- will be executed respectivelly at the end of the transmit or receive process.
+ will be executed respectively at the end of the transmit or receive process.
The HAL_UART_ErrorCallback() user callback will be executed when
a communication error is detected.
- (#) Blocking mode API's are:
+ (#) Blocking mode APIs are:
(++) HAL_UART_Transmit()
(++) HAL_UART_Receive()
- (#) Non-Blocking mode API's with Interrupt are:
+ (#) Non Blocking mode APIs with Interrupt are:
(++) HAL_UART_Transmit_IT()
(++) HAL_UART_Receive_IT()
(++) HAL_UART_IRQHandler()
- (#) No-Blocking mode functions with DMA are:
+ (#) Non Blocking mode functions with DMA are:
(++) HAL_UART_Transmit_DMA()
(++) HAL_UART_Receive_DMA()
- (#) A set of Transfer Complete Callbacks are provided in Non-Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in non blocking mode:
(++) HAL_UART_TxCpltCallback()
(++) HAL_UART_RxCpltCallback()
(++) HAL_UART_ErrorCallback()
@@ -562,7 +593,8 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
/**
* @brief Sends an amount of data in blocking mode.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @param Timeout: Timeout duration
@@ -655,7 +687,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
/**
* @brief Receives an amount of data in blocking mode.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be received
* @param Timeout: Timeout duration
@@ -754,7 +787,8 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
/**
* @brief Sends an amount of data in non blocking mode.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -798,8 +832,8 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
/* Process Unlocked */
__HAL_UNLOCK(huart);
- /* Enable the UART Transmit Complete Interrupt */
- __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+ /* Enable the UART Transmit data register empty Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
return HAL_OK;
}
@@ -811,7 +845,8 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
/**
* @brief Receives an amount of data in non blocking mode
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be received
* @retval HAL status
@@ -868,7 +903,8 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
/**
* @brief Sends an amount of data in non blocking mode.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -917,6 +953,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size);
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
+
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
huart->Instance->CR3 |= USART_CR3_DMAT;
@@ -934,7 +973,8 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
/**
* @brief Receives an amount of data in non blocking mode.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be received
* @note When the UART parity is enabled (PCE = 1) the data received contain the parity bit.
@@ -1000,8 +1040,9 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
/**
* @brief Pauses the DMA Transfer.
- * @param huart: UART handle
- * @retval None
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
{
@@ -1033,8 +1074,9 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
/**
* @brief Resumes the DMA Transfer.
- * @param huart: UART handle
- * @retval None
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
{
@@ -1048,22 +1090,19 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
}
else if(huart->State == HAL_UART_STATE_BUSY_RX)
{
+ /* Clear the Overrun flag before resuming the Rx transfer*/
+ __HAL_UART_CLEAR_OREFLAG(huart);
/* Enable the UART DMA Rx request */
huart->Instance->CR3 |= USART_CR3_DMAR;
}
else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
{
+ /* Clear the Overrun flag before resuming the Rx transfer*/
+ __HAL_UART_CLEAR_OREFLAG(huart);
/* Enable the UART DMA Tx & Rx request */
huart->Instance->CR3 |= USART_CR3_DMAT;
huart->Instance->CR3 |= USART_CR3_DMAR;
}
-
- /* If the UART peripheral is still not enabled, enable it */
- if ((huart->Instance->CR1 & USART_CR1_UE) == 0)
- {
- /* Enable UART peripheral */
- __HAL_UART_ENABLE(huart);
- }
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -1073,13 +1112,17 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
/**
* @brief Stops the DMA Transfer.
- * @param huart: UART handle
- * @retval None
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
{
- /* Process Locked */
- __HAL_LOCK(huart);
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
+ */
/* Disable the UART Tx/Rx DMA requests */
huart->Instance->CR3 &= ~USART_CR3_DMAT;
@@ -1095,20 +1138,16 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
{
HAL_DMA_Abort(huart->hdmarx);
}
- /* Disable UART peripheral */
- __HAL_UART_DISABLE(huart);
huart->State = HAL_UART_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
/**
* @brief This function handles UART interrupt request.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
@@ -1120,7 +1159,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
/* UART parity error interrupt occurred ------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
- __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_PE);
+ __HAL_UART_CLEAR_PEFLAG(huart);
huart->ErrorCode |= HAL_UART_ERROR_PE;
}
@@ -1130,7 +1169,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
/* UART frame error interrupt occurred -------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
- __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_FE);
+ __HAL_UART_CLEAR_FEFLAG(huart);
huart->ErrorCode |= HAL_UART_ERROR_FE;
}
@@ -1140,7 +1179,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
/* UART noise error interrupt occurred -------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
- __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_NE);
+ __HAL_UART_CLEAR_NEFLAG(huart);
huart->ErrorCode |= HAL_UART_ERROR_NE;
}
@@ -1150,7 +1189,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
/* UART Over-Run interrupt occurred ----------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
- __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_ORE);
+ __HAL_UART_CLEAR_OREFLAG(huart);
huart->ErrorCode |= HAL_UART_ERROR_ORE;
}
@@ -1161,18 +1200,24 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
if((tmp1 != RESET) && (tmp2 != RESET))
{
UART_Receive_IT(huart);
- __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
}
- tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TC);
- tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC);
+ tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TXE);
+ tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE);
/* UART in mode Transmitter ------------------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
UART_Transmit_IT(huart);
- __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
}
+ tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TC);
+ tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC);
+ /* UART in mode Transmitter end --------------------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ UART_EndTransmit_IT(huart);
+ }
+
if(huart->ErrorCode != HAL_UART_ERROR_NONE)
{
/* Set the UART state ready to be able to start again the process */
@@ -1184,7 +1229,8 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
/**
* @brief Tx Transfer completed callbacks.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
@@ -1196,7 +1242,8 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
/**
* @brief Tx Half Transfer completed callbacks.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
@@ -1208,7 +1255,8 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
/**
* @brief Rx Transfer completed callbacks.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
@@ -1220,7 +1268,8 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
/**
* @brief Rx Half Transfer completed callbacks.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
@@ -1232,7 +1281,8 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
/**
* @brief UART error callbacks.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
@@ -1246,7 +1296,7 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
* @}
*/
-/** @defgroup UART_Group3 Peripheral Control functions
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
* @brief UART control functions
*
@verbatim
@@ -1265,7 +1315,8 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
/**
* @brief Transmits break characters.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
@@ -1291,7 +1342,8 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
/**
* @brief Enters the UART in mute mode.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
@@ -1317,7 +1369,8 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
/**
* @brief Exits the UART mute mode: wake up software.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
@@ -1343,9 +1396,9 @@ HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
/**
* @brief Enables the UART transmitter and disables the UART receiver.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
- * @retval None
*/
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
{
@@ -1378,7 +1431,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
/**
* @brief Enables the UART receiver and disables the UART transmitter.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
@@ -1414,7 +1468,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
* @}
*/
-/** @defgroup UART_Group4 Peripheral State and Errors functions
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
* @brief UART State and Errors functions
*
@verbatim
@@ -1423,10 +1477,10 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
==============================================================================
[..]
This subsection provides a set of functions allowing to return the State of
- UART communication process, return Peripheral Errors occured during communication
+ UART communication process, return Peripheral Errors occurred during communication
process
(+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.
- (+) HAL_UART_GetError() check in run-time errors that could be occured durung communication.
+ (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication.
@endverbatim
* @{
@@ -1434,7 +1488,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
/**
* @brief Returns the UART state.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL state
*/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
@@ -1462,41 +1517,32 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
* @param hdma: DMA handle
* @retval None
*/
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- huart->TxXferCount = 0;
-
- /* Disable the DMA transfer for transmit request by setting the DMAT bit
- in the UART CR3 register */
- huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
-
- /* Wait for UART TC Flag */
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, UART_TIMEOUT_VALUE) != HAL_OK)
+ /* DMA Normal mode*/
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
{
- /* Timeout Occured */
- huart->State = HAL_UART_STATE_TIMEOUT;
- HAL_UART_ErrorCallback(huart);
+ huart->TxXferCount = 0;
+
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit
+ in the UART CR3 register */
+ huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
}
+ /* DMA Circular mode */
else
{
- /* No Timeout */
- /* Check if a receive process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_RX;
- }
- else
- {
- huart->State = HAL_UART_STATE_READY;
- }
HAL_UART_TxCpltCallback(huart);
}
}
/**
* @brief DMA UART transmit process half complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -1514,27 +1560,32 @@ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- huart->RxXferCount = 0;
+ /* DMA Normal mode*/
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ {
+ huart->RxXferCount = 0;
- /* Disable the DMA transfer for the receiver request by setting the DMAR bit
- in the UART CR3 register */
- huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
+ /* Disable the DMA transfer for the receiver request by setting the DMAR bit
+ in the UART CR3 register */
+ huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
- /* Check if a transmit process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX;
- }
- else
- {
- huart->State = HAL_UART_STATE_READY;
+ /* Check if a transmit process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_READY;
+ }
}
HAL_UART_RxCpltCallback(huart);
}
/**
* @brief DMA UART receive process half complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -1561,7 +1612,8 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma)
/**
* @brief This function handles UART Communication Timeout.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @param Flag: specifies the UART flag to check.
* @param Status: The new Flag status (SET or RESET).
* @param Timeout: Timeout duration
@@ -1569,10 +1621,11 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma)
*/
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
{
- uint32_t timeout = 0;
-
- timeout = HAL_GetTick() + Timeout;
-
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait until flag is set */
if(Status == RESET)
{
@@ -1581,7 +1634,7 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
@@ -1606,7 +1659,7 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
@@ -1624,12 +1677,13 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,
}
}
}
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Sends an amount of data in non blocking mode.
- * @param huart: UART handle
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
@@ -1640,9 +1694,6 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
tmp1 = huart->State;
if((tmp1 == HAL_UART_STATE_BUSY_TX) || (tmp1 == HAL_UART_STATE_BUSY_TX_RX))
{
- /* Process Locked */
- __HAL_LOCK(huart);
-
if(huart->Init.WordLength == UART_WORDLENGTH_9B)
{
tmp = (uint16_t*) huart->pTxBuffPtr;
@@ -1664,45 +1715,56 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
if(--huart->TxXferCount == 0)
{
/* Disable the UART Transmit Complete Interrupt */
- __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
-
- /* Check if a receive process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_RX;
- }
- else
- {
- /* Disable the UART Parity Error Interrupt */
- __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
- huart->State = HAL_UART_STATE_READY;
- }
- /* Call the Process Unlocked before calling the Tx callback API to give the possibility to
- start again the Transmission under the Tx callback API */
- __HAL_UNLOCK(huart);
-
- HAL_UART_TxCpltCallback(huart);
-
- return HAL_OK;
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
}
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- return HAL_OK;
+/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable the UART Transmit Complete Interrupt */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+
+ /* Check if a receive process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_RX;
}
else
{
- return HAL_BUSY;
+ /* Disable the UART Parity Error Interrupt */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+
+ huart->State = HAL_UART_STATE_READY;
}
+
+ HAL_UART_TxCpltCallback(huart);
+
+ return HAL_OK;
}
+
/**
* @brief Receives an amount of data in non blocking mode
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
@@ -1713,9 +1775,6 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
tmp1 = huart->State;
if((tmp1 == HAL_UART_STATE_BUSY_RX) || (tmp1 == HAL_UART_STATE_BUSY_TX_RX))
{
- /* Process Locked */
- __HAL_LOCK(huart);
-
if(huart->Init.WordLength == UART_WORDLENGTH_9B)
{
tmp = (uint16_t*) huart->pRxBuffPtr;
@@ -1741,14 +1800,11 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
*huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
}
}
-
+
if(--huart->RxXferCount == 0)
{
- while(HAL_IS_BIT_SET(huart->Instance->SR, UART_FLAG_RXNE))
- {
- }
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
-
+
/* Check if a transmit process is ongoing or not */
if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
{
@@ -1758,23 +1814,16 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
{
/* Disable the UART Parity Error Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
-
+
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
+
huart->State = HAL_UART_STATE_READY;
}
- /* Call the Process Unlocked before calling the Rx callback API to give the possibility to
- start again the reception under the Rx callback API */
- __HAL_UNLOCK(huart);
-
HAL_UART_RxCpltCallback(huart);
-
+
return HAL_OK;
}
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
else
@@ -1785,7 +1834,8 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
/**
* @brief Configures the UART peripheral.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
@@ -1793,19 +1843,10 @@ static void UART_SetConfig(UART_HandleTypeDef *huart)
uint32_t tmpreg = 0x00;
/* Check the parameters */
- assert_param(IS_UART_INSTANCE(huart->Instance));
assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
- assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
assert_param(IS_UART_PARITY(huart->Init.Parity));
assert_param(IS_UART_MODE(huart->Init.Mode));
- assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
-
- /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
- if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
- {
- assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
- }
/*-------------------------- USART CR2 Configuration -----------------------*/
tmpreg = huart->Instance->CR2;
@@ -1854,11 +1895,11 @@ static void UART_SetConfig(UART_HandleTypeDef *huart)
/*-------------------------- USART BRR Configuration ---------------------*/
if((huart->Instance == USART1) || (huart->Instance == USART6))
{
- huart->Instance->BRR = __UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
+ huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
}
else
{
- huart->Instance->BRR = __UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
+ huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
}
}
else
@@ -1866,11 +1907,11 @@ static void UART_SetConfig(UART_HandleTypeDef *huart)
/*-------------------------- USART BRR Configuration ---------------------*/
if((huart->Instance == USART1) || (huart->Instance == USART6))
{
- huart->Instance->BRR = __UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
+ huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
}
else
{
- huart->Instance->BRR = __UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
+ huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
}
}
}
diff --git a/f2/src/stm32f2xx_hal_usart.c b/f2/src/stm32f2xx_hal_usart.c
index acad15850b3ac6a23184330cdcd705d023840bee..52c18d7c340fcc773156296f75fb199d3e40c394 100755
--- a/f2/src/stm32f2xx_hal_usart.c
+++ b/f2/src/stm32f2xx_hal_usart.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_usart.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief USART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
@@ -18,7 +18,7 @@
The USART HAL driver can be used as follows:
(#) Declare a USART_HandleTypeDef handle structure.
- (#) Initialize the USART low level resources by implement the HAL_USART_MspInit ()API:
+ (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit () API:
(##) Enable the USARTx interface clock.
(##) USART pins configuration:
(+++) Enable the clock for the USART GPIOs.
@@ -33,21 +33,21 @@
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx Stream.
- (+++) Associate the initilalized DMA handle to the USART DMA Tx/Rx handle.
+ (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
(#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
flow control and Mode(Receiver/Transmitter) in the husart Init structure.
(#) Initialize the USART registers by calling the HAL_USART_Init() API:
- (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_USART_MspInit(&husart) API.
+ (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_USART_MspInit(&husart) API.
-@@- The specific USART interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
- __USART_ENABLE_IT() and __USART_DISABLE_IT() inside the transmit and receive process.
+ __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
- (#) Three mode of operations are available within this driver :
+ (#) Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -59,15 +59,11 @@
===================================
[..]
(+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
- (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
+ (+) At transmission end of transfer HAL_USART_TxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_USART_TxCpltCallback
(+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
- (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
(+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxCpltCallback
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback
(+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_USART_ErrorCallback
@@ -97,10 +93,10 @@
(+) __HAL_USART_ENABLE: Enable the USART peripheral
(+) __HAL_USART_DISABLE: Disable the USART peripheral
- (+) __HAL_USART_GET_FLAG : Checks whether the specified USART flag is set or not
- (+) __HAL_USART_CLEAR_FLAG : Clears the specified USART pending flag
- (+) __HAL_USART_ENABLE_IT: Enables the specified USART interrupt
- (+) __HAL_USART_DISABLE_IT: Disables the specified USART interrupt
+ (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
+ (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
+ (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
+ (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
[..]
(@) You can refer to the USART HAL driver header file for more useful macros
@@ -109,7 +105,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -143,19 +139,30 @@
* @{
*/
-/** @defgroup USART
+/** @defgroup USART USART
* @brief HAL USART Synchronous module driver
* @{
*/
#ifdef HAL_USART_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-#define DUMMY_DATA 0xFFFF
+/** @addtogroup USART_Private_Constants
+ * @{
+ */
+#define DUMMY_DATA 0xFFFF
#define USART_TIMEOUT_VALUE 22000
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup USART_Private_Functions
+ * @{
+ */
static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
static void USART_SetConfig (USART_HandleTypeDef *husart);
@@ -165,14 +172,16 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void USART_DMAError(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-/* Private functions ---------------------------------------------------------*/
-
+/**
+ * @}
+ */
-/** @defgroup USART_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup USART_Exported_Functions USART Exported Functions
* @{
*/
-/** @defgroup USART_Group1 USART Initialization and de-initialization functions
+/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -189,18 +198,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar
(++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible USART frame formats are as listed in the following table:
- +-------------------------------------------------------------+
- | M bit | PCE bit | USART frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
+ please refer to Reference manual for possible USART frame formats.
(++) USART polarity
(++) USART phase
(++) USART LastBit
@@ -217,7 +215,8 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar
/**
* @brief Initializes the USART mode according to the specified
* parameters in the USART_InitTypeDef and create the associated handle.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
@@ -233,6 +232,8 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
if(husart->State == HAL_USART_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ husart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_USART_MspInit(husart);
}
@@ -249,7 +250,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
husart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL);
/* Enable the Peripheral */
- __USART_ENABLE(husart);
+ __HAL_USART_ENABLE(husart);
/* Initialize the USART state */
husart->ErrorCode = HAL_USART_ERROR_NONE;
@@ -260,7 +261,8 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
/**
* @brief DeInitializes the USART peripheral.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
@@ -276,6 +278,9 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
husart->State = HAL_USART_STATE_BUSY;
+ /* Disable the Peripheral */
+ __HAL_USART_DISABLE(husart);
+
/* DeInit the low level hardware */
HAL_USART_MspDeInit(husart);
@@ -290,25 +295,27 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
/**
* @brief USART MSP Init.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
{
/* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_USART_MspInit could be implenetd in the user file
+ the HAL_USART_MspInit could be implemented in the user file
*/
}
/**
* @brief USART MSP DeInit.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
{
/* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_USART_MspDeInit could be implenetd in the user file
+ the HAL_USART_MspDeInit could be implemented in the user file
*/
}
@@ -316,7 +323,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
* @}
*/
-/** @defgroup USART_Group2 IO operation functions
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions
* @brief USART Transmit and Receive functions
*
@verbatim
@@ -331,7 +338,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
The USART supports master mode only: it cannot receive or send data related to an input
clock (SCLK is always an output).
- (#) There are two mode of transfer:
+ (#) There are two modes of transfer:
(++) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
@@ -341,42 +348,49 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback()
- user callbacks
- will be executed respectivelly at the end of the transmit or Receive process
- The HAL_USART_ErrorCallback()user callback will be executed when a communication
+ user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_USART_ErrorCallback() user callback will be executed when a communication
error is detected
- (#) Blocking mode API's are :
- (++) HAL_USART_Transmit()in simplex mode
+ (#) Blocking mode APIs are :
+ (++) HAL_USART_Transmit() in simplex mode
(++) HAL_USART_Receive() in full duplex receive only
(++) HAL_USART_TransmitReceive() in full duplex mode
- (#) Non-Blocking mode API's with Interrupt are :
+ (#) Non Blocking mode APIs with Interrupt are :
(++) HAL_USART_Transmit_IT()in simplex mode
(++) HAL_USART_Receive_IT() in full duplex receive only
- (++) HAL_USART_TransmitReceive_IT()in full duplex mode
+ (++) HAL_USART_TransmitReceive_IT() in full duplex mode
(++) HAL_USART_IRQHandler()
- (#) No-Blocking mode functions with DMA are :
+ (#) Non Blocking mode functions with DMA are :
(++) HAL_USART_Transmit_DMA()in simplex mode
(++) HAL_USART_Receive_DMA() in full duplex receive only
(++) HAL_USART_TransmitReceie_DMA() in full duplex mode
-
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (++) HAL_USART_DMAPause()
+ (++) HAL_USART_DMAResume()
+ (++) HAL_USART_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_USART_TxHalfCpltCallback()
(++) HAL_USART_TxCpltCallback()
+ (++) HAL_USART_RxHalfCpltCallback()
(++) HAL_USART_RxCpltCallback()
(++) HAL_USART_ErrorCallback()
(++) HAL_USART_TxRxCpltCallback()
-
+
@endverbatim
* @{
*/
/**
* @brief Simplex Send an amount of data in blocking mode.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @param pTxData: Pointer to data buffer
* @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
@@ -404,7 +418,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
if(husart->Init.WordLength == USART_WORDLENGTH_9B)
{
/* Wait for TC flag in order to write data in DR */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -449,9 +463,11 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
/**
* @brief Full-Duplex Receive an amount of data in blocking mode.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @param pRxData: Pointer to data buffer
* @param Size: Amount of data to be received
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
@@ -478,8 +494,8 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
husart->RxXferCount--;
if(husart->Init.WordLength == USART_WORDLENGTH_9B)
{
- /* Wait until TC flag is set to send dummy byte in order to generate the clock for the slave to send data */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -505,8 +521,8 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
}
else
{
- /* Wait until TC flag is set to send dummy byte in order to generate the clock for the slave to send data */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -548,9 +564,12 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
/**
* @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
- * @param husart: USART handle
- * @param pTxData: Pointer to data buffer
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData: Pointer to data transmitted buffer
+ * @param pRxData: Pointer to data received buffer
* @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
@@ -582,7 +601,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
if(husart->Init.WordLength == USART_WORDLENGTH_9B)
{
/* Wait for TC flag in order to write data in DR */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -617,7 +636,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
else
{
/* Wait for TC flag in order to write data in DR */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -656,7 +675,8 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
/**
* @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @param pTxData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -686,14 +706,14 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
when the USART mode is configured for transmit and receive "USART_MODE_TX_RX"
to benefit for the frame error and noise interrupts the USART mode should be
configured only for transmit "USART_MODE_TX"
- The __USART_ENABLE_IT(husart, USART_IT_ERR) can be used to enable the Frame error,
+ The __HAL_USART_ENABLE_IT(husart, USART_IT_ERR) can be used to enable the Frame error,
Noise error interrupt */
/* Process Unlocked */
__HAL_UNLOCK(husart);
- /* Enable the USART Transmit Complete Interrupt */
- __USART_ENABLE_IT(husart, USART_IT_TC);
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
return HAL_OK;
}
@@ -705,7 +725,8 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
/**
* @brief Simplex Receive an amount of data in non-blocking mode.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @param pRxData: Pointer to data buffer
* @param Size: Amount of data to be received
* @retval HAL status
@@ -728,17 +749,17 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
/* Enable the USART Data Register not empty Interrupt */
- __USART_ENABLE_IT(husart, USART_IT_RXNE);
+ __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
/* Enable the USART Parity Error Interrupt */
- __USART_ENABLE_IT(husart, USART_IT_PE);
+ __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __USART_ENABLE_IT(husart, USART_IT_ERR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
/* Send dummy byte in order to generate the clock for the slave to send data */
husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
@@ -753,8 +774,10 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
/**
* @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
- * @param husart: USART handle
- * @param pTxData: Pointer to data buffer
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData: Pointer to data transmitted buffer
+ * @param pRxData: Pointer to data received buffer
* @param Size: Amount of data to be received
* @retval HAL status
*/
@@ -779,20 +802,20 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX_RX;
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
/* Enable the USART Data Register not empty Interrupt */
- __USART_ENABLE_IT(husart, USART_IT_RXNE);
+ __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
/* Enable the USART Parity Error Interrupt */
- __USART_ENABLE_IT(husart, USART_IT_PE);
+ __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __USART_ENABLE_IT(husart, USART_IT_ERR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
- /* Enable the USART Transmit Complete Interrupt */
- __USART_ENABLE_IT(husart, USART_IT_TC);
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
return HAL_OK;
}
@@ -804,8 +827,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
/**
* @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart: USART handle
- * @param pData: Pointer to data buffer
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
*/
@@ -842,6 +866,9 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
tmp = (uint32_t*)&pTxData;
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
+
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
husart->Instance->CR3 |= USART_CR3_DMAT;
@@ -859,7 +886,8 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
/**
* @brief Full-Duplex Receive an amount of data in non-blocking mode.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @param pRxData: Pointer to data buffer
* @param Size: Amount of data to be received
* @retval HAL status
@@ -906,6 +934,10 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
this mode isn't a simplex receive mode but a full-duplex receive one */
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
+ /* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer
+ when using the USART in circular mode */
+ __HAL_USART_CLEAR_OREFLAG(husart);
+
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the USART CR3 register */
husart->Instance->CR3 |= USART_CR3_DMAR;
@@ -927,8 +959,10 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
/**
* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
- * @param husart: USART handle
- * @param pRxData: Pointer to data buffer
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData: Pointer to data transmitted buffer
+ * @param pRxData: Pointer to data received buffer
* @param Size: Amount of data to be received
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
* @retval HAL status
@@ -979,7 +1013,13 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
/* Enable the USART transmit DMA Stream */
tmp = (uint32_t*)&pTxData;
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
-
+
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
+
+ /* Clear the Overrun flag: mandatory for the second transfer in circular mode */
+ __HAL_USART_CLEAR_OREFLAG(husart);
+
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the USART CR3 register */
husart->Instance->CR3 |= USART_CR3_DMAR;
@@ -1001,92 +1041,57 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
/**
* @brief Pauses the DMA Transfer.
- * @param husart: USART handle
- * @retval None
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
{
/* Process Locked */
__HAL_LOCK(husart);
-
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
- /* Disable the USART DMA Tx request */
- husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
- }
- else if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- /* Disable the USART DMA Rx request */
- husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
- }
- else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
- {
- /* Disable the USART DMA Tx request */
- husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
- /* Disable the USART DMA Rx request */
- husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
- }
-
+
+ /* Disable the USART DMA Tx request */
+ husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
-
+
return HAL_OK;
}
/**
* @brief Resumes the DMA Transfer.
- * @param husart: USART handle
- * @retval None
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
{
/* Process Locked */
__HAL_LOCK(husart);
-
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
- /* Enable the USART DMA Tx request */
- husart->Instance->CR3 |= USART_CR3_DMAT;
- }
- else if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- /* Enable the USART DMA Rx request */
- husart->Instance->CR3 |= USART_CR3_DMAR;
- }
- else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
- {
- /* Enable the USART DMA Rx request before the DMA Tx request */
- husart->Instance->CR3 |= USART_CR3_DMAR;
- /* Enable the USART DMA Tx request */
- husart->Instance->CR3 |= USART_CR3_DMAT;
- }
-
- /* If the USART peripheral is still not enabled, enable it */
- if ((husart->Instance->CR1 & USART_CR1_UE) == 0)
- {
- /* Enable USART peripheral */
- __USART_ENABLE(husart);
- }
-
+
+ /* Enable the USART DMA Tx request */
+ husart->Instance->CR3 |= USART_CR3_DMAT;
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
-
+
return HAL_OK;
}
/**
* @brief Stops the DMA Transfer.
- * @param husart: USART handle
- * @retval None
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
{
- /* Process Locked */
- __HAL_LOCK(husart);
-
- /* Disable the USART Tx/Rx DMA requests */
- husart->Instance->CR3 &= ~USART_CR3_DMAT;
- husart->Instance->CR3 &= ~USART_CR3_DMAR;
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback()
+ */
/* Abort the USART DMA Tx Stream */
if(husart->hdmatx != NULL)
@@ -1098,20 +1103,20 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
{
HAL_DMA_Abort(husart->hdmarx);
}
- /* Disable USART peripheral */
- __USART_DISABLE(husart);
-
+
+ /* Disable the USART Tx/Rx DMA requests */
+ husart->Instance->CR3 &= ~USART_CR3_DMAT;
+ husart->Instance->CR3 &= ~USART_CR3_DMAR;
+
husart->State = HAL_USART_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
return HAL_OK;
}
/**
* @brief This function handles USART interrupt request.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
@@ -1123,7 +1128,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
/* USART parity error interrupt occurred -----------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
- __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_PE);
+ __HAL_USART_CLEAR_PEFLAG(husart);
husart->ErrorCode |= HAL_USART_ERROR_PE;
}
@@ -1132,7 +1137,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
/* USART frame error interrupt occurred ------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
- __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_FE);
+ __HAL_USART_CLEAR_FEFLAG(husart);
husart->ErrorCode |= HAL_USART_ERROR_FE;
}
@@ -1141,7 +1146,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
/* USART noise error interrupt occurred ------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
- __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_NE);
+ __HAL_USART_CLEAR_NEFLAG(husart);
husart->ErrorCode |= HAL_USART_ERROR_NE;
}
@@ -1150,7 +1155,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
/* USART Over-Run interrupt occurred ---------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
- __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_ORE);
+ __HAL_USART_CLEAR_OREFLAG(husart);
husart->ErrorCode |= HAL_USART_ERROR_ORE;
}
@@ -1177,8 +1182,8 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
}
}
- tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TC);
- tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC);
+ tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TXE);
+ tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE);
/* USART in mode Transmitter -----------------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
@@ -1191,11 +1196,20 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
USART_TransmitReceive_IT(husart);
}
}
+
+ tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TC);
+ tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC);
+ /* USART in mode Transmitter (transmission end) ----------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ USART_EndTransmit_IT(husart);
+ }
}
/**
* @brief Tx Transfer completed callbacks.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
@@ -1207,7 +1221,8 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
/**
* @brief Tx Half Transfer completed callbacks.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
@@ -1219,7 +1234,8 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
/**
* @brief Rx Transfer completed callbacks.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
@@ -1231,7 +1247,8 @@ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
/**
* @brief Rx Half Transfer completed callbacks.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
@@ -1243,7 +1260,8 @@ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
/**
* @brief Tx/Rx Transfers completed callback for the non-blocking process.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
@@ -1255,7 +1273,8 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
/**
* @brief USART error callbacks.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
@@ -1269,7 +1288,7 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
* @}
*/
-/** @defgroup USART_Group3 Peripheral State and Errors functions
+/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief USART State and Errors functions
*
@verbatim
@@ -1279,10 +1298,10 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
[..]
This subsection provides a set of functions allowing to return the State of
USART communication
- process, return Peripheral Errors occured during communication process
+ process, return Peripheral Errors occurred during communication process
(+) HAL_USART_GetState() API can be helpful to check in run-time the state
of the USART peripheral.
- (+) HAL_USART_GetError() check in run-time errors that could be occured durung
+ (+) HAL_USART_GetError() check in run-time errors that could be occurred during
communication.
@endverbatim
* @{
@@ -1290,7 +1309,8 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
/**
* @brief Returns the USART state.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval HAL state
*/
HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
@@ -1322,37 +1342,34 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- husart->TxXferCount = 0;
- if(husart->State == HAL_USART_STATE_BUSY_TX)
+ /* DMA Normal mode */
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
{
- /* Wait for USART TC Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TIMEOUT_VALUE) != HAL_OK)
- {
- /* Timeout Occured */
- husart->State = HAL_USART_STATE_TIMEOUT;
- HAL_USART_ErrorCallback(husart);
- }
- else
+ husart->TxXferCount = 0;
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
{
- /* No Timeout */
- /* Disable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- husart->Instance->CR3 &= ~(USART_CR3_DMAT);
- husart->State= HAL_USART_STATE_READY;
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the USART CR3 register */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
}
}
- /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/
+ /* DMA Circular mode */
else
{
- husart->State= HAL_USART_STATE_BUSY_RX;
- HAL_USART_TxCpltCallback(husart);
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ HAL_USART_TxCpltCallback(husart);
+ }
}
}
/**
* @brief DMA USART transmit process half complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -1367,25 +1384,53 @@ static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
* @param hdma: DMA handle
* @retval None
*/
-static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* DMA Normal mode */
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ {
+ husart->RxXferCount = 0;
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
+ in the USART CR3 register */
+ husart->Instance->CR3 &= ~(USART_CR3_DMAR);
- husart->RxXferCount = 0;
-
- /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
- in the USART CR3 register */
- husart->Instance->CR3 &= ~(USART_CR3_DMAR);
- husart->Instance->CR3 &= ~(USART_CR3_DMAT);
-
- husart->State= HAL_USART_STATE_READY;
-
- HAL_USART_RxCpltCallback(husart);
+ husart->State= HAL_USART_STATE_READY;
+ HAL_USART_RxCpltCallback(husart);
+ }
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+ else
+ {
+ /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
+ in the USART CR3 register */
+ husart->Instance->CR3 &= ~(USART_CR3_DMAR);
+ husart->Instance->CR3 &= ~(USART_CR3_DMAT);
+
+ husart->State= HAL_USART_STATE_READY;
+ HAL_USART_TxRxCpltCallback(husart);
+ }
+ }
+ /* DMA circular mode */
+ else
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ HAL_USART_RxCpltCallback(husart);
+ }
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+ else
+ {
+ HAL_USART_TxRxCpltCallback(husart);
+ }
+ }
}
/**
* @brief DMA USART receive process half complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -1400,7 +1445,7 @@ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
* @param hdma: DMA handle
* @retval None
*/
-static void USART_DMAError(DMA_HandleTypeDef *hdma)
+static void USART_DMAError(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
@@ -1414,7 +1459,8 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma)
/**
* @brief This function handles USART Communication Timeout.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @param Flag: specifies the USART flag to check.
* @param Status: The new Flag status (SET or RESET).
* @param Timeout: Timeout duration
@@ -1422,9 +1468,10 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma)
*/
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
- timeout = HAL_GetTick() + Timeout;
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Wait until flag is set */
if(Status == RESET)
@@ -1434,13 +1481,13 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __USART_DISABLE_IT(husart, USART_IT_TXE);
- __USART_DISABLE_IT(husart, USART_IT_RXNE);
- __USART_DISABLE_IT(husart, USART_IT_PE);
- __USART_DISABLE_IT(husart, USART_IT_ERR);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
husart->State= HAL_USART_STATE_READY;
@@ -1459,13 +1506,13 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __USART_DISABLE_IT(husart, USART_IT_TXE);
- __USART_DISABLE_IT(husart, USART_IT_RXNE);
- __USART_DISABLE_IT(husart, USART_IT_PE);
- __USART_DISABLE_IT(husart, USART_IT_ERR);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
husart->State= HAL_USART_STATE_READY;
@@ -1483,7 +1530,8 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar
/**
* @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval HAL status
* @note The USART errors are not managed to avoid the overrun error.
*/
@@ -1493,9 +1541,6 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
if(husart->State == HAL_USART_STATE_BUSY_TX)
{
- /* Process Locked */
- __HAL_LOCK(husart);
-
if(husart->Init.WordLength == USART_WORDLENGTH_9B)
{
tmp = (uint16_t*) husart->pTxBuffPtr;
@@ -1516,26 +1561,12 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
if(--husart->TxXferCount == 0)
{
- /* Disable the USART Transmit Complete Interrupt */
- __USART_DISABLE_IT(husart, USART_IT_TC);
-
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __USART_DISABLE_IT(husart, USART_IT_ERR);
+ /* Disable the USART Transmit data register empty Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
- husart->State = HAL_USART_STATE_READY;
-
- /* Call the Process Unlocked before calling the Tx callback API to give the possibility to
- start again the Transmission under the Tx callback API */
- __HAL_UNLOCK(husart);
-
- HAL_USART_TxCpltCallback(husart);
-
- return HAL_OK;
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
}
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
return HAL_OK;
}
else
@@ -1544,9 +1575,31 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
}
}
+/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
+{
+ /* Disable the USART Transmit Complete Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ HAL_USART_TxCpltCallback(husart);
+
+ return HAL_OK;
+}
+
/**
* @brief Simplex Receive an amount of data in non-blocking mode.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
@@ -1554,9 +1607,6 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
uint16_t* tmp;
if(husart->State == HAL_USART_STATE_BUSY_RX)
{
- /* Process Locked */
- __HAL_LOCK(husart);
-
if(husart->Init.WordLength == USART_WORDLENGTH_9B)
{
tmp = (uint16_t*) husart->pRxBuffPtr;
@@ -1597,27 +1647,19 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
if(husart->RxXferCount == 0)
{
/* Disable the USART RXNE Interrupt */
- __USART_DISABLE_IT(husart, USART_IT_RXNE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
/* Disable the USART Parity Error Interrupt */
- __USART_DISABLE_IT(husart, USART_IT_PE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __USART_DISABLE_IT(husart, USART_IT_ERR);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
husart->State = HAL_USART_STATE_READY;
- /* Call the Process Unlocked before calling the Rx callback API to give the possibility to
- start again the reception under the Rx callback API */
- __HAL_UNLOCK(husart);
-
HAL_USART_RxCpltCallback(husart);
return HAL_OK;
}
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
return HAL_OK;
}
else
@@ -1628,7 +1670,8 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
/**
* @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
@@ -1637,8 +1680,6 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
{
- /* Process Locked */
- __HAL_LOCK(husart);
if(husart->TxXferCount != 0x00)
{
if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
@@ -1665,7 +1706,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
/* Check the latest data transmitted */
if(husart->TxXferCount == 0)
{
- __USART_DISABLE_IT(husart, USART_IT_TC);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
}
}
}
@@ -1706,28 +1747,21 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
/* Check the latest data received */
if(husart->RxXferCount == 0)
{
- __USART_DISABLE_IT(husart, USART_IT_RXNE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
/* Disable the USART Parity Error Interrupt */
- __USART_DISABLE_IT(husart, USART_IT_PE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __USART_DISABLE_IT(husart, USART_IT_ERR);
-
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
husart->State = HAL_USART_STATE_READY;
- /* Call the Process Unlocked before calling the Tx\Rx callback API to give the possibility to
- start again the Transmission\Reception under the Tx\Rx callback API */
- __HAL_UNLOCK(husart);
-
HAL_USART_TxRxCpltCallback(husart);
return HAL_OK;
}
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
return HAL_OK;
}
else
@@ -1738,7 +1772,8 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
/**
* @brief Configures the USART peripheral.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
static void USART_SetConfig(USART_HandleTypeDef *husart)
@@ -1769,7 +1804,7 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
/* Set CPHA bit according to husart->Init.CLKPhase value */
/* Set LBCL bit according to husart->Init.CLKLastBit value */
/* Set Stop Bits: Set STOP[13:12] bits according to husart->Init.StopBits value */
- tmpreg |= (uint32_t)(USART_CLOCK_ENABLED| husart->Init.CLKPolarity |
+ tmpreg |= (uint32_t)(USART_CLOCK_ENABLE| husart->Init.CLKPolarity |
husart->Init.CLKPhase| husart->Init.CLKLastBit | husart->Init.StopBits);
/* Write to USART CR2 */
husart->Instance->CR2 = (uint32_t)tmpreg;
@@ -1777,15 +1812,16 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
/*-------------------------- USART CR1 Configuration -----------------------*/
tmpreg = husart->Instance->CR1;
- /* Clear M, PCE, PS, TE and RE bits */
+ /* Clear M, PCE, PS, TE, RE and OVER8 bits */
tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
- USART_CR1_RE));
+ USART_CR1_RE | USART_CR1_OVER8));
/* Configure the USART Word Length, Parity and mode:
Set the M bits according to husart->Init.WordLength value
Set PCE and PS bits according to husart->Init.Parity value
- Set TE and RE bits according to husart->Init.Mode value */
- tmpreg |= (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode;
+ Set TE and RE bits according to husart->Init.Mode value
+ Force OVER8 bit to 1 in order to reach the max USART frequencies */
+ tmpreg |= (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
/* Write to USART CR1 */
husart->Instance->CR1 = (uint32_t)tmpreg;
@@ -1797,11 +1833,11 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
/*-------------------------- USART BRR Configuration -----------------------*/
if((husart->Instance == USART1) || (husart->Instance == USART6))
{
- husart->Instance->BRR = __USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate);
+ husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate);
}
else
{
- husart->Instance->BRR = __USART_BRR(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate);
+ husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate);
}
}
diff --git a/f2/src/stm32f2xx_hal_wwdg.c b/f2/src/stm32f2xx_hal_wwdg.c
index 6bd6f2c17aa08b15afe9cda13a9a7463fd3e2c81..625e8a4b388881503d126f8de659793e055daddc 100755
--- a/f2/src/stm32f2xx_hal_wwdg.c
+++ b/f2/src/stm32f2xx_hal_wwdg.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_wwdg.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief WWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Window Watchdog (WWDG) peripheral:
@@ -31,8 +31,8 @@
(+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
(+) WWDG timeout (mS) = 1000 * Counter / WWDG clock
(+) WWDG Counter refresh is allowed between the following limits :
- (++) min time (mS) = 1000 * (Counter – Window) / WWDG clock
- (++) max time (mS) = 1000 * (Counter – 0x40) / WWDG clock
+ (++) min time (mS) = 1000 * (Counter _ Window) / WWDG clock
+ (++) max time (mS) = 1000 * (Counter _ 0x40) / WWDG clock
(+) Min-max timeout value at 50 MHz(PCLK1): 81.9 us / 41.9 ms
@@ -40,7 +40,7 @@
##### How to use this driver #####
==============================================================================
[..]
- (+) Enable WWDG APB1 clock using __WWDG_CLK_ENABLE().
+ (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
(+) Set the WWDG prescaler, refresh window and counter value
using HAL_WWDG_Init() function.
(+) Start the WWDG using HAL_WWDG_Start() function.
@@ -62,15 +62,15 @@
Below the list of most used macros in WWDG HAL driver.
(+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
- (+) __HAL_IWDG_GET_FLAG: Get the selected WWDG's flag status
- (+) __HAL_IWDG_CLEAR_FLAG: Clear the WWDG's pending flags
- (+) __HAL_IWDG_RELOAD_COUNTER: Enables the WWDG early wakeup interrupt
+ (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
+ (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
+ (+) __HAL_WWDG_ENABLE_IT: Enables the WWDG early wake-up interrupt
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -104,7 +104,7 @@
* @{
*/
-/** @defgroup WWDG
+/** @defgroup WWDG WWDG
* @brief WWDG HAL module driver.
* @{
*/
@@ -116,15 +116,14 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup WWDG_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
* @{
*/
-/** @defgroup WWDG_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
- *
+/** @defgroup WWDG_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@@ -144,26 +143,28 @@
/**
* @brief Initializes the WWDG according to the specified
* parameters in the WWDG_InitTypeDef and creates the associated handle.
- * @param hwwdg: WWDG handle
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
{
- uint32_t tmp = 0;
-
/* Check the WWDG handle allocation */
if(hwwdg == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
+ assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
if(hwwdg->State == HAL_WWDG_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hwwdg->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_WWDG_MspInit(hwwdg);
}
@@ -172,31 +173,10 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
hwwdg->State = HAL_WWDG_STATE_BUSY;
/* Set WWDG Prescaler and Window */
- /* Get the CFR register value */
- tmp = hwwdg->Instance->CFR;
-
- /* Clear WDGTB[1:0] and W[6:0] bits */
- tmp &= ((uint32_t)~(WWDG_CFR_WDGTB | WWDG_CFR_W));
-
- /* Prepare the WWDG Prescaler and Window parameters */
- tmp |= hwwdg->Init.Prescaler | hwwdg->Init.Window;
-
- /* Write to WWDG CFR */
- hwwdg->Instance->CFR = tmp;
-
+ MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window));
/* Set WWDG Counter */
- /* Get the CR register value */
- tmp = hwwdg->Instance->CR;
-
- /* Clear T[6:0] bits */
- tmp &= ((uint32_t)~(WWDG_CR_T));
-
- /* Prepare the WWDG Counter parameter */
- tmp |= (hwwdg->Init.Counter);
-
- /* Write to WWDG CR */
- hwwdg->Instance->CR = tmp;
-
+ MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter);
+
/* Change WWDG peripheral state */
hwwdg->State = HAL_WWDG_STATE_READY;
@@ -206,11 +186,21 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
/**
* @brief DeInitializes the WWDG peripheral.
- * @param hwwdg: WWDG handle
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg)
-{
+{
+ /* Check the WWDG handle allocation */
+ if(hwwdg == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
+
/* Change WWDG peripheral state */
hwwdg->State = HAL_WWDG_STATE_BUSY;
@@ -238,7 +228,8 @@ HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg)
/**
* @brief Initializes the WWDG MSP.
- * @param hwwdg: WWDG handle
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
* @retval None
*/
__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
@@ -250,7 +241,8 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
/**
* @brief DeInitializes the WWDG MSP.
- * @param hwwdg: WWDG handle
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
* @retval None
*/
__weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)
@@ -264,7 +256,7 @@ __weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)
* @}
*/
-/** @defgroup WWDG_Group2 IO operation functions
+/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
@@ -283,7 +275,8 @@ __weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)
/**
* @brief Starts the WWDG.
- * @param hwwdg: WWDG handle
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg)
@@ -309,30 +302,33 @@ HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg)
/**
* @brief Starts the WWDG with interrupt enabled.
- * @param hwwdg: WWDG handle
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg)
-{
+{
/* Process Locked */
__HAL_LOCK(hwwdg);
-
+
/* Change WWDG peripheral state */
hwwdg->State = HAL_WWDG_STATE_BUSY;
-
+
/* Enable the Early Wakeup Interrupt */
- __HAL_WWDG_ENABLE_IT(WWDG_IT_EWI);
+ __HAL_WWDG_ENABLE_IT(hwwdg, WWDG_IT_EWI);
/* Enable the peripheral */
__HAL_WWDG_ENABLE(hwwdg);
-
+
/* Return function status */
return HAL_OK;
}
/**
* @brief Refreshes the WWDG.
- * @param hwwdg: WWDG handle
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @param Counter: value of counter to put in WWDG counter
* @retval HAL status
*/
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
@@ -347,7 +343,7 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
assert_param(IS_WWDG_COUNTER(Counter));
/* Write to WWDG CR the WWDG Counter value to refresh with */
- MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, Counter);
+ MODIFY_REG(hwwdg->Instance->CR, (uint32_t)WWDG_CR_T, Counter);
/* Change WWDG peripheral state */
hwwdg->State = HAL_WWDG_STATE_READY;
@@ -368,31 +364,37 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
* generated and the corresponding Interrupt Service Routine (ISR) can
* be used to trigger specific actions (such as communications or data
* logging), before resetting the device.
- * @param hwwdg: WWDG handle
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
* @retval None
*/
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
{
- /* WWDG Early Wakeup Interrupt occurred */
- if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+ /* Check if Early Wakeup Interrupt is enable */
+ if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
{
- /* Early Wakeup callback */
- HAL_WWDG_WakeupCallback(hwwdg);
-
- /* Change WWDG peripheral state */
- hwwdg->State = HAL_WWDG_STATE_READY;
-
- /* Clear the WWDG Data Ready flag */
- __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hwwdg);
+ /* Check if WWDG Early Wakeup Interrupt occurred */
+ if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+ {
+ /* Early Wakeup callback */
+ HAL_WWDG_WakeupCallback(hwwdg);
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_READY;
+
+ /* Clear the WWDG Early Wakeup flag */
+ __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hwwdg);
+ }
}
}
/**
* @brief Early Wakeup WWDG callback.
- * @param hwwdg: WWDG handle
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
* @retval None
*/
__weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg)
@@ -406,7 +408,7 @@ __weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg)
* @}
*/
-/** @defgroup WWDG_Group3 Peripheral State functions
+/** @defgroup WWDG_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
@@ -423,7 +425,8 @@ __weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg)
/**
* @brief Returns the WWDG state.
- * @param hwwdg: WWDG handle
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
* @retval HAL state
*/
HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg)
diff --git a/f2/src/stm32f2xx_ll_fsmc.c b/f2/src/stm32f2xx_ll_fsmc.c
index 8accb7b2e98b269e154253cfcabc649b9fead3cf..aa326e5fd0fc14cebcc6fe062b91ad044d70a3d5 100755
--- a/f2/src/stm32f2xx_ll_fsmc.c
+++ b/f2/src/stm32f2xx_ll_fsmc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_ll_fsmc.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief FSMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -21,7 +21,7 @@
(+) The NAND/PC Card memory controller
[..] The FSMC functional block makes the interface with synchronous and asynchronous static
- memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
+ memories and 16-bit PC memory cards. Its main purposes are:
(+) to translate AHB transactions into the appropriate external device protocol.
(+) to meet the access time requirements of the external memory devices.
@@ -44,7 +44,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -78,7 +78,7 @@
* @{
*/
-/** @defgroup FSMC
+/** @defgroup FSMC_LL FSMC Low Layer
* @brief FSMC driver modules
* @{
*/
@@ -91,12 +91,11 @@
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FSMC_Private_Functions
+/** @addtogroup FSMC_LL_Private_Functions
* @{
*/
-/** @defgroup FSMC_NORSRAM Controller functions
+/** @addtogroup FSMC_LL_NORSRAM
* @brief NORSRAM Controller functions
*
@verbatim
@@ -120,7 +119,7 @@
* @{
*/
-/** @defgroup HAL_FSMC_NORSRAM_Group1 Initialization/de-initialization functions
+/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
@@ -163,20 +162,30 @@ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_
assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
+ /* Get the BTCR register value */
+ tmpr = Device->BTCR[Init->NSBank];
+
+ /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
+ WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
+ tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
+ FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
+ FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \
+ FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \
+ FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CBURSTRW));
/* Set NORSRAM device control parameters */
- tmpr = (uint32_t)(Init->DataAddressMux |\
- Init->MemoryType |\
- Init->MemoryDataWidth |\
- Init->BurstAccessMode |\
- Init->WaitSignalPolarity |\
- Init->WrapMode |\
- Init->WaitSignalActive |\
- Init->WriteOperation |\
- Init->WaitSignal |\
- Init->ExtendedMode |\
- Init->AsynchronousWait |\
- Init->WriteBurst
- );
+ tmpr |= (uint32_t)(Init->DataAddressMux |\
+ Init->MemoryType |\
+ Init->MemoryDataWidth |\
+ Init->BurstAccessMode |\
+ Init->WaitSignalPolarity |\
+ Init->WrapMode |\
+ Init->WaitSignalActive |\
+ Init->WriteOperation |\
+ Init->WaitSignal |\
+ Init->ExtendedMode |\
+ Init->AsynchronousWait |\
+ Init->WriteBurst
+ );
if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
{
@@ -188,7 +197,6 @@ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_
return HAL_OK;
}
-
/**
* @brief DeInitialize the FSMC_NORSRAM peripheral
* @param Device: Pointer to NORSRAM device instance
@@ -245,15 +253,22 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NO
assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
+ /* Get the BTCR register value */
+ tmpr = Device->BTCR[Bank + 1];
+
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
+ tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \
+ FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \
+ FSMC_BTR1_ACCMOD));
+
/* Set FSMC_NORSRAM device timing parameters */
- tmpr = (uint32_t)(Timing->AddressSetupTime |\
- ((Timing->AddressHoldTime) << 4) |\
- ((Timing->DataSetupTime) << 8) |\
- ((Timing->BusTurnAroundDuration) << 16) |\
- (((Timing->CLKDivision)-1) << 20) |\
- (((Timing->DataLatency)-2) << 24) |\
- (Timing->AccessMode)
- );
+ tmpr |= (uint32_t)(Timing->AddressSetupTime |\
+ ((Timing->AddressHoldTime) << 4) |\
+ ((Timing->DataSetupTime) << 8) |\
+ ((Timing->BusTurnAroundDuration) << 16) |\
+ (((Timing->CLKDivision)-1) << 20) |\
+ (((Timing->DataLatency)-2) << 24) |\
+ (Timing->AccessMode));
Device->BTCR[Bank + 1] = tmpr;
@@ -270,6 +285,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NO
*/
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
{
+ uint32_t tmpr = 0;
+
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
{
@@ -282,13 +299,23 @@ HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeD
assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
- Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime |\
- ((Timing->AddressHoldTime) << 4) |\
- ((Timing->DataSetupTime) << 8) |\
- ((Timing->BusTurnAroundDuration) << 16) |\
- (((Timing->CLKDivision)-1) << 20) |\
- (((Timing->DataLatency)-2) << 24) |\
- (Timing->AccessMode));
+ /* Get the BWTR register value */
+ tmpr = Device->BWTR[Bank];
+
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
+ tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \
+ FSMC_BWTR1_BUSTURN | FSMC_BWTR1_CLKDIV | FSMC_BWTR1_DATLAT | \
+ FSMC_BWTR1_ACCMOD));
+
+ tmpr |= (uint32_t)(Timing->AddressSetupTime |\
+ ((Timing->AddressHoldTime) << 4) |\
+ ((Timing->DataSetupTime) << 8) |\
+ ((Timing->BusTurnAroundDuration) << 16) |\
+ (((Timing->CLKDivision)-1) << 20) |\
+ (((Timing->DataLatency)-2) << 24) |\
+ (Timing->AccessMode));
+
+ Device->BWTR[Bank] = tmpr;
}
else
{
@@ -297,16 +324,13 @@ HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeD
return HAL_OK;
}
-
-
/**
* @}
*/
-
-/** @defgroup HAL_FSMC_NORSRAM_Group3 Control functions
- * @brief management functions
- *
+/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### FSMC_NORSRAM Control functions #####
@@ -346,7 +370,6 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi
return HAL_OK;
}
-
/**
* @}
*/
@@ -355,8 +378,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi
* @}
*/
-/** @defgroup FSMC_PCCARD Controller functions
- * @brief PCCARD Controller functions
+/** @addtogroup FSMC_LL_NAND
+ * @brief NAND Controller functions
*
@verbatim
==============================================================================
@@ -380,9 +403,9 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi
* @{
*/
-/** @defgroup HAL_FSMC_NAND_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
- *
+/** @addtogroup FSMC_LL_NAND_Private_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
@@ -406,7 +429,7 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi
*/
HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
{
- uint32_t tmppcr = 0;
+ uint32_t tmpr = 0;
/* Check the parameters */
assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
@@ -417,29 +440,43 @@ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDe
assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
+ if(Init->NandBank == FSMC_NAND_BANK2)
+ {
+ /* Get the NAND bank 2 register value */
+ tmpr = Device->PCR2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmpr = Device->PCR3;
+ }
+
+ /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
+ tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \
+ FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
+ FSMC_PCR2_TAR | FSMC_PCR2_ECCPS));
+
/* Set NAND device control parameters */
- tmppcr = (uint32_t)(Init->Waitfeature |\
- FSMC_PCR_MEMORY_TYPE_NAND |\
- Init->MemoryDataWidth |\
- Init->EccComputation |\
- Init->ECCPageSize |\
- ((Init->TCLRSetupTime) << 9) |\
- ((Init->TARSetupTime) << 13)
- );
+ tmpr |= (uint32_t)(Init->Waitfeature |\
+ FSMC_PCR_MEMORY_TYPE_NAND |\
+ Init->MemoryDataWidth |\
+ Init->EccComputation |\
+ Init->ECCPageSize |\
+ ((Init->TCLRSetupTime) << 9) |\
+ ((Init->TARSetupTime) << 13));
if(Init->NandBank == FSMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
- Device->PCR2 = tmppcr;
+ Device->PCR2 = tmpr;
}
else
{
/* NAND bank 3 registers configuration */
- Device->PCR3 = tmppcr;
+ Device->PCR3 = tmpr;
}
return HAL_OK;
-
}
/**
@@ -452,7 +489,7 @@ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDe
*/
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
- uint32_t tmppmem = 0;
+ uint32_t tmpr = 0;
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
@@ -460,8 +497,23 @@ HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, F
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+ if(Bank == FSMC_NAND_BANK2)
+ {
+ /* Get the NAND bank 2 register value */
+ tmpr = Device->PMEM2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmpr = Device->PMEM3;
+ }
+
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
+ tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \
+ FSMC_PMEM2_MEMHIZ2));
+
/* Set FSMC_NAND device timing parameters */
- tmppmem = (uint32_t)(Timing->SetupTime |\
+ tmpr |= (uint32_t)(Timing->SetupTime |\
((Timing->WaitSetupTime) << 8) |\
((Timing->HoldSetupTime) << 16) |\
((Timing->HiZSetupTime) << 24)
@@ -470,12 +522,12 @@ HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, F
if(Bank == FSMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
- Device->PMEM2 = tmppmem;
+ Device->PMEM2 = tmpr;
}
else
{
/* NAND bank 3 registers configuration */
- Device->PMEM3 = tmppmem;
+ Device->PMEM3 = tmpr;
}
return HAL_OK;
@@ -491,7 +543,7 @@ HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, F
*/
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
- uint32_t tmppatt = 0;
+ uint32_t tmpr = 0;
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
@@ -499,8 +551,23 @@ HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+ if(Bank == FSMC_NAND_BANK2)
+ {
+ /* Get the NAND bank 2 register value */
+ tmpr = Device->PATT2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmpr = Device->PATT3;
+ }
+
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
+ tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \
+ FSMC_PATT2_ATTHIZ2));
+
/* Set FSMC_NAND device timing parameters */
- tmppatt = (uint32_t)(Timing->SetupTime |\
+ tmpr |= (uint32_t)(Timing->SetupTime |\
((Timing->WaitSetupTime) << 8) |\
((Timing->HoldSetupTime) << 16) |\
((Timing->HiZSetupTime) << 24)
@@ -509,18 +576,17 @@ HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device
if(Bank == FSMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
- Device->PATT2 = tmppatt;
+ Device->PATT2 = tmpr;
}
else
{
/* NAND bank 3 registers configuration */
- Device->PATT3 = tmppatt;
+ Device->PATT3 = tmpr;
}
return HAL_OK;
}
-
/**
* @brief DeInitializes the FSMC_NAND device
* @param Device: Pointer to NAND device instance
@@ -553,15 +619,13 @@ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
return HAL_OK;
}
-
/**
* @}
*/
-
-/** @defgroup HAL_FSMC_NAND_Group3 Control functions
- * @brief management functions
- *
+/** @addtogroup FSMC_LL_NAND_Private_Functions_Group2
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### FSMC_NAND Control functions #####
@@ -573,7 +637,6 @@ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
@endverbatim
* @{
*/
-
/**
* @brief Enables dynamically FSMC_NAND ECC feature.
@@ -596,7 +659,6 @@ HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank
return HAL_OK;
}
-
/**
* @brief Disables dynamically FSMC_NAND ECC feature.
* @param Device: Pointer to NAND device instance
@@ -628,21 +690,22 @@ HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank
*/
HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_FSMC_NAND_DEVICE(Device));
assert_param(IS_FSMC_NAND_BANK(Bank));
-
- timeout = HAL_GetTick() + Timeout;
-
- /* Wait untill FIFO is empty */
- while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT))
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until FIFO is empty */
+ while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
return HAL_TIMEOUT;
}
@@ -671,7 +734,7 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval,
* @}
*/
-/** @defgroup FSMC_PCCARD Controller functions
+/** @addtogroup FSMC_LL_PCCARD
* @brief PCCARD Controller functions
*
@verbatim
@@ -695,9 +758,9 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval,
* @{
*/
-/** @defgroup HAL_FSMC_PCCARD_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
- *
+/** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
@@ -721,19 +784,29 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval,
*/
HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
{
+ uint32_t tmpr = 0;
+
/* Check the parameters */
assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
+ /* Get PCCARD control register value */
+ tmpr = Device->PCR4;
+
+ /* Clear TAR, TCLR, PWAITEN and PWID bits */
+ tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \
+ FSMC_PCR4_PWID));
+
/* Set FSMC_PCCARD device control parameters */
- Device->PCR4 = (uint32_t)(Init->Waitfeature |\
- FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
- (Init->TCLRSetupTime << 9) |\
- (Init->TARSetupTime << 13));
+ tmpr |= (uint32_t)(Init->Waitfeature |\
+ FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
+ (Init->TCLRSetupTime << 9) |\
+ (Init->TARSetupTime << 13));
+
+ Device->PCR4 = tmpr;
return HAL_OK;
-
}
/**
@@ -745,19 +818,28 @@ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_Init
*/
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
{
+ uint32_t tmpr = 0;
+
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+ /* Get PCCARD common space timing register value */
+ tmpr = Device->PMEM4;
+
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
+ tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \
+ FSMC_PMEM4_MEMHIZ4));
/* Set PCCARD timing parameters */
- Device->PMEM4 = (uint32_t)((Timing->SetupTime |\
- ((Timing->WaitSetupTime) << 8) |\
- (Timing->HoldSetupTime) << 16) |\
- ((Timing->HiZSetupTime) << 24)
- );
-
+ tmpr |= (uint32_t)((Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8) |\
+ (Timing->HoldSetupTime) << 16) |\
+ ((Timing->HiZSetupTime) << 24));
+
+ Device->PMEM4 = tmpr;
+
return HAL_OK;
}
@@ -770,18 +852,27 @@ HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Devic
*/
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
{
+ uint32_t tmpr = 0;
+
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+ /* Get PCCARD timing parameters */
+ tmpr = Device->PATT4;
+
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
+ tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \
+ FSMC_PATT4_ATTHIZ4));
+
/* Set PCCARD timing parameters */
- Device->PATT4 = (uint32_t)((Timing->SetupTime |\
- ((Timing->WaitSetupTime) << 8) |\
- (Timing->HoldSetupTime) << 16) |\
- ((Timing->HiZSetupTime) << 24)
- );
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8) |\
+ ((Timing->HoldSetupTime) << 16) |\
+ ((Timing->HiZSetupTime) << 24));
+ Device->PATT4 = tmpr;
return HAL_OK;
}
@@ -795,18 +886,28 @@ HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *De
*/
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
{
+ uint32_t tmpr = 0;
+
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+ /* Get FSMC_PCCARD device timing parameters */
+ tmpr = Device->PIO4;
+
+ /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
+ tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \
+ FSMC_PIO4_IOHIZ4));
+
/* Set FSMC_PCCARD device timing parameters */
- Device->PIO4 = (uint32_t)((Timing->SetupTime |\
- ((Timing->WaitSetupTime) << 8) |\
- (Timing->HoldSetupTime) << 16) |\
- ((Timing->HiZSetupTime) << 24)
- );
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8) |\
+ ((Timing->HoldSetupTime) << 16) |\
+ ((Timing->HiZSetupTime) << 24));
+
+ Device->PIO4 = tmpr;
return HAL_OK;
}
@@ -830,7 +931,6 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
return HAL_OK;
}
-
/**
* @}
*/
@@ -839,14 +939,16 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
* @}
*/
-#endif /* HAL_FSMC_MODULE_ENABLED */
-
/**
* @}
*/
+#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
/**
* @}
*/
+/**
+ * @}
+ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f2/src/stm32f2xx_ll_sdmmc.c b/f2/src/stm32f2xx_ll_sdmmc.c
index 9ab7f07d7ed88f92876f273e8251e1379b16d3dc..5afa9ce327b3aa3efb3913f41400824d6e1bf9db 100755
--- a/f2/src/stm32f2xx_ll_sdmmc.c
+++ b/f2/src/stm32f2xx_ll_sdmmc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_ll_sdmmc.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief SDMMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -21,13 +21,6 @@
peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA
devices.
- [..] The MultiMedia Card system specifications are available through the MultiMedia Card
- Association website at www.mmca.org, published by the MMCA technical committee.
- SD memory card and SD I/O card system specifications are available through the SD card
- Association website at www.sdcard.org.
- CE-ATA system specifications are available through the CE-ATA work group web site at
- www.ce-ata.org.
-
[..] The SDIO features include the following:
(+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
for three different databus modes: 1-bit (default), 4-bit and 8-bit
@@ -66,8 +59,8 @@
(+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO
peripheral.
- (+) Enable the Power ON State using the HAL_SDIO_PowerState_ON(hsdio)
- function and disable it using the function HAL_SDIO_PowerState_OFF(hsdio).
+ (+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx)
+ function and disable it using the function SDIO_PowerState_OFF(SDIOx).
(+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
@@ -81,8 +74,8 @@
__SDIO_DMA_DISABLE().
(+) To control the CPSM (Command Path State Machine) and send
- commands to the card use the HAL_SDIO_SendCommand(),
- HAL_SDIO_GetCommandResponse() and HAL_SDIO_GetResponse() functions. First, user has
+ commands to the card use the SDIO_SendCommand(SDIOx),
+ SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
to fill the command structure (pointer to SDIO_CmdInitTypeDef) according
to the selected command to be sent.
The parameters that should be filled are:
@@ -93,13 +86,13 @@
(++) CPSM Status (Enable or Disable).
-@@- To check if the command is well received, read the SDIO_CMDRESP
- register using the HAL_SDIO_GetCommandResponse().
+ register using the SDIO_GetCommandResponse().
The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
- HAL_SDIO_GetResponse() function.
+ SDIO_GetResponse() function.
(+) To control the DPSM (Data Path State Machine) and send/receive
- data to/from the card use the HAL_SDIO_DataConfig(), HAL_SDIO_GetDataCounter(),
- HAL_SDIO_ReadFIFO(), HAL_SDIO_WriteFIFO() and HAL_SDIO_GetFIFOCount() functions.
+ data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
+ SDIO_ReadFIFO(), DIO_WriteFIFO() and SDIO_GetFIFOCount() functions.
*** Read Operations ***
=======================
@@ -107,7 +100,7 @@
(#) First, user has to fill the data structure (pointer to
SDIO_DataInitTypeDef) according to the selected data type to be received.
The parameters that should be filled are:
- (++) Data TimeOut
+ (++) Data Timeout
(++) Data Length
(++) Data Block size
(++) Data Transfer direction: should be from card (To SDIO)
@@ -127,7 +120,7 @@
(#) First, user has to fill the data structure (pointer to
SDIO_DataInitTypeDef) according to the selected data type to be received.
The parameters that should be filled are:
- (++) Data TimeOut
+ (++) Data Timeout
(++) Data Length
(++) Data Block size
(++) Data Transfer direction: should be to card (To CARD)
@@ -135,9 +128,9 @@
(++) DPSM Status (Enable or Disable)
(#) Configure the SDIO resources to send the data to the card according to
- selected transfer mode (Refer to Step 8, 9 and 10).
+ selected transfer mode.
- (#) Send the selected Write command (refer to step 11).
+ (#) Send the selected Write command.
(#) Use the SDIO flags/interrupts to check the transfer status.
@@ -145,7 +138,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -179,8 +172,8 @@
* @{
*/
-/** @defgroup SDMMC
- * @brief SDMMC HAL module driver
+/** @defgroup SDMMC_LL SDMMC Low Layer
+ * @brief Low layer module for SD and MMC driver
* @{
*/
@@ -193,11 +186,11 @@
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup SDIO_Private_Functions
+/** @defgroup SDMMC_LL_Exported_Functions SDMMC_LL Exported Functions
* @{
*/
-/** @defgroup HAL_SDIO_Group1 Initialization/de-initialization functions
+/** @defgroup HAL_SDMMC_LL_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -219,7 +212,7 @@
*/
HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
{
- __IO uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));
@@ -230,12 +223,6 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));
- /* Get the SDIO CLKCR value */
- tmpreg = SDIOx->CLKCR;
-
- /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
- tmpreg &= CLKCR_CLEAR_MASK;
-
/* Set SDIO configuration parameters */
tmpreg |= (Init.ClockEdge |\
Init.ClockBypass |\
@@ -246,18 +233,16 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
);
/* Write to SDIO CLKCR */
- SDIOx->CLKCR = tmpreg;
+ MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
return HAL_OK;
}
-
-
/**
* @}
*/
-/** @defgroup HAL_SDIO_Group2 I/O operation functions
+/** @defgroup HAL_SDMMC_LL_Group2 I/O operation functions
* @brief Data transfers functions
*
@verbatim
@@ -275,7 +260,6 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
/**
* @brief Read data (word) from Rx FIFO in blocking mode (polling)
* @param SDIOx: Pointer to SDIO register base
- * @param ReadData: Data to read
* @retval HAL status
*/
uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
@@ -302,7 +286,7 @@ HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
* @}
*/
-/** @defgroup HAL_SDIO_Group3 Peripheral Control functions
+/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
* @brief management functions
*
@verbatim
@@ -325,7 +309,7 @@ HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
{
/* Set power state to ON */
- SDIOx->POWER = (uint32_t)0x00000003;
+ SDIOx->POWER = SDIO_POWER_PWRCTRL;
return HAL_OK;
}
@@ -354,7 +338,7 @@ HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
*/
uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx)
{
- return (SDIOx->POWER & (~PWR_PWRCTRL_MASK));
+ return (SDIOx->POWER & SDIO_POWER_PWRCTRL);
}
/**
@@ -377,14 +361,7 @@ HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDI
/* Set the SDIO Argument value */
SDIOx->ARG = SDIO_CmdInitStruct->Argument;
-
- /* SDIO CMD Configuration */
- /* Get the SDIO CMD value */
- tmpreg = SDIOx->CMD;
-
- /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
- tmpreg &= CMD_CLEAR_MASK;
-
+
/* Set SDIO command parameters */
tmpreg |= (uint32_t)(SDIO_CmdInitStruct->CmdIndex |\
SDIO_CmdInitStruct->Response |\
@@ -392,7 +369,7 @@ HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDI
SDIO_CmdInitStruct->CPSM);
/* Write to SDIO CMD register */
- SDIOx->CMD = tmpreg;
+ MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg);
return HAL_OK;
}
@@ -450,27 +427,20 @@ HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDI
assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->TransferMode));
assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->DPSM));
- /* Set the SDIO Data TimeOut value */
+ /* Set the SDIO Data Timeout value */
SDIOx->DTIMER = SDIO_DataInitStruct->DataTimeOut;
/* Set the SDIO DataLength value */
SDIOx->DLEN = SDIO_DataInitStruct->DataLength;
-/* SDIO DCTRL Configuration */
- /* Get the SDIO DCTRL value */
- tmpreg = SDIOx->DCTRL;
-
- /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
- tmpreg &= DCTRL_CLEAR_MASK;
-
/* Set the SDIO data configuration parameters */
tmpreg |= (uint32_t)(SDIO_DataInitStruct->DataBlockSize |\
SDIO_DataInitStruct->TransferDir |\
SDIO_DataInitStruct->TransferMode |\
SDIO_DataInitStruct->DPSM);
-
+
/* Write to SDIO DCTRL */
- SDIOx->DCTRL = tmpreg;
+ MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
return HAL_OK;
@@ -488,7 +458,7 @@ uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)
/**
* @brief Get the FIFO data
- * @param hsdio: SDIO handle
+ * @param SDIOx: Pointer to SDIO register base
* @retval Data received
*/
uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
@@ -515,26 +485,6 @@ HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
return HAL_OK;
}
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SDIO_Group3 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permit to get in runtime the status of the SDIO peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
/**
* @}
*/
diff --git a/f2/src/stm32f2xx_ll_usb.c b/f2/src/stm32f2xx_ll_usb.c
index 24ad6719c9d26a169d12e90edbf88968821d534c..ce799eac7799be395e294270f92748e68ac69ab2 100755
--- a/f2/src/stm32f2xx_ll_usb.c
+++ b/f2/src/stm32f2xx_ll_usb.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_ll_usb.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-March-2014
+ * @version V1.1.0
+ * @date 09-October-2015
* @brief USB Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -22,13 +22,13 @@
(#) Call USB_CoreInit() API to initialize the USB Core peripheral.
- (#) The upper HAL HCD/PCD driver will call the righ routines for its internal processes.
+ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -72,7 +72,9 @@
/* Private functions ---------------------------------------------------------*/
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
-/** @defgroup PCD_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions
* @{
*/
@@ -117,7 +119,6 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
}
else /* FS interface (embedded Phy) */
{
-
/* Select FS Embedded PHY */
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
@@ -166,8 +167,8 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
* @brief USB_SetCurrentMode : Set functional mode
* @param USBx : Selected device
* @param mode : current core mode
- * This parameter can be one of the these values:
- * @arg USB_OTG_DEVICE_MODE: Peripheral mode mode
+ * This parameter can be one of these values:
+ * @arg USB_OTG_DEVICE_MODE: Peripheral mode
* @arg USB_OTG_HOST_MODE: Host mode
* @arg USB_OTG_DRD_MODE: Dual Role Device mode
* @retval HAL status
@@ -237,7 +238,6 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
/* Flush the FIFOs */
USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */
USB_FlushRxFifo(USBx);
-
/* Clear all pending Device Interrupts */
USBx_DEVICE->DIEPMSK = 0;
@@ -330,7 +330,7 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
{
uint32_t count = 0;
- USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 5 ));
+ USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6));
do
{
@@ -373,7 +373,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
* depending the PHY type and the enumeration speed of the device.
* @param USBx : Selected device
* @param speed : device speed
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
@@ -390,7 +390,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
* @brief USB_GetDevSpeed :Return the Dev Speed
* @param USBx : Selected device
* @retval speed : device speed
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @arg USB_OTG_SPEED_LOW: Low speed mode
@@ -433,6 +433,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy
USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
}
+
}
else
{
@@ -500,15 +501,15 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP
/* Read DEPCTLn register */
if (ep->is_in == 1)
{
- USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
- USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
- USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
+ USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
+ USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
}
else
{
- USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
- USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
- USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
+ USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
}
return HAL_OK;
}
@@ -540,7 +541,7 @@ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, U
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @param dma: USB dma enabled or disabled
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @retval HAL status
@@ -662,7 +663,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @param dma: USB dma enabled or disabled
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @retval HAL status
@@ -751,7 +752,7 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD
* @param ch_ep_num : endpoint or host channel number
* @param len : Number of bytes to write
* @param dma: USB dma enabled or disabled
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @retval HAL status
@@ -777,12 +778,12 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin
* @param USBx : Selected device
* @param src : source pointer
* @param ch_ep_num : endpoint or host channel number
- * @param len : Noumber of bytes to read
+ * @param len : Number of bytes to read
* @param dma: USB dma enabled or disabled
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
- * @retval pointer to desctination buffer
+ * @retval pointer to destination buffer
*/
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
{
@@ -1010,7 +1011,7 @@ void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
* @brief Returns USB core mode
* @param USBx : Selected device
* @retval return core mode : Host or Device
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : Host
* 1 : Device
*/
@@ -1044,7 +1045,7 @@ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
* @brief Prepare the EP0 to start the first control setup
* @param USBx : Selected device
* @param dma: USB dma enabled or disabled
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @param psetup : pointer to setup packet
@@ -1156,7 +1157,6 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
/* Clear any pending interrupts */
USBx->GINTSTS = 0xFFFFFFFF;
-
if(USBx == USB_OTG_FS)
{
@@ -1164,9 +1164,7 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
USBx->GRXFSIZ = (uint32_t )0x80;
USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80);
USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0);
-
}
-
else
{
/* set Rx FIFO size */
@@ -1194,7 +1192,7 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
* HCFG register on the PHY type and set the right frame interval
* @param USBx : Selected device
* @param freq : clock frequency
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* HCFG_48_MHZ : Full Speed 48 MHz Clock
* HCFG_6_MHZ : Low Speed 6 MHz Clock
* @retval HAL status
@@ -1219,7 +1217,7 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq
* @brief USB_OTG_ResetPort : Reset Host Port
* @param USBx : Selected device
* @retval HAL status
- * @note : (1)The application must wait at least 10 ms
+ * @note (1)The application must wait at least 10 ms
* before clearing the reset bit.
*/
HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
@@ -1233,14 +1231,14 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
HAL_Delay (10); /* See Note #1 */
- USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
+ USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
return HAL_OK;
}
/**
* @brief USB_DriveVbus : activate or de-activate vbus
* @param state : VBUS state
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : VBUS Active
* 1 : VBUS Inactive
* @retval HAL status
@@ -1268,7 +1266,7 @@ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
* @brief Return Host Core speed
* @param USBx : Selected device
* @retval speed : Host speed
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @arg USB_OTG_SPEED_LOW: Low speed mode
@@ -1301,14 +1299,14 @@ uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
* @param dev_address : Current device address
* This parameter can be a value from 0 to 255
* @param speed : Current device speed
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @arg USB_OTG_SPEED_LOW: Low speed mode
* @param ep_type : Endpoint Type
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* @arg EP_TYPE_CTRL: Control type
- * @arg EP_TYPE_ISOC: Isochrounous type
+ * @arg EP_TYPE_ISOC: Isochronous type
* @arg EP_TYPE_BULK: Bulk type
* @arg EP_TYPE_INTR: Interrupt type
* @param mps : Max Packet Size
@@ -1352,6 +1350,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
}
}
break;
+
case EP_TYPE_INTR:
USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
@@ -1409,7 +1408,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
* @param USBx : Selected device
* @param hc : pointer to host channel structure
* @param dma: USB dma enabled or disabled
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @retval HAL state
@@ -1418,8 +1417,6 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
#pragma O0
#elif defined (__GNUC__) /*!< GNU Compiler */
#pragma GCC optimize ("O0")
-#elif defined (__TASKING__) /*!< TASKING Compiler */
-#pragma optimize=0
#endif /* __CC_ARM */
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
{
@@ -1427,7 +1424,8 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
uint16_t len_words = 0;
uint16_t num_packets = 0;
uint16_t max_hc_pkt_count = 256;
-
+ uint32_t tmpreg = 0;
+
if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))
{
if((dma == 0) && (hc->do_ping == 1))
@@ -1437,8 +1435,8 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
}
else if(dma == 1)
{
- USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
- hc->do_ping = 0;
+ USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
+ hc->do_ping = 0;
}
}
@@ -1462,27 +1460,27 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
hc->xfer_len = num_packets * hc->max_packet;
}
-
-
/* Initialize the HCTSIZn register */
USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\
- ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
- (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID);
+ ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
+ (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID);
if (dma)
{
/* xfer_buff MUST be 32-bits aligned */
USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
}
-
+
is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;
USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);
/* Set host channel enable */
- USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
- USBx_HC(hc->ch_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
-
+ tmpreg = USBx_HC(hc->ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hc->ch_num)->HCCHAR = tmpreg;
+
if (dma == 0) /* Slave mode */
{
if((hc->ep_is_in == 0) && (hc->xfer_len > 0))
@@ -1608,13 +1606,16 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
{
uint8_t num_packets = 1;
+ uint32_t tmpreg = 0;
USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
USB_OTG_HCTSIZ_DOPING;
/* Set host channel enable */
- USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
- USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ tmpreg = USBx_HC(ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(ch_num)->HCCHAR = tmpreg;
return HAL_OK;
}
@@ -1649,8 +1650,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
/* Halt all channels to put them into a known state. */
for (i = 0; i <= 15; i++)
- {
-
+ {
value = USBx_HC(i)->HCCHAR ;
value |= USB_OTG_HCCHAR_CHDIS;
@@ -1668,7 +1668,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
}
- /* Clear any pending Host interrups */
+ /* Clear any pending Host interrupts */
USBx_HOST->HAINT = 0xFFFFFFFF;
USBx->GINTSTS = 0xFFFFFFFF;
USB_EnableGlobalInt(USBx);