From 9666b3eb19f13c67f51c7382ab736b5489f397e0 Mon Sep 17 00:00:00 2001
From: Sergi Hernandez Juan <shernand@iri.upc.edu>
Date: Sun, 5 May 2024 19:54:54 +0200
Subject: [PATCH] Used the _SIM macro to avoid some simulation build warnings.
---
f3/include/core/core_cm4.h | 8 ++++++++
f4/include/core/core_cm4.h | 6 +++---
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/f3/include/core/core_cm4.h b/f3/include/core/core_cm4.h
index 308b868..0b9c0c8 100644
--- a/f3/include/core/core_cm4.h
+++ b/f3/include/core/core_cm4.h
@@ -1912,7 +1912,11 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
+ #ifdef _SIM
+ uint32_t *vectors = (uint32_t *)&SCB->VTOR;
+ #else
uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ #endif
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
@@ -1927,7 +1931,11 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
+ #ifdef _SIM
+ uint32_t *vectors = (uint32_t *)&SCB->VTOR;
+ #else
uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ #endif
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
diff --git a/f4/include/core/core_cm4.h b/f4/include/core/core_cm4.h
index d0a4fd1..961db57 100644
--- a/f4/include/core/core_cm4.h
+++ b/f4/include/core/core_cm4.h
@@ -1910,10 +1910,10 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
- #ifndef _SIM
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- #else
+ #ifdef _SIM
uint32_t *vectors = (uint32_t *)&SCB->VTOR;
+ #else
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
#endif
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M4 does not require the architectural barrier */
--
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