From 8e7057a3d52ff560169240a6b5422f78325d898a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Sergi=20Hern=C3=A1ndez?= <shernand@iri.upc.edu>
Date: Sat, 12 Dec 2015 15:29:55 +0000
Subject: [PATCH] Updated the F4 family HAL library
---
f4/include/Legacy/stm32_hal_legacy.h | 790 +-
f4/include/core/core_cm4.h | 274 +-
f4/include/core/core_cmFunc.h | 35 +-
f4/include/core/core_cmInstr.h | 180 +-
f4/include/core/core_cmSimd.h | 4 +-
f4/include/devices/stm32f401xc.h | 34 +-
f4/include/devices/stm32f401xe.h | 34 +-
f4/include/devices/stm32f405xx.h | 90 +-
f4/include/devices/stm32f407xx.h | 88 +-
f4/include/devices/stm32f410cx.h | 3971 ++++++++
f4/include/devices/stm32f410rx.h | 3975 ++++++++
f4/include/devices/stm32f410tx.h | 3941 ++++++++
f4/include/devices/stm32f411xe.h | 34 +-
f4/include/devices/stm32f415xx.h | 118 +-
f4/include/devices/stm32f417xx.h | 118 +-
f4/include/devices/stm32f427xx.h | 57 +-
f4/include/devices/stm32f429xx.h | 56 +-
f4/include/devices/stm32f437xx.h | 82 +-
f4/include/devices/stm32f439xx.h | 82 +-
f4/include/devices/stm32f446xx.h | 8220 ++++++++++++++++
f4/include/devices/stm32f469xx.h | 10141 ++++++++++++++++++++
f4/include/devices/stm32f479xx.h | 10331 +++++++++++++++++++++
f4/include/devices/stm32f4xx.h | 43 +-
f4/include/devices/system_stm32f4xx.h | 6 +-
f4/include/stm32f4xx_hal.h | 46 +-
f4/include/stm32f4xx_hal_adc.h | 82 +-
f4/include/stm32f4xx_hal_adc_ex.h | 38 +-
f4/include/stm32f4xx_hal_can.h | 17 +-
f4/include/stm32f4xx_hal_cec.h | 681 ++
f4/include/stm32f4xx_hal_cortex.h | 298 +-
f4/include/stm32f4xx_hal_crc.h | 8 +-
f4/include/stm32f4xx_hal_cryp.h | 37 +-
f4/include/stm32f4xx_hal_cryp_ex.h | 17 +-
f4/include/stm32f4xx_hal_dac.h | 31 +-
f4/include/stm32f4xx_hal_dac_ex.h | 38 +-
f4/include/stm32f4xx_hal_dcmi.h | 57 +-
f4/include/stm32f4xx_hal_dcmi_ex.h | 223 +
f4/include/stm32f4xx_hal_def.h | 11 +-
f4/include/stm32f4xx_hal_dma.h | 14 +-
f4/include/stm32f4xx_hal_dma2d.h | 11 +-
f4/include/stm32f4xx_hal_dma_ex.h | 6 +-
f4/include/stm32f4xx_hal_dsi.h | 1242 +++
f4/include/stm32f4xx_hal_eth.h | 26 +-
f4/include/stm32f4xx_hal_flash.h | 24 +-
f4/include/stm32f4xx_hal_flash_ex.h | 304 +-
f4/include/stm32f4xx_hal_flash_ramfunc.h | 21 +-
f4/include/stm32f4xx_hal_fmpi2c.h | 577 ++
f4/include/stm32f4xx_hal_fmpi2c_ex.h | 151 +
f4/include/stm32f4xx_hal_gpio.h | 20 +-
f4/include/stm32f4xx_hal_gpio_ex.h | 559 +-
f4/include/stm32f4xx_hal_hash.h | 21 +-
f4/include/stm32f4xx_hal_hash_ex.h | 10 +-
f4/include/stm32f4xx_hal_hcd.h | 57 +-
f4/include/stm32f4xx_hal_i2c.h | 6 +-
f4/include/stm32f4xx_hal_i2c_ex.h | 14 +-
f4/include/stm32f4xx_hal_i2s.h | 23 +-
f4/include/stm32f4xx_hal_i2s_ex.h | 69 +-
f4/include/stm32f4xx_hal_irda.h | 8 +-
f4/include/stm32f4xx_hal_iwdg.h | 6 +-
f4/include/stm32f4xx_hal_lptim.h | 759 ++
f4/include/stm32f4xx_hal_ltdc.h | 18 +-
f4/include/stm32f4xx_hal_ltdc_ex.h | 151 +
f4/include/stm32f4xx_hal_nand.h | 27 +-
f4/include/stm32f4xx_hal_nor.h | 30 +-
f4/include/stm32f4xx_hal_pccard.h | 18 +-
f4/include/stm32f4xx_hal_pcd.h | 86 +-
f4/include/stm32f4xx_hal_pcd_ex.h | 30 +-
f4/include/stm32f4xx_hal_pwr.h | 43 +-
f4/include/stm32f4xx_hal_pwr_ex.h | 142 +-
f4/include/stm32f4xx_hal_qspi.h | 788 ++
f4/include/stm32f4xx_hal_rcc.h | 554 +-
f4/include/stm32f4xx_hal_rcc_ex.h | 4130 +++++++-
f4/include/stm32f4xx_hal_rng.h | 13 +-
f4/include/stm32f4xx_hal_rtc.h | 27 +-
f4/include/stm32f4xx_hal_rtc_ex.h | 61 +-
f4/include/stm32f4xx_hal_sai.h | 288 +-
f4/include/stm32f4xx_hal_sai_ex.h | 102 +
f4/include/stm32f4xx_hal_sd.h | 14 +-
f4/include/stm32f4xx_hal_sdram.h | 11 +-
f4/include/stm32f4xx_hal_smartcard.h | 22 +-
f4/include/stm32f4xx_hal_spdifrx.h | 559 ++
f4/include/stm32f4xx_hal_spi.h | 8 +-
f4/include/stm32f4xx_hal_sram.h | 23 +-
f4/include/stm32f4xx_hal_tim.h | 6 +-
f4/include/stm32f4xx_hal_tim_ex.h | 64 +-
f4/include/stm32f4xx_hal_uart.h | 6 +-
f4/include/stm32f4xx_hal_usart.h | 8 +-
f4/include/stm32f4xx_hal_wwdg.h | 6 +-
f4/include/stm32f4xx_ll_fmc.h | 192 +-
f4/include/stm32f4xx_ll_fsmc.h | 32 +-
f4/include/stm32f4xx_ll_sdmmc.h | 22 +-
f4/include/stm32f4xx_ll_usb.h | 20 +-
f4/src/devices/system_stm32f4xx.c | 126 +-
f4/src/stm32f4xx_hal.c | 21 +-
f4/src/stm32f4xx_hal_adc.c | 244 +-
f4/src/stm32f4xx_hal_adc_ex.c | 74 +-
f4/src/stm32f4xx_hal_can.c | 17 +-
f4/src/stm32f4xx_hal_cec.c | 1107 +++
f4/src/stm32f4xx_hal_cortex.c | 55 +-
f4/src/stm32f4xx_hal_crc.c | 8 +-
f4/src/stm32f4xx_hal_cryp.c | 620 +-
f4/src/stm32f4xx_hal_cryp_ex.c | 566 +-
f4/src/stm32f4xx_hal_dac.c | 21 +-
f4/src/stm32f4xx_hal_dac_ex.c | 20 +-
f4/src/stm32f4xx_hal_dcmi.c | 24 +-
f4/src/stm32f4xx_hal_dcmi_ex.c | 214 +
f4/src/stm32f4xx_hal_dma.c | 182 +-
f4/src/stm32f4xx_hal_dma2d.c | 16 +-
f4/src/stm32f4xx_hal_dma_ex.c | 6 +-
f4/src/stm32f4xx_hal_dsi.c | 2244 +++++
f4/src/stm32f4xx_hal_eth.c | 226 +-
f4/src/stm32f4xx_hal_flash.c | 184 +-
f4/src/stm32f4xx_hal_flash_ex.c | 183 +-
f4/src/stm32f4xx_hal_flash_ramfunc.c | 20 +-
f4/src/stm32f4xx_hal_fmpi2c.c | 4098 ++++++++
f4/src/stm32f4xx_hal_fmpi2c_ex.c | 326 +
f4/src/stm32f4xx_hal_gpio.c | 31 +-
f4/src/stm32f4xx_hal_hash.c | 85 +-
f4/src/stm32f4xx_hal_hash_ex.c | 81 +-
f4/src/stm32f4xx_hal_hcd.c | 125 +-
f4/src/stm32f4xx_hal_i2c.c | 256 +-
f4/src/stm32f4xx_hal_i2c_ex.c | 14 +-
f4/src/stm32f4xx_hal_i2s.c | 340 +-
f4/src/stm32f4xx_hal_i2s_ex.c | 733 +-
f4/src/stm32f4xx_hal_irda.c | 8 +-
f4/src/stm32f4xx_hal_iwdg.c | 8 +-
f4/src/stm32f4xx_hal_lptim.c | 1655 ++++
f4/src/stm32f4xx_hal_ltdc.c | 96 +-
f4/src/stm32f4xx_hal_ltdc_ex.c | 164 +
f4/src/stm32f4xx_hal_nand.c | 102 +-
f4/src/stm32f4xx_hal_nor.c | 256 +-
f4/src/stm32f4xx_hal_pccard.c | 75 +-
f4/src/stm32f4xx_hal_pcd.c | 169 +-
f4/src/stm32f4xx_hal_pcd_ex.c | 65 +-
f4/src/stm32f4xx_hal_pwr.c | 22 +-
f4/src/stm32f4xx_hal_pwr_ex.c | 216 +-
f4/src/stm32f4xx_hal_qspi.c | 1945 ++++
f4/src/stm32f4xx_hal_rcc.c | 135 +-
f4/src/stm32f4xx_hal_rcc_ex.c | 2139 ++++-
f4/src/stm32f4xx_hal_rng.c | 15 +-
f4/src/stm32f4xx_hal_rtc.c | 23 +-
f4/src/stm32f4xx_hal_rtc_ex.c | 91 +-
f4/src/stm32f4xx_hal_sai.c | 1263 ++-
f4/src/stm32f4xx_hal_sai_ex.c | 272 +
f4/src/stm32f4xx_hal_sd.c | 84 +-
f4/src/stm32f4xx_hal_sdram.c | 13 +-
f4/src/stm32f4xx_hal_smartcard.c | 131 +-
f4/src/stm32f4xx_hal_spdifrx.c | 1210 +++
f4/src/stm32f4xx_hal_spi.c | 212 +-
f4/src/stm32f4xx_hal_sram.c | 15 +-
f4/src/stm32f4xx_hal_tim.c | 24 +-
f4/src/stm32f4xx_hal_tim_ex.c | 7 +-
f4/src/stm32f4xx_hal_uart.c | 20 +-
f4/src/stm32f4xx_hal_usart.c | 8 +-
f4/src/stm32f4xx_hal_wwdg.c | 8 +-
f4/src/stm32f4xx_ll_fmc.c | 377 +-
f4/src/stm32f4xx_ll_fsmc.c | 14 +-
f4/src/stm32f4xx_ll_sdmmc.c | 16 +-
f4/src/stm32f4xx_ll_usb.c | 110 +-
159 files changed, 73953 insertions(+), 4999 deletions(-)
create mode 100644 f4/include/devices/stm32f410cx.h
create mode 100644 f4/include/devices/stm32f410rx.h
create mode 100644 f4/include/devices/stm32f410tx.h
create mode 100644 f4/include/devices/stm32f446xx.h
create mode 100644 f4/include/devices/stm32f469xx.h
create mode 100644 f4/include/devices/stm32f479xx.h
create mode 100644 f4/include/stm32f4xx_hal_cec.h
create mode 100644 f4/include/stm32f4xx_hal_dcmi_ex.h
create mode 100644 f4/include/stm32f4xx_hal_dsi.h
create mode 100644 f4/include/stm32f4xx_hal_fmpi2c.h
create mode 100644 f4/include/stm32f4xx_hal_fmpi2c_ex.h
create mode 100644 f4/include/stm32f4xx_hal_lptim.h
create mode 100644 f4/include/stm32f4xx_hal_ltdc_ex.h
create mode 100644 f4/include/stm32f4xx_hal_qspi.h
create mode 100644 f4/include/stm32f4xx_hal_sai_ex.h
create mode 100644 f4/include/stm32f4xx_hal_spdifrx.h
create mode 100644 f4/src/stm32f4xx_hal_cec.c
create mode 100644 f4/src/stm32f4xx_hal_dcmi_ex.c
create mode 100644 f4/src/stm32f4xx_hal_dsi.c
create mode 100644 f4/src/stm32f4xx_hal_fmpi2c.c
create mode 100644 f4/src/stm32f4xx_hal_fmpi2c_ex.c
create mode 100644 f4/src/stm32f4xx_hal_lptim.c
create mode 100644 f4/src/stm32f4xx_hal_ltdc_ex.c
create mode 100644 f4/src/stm32f4xx_hal_qspi.c
create mode 100644 f4/src/stm32f4xx_hal_sai_ex.c
create mode 100644 f4/src/stm32f4xx_hal_spdifrx.c
diff --git a/f4/include/Legacy/stm32_hal_legacy.h b/f4/include/Legacy/stm32_hal_legacy.h
index c301214..346f37d 100644
--- a/f4/include/Legacy/stm32_hal_legacy.h
+++ b/f4/include/Legacy/stm32_hal_legacy.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -30,7 +30,7 @@
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- UART * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
@@ -51,8 +51,8 @@
/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
* @{
*/
-#define AES_FLAG_RDERR CRYP_FLAG_RDERR
-#define AES_FLAG_WRERR CRYP_FLAG_WRERR
+#define AES_FLAG_RDERR CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR CRYP_FLAG_WRERR
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
@@ -87,14 +87,22 @@
#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
-
-
+#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
/**
* @}
*/
@@ -140,11 +148,45 @@
#define DAC1_CHANNEL_1 DAC_CHANNEL_1
#define DAC1_CHANNEL_2 DAC_CHANNEL_2
#define DAC2_CHANNEL_1 DAC_CHANNEL_1
+#define DAC_WAVE_NONE ((uint32_t)0x00000000)
+#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
+#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
+#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
/**
* @}
*/
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+
+
+/**
+ * @}
+ */
/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
* @{
@@ -182,7 +224,7 @@
#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
-#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
@@ -192,7 +234,6 @@
#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
-#define IS_NBSECTORS IS_FLASH_NBSECTORS
#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
@@ -212,7 +253,16 @@
#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
-
+#define OB_WDG_SW OB_IWDG_SW
+#define OB_WDG_HW OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
/**
* @}
*/
@@ -221,19 +271,38 @@
* @{
*/
-#define SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
-#define SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
-#define SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
-#define SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
-#define SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
-#define SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
-#define SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
-
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
/**
* @}
*/
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+ * @{
+ */
+#if defined(STM32L4) || defined(STM32F7)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
+#else
+#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+ * @}
+ */
+
/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
* @{
*/
@@ -249,10 +318,52 @@
*/
#define GET_GPIO_SOURCE GPIO_GET_INDEX
#define GET_GPIO_INDEX GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32F4)
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32F4 */
+
/**
* @}
*/
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+/**
+ * @}
+ */
/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
* @{
@@ -286,6 +397,34 @@
#define KR_KEY_ENABLE IWDG_KEY_ENABLE
#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
/**
* @}
*/
@@ -403,14 +542,27 @@
#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
-#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
/**
* @}
@@ -449,6 +601,8 @@
#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
/**
* @}
@@ -502,6 +656,7 @@
#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
#define TIM_DMABase_OR2 TIM_DMABASE_OR2
#define TIM_DMABase_OR3 TIM_DMABASE_OR3
+#define TIM_DMABase_OR TIM_DMABASE_OR
#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
@@ -532,6 +687,15 @@
#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
/**
* @}
*/
@@ -686,12 +850,12 @@
#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) ((cmd==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
-#define HAL_Lock_Cmd(cmd) ((cmd==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
-#define HAL_VREFINT_Cmd(cmd) ((cmd==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
-#define HAL_ADC_EnableBuffer_Cmd(cmd) ((cmd==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) ((cmd==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
/**
* @}
*/
@@ -717,7 +881,7 @@
#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
/**
* @}
*/
@@ -769,16 +933,6 @@
/**
* @}
*/
-
-/** @defgroup HAL_RCC_Aliased_Functions HAL RCC Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) ((cmd==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
-
- /**
- * @}
- */
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{
@@ -816,6 +970,14 @@
/**
* @}
*/
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+/**
+ * @}
+ */
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
@@ -847,9 +1009,14 @@
#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
+
#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
@@ -952,7 +1119,8 @@
#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
-
+#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
+
/**
* @}
*/
@@ -1044,6 +1212,18 @@
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+ ((WAVE) == DAC_WAVE_NOISE)|| \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
+
/**
* @}
*/
@@ -1056,6 +1236,8 @@
#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
#define IS_TYPEERASE IS_FLASH_TYPEERASE
+#define IS_NBSECTORS IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
/**
* @}
@@ -1136,6 +1318,29 @@
/**
* @}
*/
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
+
+/**
+ * @}
+ */
+
/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
* @{
@@ -1194,19 +1399,28 @@
*/
-/** @defgroup HAL_RCC_Aliased_Macros HAL RCC Aliased Macros maintained for legacy purpose
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
* @{
*/
+
+#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
@@ -1253,12 +1467,22 @@
#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
@@ -1277,6 +1501,10 @@
#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
@@ -1311,8 +1539,12 @@
#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
-#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
-#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
@@ -1623,9 +1855,31 @@
#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
-#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
-#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
+#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
+#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
+#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
+#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
+#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
+#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
+#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
+#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
@@ -1664,9 +1918,6 @@
#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
-#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
-#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
-#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
@@ -1767,57 +2018,321 @@
#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
-#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE
-#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE
-#define __OTGHS_FORCE_RESET __HAL_RCC_OTGHS_FORCE_RESET
-#define __OTGHS_RELEASE_RESET __HAL_RCC_OTGHS_RELEASE_RESET
-#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE
-#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE
-#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
-#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
-#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
-#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
-#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
-#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
-#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
-#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
-#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
-#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
-#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
-#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
+#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
-#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
/* alias define maintained for legacy */
#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define Sdmmc1ClockSelection SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
+#define SdioClockSelection Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
-#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
+#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV IS_RCC_PCLK
+
+#define RCC_IT_HSI14 RCC_IT_HSI14RDY
+
+#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV RCC_MCODIV_1
+#define RCC_MCO_DIV1 RCC_MCODIV_1
+#define RCC_MCO_DIV2 RCC_MCODIV_2
+#define RCC_MCO_DIV4 RCC_MCODIV_4
+#define RCC_MCO_DIV8 RCC_MCODIV_8
+#define RCC_MCO_DIV16 RCC_MCODIV_16
+#define RCC_MCO_DIV32 RCC_MCODIV_32
+#define RCC_MCO_DIV64 RCC_MCODIV_64
+#define RCC_MCO_DIV128 RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
+
+#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
#define HSION_BitNumber RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
#define LSION_BitNumber RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
-
+#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
@@ -1829,10 +2344,17 @@
#define CR_CSSON_BB RCC_CR_CSSON_BB
#define CR_PLLON_BB RCC_CR_PLLON_BB
#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB RCC_CR_MSION_BB
+#define CSR_LSION_BB RCC_CSR_LSION_BB
+#define CSR_LSEON_BB RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
-#define CSR_LSION_BB RCC_CSR_LSION_BB
+#define CR_HSEON_BB RCC_CR_HSEON_BB
+#define CSR_RMVF_BB RCC_CSR_RMVF_BB
#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
@@ -1843,7 +2365,7 @@
/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
* @{
*/
-#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback(__HANDLE__, uint32_t random32bit)
+#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
/**
* @}
@@ -1856,24 +2378,8 @@
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
-#if defined (RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
-((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
- ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
- ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
- ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
- ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
-#else
+#if defined (STM32F1)
#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
@@ -1883,8 +2389,23 @@
#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
-
-#endif
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif /* STM32F1 */
#define IS_ALARM IS_RTC_ALARM
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
@@ -1914,7 +2435,58 @@
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
-
+
+#if defined(STM32F4)
+#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
+#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
+#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
+#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
+#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
+#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
+#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
+#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
+#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
+#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
+#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
+#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
+#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
+#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
+#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
+#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
+#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
+#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
+#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define SDMMC1_IRQn SDIO_IRQn
+#define SDMMC1_IRQHandler SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
+#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
+#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
+#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
+#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
+#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
+#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
+#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
+#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
+#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
+#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
+#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
+#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
+#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
+#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
+#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
+#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define SDIO_IRQn SDMMC1_IRQn
+#define SDIO_IRQHandler SDMMC1_IRQHandler
+#endif
/**
* @}
*/
@@ -2060,6 +2632,8 @@
#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
+#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+
#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
diff --git a/f4/include/core/core_cm4.h b/f4/include/core/core_cm4.h
index 827dc38..544d414 100755
--- a/f4/include/core/core_cm4.h
+++ b/f4/include/core/core_cm4.h
@@ -1,13 +1,13 @@
/**************************************************************************//**
* @file core_cm4.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version V4.00
- * @date 22. August 2014
+ * @version V4.10
+ * @date 18. March 2015
*
* @note
*
******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
+/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -279,13 +279,9 @@ typedef union
{
struct
{
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
@@ -295,6 +291,25 @@ typedef union
uint32_t w; /*!< Type used for word access */
} APSR_Type;
+/* APSR Register Definitions */
+#define APSR_N_Pos 31 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27 /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16 /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
@@ -308,6 +323,10 @@ typedef union
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
@@ -316,13 +335,9 @@ typedef union
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
@@ -334,6 +349,34 @@ typedef union
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
/** \brief Union type to access the Control Registers (CONTROL).
*/
@@ -349,6 +392,16 @@ typedef union
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
/*@} end of group CMSIS_CORE */
@@ -379,7 +432,7 @@ typedef struct
/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
/*@} end of group CMSIS_NVIC */
@@ -431,7 +484,7 @@ typedef struct
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
@@ -462,7 +515,7 @@ typedef struct
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
@@ -488,7 +541,7 @@ typedef struct
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
@@ -517,7 +570,7 @@ typedef struct
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
@@ -560,7 +613,7 @@ typedef struct
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Registers Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
@@ -570,7 +623,7 @@ typedef struct
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* SCB Hard Fault Status Registers Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
@@ -596,7 +649,7 @@ typedef struct
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
/*@} end of group CMSIS_SCB */
@@ -618,7 +671,7 @@ typedef struct
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
@@ -634,7 +687,7 @@ typedef struct
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
@@ -666,15 +719,15 @@ typedef struct
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
@@ -684,7 +737,7 @@ typedef struct
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
@@ -735,7 +788,7 @@ typedef struct
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
@@ -763,19 +816,19 @@ typedef struct
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
/* ITM Integration Write Register Definitions */
#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
/* ITM Integration Read Register Definitions */
#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
/* ITM Integration Mode Control Register Definitions */
#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
@@ -785,7 +838,7 @@ typedef struct
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
@@ -878,31 +931,31 @@ typedef struct
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
/* DWT Comparator Mask Register Definitions */
#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
@@ -930,7 +983,7 @@ typedef struct
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
/*@}*/ /* end of group CMSIS_DWT */
@@ -973,11 +1026,11 @@ typedef struct
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
@@ -990,7 +1043,7 @@ typedef struct
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
@@ -1001,7 +1054,7 @@ typedef struct
/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
/* TPI Integration ETM Data Register Definitions (FIFO0) */
#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
@@ -1023,11 +1076,11 @@ typedef struct
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
@@ -1049,15 +1102,15 @@ typedef struct
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
@@ -1076,15 +1129,15 @@ typedef struct
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
-
#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
/*@}*/ /* end of group CMSIS_TPI */
@@ -1120,7 +1173,7 @@ typedef struct
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
@@ -1130,11 +1183,11 @@ typedef struct
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
@@ -1144,7 +1197,7 @@ typedef struct
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
@@ -1175,7 +1228,7 @@ typedef struct
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
@@ -1226,7 +1279,7 @@ typedef struct
#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
/* Floating-Point Context Address Register */
#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
@@ -1268,7 +1321,7 @@ typedef struct
#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
/* Media and FP Feature Register 1 */
#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
@@ -1281,7 +1334,7 @@ typedef struct
#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
/*@} end of group CMSIS_FPU */
#endif
@@ -1338,14 +1391,14 @@ typedef struct
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register */
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register */
#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
@@ -1385,7 +1438,7 @@ typedef struct
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
/*@} end of group CMSIS_CoreDebug */
@@ -1462,13 +1515,13 @@ typedef struct
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
SCB->AIRCR = reg_value;
}
@@ -1481,7 +1534,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
*/
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
@@ -1493,8 +1546,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
-/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
- NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1506,7 +1558,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1522,7 +1574,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
@@ -1534,7 +1586,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1546,7 +1598,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1561,7 +1613,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
@@ -1576,10 +1628,12 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
- if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ if((int32_t)IRQn < 0) {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
}
@@ -1597,10 +1651,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ if((int32_t)IRQn < 0) {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+ }
else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
+ }
}
@@ -1618,16 +1674,16 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
@@ -1646,15 +1702,15 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
@@ -1664,13 +1720,13 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1) { __NOP(); } /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
@@ -1703,15 +1759,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
}
#endif
@@ -1743,11 +1799,11 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
+ while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+ ITM->PORT[0].u8 = (uint8_t)ch;
}
return (ch);
}
diff --git a/f4/include/core/core_cmFunc.h b/f4/include/core/core_cmFunc.h
index a1bd88c..e3c057e 100755
--- a/f4/include/core/core_cmFunc.h
+++ b/f4/include/core/core_cmFunc.h
@@ -1,13 +1,13 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
- * @version V4.00
- * @date 28. August 2014
+ * @version V4.10
+ * @date 18. March 2015
*
* @note
*
******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
+/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -242,6 +242,20 @@ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
}
+/** \brief Set Base Priority with condition
+
+ This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xff);
+}
+
+
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
@@ -518,7 +532,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
return(result);
}
@@ -535,6 +549,19 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t v
}
+/** \brief Set Base Priority with condition
+
+ This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
diff --git a/f4/include/core/core_cmInstr.h b/f4/include/core/core_cmInstr.h
index cabf4a0..c8e045f 100755
--- a/f4/include/core/core_cmInstr.h
+++ b/f4/include/core/core_cmInstr.h
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
- * @version V4.00
- * @date 28. August 2014
+ * @version V4.10
+ * @date 18. March 2015
*
* @note
*
@@ -89,24 +89,33 @@
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
-#define __ISB() __isb(0xF)
-
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
-#define __DSB() __dsb(0xF)
-
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
-#define __DMB() __dmb(0xF)
-
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0)
/** \brief Reverse byte order (32 bit)
@@ -171,8 +180,6 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
#define __BKPT(value) __breakpoint(value)
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
@@ -180,8 +187,38 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\param [in] value Value to reverse
\return Reversed value
*/
-#define __RBIT __rbit
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+ result = value; // r will be reversed bits of v; first get LSB of v
+ for (value >>= 1; value; value >>= 1)
+ {
+ result <<= 1;
+ result |= value & 1;
+ s--;
+ }
+ result <<= s; // shift when v's highest bits are zero
+ return(result);
+}
+#endif
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
/** \brief LDR Exclusive (8 bit)
@@ -279,19 +316,10 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
#define __USAT __usat
-/** \brief Count leading zeros
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __clz
-
-
/** \brief Rotate Right with Extend (32 bit)
- This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+ This function moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
@@ -385,7 +413,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
@@ -396,7 +424,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
@@ -407,7 +435,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
@@ -417,7 +445,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
@@ -429,9 +457,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
{
- __ASM volatile ("isb");
+ __ASM volatile ("isb 0xF":::"memory");
}
@@ -440,9 +468,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
{
- __ASM volatile ("dsb");
+ __ASM volatile ("dsb 0xF":::"memory");
}
@@ -451,9 +479,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
{
- __ASM volatile ("dmb");
+ __ASM volatile ("dmb 0xF":::"memory");
}
@@ -464,7 +492,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
\param [in] value Value to reverse
\return Reversed value
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
@@ -484,7 +512,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value
\param [in] value Value to reverse
\return Reversed value
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
@@ -500,7 +528,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t val
\param [in] value Value to reverse
\return Reversed value
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
@@ -521,9 +549,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value
\param [in] value Number of Bits to rotate
\return Rotated value
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
- return (op1 >> op2) | (op1 << (32 - op2));
+ return (op1 >> op2) | (op1 << (32 - op2));
}
@@ -538,8 +566,6 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1,
#define __BKPT(value) __ASM volatile ("bkpt "#value)
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
@@ -547,15 +573,40 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1,
\param [in] value Value to reverse
\return Reversed value
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- return(result);
+#else
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+ result = value; // r will be reversed bits of v; first get LSB of v
+ for (value >>= 1; value; value >>= 1)
+ {
+ result <<= 1;
+ result |= value & 1;
+ s--;
+ }
+ result <<= s; // shift when v's highest bits are zero
+#endif
+ return(result);
}
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
/** \brief LDR Exclusive (8 bit)
This function executes a exclusive LDR instruction for 8 bit value.
@@ -563,7 +614,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t valu
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
@@ -586,7 +637,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uin
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
@@ -609,7 +660,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile ui
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
@@ -627,7 +678,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile ui
\return 0 Function succeeded
\return 1 Function failed
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
@@ -645,7 +696,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t val
\return 0 Function succeeded
\return 1 Function failed
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
@@ -663,7 +714,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t va
\return 0 Function succeeded
\return 1 Function failed
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
@@ -677,7 +728,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t va
This function removes the exclusive lock which is created by LDREX.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
@@ -715,30 +766,15 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
})
-/** \brief Count leading zeros
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
/** \brief Rotate Right with Extend (32 bit)
- This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+ This function moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
{
uint32_t result;
@@ -754,7 +790,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t result;
@@ -777,7 +813,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t result;
@@ -800,7 +836,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uin
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t result;
@@ -816,7 +852,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
}
@@ -829,7 +865,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, v
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
}
@@ -842,7 +878,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value,
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
}
diff --git a/f4/include/core/core_cmSimd.h b/f4/include/core/core_cmSimd.h
index 0466561..fd7214e 100755
--- a/f4/include/core/core_cmSimd.h
+++ b/f4/include/core/core_cmSimd.h
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
- * @version V4.00
- * @date 22. August 2014
+ * @version V4.10
+ * @date 18. March 2015
*
* @note
*
diff --git a/f4/include/devices/stm32f401xc.h b/f4/include/devices/stm32f401xc.h
index a477791..ee4e17f 100755
--- a/f4/include/devices/stm32f401xc.h
+++ b/f4/include/devices/stm32f401xc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f401xc.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 15-December-2014
+ * @version V2.4.1
+ * @date 09-October-2015
* @brief CMSIS STM32F401xCxx Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -665,15 +665,12 @@ USB_OTG_HostChannelTypeDef;
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
-#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END ((uint32_t)0x0803FFFF) /*!< FLASH end address */
/* Legacy defines */
@@ -1422,6 +1419,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -1444,6 +1444,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -1466,6 +1469,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -1488,6 +1494,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -1510,6 +1519,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -1532,6 +1544,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -2429,7 +2444,6 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
-#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
@@ -2625,7 +2639,7 @@ USB_OTG_HostChannelTypeDef;
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
diff --git a/f4/include/devices/stm32f401xe.h b/f4/include/devices/stm32f401xe.h
index 5d1d175..94b86ac 100755
--- a/f4/include/devices/stm32f401xe.h
+++ b/f4/include/devices/stm32f401xe.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f401xe.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 15-December-2014
+ * @version V2.4.1
+ * @date 09-October-2015
* @brief CMSIS STM32F401xExx Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -665,15 +665,12 @@ USB_OTG_HostChannelTypeDef;
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
-#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
/* Legacy defines */
@@ -1422,6 +1419,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -1444,6 +1444,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -1466,6 +1469,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -1488,6 +1494,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -1510,6 +1519,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -1532,6 +1544,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -2429,7 +2444,6 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
-#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
@@ -2625,7 +2639,7 @@ USB_OTG_HostChannelTypeDef;
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
diff --git a/f4/include/devices/stm32f405xx.h b/f4/include/devices/stm32f405xx.h
index c185d19..fa20b6c 100755
--- a/f4/include/devices/stm32f405xx.h
+++ b/f4/include/devices/stm32f405xx.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f405xx.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 15-December-2014
+ * @version V2.4.1
+ * @date 09-October-2015
* @brief CMSIS STM32F405xx Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -843,16 +843,13 @@ USB_OTG_HostChannelTypeDef;
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
-#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
@@ -3063,6 +3060,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -3085,6 +3085,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -3107,6 +3110,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -3129,6 +3135,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -3151,6 +3160,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -3173,6 +3185,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -3382,11 +3397,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3423,11 +3442,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3464,11 +3487,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3505,11 +3532,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3546,11 +3577,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3587,11 +3622,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3628,11 +3667,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3674,6 +3717,10 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -4589,11 +4636,9 @@ USB_OTG_HostChannelTypeDef;
#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
-#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
-#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
-#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
-#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
+#define PWR_CR_VOS ((uint32_t)0x00004000) /*!< VOS bit (Regulator voltage scaling output selection) */
/* Legacy define */
#define PWR_CR_PMODE PWR_CR_VOS
@@ -4806,7 +4851,7 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
-#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
@@ -4941,7 +4986,6 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
-#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
@@ -5170,7 +5214,7 @@ USB_OTG_HostChannelTypeDef;
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
diff --git a/f4/include/devices/stm32f407xx.h b/f4/include/devices/stm32f407xx.h
index 6b7ba0c..869963d 100755
--- a/f4/include/devices/stm32f407xx.h
+++ b/f4/include/devices/stm32f407xx.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f407xx.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 15-December-2014
+ * @version V2.4.1
+ * @date 09-October-2015
* @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -937,16 +937,13 @@ USB_OTG_HostChannelTypeDef;
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
-#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
@@ -3219,6 +3216,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -3241,6 +3241,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -3263,6 +3266,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -3285,6 +3291,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -3307,6 +3316,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -3329,6 +3341,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -3538,11 +3553,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3579,11 +3598,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3620,11 +3643,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3666,6 +3693,10 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3702,11 +3733,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3743,11 +3778,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3784,11 +3823,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3830,6 +3873,10 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -4745,11 +4792,9 @@ USB_OTG_HostChannelTypeDef;
#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
-#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
-#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
-#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
-#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
+#define PWR_CR_VOS ((uint32_t)0x00004000) /*!< VOS bit (Regulator voltage scaling output selection) */
/* Legacy define */
#define PWR_CR_PMODE PWR_CR_VOS
@@ -4963,7 +5008,7 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
-#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
@@ -5104,7 +5149,6 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
-#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
@@ -5338,7 +5382,7 @@ USB_OTG_HostChannelTypeDef;
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
diff --git a/f4/include/devices/stm32f410cx.h b/f4/include/devices/stm32f410cx.h
new file mode 100644
index 0000000..2632546
--- /dev/null
+++ b/f4/include/devices/stm32f410cx.h
@@ -0,0 +1,3971 @@
+/**
+ ******************************************************************************
+ * @file stm32f410cx.h
+ * @author MCD Application Team
+ * @version V2.4.1
+ * @date 09-October-2015
+ * @brief CMSIS STM32F410Cx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f410xx
+ * @{
+ */
+
+#ifndef __STM32F410xx_H
+#define __STM32F410xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1 global Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global Interrupt and DAC Global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ RNG_IRQn = 80, /*!< RNG global Interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
+ FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
+ LPTIM1_IRQn = 97 /*!< LPTIM1 interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED; /*!< Reserved, 0x18 */
+ uint32_t CFGR2; /*!< Reserved, 0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
+ __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
+} FMPI2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ uint32_t RESERVED0[3]; /*!< Reserved, 0x14-0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ uint32_t RESERVED4[3]; /*!< Reserved, 0x54-0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ uint32_t RESERVED7[2]; /*!< Reserved, 0x84-0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+ __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+/**
+ * @brief LPTIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(32 KB) base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(32 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define FLASH_END ((uint32_t)0x0801FFFF) /*!< FLASH end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
+
+/*!< APB1 peripherals */
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
+#define RNG_BASE (PERIPH_BASE + 0x80000)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t )0xE0042000)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
+#define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
+#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
+#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
+#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
+#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
+#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
+#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
+#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
+#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
+#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
+#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
+#define DMA_SxCR_ACK ((uint32_t)0x00100000)
+#define DMA_SxCR_CT ((uint32_t)0x00080000)
+#define DMA_SxCR_DBM ((uint32_t)0x00040000)
+#define DMA_SxCR_PL ((uint32_t)0x00030000)
+#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
+#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
+#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
+#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
+#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
+#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
+#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
+#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
+#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
+#define DMA_SxCR_MINC ((uint32_t)0x00000400)
+#define DMA_SxCR_PINC ((uint32_t)0x00000200)
+#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
+#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
+#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
+#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
+#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
+#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
+#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
+#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
+#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
+#define DMA_SxCR_EN ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT ((uint32_t)0x0000FFFF)
+#define DMA_SxNDT_0 ((uint32_t)0x00000001)
+#define DMA_SxNDT_1 ((uint32_t)0x00000002)
+#define DMA_SxNDT_2 ((uint32_t)0x00000004)
+#define DMA_SxNDT_3 ((uint32_t)0x00000008)
+#define DMA_SxNDT_4 ((uint32_t)0x00000010)
+#define DMA_SxNDT_5 ((uint32_t)0x00000020)
+#define DMA_SxNDT_6 ((uint32_t)0x00000040)
+#define DMA_SxNDT_7 ((uint32_t)0x00000080)
+#define DMA_SxNDT_8 ((uint32_t)0x00000100)
+#define DMA_SxNDT_9 ((uint32_t)0x00000200)
+#define DMA_SxNDT_10 ((uint32_t)0x00000400)
+#define DMA_SxNDT_11 ((uint32_t)0x00000800)
+#define DMA_SxNDT_12 ((uint32_t)0x00001000)
+#define DMA_SxNDT_13 ((uint32_t)0x00002000)
+#define DMA_SxNDT_14 ((uint32_t)0x00004000)
+#define DMA_SxNDT_15 ((uint32_t)0x00008000)
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
+#define DMA_SxFCR_FS ((uint32_t)0x00000038)
+#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
+#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
+#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
+#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
+#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
+#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
+#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
+#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
+#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
+#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
+#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
+#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
+#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
+#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
+#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
+#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
+#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
+#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
+#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
+#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
+#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
+#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
+#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
+#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
+#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
+#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
+#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
+#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
+#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
+#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
+#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
+#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
+#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
+#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
+#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
+#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
+#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
+#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
+#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
+#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
+#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
+#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
+#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
+#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
+#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
+#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
+#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
+#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
+#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
+#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
+#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
+#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
+#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
+#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
+#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
+#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
+#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
+#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
+#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
+#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
+#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
+#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
+#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
+#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
+#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
+#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
+#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
+#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
+#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
+#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
+#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
+#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
+#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
+#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
+#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
+#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
+#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
+#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
+#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
+#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
+#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
+#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
+#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
+#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
+#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
+#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
+#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
+#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
+#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
+#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
+#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
+#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
+
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
+#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
+#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
+#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
+#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
+#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
+#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP ((uint32_t)0x00000001)
+#define FLASH_SR_SOP ((uint32_t)0x00000002)
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
+#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
+#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
+#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
+#define FLASH_SR_BSY ((uint32_t)0x00010000)
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001)
+#define FLASH_CR_SER ((uint32_t)0x00000002)
+#define FLASH_CR_MER ((uint32_t)0x00000004)
+#define FLASH_CR_SNB ((uint32_t)0x000000F8)
+#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
+#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
+#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
+#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
+#define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
+#define FLASH_CR_PSIZE ((uint32_t)0x00000300)
+#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
+#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
+#define FLASH_CR_STRT ((uint32_t)0x00010000)
+#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
+#define FLASH_CR_LOCK ((uint32_t)0x80000000)
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
+#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
+#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
+#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
+#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
+
+#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
+#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
+#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
+#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
+#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
+#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
+#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
+#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
+#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
+#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
+#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
+#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
+#define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
+#define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
+#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
+#define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
+#define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
+#define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
+#define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
+#define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
+#define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
+#define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
+#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
+#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
+#define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
+#define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
+#define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
+#define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define FMPI2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
+#define FMPI2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
+#define FMPI2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
+#define FMPI2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
+#define FMPI2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
+#define FMPI2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
+#define FMPI2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
+#define FMPI2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
+#define FMPI2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define FMPI2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
+#define FMPI2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
+#define FMPI2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
+#define FMPI2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
+#define FMPI2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
+#define FMPI2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
+#define FMPI2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
+#define FMPI2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
+#define FMPI2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
+#define FMPI2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
+#define FMPI2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
+#define FMPI2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define FMPI2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
+#define FMPI2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
+#define FMPI2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
+#define FMPI2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
+#define FMPI2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
+#define FMPI2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
+#define FMPI2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
+#define FMPI2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
+#define FMPI2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
+#define FMPI2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
+#define FMPI2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define FMPI2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
+#define FMPI2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
+#define FMPI2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define FMPI2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define FMPI2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define FMPI2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define FMPI2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
+#define FMPI2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
+#define FMPI2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
+#define FMPI2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
+#define FMPI2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define FMPI2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
+#define FMPI2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
+#define FMPI2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
+#define FMPI2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B */
+#define FMPI2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define FMPI2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
+#define FMPI2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
+#define FMPI2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
+#define FMPI2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode) */
+#define FMPI2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
+#define FMPI2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
+#define FMPI2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
+#define FMPI2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
+#define FMPI2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
+#define FMPI2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
+#define FMPI2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
+#define FMPI2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
+#define FMPI2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
+#define FMPI2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
+#define FMPI2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
+#define FMPI2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
+#define FMPI2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define FMPI2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
+#define FMPI2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
+#define FMPI2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
+#define FMPI2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
+#define FMPI2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
+#define FMPI2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
+#define FMPI2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
+#define FMPI2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
+#define FMPI2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define FMPI2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define FMPI2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define FMPI2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
+
+#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define PWR_CR_FMSSR ((uint32_t)0x00100000) /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR ((uint32_t)0x00200000) /*!< Flash Interface Stop while System Run */
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
+#define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
+#define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001)
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000)
+#define RCC_CR_HSERDY ((uint32_t)0x00020000)
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
+#define RCC_CR_CSSON ((uint32_t)0x00080000)
+#define RCC_CR_PLLON ((uint32_t)0x01000000)
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
+#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
+#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
+#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
+#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
+#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
+#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
+
+#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
+#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
+#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
+#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
+#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
+#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
+#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
+#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
+#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
+#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
+#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
+#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
+
+#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
+
+#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
+#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
+#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
+#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
+#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
+
+#define RCC_PLLCFGR_PLLR ((uint32_t)0x70000000)
+#define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x10000000)
+#define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x20000000)
+#define RCC_PLLCFGR_PLLR_2 ((uint32_t)0x40000000)
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< MCO1EN configuration */
+#define RCC_CFGR_MCO1EN ((uint32_t)0x00000100) /*!< MCO1EN bit */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
+#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
+#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
+#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
+#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
+#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
+#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
+#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
+
+#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
+#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
+#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
+#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
+
+#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
+#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
+#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
+#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
+
+#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
+#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
+#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
+
+#define RCC_CIR_CSSF ((uint32_t)0x00000080)
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
+
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
+
+#define RCC_CIR_CSSC ((uint32_t)0x00800000)
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
+#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
+#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
+#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
+#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
+#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
+#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
+#define RCC_AHB1RSTR_RNGRST ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
+#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x00000200)
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
+#define RCC_APB1RSTR_FMPI2C1RST ((uint32_t)0x01000000)
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
+#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
+#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
+#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
+#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
+#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
+#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
+#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
+#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
+#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
+#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
+#define RCC_AHB1ENR_RNGEN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
+#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x00000200)
+#define RCC_APB1ENR_RTCAPBEN ((uint32_t)0x00000400)
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
+#define RCC_APB1ENR_FMPI2C1EN ((uint32_t)0x01000000)
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
+#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
+#define RCC_APB2ENR_EXTITEN ((uint32_t)0x00008000)
+#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
+#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
+#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
+#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
+#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
+#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
+#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
+#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
+#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
+#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
+#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
+#define RCC_AHB1LPENR_RNGLPEN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
+#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
+#define RCC_APB1LPENR_LPTIM1LPEN ((uint32_t)0x00000200)
+#define RCC_APB1LPENR_RTCAPBLPEN ((uint32_t)0x00000400)
+#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
+#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
+#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
+#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
+#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
+#define RCC_APB1LPENR_FMPI2C1LPEN ((uint32_t)0x01000000)
+#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
+#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
+#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
+#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
+#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
+#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
+#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
+#define RCC_APB2LPENR_EXTITLPEN ((uint32_t)0x00008000)
+#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
+#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
+#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
+#define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001)
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
+#define RCC_CSR_RMVF ((uint32_t)0x01000000)
+#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
+#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
+#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
+#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
+#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
+#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
+#define RCC_DCKCFGR_I2SSRC ((uint32_t)0x06000000)
+#define RCC_DCKCFGR_I2SSRC_0 ((uint32_t)0x02000000)
+#define RCC_DCKCFGR_I2SSRC_1 ((uint32_t)0x04000000)
+
+/******************** Bit definition for RCC_CKGATENR register **************/
+#define RCC_CKGATENR_AHB2APB1_CKEN ((uint32_t)0x00000001)
+#define RCC_CKGATENR_AHB2APB2_CKEN ((uint32_t)0x00000002)
+#define RCC_CKGATENR_CM4DBG_CKEN ((uint32_t)0x00000004)
+#define RCC_CKGATENR_SPARE_CKEN ((uint32_t)0x00000008)
+#define RCC_CKGATENR_SRAM_CKEN ((uint32_t)0x00000010)
+#define RCC_CKGATENR_FLITF_CKEN ((uint32_t)0x00000020)
+#define RCC_CKGATENR_RCC_CKEN ((uint32_t)0x00000040)
+
+/******************** Bit definition for RCC_DCKCFGR2 register **************/
+#define RCC_DCKCFGR2_FMPI2C1SEL ((uint32_t)0x00C00000)
+#define RCC_DCKCFGR2_FMPI2C1SEL_0 ((uint32_t)0x00400000)
+#define RCC_DCKCFGR2_FMPI2C1SEL_1 ((uint32_t)0x00800000)
+#define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0xC0000000)
+#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x40000000)
+#define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x80000000)
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN ((uint32_t)0x00000004)
+#define RNG_CR_IE ((uint32_t)0x00000008)
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY ((uint32_t)0x00000001)
+#define RNG_SR_CECS ((uint32_t)0x00000002)
+#define RNG_SR_SECS ((uint32_t)0x00000004)
+#define RNG_SR_CEIS ((uint32_t)0x00000020)
+#define RNG_SR_SEIS ((uint32_t)0x00000040)
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_DCE ((uint32_t)0x00000080)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
+#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
+#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
+
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
+#define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
+#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
+#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
+
+/****************** Bit definition for SYSCFG_CFGR register *****************/
+#define SYSCFG_CFGR_FMPI2C1_SCL ((uint32_t)0x00000001) /*!<FM+ drive capability for FMPI2C1_SCL pin */
+#define SYSCFG_CFGR_FMPI2C1_SDA ((uint32_t)0x00000002) /*!<FM+ drive capability for FMPI2C1_SDA pin */
+
+/****************** Bit definition for SYSCFG_CFGR2 register *****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!<Core Lockup lock */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!<PVD Lock */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
+
+#define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /*!< Compare match */
+#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /*!< Bit 0 */
+#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /*!< Bit 1 */
+
+#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+
+#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /*!< Timout enable */
+#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT ((uint32_t)0x00080002) /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!< Counter register */
+
+/****************** Bit definition for LPTIM_OR register *******************/
+#define LPTIM_OR_OR ((uint32_t)0x00000003) /*!< LPTIMER[1:0] bits (Remap selection) */
+#define LPTIM_OR_OR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define LPTIM_OR_OR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
+#define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
+#define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
+#define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
+#define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
+#define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
+#define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
+#define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
+#define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
+#define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
+#define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
+#define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
+#define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
+#define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
+#define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
+#define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
+
+#define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI5))
+
+/******************************* LPTIM Instances ******************************/
+#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI5))
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI5))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM11))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM9))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/***************************** FMPI2C Instances *******************************/
+#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F410xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/include/devices/stm32f410rx.h b/f4/include/devices/stm32f410rx.h
new file mode 100644
index 0000000..74c7298
--- /dev/null
+++ b/f4/include/devices/stm32f410rx.h
@@ -0,0 +1,3975 @@
+/**
+ ******************************************************************************
+ * @file stm32f410rx.h
+ * @author MCD Application Team
+ * @version V2.4.1
+ * @date 09-October-2015
+ * @brief CMSIS STM32F410Rx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f410xx
+ * @{
+ */
+
+#ifndef __STM32F410xx_H
+#define __STM32F410xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1 global Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global Interrupt and DAC Global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ RNG_IRQn = 80, /*!< RNG global Interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
+ FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
+ LPTIM1_IRQn = 97 /*!< LPTIM1 interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED; /*!< Reserved, 0x18 */
+ uint32_t CFGR2; /*!< Reserved, 0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
+ __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
+} FMPI2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ uint32_t RESERVED0[3]; /*!< Reserved, 0x14-0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ uint32_t RESERVED4[3]; /*!< Reserved, 0x54-0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ uint32_t RESERVED7[2]; /*!< Reserved, 0x84-0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+ __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+/**
+ * @brief LPTIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(32 KB) base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(32 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define FLASH_END ((uint32_t)0x0801FFFF) /*!< FLASH end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
+
+/*!< APB1 peripherals */
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
+#define RNG_BASE (PERIPH_BASE + 0x80000)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t )0xE0042000)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
+#define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
+#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
+#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
+#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
+#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
+#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
+#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
+#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
+#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
+#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
+#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
+#define DMA_SxCR_ACK ((uint32_t)0x00100000)
+#define DMA_SxCR_CT ((uint32_t)0x00080000)
+#define DMA_SxCR_DBM ((uint32_t)0x00040000)
+#define DMA_SxCR_PL ((uint32_t)0x00030000)
+#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
+#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
+#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
+#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
+#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
+#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
+#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
+#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
+#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
+#define DMA_SxCR_MINC ((uint32_t)0x00000400)
+#define DMA_SxCR_PINC ((uint32_t)0x00000200)
+#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
+#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
+#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
+#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
+#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
+#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
+#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
+#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
+#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
+#define DMA_SxCR_EN ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT ((uint32_t)0x0000FFFF)
+#define DMA_SxNDT_0 ((uint32_t)0x00000001)
+#define DMA_SxNDT_1 ((uint32_t)0x00000002)
+#define DMA_SxNDT_2 ((uint32_t)0x00000004)
+#define DMA_SxNDT_3 ((uint32_t)0x00000008)
+#define DMA_SxNDT_4 ((uint32_t)0x00000010)
+#define DMA_SxNDT_5 ((uint32_t)0x00000020)
+#define DMA_SxNDT_6 ((uint32_t)0x00000040)
+#define DMA_SxNDT_7 ((uint32_t)0x00000080)
+#define DMA_SxNDT_8 ((uint32_t)0x00000100)
+#define DMA_SxNDT_9 ((uint32_t)0x00000200)
+#define DMA_SxNDT_10 ((uint32_t)0x00000400)
+#define DMA_SxNDT_11 ((uint32_t)0x00000800)
+#define DMA_SxNDT_12 ((uint32_t)0x00001000)
+#define DMA_SxNDT_13 ((uint32_t)0x00002000)
+#define DMA_SxNDT_14 ((uint32_t)0x00004000)
+#define DMA_SxNDT_15 ((uint32_t)0x00008000)
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
+#define DMA_SxFCR_FS ((uint32_t)0x00000038)
+#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
+#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
+#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
+#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
+#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
+#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
+#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
+#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
+#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
+#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
+#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
+#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
+#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
+#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
+#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
+#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
+#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
+#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
+#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
+#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
+#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
+#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
+#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
+#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
+#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
+#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
+#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
+#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
+#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
+#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
+#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
+#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
+#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
+#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
+#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
+#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
+#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
+#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
+#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
+#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
+#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
+#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
+#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
+#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
+#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
+#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
+#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
+#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
+#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
+#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
+#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
+#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
+#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
+#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
+#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
+#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
+#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
+#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
+#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
+#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
+#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
+#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
+#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
+#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
+#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
+#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
+#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
+#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
+#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
+#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
+#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
+#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
+#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
+#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
+#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
+#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
+#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
+#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
+#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
+#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
+#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
+#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
+#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
+#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
+#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
+#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
+#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
+#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
+#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
+#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
+#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
+#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
+
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
+#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
+#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
+#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
+#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
+#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
+#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP ((uint32_t)0x00000001)
+#define FLASH_SR_SOP ((uint32_t)0x00000002)
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
+#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
+#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
+#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
+#define FLASH_SR_BSY ((uint32_t)0x00010000)
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001)
+#define FLASH_CR_SER ((uint32_t)0x00000002)
+#define FLASH_CR_MER ((uint32_t)0x00000004)
+#define FLASH_CR_SNB ((uint32_t)0x000000F8)
+#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
+#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
+#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
+#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
+#define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
+#define FLASH_CR_PSIZE ((uint32_t)0x00000300)
+#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
+#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
+#define FLASH_CR_STRT ((uint32_t)0x00010000)
+#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
+#define FLASH_CR_LOCK ((uint32_t)0x80000000)
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
+#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
+#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
+#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
+#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
+
+#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
+#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
+#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
+#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
+#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
+#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
+#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
+#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
+#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
+#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
+#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
+#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
+#define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
+#define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
+#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
+#define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
+#define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
+#define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
+#define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
+#define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
+#define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
+#define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
+#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
+#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
+#define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
+#define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
+#define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
+#define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define FMPI2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
+#define FMPI2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
+#define FMPI2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
+#define FMPI2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
+#define FMPI2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
+#define FMPI2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
+#define FMPI2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
+#define FMPI2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
+#define FMPI2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define FMPI2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
+#define FMPI2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
+#define FMPI2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
+#define FMPI2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
+#define FMPI2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
+#define FMPI2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
+#define FMPI2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
+#define FMPI2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
+#define FMPI2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
+#define FMPI2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
+#define FMPI2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
+#define FMPI2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define FMPI2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
+#define FMPI2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
+#define FMPI2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
+#define FMPI2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
+#define FMPI2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
+#define FMPI2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
+#define FMPI2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
+#define FMPI2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
+#define FMPI2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
+#define FMPI2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
+#define FMPI2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define FMPI2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
+#define FMPI2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
+#define FMPI2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define FMPI2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define FMPI2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define FMPI2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define FMPI2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
+#define FMPI2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
+#define FMPI2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
+#define FMPI2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
+#define FMPI2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define FMPI2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
+#define FMPI2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
+#define FMPI2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
+#define FMPI2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B */
+#define FMPI2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define FMPI2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
+#define FMPI2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
+#define FMPI2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
+#define FMPI2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode) */
+#define FMPI2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
+#define FMPI2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
+#define FMPI2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
+#define FMPI2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
+#define FMPI2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
+#define FMPI2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
+#define FMPI2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
+#define FMPI2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
+#define FMPI2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
+#define FMPI2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
+#define FMPI2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
+#define FMPI2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
+#define FMPI2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define FMPI2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
+#define FMPI2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
+#define FMPI2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
+#define FMPI2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
+#define FMPI2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
+#define FMPI2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
+#define FMPI2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
+#define FMPI2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
+#define FMPI2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define FMPI2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define FMPI2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define FMPI2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
+
+#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define PWR_CR_FMSSR ((uint32_t)0x00100000) /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR ((uint32_t)0x00200000) /*!< Flash Interface Stop while System Run */
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
+#define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
+#define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001)
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000)
+#define RCC_CR_HSERDY ((uint32_t)0x00020000)
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
+#define RCC_CR_CSSON ((uint32_t)0x00080000)
+#define RCC_CR_PLLON ((uint32_t)0x01000000)
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
+#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
+#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
+#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
+#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
+#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
+#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
+
+#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
+#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
+#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
+#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
+#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
+#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
+#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
+#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
+#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
+#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
+#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
+#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
+
+#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
+
+#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
+#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
+#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
+#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
+#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
+
+#define RCC_PLLCFGR_PLLR ((uint32_t)0x70000000)
+#define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x10000000)
+#define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x20000000)
+#define RCC_PLLCFGR_PLLR_2 ((uint32_t)0x40000000)
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< MCO1EN configuration */
+#define RCC_CFGR_MCO1EN ((uint32_t)0x00000100) /*!< MCO1EN bit */
+
+/*!< MCO2EN configuration */
+#define RCC_CFGR_MCO2EN ((uint32_t)0x00000200) /*!< MCO2EN bit */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
+#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
+#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
+#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
+#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
+#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
+#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
+#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
+
+#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
+#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
+#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
+#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
+
+#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
+#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
+#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
+#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
+
+#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
+#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
+#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
+
+#define RCC_CIR_CSSF ((uint32_t)0x00000080)
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
+
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
+
+#define RCC_CIR_CSSC ((uint32_t)0x00800000)
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
+#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
+#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
+#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
+#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
+#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
+#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
+#define RCC_AHB1RSTR_RNGRST ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
+#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x00000200)
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
+#define RCC_APB1RSTR_FMPI2C1RST ((uint32_t)0x01000000)
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
+#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
+#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
+#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
+#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
+#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
+#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
+#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
+#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
+#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
+#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
+#define RCC_AHB1ENR_RNGEN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
+#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x00000200)
+#define RCC_APB1ENR_RTCAPBEN ((uint32_t)0x00000400)
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
+#define RCC_APB1ENR_FMPI2C1EN ((uint32_t)0x01000000)
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
+#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
+#define RCC_APB2ENR_EXTITEN ((uint32_t)0x00008000)
+#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
+#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
+#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
+#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
+#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
+#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
+#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
+#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
+#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
+#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
+#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
+#define RCC_AHB1LPENR_RNGLPEN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
+#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
+#define RCC_APB1LPENR_LPTIM1LPEN ((uint32_t)0x00000200)
+#define RCC_APB1LPENR_RTCAPBLPEN ((uint32_t)0x00000400)
+#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
+#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
+#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
+#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
+#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
+#define RCC_APB1LPENR_FMPI2C1LPEN ((uint32_t)0x01000000)
+#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
+#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
+#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
+#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
+#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
+#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
+#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
+#define RCC_APB2LPENR_EXTITLPEN ((uint32_t)0x00008000)
+#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
+#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
+#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
+#define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001)
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
+#define RCC_CSR_RMVF ((uint32_t)0x01000000)
+#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
+#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
+#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
+#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
+#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
+#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
+#define RCC_DCKCFGR_I2SSRC ((uint32_t)0x06000000)
+#define RCC_DCKCFGR_I2SSRC_0 ((uint32_t)0x02000000)
+#define RCC_DCKCFGR_I2SSRC_1 ((uint32_t)0x04000000)
+
+/******************** Bit definition for RCC_CKGATENR register **************/
+#define RCC_CKGATENR_AHB2APB1_CKEN ((uint32_t)0x00000001)
+#define RCC_CKGATENR_AHB2APB2_CKEN ((uint32_t)0x00000002)
+#define RCC_CKGATENR_CM4DBG_CKEN ((uint32_t)0x00000004)
+#define RCC_CKGATENR_SPARE_CKEN ((uint32_t)0x00000008)
+#define RCC_CKGATENR_SRAM_CKEN ((uint32_t)0x00000010)
+#define RCC_CKGATENR_FLITF_CKEN ((uint32_t)0x00000020)
+#define RCC_CKGATENR_RCC_CKEN ((uint32_t)0x00000040)
+
+/******************** Bit definition for RCC_DCKCFGR2 register **************/
+#define RCC_DCKCFGR2_FMPI2C1SEL ((uint32_t)0x00C00000)
+#define RCC_DCKCFGR2_FMPI2C1SEL_0 ((uint32_t)0x00400000)
+#define RCC_DCKCFGR2_FMPI2C1SEL_1 ((uint32_t)0x00800000)
+#define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0xC0000000)
+#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x40000000)
+#define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x80000000)
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN ((uint32_t)0x00000004)
+#define RNG_CR_IE ((uint32_t)0x00000008)
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY ((uint32_t)0x00000001)
+#define RNG_SR_CECS ((uint32_t)0x00000002)
+#define RNG_SR_SECS ((uint32_t)0x00000004)
+#define RNG_SR_CEIS ((uint32_t)0x00000020)
+#define RNG_SR_SEIS ((uint32_t)0x00000040)
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_DCE ((uint32_t)0x00000080)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
+#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
+#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
+
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
+#define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
+#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
+#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
+
+/****************** Bit definition for SYSCFG_CFGR register *****************/
+#define SYSCFG_CFGR_FMPI2C1_SCL ((uint32_t)0x00000001) /*!<FM+ drive capability for FMPI2C1_SCL pin */
+#define SYSCFG_CFGR_FMPI2C1_SDA ((uint32_t)0x00000002) /*!<FM+ drive capability for FMPI2C1_SDA pin */
+
+/****************** Bit definition for SYSCFG_CFGR2 register *****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!<Core Lockup lock */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!<PVD Lock */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
+
+#define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /*!< Compare match */
+#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /*!< Bit 0 */
+#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /*!< Bit 1 */
+
+#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+
+#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /*!< Timout enable */
+#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT ((uint32_t)0x00080002) /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!< Counter register */
+
+/****************** Bit definition for LPTIM_OR register *******************/
+#define LPTIM_OR_OR ((uint32_t)0x00000003) /*!< LPTIMER[1:0] bits (Remap selection) */
+#define LPTIM_OR_OR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define LPTIM_OR_OR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
+#define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
+#define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
+#define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
+#define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
+#define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
+#define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
+#define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
+#define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
+#define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
+#define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
+#define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
+#define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
+#define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
+#define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
+#define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
+
+#define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI5))
+
+/******************************* LPTIM Instances ******************************/
+#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI5))
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI5))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM11))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM9))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/***************************** FMPI2C Instances *******************************/
+#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F410xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/include/devices/stm32f410tx.h b/f4/include/devices/stm32f410tx.h
new file mode 100644
index 0000000..b56e037
--- /dev/null
+++ b/f4/include/devices/stm32f410tx.h
@@ -0,0 +1,3941 @@
+/**
+ ******************************************************************************
+ * @file stm32f410tx.h
+ * @author MCD Application Team
+ * @version V2.4.1
+ * @date 09-October-2015
+ * @brief CMSIS STM32F410Tx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f410xx
+ * @{
+ */
+
+#ifndef __STM32F410xx_H
+#define __STM32F410xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1 global Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global Interrupt and DAC Global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ RNG_IRQn = 80, /*!< RNG global Interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
+ FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
+ LPTIM1_IRQn = 97 /*!< LPTIM1 interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED; /*!< Reserved, 0x18 */
+ uint32_t CFGR2; /*!< Reserved, 0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
+ __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
+} FMPI2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ uint32_t RESERVED0[3]; /*!< Reserved, 0x14-0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ uint32_t RESERVED4[3]; /*!< Reserved, 0x54-0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ uint32_t RESERVED7[2]; /*!< Reserved, 0x84-0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+ __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+/**
+ * @brief LPTIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(32 KB) base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(32 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define FLASH_END ((uint32_t)0x0801FFFF) /*!< FLASH end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
+
+/*!< APB1 peripherals */
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
+#define RNG_BASE (PERIPH_BASE + 0x80000)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t )0xE0042000)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
+#define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
+#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
+#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
+#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
+#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
+#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
+#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
+#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
+#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
+#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
+#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
+#define DMA_SxCR_ACK ((uint32_t)0x00100000)
+#define DMA_SxCR_CT ((uint32_t)0x00080000)
+#define DMA_SxCR_DBM ((uint32_t)0x00040000)
+#define DMA_SxCR_PL ((uint32_t)0x00030000)
+#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
+#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
+#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
+#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
+#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
+#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
+#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
+#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
+#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
+#define DMA_SxCR_MINC ((uint32_t)0x00000400)
+#define DMA_SxCR_PINC ((uint32_t)0x00000200)
+#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
+#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
+#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
+#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
+#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
+#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
+#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
+#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
+#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
+#define DMA_SxCR_EN ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT ((uint32_t)0x0000FFFF)
+#define DMA_SxNDT_0 ((uint32_t)0x00000001)
+#define DMA_SxNDT_1 ((uint32_t)0x00000002)
+#define DMA_SxNDT_2 ((uint32_t)0x00000004)
+#define DMA_SxNDT_3 ((uint32_t)0x00000008)
+#define DMA_SxNDT_4 ((uint32_t)0x00000010)
+#define DMA_SxNDT_5 ((uint32_t)0x00000020)
+#define DMA_SxNDT_6 ((uint32_t)0x00000040)
+#define DMA_SxNDT_7 ((uint32_t)0x00000080)
+#define DMA_SxNDT_8 ((uint32_t)0x00000100)
+#define DMA_SxNDT_9 ((uint32_t)0x00000200)
+#define DMA_SxNDT_10 ((uint32_t)0x00000400)
+#define DMA_SxNDT_11 ((uint32_t)0x00000800)
+#define DMA_SxNDT_12 ((uint32_t)0x00001000)
+#define DMA_SxNDT_13 ((uint32_t)0x00002000)
+#define DMA_SxNDT_14 ((uint32_t)0x00004000)
+#define DMA_SxNDT_15 ((uint32_t)0x00008000)
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
+#define DMA_SxFCR_FS ((uint32_t)0x00000038)
+#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
+#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
+#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
+#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
+#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
+#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
+#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
+#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
+#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
+#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
+#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
+#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
+#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
+#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
+#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
+#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
+#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
+#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
+#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
+#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
+#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
+#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
+#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
+#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
+#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
+#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
+#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
+#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
+#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
+#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
+#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
+#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
+#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
+#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
+#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
+#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
+#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
+#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
+#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
+#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
+#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
+#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
+#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
+#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
+#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
+#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
+#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
+#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
+#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
+#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
+#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
+#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
+#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
+#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
+#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
+#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
+#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
+#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
+#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
+#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
+#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
+#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
+#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
+#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
+#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
+#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
+#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
+#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
+#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
+#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
+#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
+#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
+#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
+#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
+#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
+#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
+#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
+#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
+#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
+#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
+#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
+#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
+#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
+#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
+#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
+#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
+#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
+#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
+#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
+#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
+#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
+#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
+
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
+#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
+#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
+#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
+#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
+#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
+#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP ((uint32_t)0x00000001)
+#define FLASH_SR_SOP ((uint32_t)0x00000002)
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
+#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
+#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
+#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
+#define FLASH_SR_BSY ((uint32_t)0x00010000)
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001)
+#define FLASH_CR_SER ((uint32_t)0x00000002)
+#define FLASH_CR_MER ((uint32_t)0x00000004)
+#define FLASH_CR_SNB ((uint32_t)0x000000F8)
+#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
+#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
+#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
+#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
+#define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
+#define FLASH_CR_PSIZE ((uint32_t)0x00000300)
+#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
+#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
+#define FLASH_CR_STRT ((uint32_t)0x00010000)
+#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
+#define FLASH_CR_LOCK ((uint32_t)0x80000000)
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
+#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
+#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
+#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
+#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
+
+#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
+#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
+#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
+#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
+#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
+#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
+#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
+#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
+#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
+#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
+#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
+#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
+#define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
+#define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
+#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
+#define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
+#define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
+#define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
+#define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
+#define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
+#define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
+#define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
+#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
+#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
+#define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
+#define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
+#define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
+#define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define FMPI2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
+#define FMPI2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
+#define FMPI2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
+#define FMPI2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
+#define FMPI2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
+#define FMPI2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
+#define FMPI2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
+#define FMPI2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
+#define FMPI2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define FMPI2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
+#define FMPI2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
+#define FMPI2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
+#define FMPI2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
+#define FMPI2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
+#define FMPI2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
+#define FMPI2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
+#define FMPI2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
+#define FMPI2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
+#define FMPI2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define FMPI2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
+#define FMPI2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
+#define FMPI2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
+#define FMPI2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
+#define FMPI2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
+#define FMPI2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
+#define FMPI2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
+#define FMPI2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
+#define FMPI2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
+#define FMPI2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
+#define FMPI2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define FMPI2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
+#define FMPI2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
+#define FMPI2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define FMPI2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define FMPI2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define FMPI2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define FMPI2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
+#define FMPI2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
+#define FMPI2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
+#define FMPI2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
+#define FMPI2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define FMPI2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
+#define FMPI2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
+#define FMPI2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
+#define FMPI2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B */
+#define FMPI2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define FMPI2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
+#define FMPI2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
+#define FMPI2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
+#define FMPI2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode) */
+#define FMPI2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
+#define FMPI2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
+#define FMPI2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
+#define FMPI2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
+#define FMPI2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
+#define FMPI2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
+#define FMPI2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
+#define FMPI2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
+#define FMPI2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
+#define FMPI2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
+#define FMPI2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
+#define FMPI2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
+#define FMPI2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define FMPI2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
+#define FMPI2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
+#define FMPI2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
+#define FMPI2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
+#define FMPI2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
+#define FMPI2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
+#define FMPI2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
+#define FMPI2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
+#define FMPI2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define FMPI2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define FMPI2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define FMPI2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
+
+#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define PWR_CR_FMSSR ((uint32_t)0x00100000) /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR ((uint32_t)0x00200000) /*!< Flash Interface Stop while System Run */
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
+#define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
+#define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001)
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000)
+#define RCC_CR_HSERDY ((uint32_t)0x00020000)
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
+#define RCC_CR_CSSON ((uint32_t)0x00080000)
+#define RCC_CR_PLLON ((uint32_t)0x01000000)
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
+#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
+#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
+#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
+#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
+#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
+#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
+
+#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
+#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
+#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
+#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
+#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
+#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
+#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
+#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
+#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
+#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
+#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
+#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
+
+#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
+
+#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
+#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
+#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
+#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
+#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
+
+#define RCC_PLLCFGR_PLLR ((uint32_t)0x70000000)
+#define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x10000000)
+#define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x20000000)
+#define RCC_PLLCFGR_PLLR_2 ((uint32_t)0x40000000)
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< MCO1EN configuration */
+#define RCC_CFGR_MCO1EN ((uint32_t)0x00000100) /*!< MCO1EN bit */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
+#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
+#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
+#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
+#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
+#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
+#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
+#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
+
+#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
+#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
+#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
+#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
+
+#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
+#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
+#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
+#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
+
+#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
+#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
+#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
+
+#define RCC_CIR_CSSF ((uint32_t)0x00000080)
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
+
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
+
+#define RCC_CIR_CSSC ((uint32_t)0x00800000)
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
+#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
+#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
+#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
+#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
+#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
+#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
+#define RCC_AHB1RSTR_RNGRST ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
+#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x00000200)
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
+#define RCC_APB1RSTR_FMPI2C1RST ((uint32_t)0x01000000)
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
+#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
+#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
+#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
+#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
+#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
+#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
+#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
+#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
+#define RCC_AHB1ENR_RNGEN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
+#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x00000200)
+#define RCC_APB1ENR_RTCAPBEN ((uint32_t)0x00000400)
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
+#define RCC_APB1ENR_FMPI2C1EN ((uint32_t)0x01000000)
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
+#define RCC_APB2ENR_EXTITEN ((uint32_t)0x00008000)
+#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
+#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
+#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
+#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
+#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
+#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
+#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
+#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
+#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
+#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
+#define RCC_AHB1LPENR_RNGLPEN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
+#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
+#define RCC_APB1LPENR_LPTIM1LPEN ((uint32_t)0x00000200)
+#define RCC_APB1LPENR_RTCAPBLPEN ((uint32_t)0x00000400)
+#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
+#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
+#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
+#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
+#define RCC_APB1LPENR_FMPI2C1LPEN ((uint32_t)0x01000000)
+#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
+#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
+#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
+#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
+#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
+#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
+#define RCC_APB2LPENR_EXTITLPEN ((uint32_t)0x00008000)
+#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
+#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
+#define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001)
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
+#define RCC_CSR_RMVF ((uint32_t)0x01000000)
+#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
+#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
+#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
+#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
+#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
+#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
+#define RCC_DCKCFGR_I2SSRC ((uint32_t)0x06000000)
+#define RCC_DCKCFGR_I2SSRC_0 ((uint32_t)0x02000000)
+#define RCC_DCKCFGR_I2SSRC_1 ((uint32_t)0x04000000)
+
+/******************** Bit definition for RCC_CKGATENR register **************/
+#define RCC_CKGATENR_AHB2APB1_CKEN ((uint32_t)0x00000001)
+#define RCC_CKGATENR_AHB2APB2_CKEN ((uint32_t)0x00000002)
+#define RCC_CKGATENR_CM4DBG_CKEN ((uint32_t)0x00000004)
+#define RCC_CKGATENR_SPARE_CKEN ((uint32_t)0x00000008)
+#define RCC_CKGATENR_SRAM_CKEN ((uint32_t)0x00000010)
+#define RCC_CKGATENR_FLITF_CKEN ((uint32_t)0x00000020)
+#define RCC_CKGATENR_RCC_CKEN ((uint32_t)0x00000040)
+
+/******************** Bit definition for RCC_DCKCFGR2 register **************/
+#define RCC_DCKCFGR2_FMPI2C1SEL ((uint32_t)0x00C00000)
+#define RCC_DCKCFGR2_FMPI2C1SEL_0 ((uint32_t)0x00400000)
+#define RCC_DCKCFGR2_FMPI2C1SEL_1 ((uint32_t)0x00800000)
+#define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0xC0000000)
+#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x40000000)
+#define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x80000000)
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN ((uint32_t)0x00000004)
+#define RNG_CR_IE ((uint32_t)0x00000008)
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY ((uint32_t)0x00000001)
+#define RNG_SR_CECS ((uint32_t)0x00000002)
+#define RNG_SR_SECS ((uint32_t)0x00000004)
+#define RNG_SR_CEIS ((uint32_t)0x00000020)
+#define RNG_SR_SEIS ((uint32_t)0x00000040)
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_DCE ((uint32_t)0x00000080)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
+#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
+#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
+
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
+#define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
+#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
+#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
+
+/****************** Bit definition for SYSCFG_CFGR register *****************/
+#define SYSCFG_CFGR_FMPI2C1_SCL ((uint32_t)0x00000001) /*!<FM+ drive capability for FMPI2C1_SCL pin */
+#define SYSCFG_CFGR_FMPI2C1_SDA ((uint32_t)0x00000002) /*!<FM+ drive capability for FMPI2C1_SDA pin */
+
+/****************** Bit definition for SYSCFG_CFGR2 register *****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!<Core Lockup lock */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!<PVD Lock */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
+
+#define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /*!< Compare match */
+#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /*!< Bit 0 */
+#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /*!< Bit 1 */
+
+#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+
+#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /*!< Timout enable */
+#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT ((uint32_t)0x00080002) /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!< Counter register */
+
+/****************** Bit definition for LPTIM_OR register *******************/
+#define LPTIM_OR_OR ((uint32_t)0x00000003) /*!< LPTIMER[1:0] bits (Remap selection) */
+#define LPTIM_OR_OR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define LPTIM_OR_OR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
+#define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
+#define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
+#define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
+#define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
+#define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
+#define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
+#define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
+#define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
+#define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
+#define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
+#define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
+#define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
+#define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
+#define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
+#define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
+
+#define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
+
+/******************************* LPTIM Instances ******************************/
+#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) ((INSTANCE) == SPI1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM11))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM9))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (0)
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/***************************** FMPI2C Instances *******************************/
+#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F410xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/include/devices/stm32f411xe.h b/f4/include/devices/stm32f411xe.h
index 304a50b..4c719b8 100755
--- a/f4/include/devices/stm32f411xe.h
+++ b/f4/include/devices/stm32f411xe.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f411xe.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 15-December-2014
+ * @version V2.4.1
+ * @date 09-October-2015
* @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -667,15 +667,12 @@ USB_OTG_HostChannelTypeDef;
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
-#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
/* Legacy defines */
@@ -1426,6 +1423,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -1448,6 +1448,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -1470,6 +1473,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -1492,6 +1498,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -1514,6 +1523,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -1536,6 +1548,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -2438,7 +2453,6 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
-#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
@@ -2645,7 +2659,7 @@ USB_OTG_HostChannelTypeDef;
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
diff --git a/f4/include/devices/stm32f415xx.h b/f4/include/devices/stm32f415xx.h
index c613a66..4134665 100755
--- a/f4/include/devices/stm32f415xx.h
+++ b/f4/include/devices/stm32f415xx.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f415xx.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 15-December-2014
+ * @version V2.4.1
+ * @date 09-October-2015
* @brief CMSIS STM32F415xx Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -912,16 +912,13 @@ USB_OTG_HostChannelTypeDef;
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
-#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
@@ -3191,6 +3188,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -3213,6 +3213,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -3235,6 +3238,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -3257,6 +3263,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -3279,6 +3288,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -3301,6 +3313,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -3510,11 +3525,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3551,11 +3570,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3592,11 +3615,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3633,11 +3660,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3674,11 +3705,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3715,11 +3750,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3756,11 +3795,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3797,11 +3840,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -4595,17 +4642,27 @@ USB_OTG_HostChannelTypeDef;
#define HASH_CR_LKEY ((uint32_t)0x00010000)
/****************** Bits definition for HASH_STR register *******************/
-#define HASH_STR_NBW ((uint32_t)0x0000001F)
-#define HASH_STR_NBW_0 ((uint32_t)0x00000001)
-#define HASH_STR_NBW_1 ((uint32_t)0x00000002)
-#define HASH_STR_NBW_2 ((uint32_t)0x00000004)
-#define HASH_STR_NBW_3 ((uint32_t)0x00000008)
-#define HASH_STR_NBW_4 ((uint32_t)0x00000010)
+#define HASH_STR_NBLW ((uint32_t)0x0000001F)
+#define HASH_STR_NBLW_0 ((uint32_t)0x00000001)
+#define HASH_STR_NBLW_1 ((uint32_t)0x00000002)
+#define HASH_STR_NBLW_2 ((uint32_t)0x00000004)
+#define HASH_STR_NBLW_3 ((uint32_t)0x00000008)
+#define HASH_STR_NBLW_4 ((uint32_t)0x00000010)
#define HASH_STR_DCAL ((uint32_t)0x00000100)
+/* Aliases for HASH_STR register */
+#define HASH_STR_NBW HASH_STR_NBLW
+#define HASH_STR_NBW_0 HASH_STR_NBLW_0
+#define HASH_STR_NBW_1 HASH_STR_NBLW_1
+#define HASH_STR_NBW_2 HASH_STR_NBLW_2
+#define HASH_STR_NBW_3 HASH_STR_NBLW_3
+#define HASH_STR_NBW_4 HASH_STR_NBLW_4
/****************** Bits definition for HASH_IMR register *******************/
-#define HASH_IMR_DINIM ((uint32_t)0x00000001)
-#define HASH_IMR_DCIM ((uint32_t)0x00000002)
+#define HASH_IMR_DINIE ((uint32_t)0x00000001)
+#define HASH_IMR_DCIE ((uint32_t)0x00000002)
+/* Aliases for HASH_IMR register */
+#define HASH_IMR_DINIM HASH_IMR_DINIE
+#define HASH_IMR_DCIM HASH_IMR_DCIE
/****************** Bits definition for HASH_SR register ********************/
#define HASH_SR_DINIS ((uint32_t)0x00000001)
@@ -4760,11 +4817,9 @@ USB_OTG_HostChannelTypeDef;
#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
-#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
-#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
-#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
-#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
+#define PWR_CR_VOS ((uint32_t)0x00004000) /*!< VOS bit (Regulator voltage scaling output selection) */
/* Legacy define */
#define PWR_CR_PMODE PWR_CR_VOS
@@ -4977,7 +5032,7 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
-#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
@@ -5118,7 +5173,6 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
-#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
@@ -5349,7 +5403,7 @@ USB_OTG_HostChannelTypeDef;
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
diff --git a/f4/include/devices/stm32f417xx.h b/f4/include/devices/stm32f417xx.h
index b214472..495f347 100755
--- a/f4/include/devices/stm32f417xx.h
+++ b/f4/include/devices/stm32f417xx.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f417xx.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 15-December-2014
+ * @version V2.4.1
+ * @date 09-October-2015
* @brief CMSIS STM32F417xx Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -1007,16 +1007,13 @@ USB_OTG_HostChannelTypeDef;
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
-#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
@@ -3348,6 +3345,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -3370,6 +3370,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -3392,6 +3395,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -3414,6 +3420,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -3436,6 +3445,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -3458,6 +3470,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -3667,11 +3682,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3708,11 +3727,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3749,11 +3772,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3790,11 +3817,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3831,11 +3862,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3872,11 +3907,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3913,11 +3952,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -3954,11 +3997,15 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
@@ -4752,17 +4799,27 @@ USB_OTG_HostChannelTypeDef;
#define HASH_CR_LKEY ((uint32_t)0x00010000)
/****************** Bits definition for HASH_STR register *******************/
-#define HASH_STR_NBW ((uint32_t)0x0000001F)
-#define HASH_STR_NBW_0 ((uint32_t)0x00000001)
-#define HASH_STR_NBW_1 ((uint32_t)0x00000002)
-#define HASH_STR_NBW_2 ((uint32_t)0x00000004)
-#define HASH_STR_NBW_3 ((uint32_t)0x00000008)
-#define HASH_STR_NBW_4 ((uint32_t)0x00000010)
+#define HASH_STR_NBLW ((uint32_t)0x0000001F)
+#define HASH_STR_NBLW_0 ((uint32_t)0x00000001)
+#define HASH_STR_NBLW_1 ((uint32_t)0x00000002)
+#define HASH_STR_NBLW_2 ((uint32_t)0x00000004)
+#define HASH_STR_NBLW_3 ((uint32_t)0x00000008)
+#define HASH_STR_NBLW_4 ((uint32_t)0x00000010)
#define HASH_STR_DCAL ((uint32_t)0x00000100)
+/* Aliases for HASH_STR register */
+#define HASH_STR_NBW HASH_STR_NBLW
+#define HASH_STR_NBW_0 HASH_STR_NBLW_0
+#define HASH_STR_NBW_1 HASH_STR_NBLW_1
+#define HASH_STR_NBW_2 HASH_STR_NBLW_2
+#define HASH_STR_NBW_3 HASH_STR_NBLW_3
+#define HASH_STR_NBW_4 HASH_STR_NBLW_4
/****************** Bits definition for HASH_IMR register *******************/
-#define HASH_IMR_DINIM ((uint32_t)0x00000001)
-#define HASH_IMR_DCIM ((uint32_t)0x00000002)
+#define HASH_IMR_DINIE ((uint32_t)0x00000001)
+#define HASH_IMR_DCIE ((uint32_t)0x00000002)
+/* Aliases for HASH_IMR register */
+#define HASH_IMR_DINIM HASH_IMR_DINIE
+#define HASH_IMR_DCIM HASH_IMR_DCIE
/****************** Bits definition for HASH_SR register ********************/
#define HASH_SR_DINIS ((uint32_t)0x00000001)
@@ -4917,11 +4974,9 @@ USB_OTG_HostChannelTypeDef;
#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
-#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
-#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
-#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
-#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
+#define PWR_CR_VOS ((uint32_t)0x00004000) /*!< VOS bit (Regulator voltage scaling output selection) */
/* Legacy define */
#define PWR_CR_PMODE PWR_CR_VOS
@@ -5135,7 +5190,7 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
-#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
@@ -5282,7 +5337,6 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
-#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
@@ -5518,7 +5572,7 @@ USB_OTG_HostChannelTypeDef;
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
diff --git a/f4/include/devices/stm32f427xx.h b/f4/include/devices/stm32f427xx.h
index aa3594e..0767d0a 100755
--- a/f4/include/devices/stm32f427xx.h
+++ b/f4/include/devices/stm32f427xx.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f427xx.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 15-December-2014
+ * @version V2.4.1
+ * @date 09-October-2015
* @brief CMSIS STM32F427xx Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -1006,16 +1006,13 @@ USB_OTG_HostChannelTypeDef;
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
-#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
@@ -3462,6 +3459,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -3484,6 +3484,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -3506,6 +3509,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -3528,6 +3534,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -3550,6 +3559,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -3572,6 +3584,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -4688,7 +4703,7 @@ USB_OTG_HostChannelTypeDef;
#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
+#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
@@ -5446,7 +5461,7 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
-#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
@@ -5602,7 +5617,6 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
-#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
#define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
@@ -5750,7 +5764,11 @@ USB_OTG_HostChannelTypeDef;
#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
#define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
+#define RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000)
+#define RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000)
#define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
+#define RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000)
+#define RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000)
#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
@@ -5882,7 +5900,7 @@ USB_OTG_HostChannelTypeDef;
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
@@ -6191,16 +6209,17 @@ USB_OTG_HostChannelTypeDef;
#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
-#define SAI_xCR1_MCKDIV ((uint32_t)0x00780000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
-#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) /*!<Bit 0 */
-#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) /*!<Bit 1 */
-#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) /*!<Bit 2 */
-#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) /*!<Bit 3 */
+#define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
/******************* Bit definition for SAI_xCR2 register *******************/
-#define SAI_xCR2_FTH ((uint32_t)0x00000003) /*!<FTH[1:0](Fifo THreshold) */
+#define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */
#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
@@ -6286,7 +6305,7 @@ USB_OTG_HostChannelTypeDef;
#define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */
+#define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
/****************** Bit definition for SAI_xCLRFR register ******************/
#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
diff --git a/f4/include/devices/stm32f429xx.h b/f4/include/devices/stm32f429xx.h
index 72410ce..177f95f 100755
--- a/f4/include/devices/stm32f429xx.h
+++ b/f4/include/devices/stm32f429xx.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f429xx.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 15-December-2014
+ * @version V2.4.1
+ * @date 09-October-2015
* @brief CMSIS STM32F429xx Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -1060,12 +1060,11 @@ USB_OTG_HostChannelTypeDef;
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
@@ -3518,6 +3517,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -3540,6 +3542,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -3562,6 +3567,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -3584,6 +3592,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -3606,6 +3617,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -3628,6 +3642,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -4744,7 +4761,7 @@ USB_OTG_HostChannelTypeDef;
#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
+#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
@@ -5651,7 +5668,7 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
-#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
@@ -5958,7 +5975,11 @@ USB_OTG_HostChannelTypeDef;
#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
#define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
+#define RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000)
+#define RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000)
#define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
+#define RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000)
+#define RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000)
#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
@@ -6090,7 +6111,7 @@ USB_OTG_HostChannelTypeDef;
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
@@ -6399,16 +6420,17 @@ USB_OTG_HostChannelTypeDef;
#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
-#define SAI_xCR1_MCKDIV ((uint32_t)0x00780000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
-#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) /*!<Bit 0 */
-#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) /*!<Bit 1 */
-#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) /*!<Bit 2 */
-#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) /*!<Bit 3 */
+#define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
/******************* Bit definition for SAI_xCR2 register *******************/
-#define SAI_xCR2_FTH ((uint32_t)0x00000003) /*!<FTH[1:0](Fifo THreshold) */
+#define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */
#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
@@ -6494,7 +6516,7 @@ USB_OTG_HostChannelTypeDef;
#define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */
+#define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
/****************** Bit definition for SAI_xCLRFR register ******************/
#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
diff --git a/f4/include/devices/stm32f437xx.h b/f4/include/devices/stm32f437xx.h
index 7857fa2..930e80e 100755
--- a/f4/include/devices/stm32f437xx.h
+++ b/f4/include/devices/stm32f437xx.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f437xx.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 15-December-2014
+ * @version V2.4.1
+ * @date 09-October-2015
* @brief CMSIS STM32F437xx Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -1080,12 +1080,11 @@ USB_OTG_HostChannelTypeDef;
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
@@ -3592,6 +3591,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -3614,6 +3616,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -3636,6 +3641,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -3658,6 +3666,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -3680,6 +3691,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -3702,6 +3716,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -4818,7 +4835,7 @@ USB_OTG_HostChannelTypeDef;
#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
+#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
@@ -5219,17 +5236,27 @@ USB_OTG_HostChannelTypeDef;
#define HASH_CR_LKEY ((uint32_t)0x00010000)
/****************** Bits definition for HASH_STR register *******************/
-#define HASH_STR_NBW ((uint32_t)0x0000001F)
-#define HASH_STR_NBW_0 ((uint32_t)0x00000001)
-#define HASH_STR_NBW_1 ((uint32_t)0x00000002)
-#define HASH_STR_NBW_2 ((uint32_t)0x00000004)
-#define HASH_STR_NBW_3 ((uint32_t)0x00000008)
-#define HASH_STR_NBW_4 ((uint32_t)0x00000010)
+#define HASH_STR_NBLW ((uint32_t)0x0000001F)
+#define HASH_STR_NBLW_0 ((uint32_t)0x00000001)
+#define HASH_STR_NBLW_1 ((uint32_t)0x00000002)
+#define HASH_STR_NBLW_2 ((uint32_t)0x00000004)
+#define HASH_STR_NBLW_3 ((uint32_t)0x00000008)
+#define HASH_STR_NBLW_4 ((uint32_t)0x00000010)
#define HASH_STR_DCAL ((uint32_t)0x00000100)
+/* Aliases for HASH_STR register */
+#define HASH_STR_NBW HASH_STR_NBLW
+#define HASH_STR_NBW_0 HASH_STR_NBLW_0
+#define HASH_STR_NBW_1 HASH_STR_NBLW_1
+#define HASH_STR_NBW_2 HASH_STR_NBLW_2
+#define HASH_STR_NBW_3 HASH_STR_NBLW_3
+#define HASH_STR_NBW_4 HASH_STR_NBLW_4
/****************** Bits definition for HASH_IMR register *******************/
-#define HASH_IMR_DINIM ((uint32_t)0x00000001)
-#define HASH_IMR_DCIM ((uint32_t)0x00000002)
+#define HASH_IMR_DINIE ((uint32_t)0x00000001)
+#define HASH_IMR_DCIE ((uint32_t)0x00000002)
+/* Aliases for HASH_IMR register */
+#define HASH_IMR_DINIM HASH_IMR_DINIE
+#define HASH_IMR_DCIM HASH_IMR_DCIE
/****************** Bits definition for HASH_SR register ********************/
#define HASH_SR_DINIS ((uint32_t)0x00000001)
@@ -5618,7 +5645,7 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
-#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
@@ -5930,7 +5957,11 @@ USB_OTG_HostChannelTypeDef;
#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
#define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
+#define RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000)
+#define RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000)
#define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
+#define RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000)
+#define RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000)
#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
@@ -6062,7 +6093,7 @@ USB_OTG_HostChannelTypeDef;
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
@@ -6371,16 +6402,17 @@ USB_OTG_HostChannelTypeDef;
#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
-#define SAI_xCR1_MCKDIV ((uint32_t)0x00780000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
-#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) /*!<Bit 0 */
-#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) /*!<Bit 1 */
-#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) /*!<Bit 2 */
-#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) /*!<Bit 3 */
+#define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
/******************* Bit definition for SAI_xCR2 register *******************/
-#define SAI_xCR2_FTH ((uint32_t)0x00000003) /*!<FTH[1:0](Fifo THreshold) */
+#define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */
#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
@@ -6466,7 +6498,7 @@ USB_OTG_HostChannelTypeDef;
#define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */
+#define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
/****************** Bit definition for SAI_xCLRFR register ******************/
#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
diff --git a/f4/include/devices/stm32f439xx.h b/f4/include/devices/stm32f439xx.h
index 3c98721..aadb9a7 100755
--- a/f4/include/devices/stm32f439xx.h
+++ b/f4/include/devices/stm32f439xx.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f439xx.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 15-December-2014
+ * @version V2.4.1
+ * @date 09-October-2015
* @brief CMSIS STM32F439xx Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -1129,12 +1129,11 @@ USB_OTG_HostChannelTypeDef;
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
@@ -3647,6 +3646,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -3669,6 +3671,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -3691,6 +3696,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -3713,6 +3721,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -3735,6 +3746,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -3757,6 +3771,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/
/* */
@@ -4873,7 +4890,7 @@ USB_OTG_HostChannelTypeDef;
#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
+#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
@@ -5274,17 +5291,27 @@ USB_OTG_HostChannelTypeDef;
#define HASH_CR_LKEY ((uint32_t)0x00010000)
/****************** Bits definition for HASH_STR register *******************/
-#define HASH_STR_NBW ((uint32_t)0x0000001F)
-#define HASH_STR_NBW_0 ((uint32_t)0x00000001)
-#define HASH_STR_NBW_1 ((uint32_t)0x00000002)
-#define HASH_STR_NBW_2 ((uint32_t)0x00000004)
-#define HASH_STR_NBW_3 ((uint32_t)0x00000008)
-#define HASH_STR_NBW_4 ((uint32_t)0x00000010)
+#define HASH_STR_NBLW ((uint32_t)0x0000001F)
+#define HASH_STR_NBLW_0 ((uint32_t)0x00000001)
+#define HASH_STR_NBLW_1 ((uint32_t)0x00000002)
+#define HASH_STR_NBLW_2 ((uint32_t)0x00000004)
+#define HASH_STR_NBLW_3 ((uint32_t)0x00000008)
+#define HASH_STR_NBLW_4 ((uint32_t)0x00000010)
#define HASH_STR_DCAL ((uint32_t)0x00000100)
+/* Aliases for HASH_STR register */
+#define HASH_STR_NBW HASH_STR_NBLW
+#define HASH_STR_NBW_0 HASH_STR_NBLW_0
+#define HASH_STR_NBW_1 HASH_STR_NBLW_1
+#define HASH_STR_NBW_2 HASH_STR_NBLW_2
+#define HASH_STR_NBW_3 HASH_STR_NBLW_3
+#define HASH_STR_NBW_4 HASH_STR_NBLW_4
/****************** Bits definition for HASH_IMR register *******************/
-#define HASH_IMR_DINIM ((uint32_t)0x00000001)
-#define HASH_IMR_DCIM ((uint32_t)0x00000002)
+#define HASH_IMR_DINIE ((uint32_t)0x00000001)
+#define HASH_IMR_DCIE ((uint32_t)0x00000002)
+/* Aliases for HASH_IMR register */
+#define HASH_IMR_DINIM HASH_IMR_DINIE
+#define HASH_IMR_DCIM HASH_IMR_DCIE
/****************** Bits definition for HASH_SR register ********************/
#define HASH_SR_DINIS ((uint32_t)0x00000001)
@@ -5823,7 +5850,7 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
-#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
@@ -6138,7 +6165,11 @@ USB_OTG_HostChannelTypeDef;
#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
#define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
+#define RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000)
+#define RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000)
#define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
+#define RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000)
+#define RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000)
#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
@@ -6270,7 +6301,7 @@ USB_OTG_HostChannelTypeDef;
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
@@ -6579,16 +6610,17 @@ USB_OTG_HostChannelTypeDef;
#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
-#define SAI_xCR1_MCKDIV ((uint32_t)0x00780000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
-#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) /*!<Bit 0 */
-#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) /*!<Bit 1 */
-#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) /*!<Bit 2 */
-#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) /*!<Bit 3 */
+#define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
/******************* Bit definition for SAI_xCR2 register *******************/
-#define SAI_xCR2_FTH ((uint32_t)0x00000003) /*!<FTH[1:0](Fifo THreshold) */
+#define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */
#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
@@ -6674,7 +6706,7 @@ USB_OTG_HostChannelTypeDef;
#define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
-#define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */
+#define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
/****************** Bit definition for SAI_xCLRFR register ******************/
#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
diff --git a/f4/include/devices/stm32f446xx.h b/f4/include/devices/stm32f446xx.h
new file mode 100644
index 0000000..7317298
--- /dev/null
+++ b/f4/include/devices/stm32f446xx.h
@@ -0,0 +1,8220 @@
+/**
+ ******************************************************************************
+ * @file stm32f446xx.h
+ * @author MCD Application Team
+ * @version V2.4.1
+ * @date 09-October-2015
+ * @brief CMSIS STM32F446xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f446xx
+ * @{
+ */
+
+#ifndef __STM32F446xx_H
+#define __STM32F446xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
+ QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
+ CEC_IRQn = 93, /*!< CEC global Interrupt */
+ SPDIF_RX_IRQn = 94, /*!< SPDIF-RX global Interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
+ FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief Consumer Electronics Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
+ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
+ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
+ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
+ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
+ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
+}CEC_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank3
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+ uint32_t RESERVED; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank5_6
+ */
+
+typedef struct
+{
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
+ __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
+} FMPI2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+ __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief QUAD Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+ * @brief SPDIFRX Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
+ __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
+ uint16_t RESERVED0; /*!< Reserved, 0x06 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
+ __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
+ uint16_t RESERVED1; /*!< Reserved, 0x0E */
+ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
+ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
+ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
+ uint16_t RESERVED2; /*!< Reserved, 0x1A */
+} SPDIFRX_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
+ uint32_t Reserved6; /*!< Reserved 050h */
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
+ __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
+ __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
+ uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
+#define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< QuadSPI registers base address */
+
+#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
+#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+#define CEC_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
+#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00)
+#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
+#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t )0xE0042000)
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
+#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
+
+#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
+#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
+#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
+#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
+#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
+#define USB_OTG_HOST_BASE ((uint32_t )0x400)
+#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
+#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
+#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
+#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
+#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
+#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define CEC ((CEC_TypeDef *) CEC_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
+#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
+#define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
+#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
+#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
+#define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
+#define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
+#define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
+#define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
+#define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
+
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
+#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
+
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* HDMI-CEC (CEC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CEC_CR register *********************/
+#define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
+#define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
+#define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
+
+/******************* Bit definition for CEC_CFGR register *******************/
+#define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
+#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
+#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
+#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
+#define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Bit Period Error generation */
+#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
+#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast No error generation */
+#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
+#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
+
+/******************* Bit definition for CEC_TXDR register *******************/
+#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
+
+/******************* Bit definition for CEC_RXDR register *******************/
+#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
+
+/******************* Bit definition for CEC_ISR register ********************/
+#define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
+#define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
+#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
+#define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
+#define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
+#define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
+#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
+#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
+#define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
+#define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
+#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
+#define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
+#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
+
+/******************* Bit definition for CEC_IER register ********************/
+#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
+#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
+#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
+#define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
+#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable */
+#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
+#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
+#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
+#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
+#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
+#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
+#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
+#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
+#define DCMI_CR_CM ((uint32_t)0x00000002)
+#define DCMI_CR_CROP ((uint32_t)0x00000004)
+#define DCMI_CR_JPEG ((uint32_t)0x00000008)
+#define DCMI_CR_ESS ((uint32_t)0x00000010)
+#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
+#define DCMI_CR_HSPOL ((uint32_t)0x00000040)
+#define DCMI_CR_VSPOL ((uint32_t)0x00000080)
+#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
+#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
+#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
+#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
+#define DCMI_CR_OUTEN ((uint32_t)0x00002000)
+#define DCMI_CR_ENABLE ((uint32_t)0x00004000)
+#define DCMI_CR_BSM_0 ((uint32_t)0x00010000)
+#define DCMI_CR_BSM_1 ((uint32_t)0x00020000)
+#define DCMI_CR_OEBS ((uint32_t)0x00040000)
+#define DCMI_CR_LSM ((uint32_t)0x00080000)
+#define DCMI_CR_OELS ((uint32_t)0x00100000)
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC ((uint32_t)0x00000001)
+#define DCMI_SR_VSYNC ((uint32_t)0x00000002)
+#define DCMI_SR_FNE ((uint32_t)0x00000004)
+
+/******************** Bits definition for DCMI_RISR register ****************/
+#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
+#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
+#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
+#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
+#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
+#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
+#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
+#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
+#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
+
+/******************** Bits definition for DCMI_MISR register ****************/
+#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
+#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
+#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
+#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
+#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
+#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
+#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
+#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
+#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
+#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
+#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
+#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
+#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
+#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
+#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
+#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
+#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
+#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
+#define DMA_SxCR_ACK ((uint32_t)0x00100000)
+#define DMA_SxCR_CT ((uint32_t)0x00080000)
+#define DMA_SxCR_DBM ((uint32_t)0x00040000)
+#define DMA_SxCR_PL ((uint32_t)0x00030000)
+#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
+#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
+#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
+#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
+#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
+#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
+#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
+#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
+#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
+#define DMA_SxCR_MINC ((uint32_t)0x00000400)
+#define DMA_SxCR_PINC ((uint32_t)0x00000200)
+#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
+#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
+#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
+#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
+#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
+#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
+#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
+#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
+#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
+#define DMA_SxCR_EN ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT ((uint32_t)0x0000FFFF)
+#define DMA_SxNDT_0 ((uint32_t)0x00000001)
+#define DMA_SxNDT_1 ((uint32_t)0x00000002)
+#define DMA_SxNDT_2 ((uint32_t)0x00000004)
+#define DMA_SxNDT_3 ((uint32_t)0x00000008)
+#define DMA_SxNDT_4 ((uint32_t)0x00000010)
+#define DMA_SxNDT_5 ((uint32_t)0x00000020)
+#define DMA_SxNDT_6 ((uint32_t)0x00000040)
+#define DMA_SxNDT_7 ((uint32_t)0x00000080)
+#define DMA_SxNDT_8 ((uint32_t)0x00000100)
+#define DMA_SxNDT_9 ((uint32_t)0x00000200)
+#define DMA_SxNDT_10 ((uint32_t)0x00000400)
+#define DMA_SxNDT_11 ((uint32_t)0x00000800)
+#define DMA_SxNDT_12 ((uint32_t)0x00001000)
+#define DMA_SxNDT_13 ((uint32_t)0x00002000)
+#define DMA_SxNDT_14 ((uint32_t)0x00004000)
+#define DMA_SxNDT_15 ((uint32_t)0x00008000)
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
+#define DMA_SxFCR_FS ((uint32_t)0x00000038)
+#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
+#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
+#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
+#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
+#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
+#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
+#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
+#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
+#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
+#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
+#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
+#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
+#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
+#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
+#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
+#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
+#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
+#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
+#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
+#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
+#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
+#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
+#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
+#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
+#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
+#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
+#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
+#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
+#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
+#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
+#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
+#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
+#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
+#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
+#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
+#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
+#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
+#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
+#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
+#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
+#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
+#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
+#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
+#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
+#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
+#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
+#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
+#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
+#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
+#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
+#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
+#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
+#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
+#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
+#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
+#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
+#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
+#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
+#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
+#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
+#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
+#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
+#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
+#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
+#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
+#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
+#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
+#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
+#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
+#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
+#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
+#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
+#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
+#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
+#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
+#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
+#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
+#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
+#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
+#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
+#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
+#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
+#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
+#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
+#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
+#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
+#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
+#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
+#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
+#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
+#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
+#define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
+#define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
+#define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
+#define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
+#define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
+#define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
+#define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
+#define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
+#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
+#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
+#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
+#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
+#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
+#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP ((uint32_t)0x00000001)
+#define FLASH_SR_SOP ((uint32_t)0x00000002)
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
+#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
+#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
+#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
+#define FLASH_SR_BSY ((uint32_t)0x00010000)
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001)
+#define FLASH_CR_SER ((uint32_t)0x00000002)
+#define FLASH_CR_MER ((uint32_t)0x00000004)
+#define FLASH_CR_MER1 FLASH_CR_MER
+#define FLASH_CR_SNB ((uint32_t)0x000000F8)
+#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
+#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
+#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
+#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
+#define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
+#define FLASH_CR_PSIZE ((uint32_t)0x00000300)
+#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
+#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
+#define FLASH_CR_MER2 ((uint32_t)0x00008000)
+#define FLASH_CR_STRT ((uint32_t)0x00010000)
+#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
+#define FLASH_CR_LOCK ((uint32_t)0x80000000)
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
+#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
+#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
+#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
+#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
+#define FLASH_OPTCR_BFB2 ((uint32_t)0x00000010)
+#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
+#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
+#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
+#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
+#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
+#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
+#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
+#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
+#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
+#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
+#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
+#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
+#define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
+#define FLASH_OPTCR_DB1M ((uint32_t)0x40000000)
+#define FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000)
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR1_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
+#define FMC_BCR1_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BCR1_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BCR1_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
+#define FMC_BCR1_WFDIS ((uint32_t)0x00200000) /*!<Write FIFO Disable */
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_PCR register *******************/
+#define FMC_PCR_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FMC_PCR_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FMC_PCR_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_PCR_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_PCR_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FMC_PCR_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FMC_PCR_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_PCR_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FMC_PCR_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FMC_PCR_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FMC_PCR_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/******************* Bit definition for FMC_SR register *******************/
+#define FMC_SR_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FMC_SR_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FMC_SR_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FMC_SR_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FMC_SR_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEM register ******************/
+#define FMC_PMEM_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PMEM_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PMEM_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PMEM_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PMEM_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PMEM_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PMEM_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PMEM_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PMEM_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PMEM_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PMEM_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PMEM_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PMEM_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PMEM_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PMEM_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PMEM_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PMEM_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PMEM_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PMEM_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PMEM_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PMEM_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PMEM_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PMEM_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PMEM_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PMEM_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PMEM_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PMEM_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PMEM_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PMEM_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PMEM_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PMEM_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PMEM_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT register ******************/
+#define FMC_PATT_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PATT_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PATT_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PATT_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PATT_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PATT_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PATT_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PATT_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PATT_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PATT_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PATT_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PATT_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PATT_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PATT_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PATT_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PATT_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PATT_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PATT_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PATT_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PATT_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PATT_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PATT_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PATT_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PATT_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PATT_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PATT_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PATT_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PATT_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PATT_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PATT_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PATT_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PATT_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_ECCR register ******************/
+#define FMC_ECCR_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
+
+/****************** Bit definition for FMC_SDCR1 register ******************/
+#define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
+
+#define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+
+#define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
+
+#define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
+#define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
+
+#define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
+#define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDCR2 register ******************/
+#define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
+
+#define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+
+#define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
+
+#define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
+
+#define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
+#define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDTR1 register ******************/
+#define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+
+#define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+
+#define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDTR2 register ******************/
+#define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+
+#define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+
+#define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDCMR register ******************/
+#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+
+#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+
+#define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
+
+/****************** Bit definition for FMC_SDRTR register ******************/
+#define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
+
+/****************** Bit definition for FMC_SDSR register ******************/
+#define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+
+#define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
+#define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
+#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
+#define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
+#define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
+#define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
+#define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
+#define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
+#define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
+#define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
+#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
+#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
+#define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
+#define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
+#define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
+#define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define FMPI2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
+#define FMPI2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
+#define FMPI2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
+#define FMPI2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
+#define FMPI2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
+#define FMPI2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
+#define FMPI2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
+#define FMPI2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
+#define FMPI2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define FMPI2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
+#define FMPI2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
+#define FMPI2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
+#define FMPI2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
+#define FMPI2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
+#define FMPI2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
+#define FMPI2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
+#define FMPI2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
+#define FMPI2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
+#define FMPI2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
+#define FMPI2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
+#define FMPI2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define FMPI2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
+#define FMPI2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
+#define FMPI2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
+#define FMPI2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
+#define FMPI2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
+#define FMPI2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
+#define FMPI2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
+#define FMPI2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
+#define FMPI2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
+#define FMPI2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
+#define FMPI2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define FMPI2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
+#define FMPI2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
+#define FMPI2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define FMPI2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define FMPI2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define FMPI2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define FMPI2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
+#define FMPI2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
+#define FMPI2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
+#define FMPI2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
+#define FMPI2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define FMPI2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
+#define FMPI2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
+#define FMPI2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
+#define FMPI2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B */
+#define FMPI2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define FMPI2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
+#define FMPI2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
+#define FMPI2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
+#define FMPI2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode) */
+#define FMPI2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
+#define FMPI2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
+#define FMPI2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
+#define FMPI2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
+#define FMPI2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
+#define FMPI2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
+#define FMPI2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
+#define FMPI2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
+#define FMPI2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
+#define FMPI2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
+#define FMPI2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
+#define FMPI2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
+#define FMPI2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define FMPI2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
+#define FMPI2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
+#define FMPI2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
+#define FMPI2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
+#define FMPI2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
+#define FMPI2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
+#define FMPI2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
+#define FMPI2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
+#define FMPI2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define FMPI2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define FMPI2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define FMPI2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define PWR_CR_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */
+#define PWR_CR_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */
+#define PWR_CR_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */
+#define PWR_CR_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define PWR_CR_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define PWR_CR_FMSSR ((uint32_t)0x00100000) /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR ((uint32_t)0x00200000) /*!< Flash Interface Stop while System Run */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+#define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
+#define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
+#define PWR_CSR_EWUP2 ((uint32_t)0x00000080) /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
+#define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
+#define PWR_CSR_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */
+#define PWR_CSR_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */
+#define PWR_CSR_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* QUADSPI */
+/* */
+/******************************************************************************/
+/***************** Bit definition for QUADSPI_CR register *******************/
+#define QUADSPI_CR_EN ((uint32_t)0x00000001) /*!< Enable */
+#define QUADSPI_CR_ABORT ((uint32_t)0x00000002) /*!< Abort request */
+#define QUADSPI_CR_DMAEN ((uint32_t)0x00000004) /*!< DMA Enable */
+#define QUADSPI_CR_TCEN ((uint32_t)0x00000008) /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010) /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM ((uint32_t)0x00000040) /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL ((uint32_t)0x00000080) /*!< Flash Select */
+#define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00) /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define QUADSPI_CR_FTHRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define QUADSPI_CR_FTHRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define QUADSPI_CR_FTHRES_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define QUADSPI_CR_TEIE ((uint32_t)0x00010000) /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE ((uint32_t)0x00020000) /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE ((uint32_t)0x00040000) /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE ((uint32_t)0x00080000) /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE ((uint32_t)0x00100000) /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS ((uint32_t)0x00400000) /*!< Bit 1 */
+#define QUADSPI_CR_PMM ((uint32_t)0x00800000) /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000) /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define QUADSPI_CR_PRESCALER_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define QUADSPI_CR_PRESCALER_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define QUADSPI_CR_PRESCALER_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define QUADSPI_CR_PRESCALER_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define QUADSPI_CR_PRESCALER_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define QUADSPI_CR_PRESCALER_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define QUADSPI_CR_PRESCALER_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/***************** Bit definition for QUADSPI_DCR register ******************/
+#define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001) /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT ((uint32_t)0x00000700) /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000) /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define QUADSPI_DCR_FSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define QUADSPI_DCR_FSIZE_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define QUADSPI_DCR_FSIZE_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define QUADSPI_DCR_FSIZE_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+
+/****************** Bit definition for QUADSPI_SR register *******************/
+#define QUADSPI_SR_TEF ((uint32_t)0x00000001) /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF ((uint32_t)0x00000002) /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF ((uint32_t)0x00000004) /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF ((uint32_t)0x00000008) /*!< Status Match Flag */
+#define QUADSPI_SR_TOF ((uint32_t)0x00000010) /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY ((uint32_t)0x00000020) /*!< Busy */
+#define QUADSPI_SR_FLEVEL ((uint32_t)0x00003F00) /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define QUADSPI_SR_FLEVEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define QUADSPI_SR_FLEVEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define QUADSPI_SR_FLEVEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define QUADSPI_SR_FLEVEL_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define QUADSPI_SR_FLEVEL_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+
+/****************** Bit definition for QUADSPI_FCR register ******************/
+#define QUADSPI_FCR_CTEF ((uint32_t)0x00000001) /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF ((uint32_t)0x00000002) /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF ((uint32_t)0x00000008) /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF ((uint32_t)0x00000010) /*!< Clear Timeout Flag */
+
+/****************** Bit definition for QUADSPI_DLR register ******************/
+#define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFF) /*!< DL[31:0]: Data Length */
+
+/****************** Bit definition for QUADSPI_CCR register ******************/
+#define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define QUADSPI_CCR_INSTRUCTION_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define QUADSPI_CCR_INSTRUCTION_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define QUADSPI_CCR_INSTRUCTION_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define QUADSPI_CCR_INSTRUCTION_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define QUADSPI_CCR_INSTRUCTION_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define QUADSPI_CCR_INSTRUCTION_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define QUADSPI_CCR_INSTRUCTION_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define QUADSPI_CCR_IMODE ((uint32_t)0x00000300) /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00) /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000) /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000) /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000) /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000) /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define QUADSPI_CCR_DCYC_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define QUADSPI_CCR_DCYC_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define QUADSPI_CCR_DCYC_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+#define QUADSPI_CCR_DCYC_4 ((uint32_t)0x00400000) /*!< Bit 4 */
+#define QUADSPI_CCR_DMODE ((uint32_t)0x03000000) /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000) /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define QUADSPI_CCR_SIOO ((uint32_t)0x10000000) /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC ((uint32_t)0x40000000) /*!< DHHC: Delay Half Hclk Cycle */
+#define QUADSPI_CCR_DDRM ((uint32_t)0x80000000) /*!< DDRM: Double Data Rate Mode */
+/****************** Bit definition for QUADSPI_AR register *******************/
+#define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< ADDRESS[31:0]: Address */
+
+/****************** Bit definition for QUADSPI_ABR register ******************/
+#define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/****************** Bit definition for QUADSPI_DR register *******************/
+#define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFF) /*!< DATA[31:0]: Data */
+
+/****************** Bit definition for QUADSPI_PSMKR register ****************/
+#define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) /*!< MASK[31:0]: Status Mask */
+
+/****************** Bit definition for QUADSPI_PSMAR register ****************/
+#define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) /*!< MATCH[31:0]: Status Match */
+
+/****************** Bit definition for QUADSPI_PIR register *****************/
+#define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFF) /*!< INTERVAL[15:0]: Polling Interval */
+
+/****************** Bit definition for QUADSPI_LPTR register *****************/
+#define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFF) /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001)
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000)
+#define RCC_CR_HSERDY ((uint32_t)0x00020000)
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
+#define RCC_CR_CSSON ((uint32_t)0x00080000)
+#define RCC_CR_PLLON ((uint32_t)0x01000000)
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
+#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
+#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
+#define RCC_CR_PLLSAION ((uint32_t)0x10000000)
+#define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
+#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
+#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
+#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
+#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
+#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
+#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
+
+#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
+#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
+#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
+#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
+#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
+#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
+#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
+#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
+#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
+#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
+#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
+#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
+
+#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
+
+#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
+#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
+#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
+#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
+#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
+
+#define RCC_PLLCFGR_PLLR ((uint32_t)0x70000000)
+#define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x10000000)
+#define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x20000000)
+#define RCC_PLLCFGR_PLLR_2 ((uint32_t)0x40000000)
+
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL/PLLP selected as system clock */
+#define RCC_CFGR_SW_PLLR ((uint32_t)0x00000003) /*!< PLL/PLLR selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL/PLLP used as system clock */
+#define RCC_CFGR_SWS_PLLR ((uint32_t)0x0000000C) /*!< PLL/PLLR used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
+#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
+#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
+#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
+#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
+#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
+#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
+#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
+
+#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
+
+#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
+#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
+#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
+#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
+
+#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
+#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
+#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
+#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
+
+#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
+#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
+#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
+#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
+#define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
+#define RCC_CIR_CSSF ((uint32_t)0x00000080)
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
+#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
+#define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
+#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
+#define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
+#define RCC_CIR_CSSC ((uint32_t)0x00800000)
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
+#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
+#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
+#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
+#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
+#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
+#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
+#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
+#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
+#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
+#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
+#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
+#define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
+#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
+#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
+#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
+#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
+#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
+#define RCC_APB1RSTR_SPDIFRXRST ((uint32_t)0x00010000)
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
+#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
+#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
+#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
+#define RCC_APB1RSTR_FMPI2C1RST ((uint32_t)0x01000000)
+#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
+#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
+#define RCC_APB1RSTR_CECRST ((uint32_t)0x08000000)
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
+#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
+#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
+#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
+#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
+#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
+#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
+#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
+#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
+#define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00800000)
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
+#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
+#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
+#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
+#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
+#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
+#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
+#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
+
+#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
+#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
+#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
+#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
+
+#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
+#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
+#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
+#define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
+#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
+#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
+#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
+#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
+#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
+#define RCC_APB1ENR_SPDIFRXEN ((uint32_t)0x00010000)
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
+#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
+#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
+#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
+#define RCC_APB1ENR_FMPI2C1EN ((uint32_t)0x01000000)
+#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
+#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
+#define RCC_APB1ENR_CECEN ((uint32_t)0x08000000)
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
+#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
+#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
+#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
+#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
+#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
+#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
+#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
+#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
+#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
+#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
+#define RCC_APB2ENR_SAI2EN ((uint32_t)0x00800000)
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
+#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
+#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
+#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
+#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
+#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
+#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
+#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
+#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
+#define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
+#define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
+
+#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
+#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
+#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
+#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
+#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
+#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
+#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
+
+#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
+#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
+#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
+#define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002)
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
+#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
+#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
+#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
+#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
+#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
+#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
+#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
+#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
+#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
+#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
+#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
+#define RCC_APB1LPENR_SPDIFRXLPEN ((uint32_t)0x00010000)
+#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
+#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
+#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
+#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
+#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
+#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
+#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
+#define RCC_APB1LPENR_FMPI2C1LPEN ((uint32_t)0x01000000)
+#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
+#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
+#define RCC_APB1LPENR_CECLPEN ((uint32_t)0x08000000)
+#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
+#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
+#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
+#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
+#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
+#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
+#define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
+#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
+#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
+#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
+#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
+#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
+#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
+#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
+#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
+#define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
+#define RCC_APB2LPENR_SAI2LPEN ((uint32_t)0x00800000)
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
+#define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001)
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
+#define RCC_CSR_RMVF ((uint32_t)0x01000000)
+#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
+#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
+#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
+#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
+#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
+#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F)
+#define RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001)
+#define RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002)
+#define RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004)
+#define RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008)
+#define RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010)
+#define RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020)
+
+#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
+#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
+#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
+#define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
+#define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
+#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
+#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
+#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
+#define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
+#define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLI2SCFGR_PLLI2SP ((uint32_t)0x00030000)
+#define RCC_PLLI2SCFGR_PLLI2SP_0 ((uint32_t)0x00010000)
+#define RCC_PLLI2SCFGR_PLLI2SP_1 ((uint32_t)0x00020000)
+
+#define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
+
+#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
+
+
+/******************** Bit definition for RCC_PLLSAICFGR register ************/
+#define RCC_PLLSAICFGR_PLLSAIM ((uint32_t)0x0000003F)
+#define RCC_PLLSAICFGR_PLLSAIM_0 ((uint32_t)0x00000001)
+#define RCC_PLLSAICFGR_PLLSAIM_1 ((uint32_t)0x00000002)
+#define RCC_PLLSAICFGR_PLLSAIM_2 ((uint32_t)0x00000004)
+#define RCC_PLLSAICFGR_PLLSAIM_3 ((uint32_t)0x00000008)
+#define RCC_PLLSAICFGR_PLLSAIM_4 ((uint32_t)0x00000010)
+#define RCC_PLLSAICFGR_PLLSAIM_5 ((uint32_t)0x00000020)
+
+#define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
+#define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
+#define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
+#define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
+#define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
+#define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
+#define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
+#define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
+#define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
+#define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)
+#define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)
+#define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)
+
+#define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
+#define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
+#define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)
+#define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
+#define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)
+#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
+#define RCC_DCKCFGR_SAI1SRC ((uint32_t)0x00300000)
+#define RCC_DCKCFGR_SAI1SRC_0 ((uint32_t)0x00100000)
+#define RCC_DCKCFGR_SAI1SRC_1 ((uint32_t)0x00200000)
+#define RCC_DCKCFGR_SAI2SRC ((uint32_t)0x00C00000)
+#define RCC_DCKCFGR_SAI2SRC_0 ((uint32_t)0x00400000)
+#define RCC_DCKCFGR_SAI2SRC_1 ((uint32_t)0x00800000)
+#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
+#define RCC_DCKCFGR_I2S1SRC ((uint32_t)0x06000000)
+#define RCC_DCKCFGR_I2S1SRC_0 ((uint32_t)0x02000000)
+#define RCC_DCKCFGR_I2S1SRC_1 ((uint32_t)0x04000000)
+#define RCC_DCKCFGR_I2S2SRC ((uint32_t)0x18000000)
+#define RCC_DCKCFGR_I2S2SRC_0 ((uint32_t)0x08000000)
+#define RCC_DCKCFGR_I2S2SRC_1 ((uint32_t)0x10000000)
+
+/******************** Bit definition for RCC_CKGATENR register ***************/
+#define RCC_CKGATENR_AHB2APB1_CKEN ((uint32_t)0x00000001)
+#define RCC_CKGATENR_AHB2APB2_CKEN ((uint32_t)0x00000002)
+#define RCC_CKGATENR_CM4DBG_CKEN ((uint32_t)0x00000004)
+#define RCC_CKGATENR_SPARE_CKEN ((uint32_t)0x00000008)
+#define RCC_CKGATENR_SRAM_CKEN ((uint32_t)0x00000010)
+#define RCC_CKGATENR_FLITF_CKEN ((uint32_t)0x00000020)
+#define RCC_CKGATENR_RCC_CKEN ((uint32_t)0x00000040)
+
+/******************** Bit definition for RCC_DCKCFGR2 register ***************/
+#define RCC_DCKCFGR2_FMPI2C1SEL ((uint32_t)0x00C00000)
+#define RCC_DCKCFGR2_FMPI2C1SEL_0 ((uint32_t)0x00400000)
+#define RCC_DCKCFGR2_FMPI2C1SEL_1 ((uint32_t)0x00800000)
+#define RCC_DCKCFGR2_CECSEL ((uint32_t)0x04000000)
+#define RCC_DCKCFGR2_CK48MSEL ((uint32_t)0x08000000)
+#define RCC_DCKCFGR2_SDIOSEL ((uint32_t)0x10000000)
+#define RCC_DCKCFGR2_SPDIFRXSEL ((uint32_t)0x20000000)
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_DCE ((uint32_t)0x00000080)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
+#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
+#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+#define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+#define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */
+#define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+#define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+
+#define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */
+#define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */
+
+#define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */
+#define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */
+#define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */
+#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
+#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
+
+#define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+#define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */
+#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+
+#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
+#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */
+#define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */
+
+#define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+#define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */
+#define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */
+#define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */
+#define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */
+
+#define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */
+
+#define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+#define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */
+#define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */
+#define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+
+#define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */
+#define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+#define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */
+#define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */
+#define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+
+#define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+#define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */
+
+/******************* Bit definition for SAI_xIMR register *******************/
+#define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */
+#define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */
+#define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */
+#define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */
+#define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */
+#define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */
+#define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */
+
+/******************** Bit definition for SAI_xSR register *******************/
+#define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */
+#define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */
+#define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */
+#define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */
+#define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */
+#define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */
+#define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */
+
+#define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
+#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
+#define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */
+#define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */
+#define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */
+#define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */
+#define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */
+#define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */
+
+/****************** Bit definition for SAI_xDR register ******************/
+#define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/* */
+/* SPDIF-RX Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SPDIFRX_CR register *******************/
+#define SPDIFRX_CR_SPDIFEN ((uint32_t)0x00000003) /*!<Peripheral Block Enable */
+#define SPDIFRX_CR_RXDMAEN ((uint32_t)0x00000004) /*!<Receiver DMA Enable for data flow */
+#define SPDIFRX_CR_RXSTEO ((uint32_t)0x00000008) /*!<Stereo Mode */
+#define SPDIFRX_CR_DRFMT ((uint32_t)0x00000030) /*!<RX Data format */
+#define SPDIFRX_CR_PMSK ((uint32_t)0x00000040) /*!<Mask Parity error bit */
+#define SPDIFRX_CR_VMSK ((uint32_t)0x00000080) /*!<Mask of Validity bit */
+#define SPDIFRX_CR_CUMSK ((uint32_t)0x00000100) /*!<Mask of channel status and user bits */
+#define SPDIFRX_CR_PTMSK ((uint32_t)0x00000200) /*!<Mask of Preamble Type bits */
+#define SPDIFRX_CR_CBDMAEN ((uint32_t)0x00000400) /*!<Control Buffer DMA ENable for control flow */
+#define SPDIFRX_CR_CHSEL ((uint32_t)0x00000800) /*!<Channel Selection */
+#define SPDIFRX_CR_NBTR ((uint32_t)0x00003000) /*!<Maximum allowed re-tries during synchronization phase */
+#define SPDIFRX_CR_WFA ((uint32_t)0x00004000) /*!<Wait For Activity */
+#define SPDIFRX_CR_INSEL ((uint32_t)0x00070000) /*!<SPDIFRX input selection */
+
+/******************* Bit definition for SPDIFRX_IMR register *******************/
+#define SPDIFRX_IMR_RXNEIE ((uint32_t)0x00000001) /*!<RXNE interrupt enable */
+#define SPDIFRX_IMR_CSRNEIE ((uint32_t)0x00000002) /*!<Control Buffer Ready Interrupt Enable */
+#define SPDIFRX_IMR_PERRIE ((uint32_t)0x00000004) /*!<Parity error interrupt enable */
+#define SPDIFRX_IMR_OVRIE ((uint32_t)0x00000008) /*!<Overrun error Interrupt Enable */
+#define SPDIFRX_IMR_SBLKIE ((uint32_t)0x00000010) /*!<Synchronization Block Detected Interrupt Enable */
+#define SPDIFRX_IMR_SYNCDIE ((uint32_t)0x00000020) /*!<Synchronization Done */
+#define SPDIFRX_IMR_IFEIE ((uint32_t)0x00000040) /*!<Serial Interface Error Interrupt Enable */
+
+/******************* Bit definition for SPDIFRX_SR register *******************/
+#define SPDIFRX_SR_RXNE ((uint32_t)0x00000001) /*!<Read data register not empty */
+#define SPDIFRX_SR_CSRNE ((uint32_t)0x00000002) /*!<The Control Buffer register is not empty */
+#define SPDIFRX_SR_PERR ((uint32_t)0x00000004) /*!<Parity error */
+#define SPDIFRX_SR_OVR ((uint32_t)0x00000008) /*!<Overrun error */
+#define SPDIFRX_SR_SBD ((uint32_t)0x00000010) /*!<Synchronization Block Detected */
+#define SPDIFRX_SR_SYNCD ((uint32_t)0x00000020) /*!<Synchronization Done */
+#define SPDIFRX_SR_FERR ((uint32_t)0x00000040) /*!<Framing error */
+#define SPDIFRX_SR_SERR ((uint32_t)0x00000080) /*!<Synchronization error */
+#define SPDIFRX_SR_TERR ((uint32_t)0x00000100) /*!<Time-out error */
+#define SPDIFRX_SR_WIDTH5 ((uint32_t)0x7FFF0000) /*!<Duration of 5 symbols counted with SPDIFRX_clk */
+
+/******************* Bit definition for SPDIFRX_IFCR register *******************/
+#define SPDIFRX_IFCR_PERRCF ((uint32_t)0x00000004) /*!<Clears the Parity error flag */
+#define SPDIFRX_IFCR_OVRCF ((uint32_t)0x00000008) /*!<Clears the Overrun error flag */
+#define SPDIFRX_IFCR_SBDCF ((uint32_t)0x00000010) /*!<Clears the Synchronization Block Detected flag */
+#define SPDIFRX_IFCR_SYNCDCF ((uint32_t)0x00000020) /*!<Clears the Synchronization Done flag */
+
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
+#define SPDIFRX_DR0_DR ((uint32_t)0x00FFFFFF) /*!<Data value */
+#define SPDIFRX_DR0_PE ((uint32_t)0x01000000) /*!<Parity Error bit */
+#define SPDIFRX_DR0_V ((uint32_t)0x02000000) /*!<Validity bit */
+#define SPDIFRX_DR0_U ((uint32_t)0x04000000) /*!<User bit */
+#define SPDIFRX_DR0_C ((uint32_t)0x08000000) /*!<Channel Status bit */
+#define SPDIFRX_DR0_PT ((uint32_t)0x30000000) /*!<Preamble Type */
+
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
+#define SPDIFRX_DR1_DR ((uint32_t)0xFFFFFF00) /*!<Data value */
+#define SPDIFRX_DR1_PT ((uint32_t)0x00000030) /*!<Preamble Type */
+#define SPDIFRX_DR1_C ((uint32_t)0x00000008) /*!<Channel Status bit */
+#define SPDIFRX_DR1_U ((uint32_t)0x00000004) /*!<User bit */
+#define SPDIFRX_DR1_V ((uint32_t)0x00000002) /*!<Validity bit */
+#define SPDIFRX_DR1_PE ((uint32_t)0x00000001) /*!<Parity Error bit */
+
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
+#define SPDIFRX_DR1_DRNL1 ((uint32_t)0xFFFF0000) /*!<Data value Channel B */
+#define SPDIFRX_DR1_DRNL2 ((uint32_t)0x0000FFFF) /*!<Data value Channel A */
+
+/******************* Bit definition for SPDIFRX_CSR register *******************/
+#define SPDIFRX_CSR_USR ((uint32_t)0x0000FFFF) /*!<User data information */
+#define SPDIFRX_CSR_CS ((uint32_t)0x00FF0000) /*!<Channel A status information */
+#define SPDIFRX_CSR_SOB ((uint32_t)0x01000000) /*!<Start Of Block */
+
+/******************* Bit definition for SPDIFRX_DIR register *******************/
+#define SPDIFRX_DIR_THI ((uint32_t)0x000013FF) /*!<Threshold LOW */
+#define SPDIFRX_DIR_TLO ((uint32_t)0x1FFF0000) /*!<Threshold HIGH */
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
+
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
+#define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+#define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x00001000) /*!<Asynchronous start enable */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
+#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
+#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
+
+#define SYSCFG_MEMRMP_UFB_MODE ((uint32_t)0x00000100) /*!< User Flash Bank mode */
+#define SYSCFG_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC memory mapping swap */
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /*!<PK[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /*!<PK[1] pin */
+
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /*!<PK[2] pin */
+
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /*!<PK[3] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /*!<PK[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /*!<PK[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /*!<PK[6] pin */
+
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /*!<PK[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /*!<PJ[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /*!<PJ[9] pin */
+
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /*!<PJ[10] pin */
+
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /*!<PJ[11] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /*!<PJ[12] pin */
+
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /*!<PJ[13] pin */
+
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /*!<PJ[14] pin */
+
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /*!<PJ[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
+
+/****************** Bit definition for SYSCFG_CFGR register ****************/
+#define SYSCFG_CFGR_FMPI2C1_SCL ((uint32_t)0x00000001) /*!<FM+ drive capability for FMPI2C1_SCL pin */
+#define SYSCFG_CFGR_FMPI2C1_SDA ((uint32_t)0x00000002) /*!<FM+ drive capability for FMPI2C1_SDA pin */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
+
+#define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
+#define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
+#define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
+#define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
+#define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
+#define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
+#define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
+#define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
+#define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
+#define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
+#define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
+#define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
+#define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
+#define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
+#define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
+#define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
+
+#define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
+
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008) /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010) /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020) /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040) /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080) /*!< B-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN ((uint32_t)0x00001000) /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER ((uint32_t)0x00100000) /*!< OTG version */
+
+/******************** Bit definition for USB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+
+/******************** Bit definition for USB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
+#define USB_OTG_GOTGINT_IDCHNG ((uint32_t)0x00100000) /*!< Change in ID pin input value */
+
+/******************** Bit definition for USB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/******************** Bit definition for USB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_RSTDET ((uint32_t)0x00800000) /*!< Reset detected interrupt */
+#define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000) /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_RSTDEM ((uint32_t)0x00800000) /*!< Reset detected interrupt mask */
+#define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000) /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
+#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
+
+#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
+#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
+#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+
+#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
+#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
+#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
+
+#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
+#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
+#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+
+#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
+#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
+#define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /*!< USB VBUS Detection Enable */
+
+/******************** Bit definition for USB_OTG_GPWRDN) register ********************/
+#define USB_OTG_GPWRDN_ADPMEN ((uint32_t)0x00000001) /*!< ADP module enable */
+#define USB_OTG_GPWRDN_ADPIF ((uint32_t)0x00800000) /*!< ADP Interrupt flag */
+
+/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
+#define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001) /*!< LPM support enable */
+#define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002) /*!< LPM Token acknowledge enable */
+#define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003C) /*!< BESL value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040) /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080) /*!< L1 shallow sleep enable */
+#define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00) /*!< BESL threshold */
+#define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000) /*!< L1 deep sleep enable */
+#define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000) /*!< LPM response */
+#define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000) /*!< Port sleep status */
+#define USB_OTG_GLPMCFG_L1RSMOK ((uint32_t)0x00010000) /*!< Sleep State Resume OK */
+#define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000) /*!< LPM Channel Index */
+#define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000) /*!< LPM retry count */
+#define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000) /*!< Send LPM transaction */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /*!< LPM retry count status */
+#define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /*!< Enable best effort service latency */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
+#define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
+#define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
+
+/******************** Bit definition for USB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+ ((PERIPH) == SAI1_Block_B) || \
+ ((PERIPH) == SAI2_Block_A) || \
+ ((PERIPH) == SAI2_Block_B))
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** QSPI Instances ********************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+
+/******************************* CEC Instances ********************************/
+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
+
+/***************************** FMPI2C Instances *******************************/
+#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
+
+/******************************* SPDIFRX Instances ********************************/
+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 5 /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 5 /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 8 /* Including EP0 */
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 8 /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQHandler */
+#define QuadSPI_IRQHandler QUADSPI_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F446xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/include/devices/stm32f469xx.h b/f4/include/devices/stm32f469xx.h
new file mode 100644
index 0000000..0f3915a
--- /dev/null
+++ b/f4/include/devices/stm32f469xx.h
@@ -0,0 +1,10141 @@
+/**
+ ******************************************************************************
+ * @file stm32f469xx.h
+ * @author MCD Application Team
+ * @version V2.4.1
+ * @date 09-October-2015
+ * @brief CMSIS STM32F469xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f469xx
+ * @{
+ */
+
+#ifndef __STM32F469xx_H
+#define __STM32F469xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ UART7_IRQn = 82, /*!< UART7 global interrupt */
+ UART8_IRQn = 83, /*!< UART8 global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ LTDC_IRQn = 88, /*!< LTDC global Interrupt */
+ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
+ DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
+ QUADSPI_IRQn = 91, /*!< QUADSPI global Interrupt */
+ DSI_IRQn = 92 /*!< DSI global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief DMA2D Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+/**
+ * @brief DSI Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
+ __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
+ __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
+ __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
+ __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
+ __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
+ uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
+ __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
+ __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
+ __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
+ __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
+ __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
+ __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
+ __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
+ __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
+ __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
+ __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
+ __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
+ __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
+ __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
+ __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
+ __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
+ __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
+ __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
+ __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
+ __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
+ __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
+ __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
+ __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
+ __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
+ __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
+ __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
+ __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
+ __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
+ __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
+ __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
+ __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
+ __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
+ uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
+ __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
+ uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
+ __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
+ uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
+ __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
+ __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
+ uint32_t RESERVED5; /*!< Reserved, 0x114 */
+ __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
+ uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
+ __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
+ __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
+ __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
+ __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
+ __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
+ __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
+ __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
+ __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
+ __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
+ __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
+ __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
+ uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
+ __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
+ uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
+ __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
+ __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
+ __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
+ __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
+ __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
+ uint32_t RESERVED9; /*!< Reserved, 0x414 */
+ __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
+ uint32_t RESERVED10; /*!< Reserved, 0x42C */
+ __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
+} DSI_TypeDef;
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1[2];
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ __IO uint32_t RESERVED8;
+ __IO uint32_t PTPTSSR;
+ uint32_t RESERVED9[565];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ __IO uint32_t DMARSWTR;
+ uint32_t RESERVED10[8];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank3
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+ uint32_t RESERVED; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank5_6
+ */
+
+typedef struct
+{
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief LCD-TFT Display Controller
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
+ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
+ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
+ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
+ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
+ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
+ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
+ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
+ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
+ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
+ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
+ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
+ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
+ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
+ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
+} LTDC_TypeDef;
+
+/**
+ * @brief LCD-TFT Display layer x Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
+ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
+ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
+ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
+ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
+ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
+ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
+ uint32_t RESERVED0[2]; /*!< Reserved */
+ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
+ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
+ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
+ uint32_t RESERVED1[3]; /*!< Reserved */
+ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief QUAD Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
+ uint32_t Reserved6; /*!< Reserved 050h */
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
+ __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
+ __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
+ uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
+#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(160 KB) base address in the alias region */
+#define SRAM2_BASE ((uint32_t)0x20028000) /*!< SRAM2(32 KB) base address in the alias region */
+#define SRAM3_BASE ((uint32_t)0x20030000) /*!< SRAM3(128 KB) base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
+#define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< QuadSPI registers base address */
+#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x22500000) /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE ((uint32_t)0x22600000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
+#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800)
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
+#define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
+#define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
+#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
+#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
+#define DSI_BASE (APB2PERIPH_BASE + 0x6C00)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
+#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
+#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000)
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t )0xE0042000)
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
+#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
+
+#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
+#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
+#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
+#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
+#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
+#define USB_OTG_HOST_BASE ((uint32_t )0x400)
+#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
+#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
+#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
+#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
+#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
+#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define UART7 ((USART_TypeDef *) UART7_BASE)
+#define UART8 ((USART_TypeDef *) UART8_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+#define DSI ((DSI_TypeDef *)DSI_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
+#define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
+#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
+#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
+#define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
+#define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
+#define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
+#define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
+#define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
+
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
+#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
+
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
+
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
+#define DCMI_CR_CM ((uint32_t)0x00000002)
+#define DCMI_CR_CROP ((uint32_t)0x00000004)
+#define DCMI_CR_JPEG ((uint32_t)0x00000008)
+#define DCMI_CR_ESS ((uint32_t)0x00000010)
+#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
+#define DCMI_CR_HSPOL ((uint32_t)0x00000040)
+#define DCMI_CR_VSPOL ((uint32_t)0x00000080)
+#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
+#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
+#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
+#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
+#define DCMI_CR_OUTEN ((uint32_t)0x00002000)
+#define DCMI_CR_ENABLE ((uint32_t)0x00004000)
+#define DCMI_CR_BSM_0 ((uint32_t)0x00010000)
+#define DCMI_CR_BSM_1 ((uint32_t)0x00020000)
+#define DCMI_CR_OEBS ((uint32_t)0x00040000)
+#define DCMI_CR_LSM ((uint32_t)0x00080000)
+#define DCMI_CR_OELS ((uint32_t)0x00100000)
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC ((uint32_t)0x00000001)
+#define DCMI_SR_VSYNC ((uint32_t)0x00000002)
+#define DCMI_SR_FNE ((uint32_t)0x00000004)
+
+/******************** Bits definition for DCMI_RISR register ****************/
+#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
+#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
+#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
+#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
+#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
+#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
+#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
+#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
+#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
+
+/******************** Bits definition for DCMI_MISR register ****************/
+#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
+#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
+#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
+#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
+#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
+#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
+#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
+#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
+#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
+#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
+#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
+#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
+#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
+#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
+#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
+#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
+#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
+#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
+#define DMA_SxCR_ACK ((uint32_t)0x00100000)
+#define DMA_SxCR_CT ((uint32_t)0x00080000)
+#define DMA_SxCR_DBM ((uint32_t)0x00040000)
+#define DMA_SxCR_PL ((uint32_t)0x00030000)
+#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
+#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
+#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
+#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
+#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
+#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
+#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
+#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
+#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
+#define DMA_SxCR_MINC ((uint32_t)0x00000400)
+#define DMA_SxCR_PINC ((uint32_t)0x00000200)
+#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
+#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
+#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
+#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
+#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
+#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
+#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
+#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
+#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
+#define DMA_SxCR_EN ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT ((uint32_t)0x0000FFFF)
+#define DMA_SxNDT_0 ((uint32_t)0x00000001)
+#define DMA_SxNDT_1 ((uint32_t)0x00000002)
+#define DMA_SxNDT_2 ((uint32_t)0x00000004)
+#define DMA_SxNDT_3 ((uint32_t)0x00000008)
+#define DMA_SxNDT_4 ((uint32_t)0x00000010)
+#define DMA_SxNDT_5 ((uint32_t)0x00000020)
+#define DMA_SxNDT_6 ((uint32_t)0x00000040)
+#define DMA_SxNDT_7 ((uint32_t)0x00000080)
+#define DMA_SxNDT_8 ((uint32_t)0x00000100)
+#define DMA_SxNDT_9 ((uint32_t)0x00000200)
+#define DMA_SxNDT_10 ((uint32_t)0x00000400)
+#define DMA_SxNDT_11 ((uint32_t)0x00000800)
+#define DMA_SxNDT_12 ((uint32_t)0x00001000)
+#define DMA_SxNDT_13 ((uint32_t)0x00002000)
+#define DMA_SxNDT_14 ((uint32_t)0x00004000)
+#define DMA_SxNDT_15 ((uint32_t)0x00008000)
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
+#define DMA_SxFCR_FS ((uint32_t)0x00000038)
+#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
+#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
+#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
+#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
+#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
+#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
+#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
+#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
+#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
+#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
+#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
+#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
+#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
+#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
+#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
+#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
+#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
+#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
+#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
+#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
+#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
+#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
+#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
+#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
+#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
+#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
+#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
+#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
+#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
+#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
+#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
+#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
+#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
+#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
+#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
+#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
+#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
+#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
+#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
+#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
+#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
+#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
+#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
+#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
+#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
+#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
+#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
+#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
+#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
+#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
+#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
+#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
+#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
+#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
+#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
+#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
+#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
+#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
+#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
+#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
+#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
+#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
+#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
+#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
+#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
+#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
+#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
+#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
+#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
+#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
+#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
+#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
+#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
+#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
+#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
+#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
+#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
+#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
+#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
+#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
+#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
+#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
+#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
+
+
+/******************************************************************************/
+/* */
+/* AHB Master DMA2D Controller (DMA2D) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DMA2D_CR register ******************/
+
+#define DMA2D_CR_START ((uint32_t)0x00000001) /*!< Start transfer */
+#define DMA2D_CR_SUSP ((uint32_t)0x00000002) /*!< Suspend transfer */
+#define DMA2D_CR_ABORT ((uint32_t)0x00000004) /*!< Abort transfer */
+#define DMA2D_CR_TEIE ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE ((uint32_t)0x00030000) /*!< DMA2D Mode */
+
+/******************** Bit definition for DMA2D_ISR register *****************/
+
+#define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_IFSR register ****************/
+
+#define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_FGMAR register ***************/
+
+#define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_FGOR register ****************/
+
+#define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_BGMAR register ***************/
+
+#define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGOR register ****************/
+
+#define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_FGPFCCR register *************/
+
+#define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
+#define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
+#define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha mode */
+#define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
+
+/******************** Bit definition for DMA2D_FGCOLR register **************/
+
+#define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
+#define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
+
+/******************** Bit definition for DMA2D_BGPFCCR register *************/
+
+#define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
+#define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
+#define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha Mode */
+#define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
+
+/******************** Bit definition for DMA2D_BGCOLR register **************/
+
+#define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
+#define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
+
+/******************** Bit definition for DMA2D_FGCMAR register **************/
+
+#define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGCMAR register **************/
+
+#define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OPFCCR register **************/
+
+#define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /*!< Color mode */
+
+/******************** Bit definition for DMA2D_OCOLR register ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /*!< Alpha Channel Value */
+
+/******************** Bit definition for DMA2D_OMAR register ****************/
+
+#define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OOR register *****************/
+
+#define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_NLR register *****************/
+
+#define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /*!< Number of Lines */
+#define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */
+
+/******************** Bit definition for DMA2D_LWR register *****************/
+
+#define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /*!< Line Watermark */
+
+/******************** Bit definition for DMA2D_AMTCR register ***************/
+
+#define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /*!< Enable */
+#define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /*!< Dead Time */
+
+
+/******************** Bit definition for DMA2D_FGCLUT register **************/
+
+/******************** Bit definition for DMA2D_BGCLUT register **************/
+
+
+/******************************************************************************/
+/* */
+/* Display Serial Interface (DSI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DSI_VR register *****************/
+#define DSI_VR ((uint32_t)0x3133302A) /*!< DSI Host Version */
+
+/******************* Bit definition for DSI_CR register *****************/
+#define DSI_CR_EN ((uint32_t)0x00000001) /*!< DSI Host power up and reset */
+
+/******************* Bit definition for DSI_CCR register ****************/
+#define DSI_CCR_TXECKDIV ((uint32_t)0x000000FF) /*!< TX Escape Clock Division */
+#define DSI_CCR_TXECKDIV0 ((uint32_t)0x00000001)
+#define DSI_CCR_TXECKDIV1 ((uint32_t)0x00000002)
+#define DSI_CCR_TXECKDIV2 ((uint32_t)0x00000004)
+#define DSI_CCR_TXECKDIV3 ((uint32_t)0x00000008)
+#define DSI_CCR_TXECKDIV4 ((uint32_t)0x00000010)
+#define DSI_CCR_TXECKDIV5 ((uint32_t)0x00000020)
+#define DSI_CCR_TXECKDIV6 ((uint32_t)0x00000040)
+#define DSI_CCR_TXECKDIV7 ((uint32_t)0x00000080)
+
+#define DSI_CCR_TOCKDIV ((uint32_t)0x0000FF00) /*!< Timeout Clock Division */
+#define DSI_CCR_TOCKDIV0 ((uint32_t)0x00000100)
+#define DSI_CCR_TOCKDIV1 ((uint32_t)0x00000200)
+#define DSI_CCR_TOCKDIV2 ((uint32_t)0x00000400)
+#define DSI_CCR_TOCKDIV3 ((uint32_t)0x00000800)
+#define DSI_CCR_TOCKDIV4 ((uint32_t)0x00001000)
+#define DSI_CCR_TOCKDIV5 ((uint32_t)0x00002000)
+#define DSI_CCR_TOCKDIV6 ((uint32_t)0x00004000)
+#define DSI_CCR_TOCKDIV7 ((uint32_t)0x00008000)
+
+/******************* Bit definition for DSI_LVCIDR register *************/
+#define DSI_LVCIDR_VCID ((uint32_t)0x00000003) /*!< Virtual Channel ID */
+#define DSI_LVCIDR_VCID0 ((uint32_t)0x00000001)
+#define DSI_LVCIDR_VCID1 ((uint32_t)0x00000002)
+
+/******************* Bit definition for DSI_LCOLCR register *************/
+#define DSI_LCOLCR_COLC ((uint32_t)0x0000000F) /*!< Color Coding */
+#define DSI_LCOLCR_COLC0 ((uint32_t)0x00000001)
+#define DSI_LCOLCR_COLC1 ((uint32_t)0x00000020)
+#define DSI_LCOLCR_COLC2 ((uint32_t)0x00000040)
+#define DSI_LCOLCR_COLC3 ((uint32_t)0x00000080)
+
+#define DSI_LCOLCR_LPE ((uint32_t)0x00000100) /*!< Loosly Packet Enable */
+
+/******************* Bit definition for DSI_LPCR register ***************/
+#define DSI_LPCR_DEP ((uint32_t)0x00000001) /*!< Data Enable Polarity */
+#define DSI_LPCR_VSP ((uint32_t)0x00000002) /*!< VSYNC Polarity */
+#define DSI_LPCR_HSP ((uint32_t)0x00000004) /*!< HSYNC Polarity */
+
+/******************* Bit definition for DSI_LPMCR register **************/
+#define DSI_LPMCR_VLPSIZE ((uint32_t)0x000000FF) /*!< VACT Largest Packet Size */
+#define DSI_LPMCR_VLPSIZE0 ((uint32_t)0x00000001)
+#define DSI_LPMCR_VLPSIZE1 ((uint32_t)0x00000002)
+#define DSI_LPMCR_VLPSIZE2 ((uint32_t)0x00000004)
+#define DSI_LPMCR_VLPSIZE3 ((uint32_t)0x00000008)
+#define DSI_LPMCR_VLPSIZE4 ((uint32_t)0x00000010)
+#define DSI_LPMCR_VLPSIZE5 ((uint32_t)0x00000020)
+#define DSI_LPMCR_VLPSIZE6 ((uint32_t)0x00000040)
+#define DSI_LPMCR_VLPSIZE7 ((uint32_t)0x00000080)
+
+#define DSI_LPMCR_LPSIZE ((uint32_t)0x00FF0000) /*!< Largest Packet Size */
+#define DSI_LPMCR_LPSIZE0 ((uint32_t)0x00010000)
+#define DSI_LPMCR_LPSIZE1 ((uint32_t)0x00020000)
+#define DSI_LPMCR_LPSIZE2 ((uint32_t)0x00040000)
+#define DSI_LPMCR_LPSIZE3 ((uint32_t)0x00080000)
+#define DSI_LPMCR_LPSIZE4 ((uint32_t)0x00100000)
+#define DSI_LPMCR_LPSIZE5 ((uint32_t)0x00200000)
+#define DSI_LPMCR_LPSIZE6 ((uint32_t)0x00400000)
+#define DSI_LPMCR_LPSIZE7 ((uint32_t)0x00800000)
+
+/******************* Bit definition for DSI_PCR register ****************/
+#define DSI_PCR_ETTXE ((uint32_t)0x00000001) /*!< EoTp Transmission Enable */
+#define DSI_PCR_ETRXE ((uint32_t)0x00000002) /*!< EoTp Reception Enable */
+#define DSI_PCR_BTAE ((uint32_t)0x00000004) /*!< Bus Turn Around Enable */
+#define DSI_PCR_ECCRXE ((uint32_t)0x00000008) /*!< ECC Reception Enable */
+#define DSI_PCR_CRCRXE ((uint32_t)0x00000010) /*!< CRC Reception Enable */
+
+/******************* Bit definition for DSI_GVCIDR register *************/
+#define DSI_GVCIDR_VCID ((uint32_t)0x00000003) /*!< Virtual Channel ID */
+#define DSI_GVCIDR_VCID0 ((uint32_t)0x00000001)
+#define DSI_GVCIDR_VCID1 ((uint32_t)0x00000002)
+
+/******************* Bit definition for DSI_MCR register ****************/
+#define DSI_MCR_CMDM ((uint32_t)0x00000001) /*!< Command Mode */
+
+/******************* Bit definition for DSI_VMCR register ***************/
+#define DSI_VMCR_VMT ((uint32_t)0x00000003) /*!< Video Mode Type */
+#define DSI_VMCR_VMT0 ((uint32_t)0x00000001)
+#define DSI_VMCR_VMT1 ((uint32_t)0x00000002)
+
+#define DSI_VMCR_LPVSAE ((uint32_t)0x00000100) /*!< Low-Power Vertical Sync Active Enable */
+#define DSI_VMCR_LPVBPE ((uint32_t)0x00000200) /*!< Low-power Vertical Back-Porch Enable */
+#define DSI_VMCR_LPVFPE ((uint32_t)0x00000400) /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCR_LPVAE ((uint32_t)0x00000800) /*!< Low-Power Vertical Active Enable */
+#define DSI_VMCR_LPHBPE ((uint32_t)0x00001000) /*!< Low-Power Horizontal Back-Porch Enable */
+#define DSI_VMCR_LPHFPE ((uint32_t)0x00002000) /*!< Low-Power Horizontal Front-Porch Enable */
+#define DSI_VMCR_FBTAAE ((uint32_t)0x00004000) /*!< Frame Bus-Turn-Around Acknowledge Enable */
+#define DSI_VMCR_LPCE ((uint32_t)0x00008000) /*!< Low-Power Command Enable */
+#define DSI_VMCR_PGE ((uint32_t)0x00010000) /*!< Pattern Generator Enable */
+#define DSI_VMCR_PGM ((uint32_t)0x00100000) /*!< Pattern Generator Mode */
+#define DSI_VMCR_PGO ((uint32_t)0x01000000) /*!< Pattern Generator Orientation */
+
+/******************* Bit definition for DSI_VPCR register ***************/
+#define DSI_VPCR_VPSIZE ((uint32_t)0x00003FFF) /*!< Video Packet Size */
+#define DSI_VPCR_VPSIZE0 ((uint32_t)0x00000001)
+#define DSI_VPCR_VPSIZE1 ((uint32_t)0x00000002)
+#define DSI_VPCR_VPSIZE2 ((uint32_t)0x00000004)
+#define DSI_VPCR_VPSIZE3 ((uint32_t)0x00000008)
+#define DSI_VPCR_VPSIZE4 ((uint32_t)0x00000010)
+#define DSI_VPCR_VPSIZE5 ((uint32_t)0x00000020)
+#define DSI_VPCR_VPSIZE6 ((uint32_t)0x00000040)
+#define DSI_VPCR_VPSIZE7 ((uint32_t)0x00000080)
+#define DSI_VPCR_VPSIZE8 ((uint32_t)0x00000100)
+#define DSI_VPCR_VPSIZE9 ((uint32_t)0x00000200)
+#define DSI_VPCR_VPSIZE10 ((uint32_t)0x00000400)
+#define DSI_VPCR_VPSIZE11 ((uint32_t)0x00000800)
+#define DSI_VPCR_VPSIZE12 ((uint32_t)0x00001000)
+#define DSI_VPCR_VPSIZE13 ((uint32_t)0x00002000)
+
+/******************* Bit definition for DSI_VCCR register ***************/
+#define DSI_VCCR_NUMC ((uint32_t)0x00001FFF) /*!< Number of Chunks */
+#define DSI_VCCR_NUMC0 ((uint32_t)0x00000001)
+#define DSI_VCCR_NUMC1 ((uint32_t)0x00000002)
+#define DSI_VCCR_NUMC2 ((uint32_t)0x00000004)
+#define DSI_VCCR_NUMC3 ((uint32_t)0x00000008)
+#define DSI_VCCR_NUMC4 ((uint32_t)0x00000010)
+#define DSI_VCCR_NUMC5 ((uint32_t)0x00000020)
+#define DSI_VCCR_NUMC6 ((uint32_t)0x00000040)
+#define DSI_VCCR_NUMC7 ((uint32_t)0x00000080)
+#define DSI_VCCR_NUMC8 ((uint32_t)0x00000100)
+#define DSI_VCCR_NUMC9 ((uint32_t)0x00000200)
+#define DSI_VCCR_NUMC10 ((uint32_t)0x00000400)
+#define DSI_VCCR_NUMC11 ((uint32_t)0x00000800)
+#define DSI_VCCR_NUMC12 ((uint32_t)0x00001000)
+
+/******************* Bit definition for DSI_VNPCR register **************/
+#define DSI_VNPCR_NPSIZE ((uint32_t)0x00001FFF) /*!< Null Packet Size */
+#define DSI_VNPCR_NPSIZE0 ((uint32_t)0x00000001)
+#define DSI_VNPCR_NPSIZE1 ((uint32_t)0x00000002)
+#define DSI_VNPCR_NPSIZE2 ((uint32_t)0x00000004)
+#define DSI_VNPCR_NPSIZE3 ((uint32_t)0x00000008)
+#define DSI_VNPCR_NPSIZE4 ((uint32_t)0x00000010)
+#define DSI_VNPCR_NPSIZE5 ((uint32_t)0x00000020)
+#define DSI_VNPCR_NPSIZE6 ((uint32_t)0x00000040)
+#define DSI_VNPCR_NPSIZE7 ((uint32_t)0x00000080)
+#define DSI_VNPCR_NPSIZE8 ((uint32_t)0x00000100)
+#define DSI_VNPCR_NPSIZE9 ((uint32_t)0x00000200)
+#define DSI_VNPCR_NPSIZE10 ((uint32_t)0x00000400)
+#define DSI_VNPCR_NPSIZE11 ((uint32_t)0x00000800)
+#define DSI_VNPCR_NPSIZE12 ((uint32_t)0x00001000)
+
+/******************* Bit definition for DSI_VHSACR register *************/
+#define DSI_VHSACR_HSA ((uint32_t)0x00000FFF) /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACR_HSA0 ((uint32_t)0x00000001)
+#define DSI_VHSACR_HSA1 ((uint32_t)0x00000002)
+#define DSI_VHSACR_HSA2 ((uint32_t)0x00000004)
+#define DSI_VHSACR_HSA3 ((uint32_t)0x00000008)
+#define DSI_VHSACR_HSA4 ((uint32_t)0x00000010)
+#define DSI_VHSACR_HSA5 ((uint32_t)0x00000020)
+#define DSI_VHSACR_HSA6 ((uint32_t)0x00000040)
+#define DSI_VHSACR_HSA7 ((uint32_t)0x00000080)
+#define DSI_VHSACR_HSA8 ((uint32_t)0x00000100)
+#define DSI_VHSACR_HSA9 ((uint32_t)0x00000200)
+#define DSI_VHSACR_HSA10 ((uint32_t)0x00000400)
+#define DSI_VHSACR_HSA11 ((uint32_t)0x00000800)
+
+/******************* Bit definition for DSI_VHBPCR register *************/
+#define DSI_VHBPCR_HBP ((uint32_t)0x00000FFF) /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCR_HBP0 ((uint32_t)0x00000001)
+#define DSI_VHBPCR_HBP1 ((uint32_t)0x00000002)
+#define DSI_VHBPCR_HBP2 ((uint32_t)0x00000004)
+#define DSI_VHBPCR_HBP3 ((uint32_t)0x00000008)
+#define DSI_VHBPCR_HBP4 ((uint32_t)0x00000010)
+#define DSI_VHBPCR_HBP5 ((uint32_t)0x00000020)
+#define DSI_VHBPCR_HBP6 ((uint32_t)0x00000040)
+#define DSI_VHBPCR_HBP7 ((uint32_t)0x00000080)
+#define DSI_VHBPCR_HBP8 ((uint32_t)0x00000100)
+#define DSI_VHBPCR_HBP9 ((uint32_t)0x00000200)
+#define DSI_VHBPCR_HBP10 ((uint32_t)0x00000400)
+#define DSI_VHBPCR_HBP11 ((uint32_t)0x00000800)
+
+/******************* Bit definition for DSI_VLCR register ***************/
+#define DSI_VLCR_HLINE ((uint32_t)0x00007FFF) /*!< Horizontal Line duration */
+#define DSI_VLCR_HLINE0 ((uint32_t)0x00000001)
+#define DSI_VLCR_HLINE1 ((uint32_t)0x00000002)
+#define DSI_VLCR_HLINE2 ((uint32_t)0x00000004)
+#define DSI_VLCR_HLINE3 ((uint32_t)0x00000008)
+#define DSI_VLCR_HLINE4 ((uint32_t)0x00000010)
+#define DSI_VLCR_HLINE5 ((uint32_t)0x00000020)
+#define DSI_VLCR_HLINE6 ((uint32_t)0x00000040)
+#define DSI_VLCR_HLINE7 ((uint32_t)0x00000080)
+#define DSI_VLCR_HLINE8 ((uint32_t)0x00000100)
+#define DSI_VLCR_HLINE9 ((uint32_t)0x00000200)
+#define DSI_VLCR_HLINE10 ((uint32_t)0x00000400)
+#define DSI_VLCR_HLINE11 ((uint32_t)0x00000800)
+#define DSI_VLCR_HLINE12 ((uint32_t)0x00001000)
+#define DSI_VLCR_HLINE13 ((uint32_t)0x00002000)
+#define DSI_VLCR_HLINE14 ((uint32_t)0x00004000)
+
+/******************* Bit definition for DSI_VVSACR register *************/
+#define DSI_VVSACR_VSA ((uint32_t)0x000003FF) /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACR_VSA0 ((uint32_t)0x00000001)
+#define DSI_VVSACR_VSA1 ((uint32_t)0x00000002)
+#define DSI_VVSACR_VSA2 ((uint32_t)0x00000004)
+#define DSI_VVSACR_VSA3 ((uint32_t)0x00000008)
+#define DSI_VVSACR_VSA4 ((uint32_t)0x00000010)
+#define DSI_VVSACR_VSA5 ((uint32_t)0x00000020)
+#define DSI_VVSACR_VSA6 ((uint32_t)0x00000040)
+#define DSI_VVSACR_VSA7 ((uint32_t)0x00000080)
+#define DSI_VVSACR_VSA8 ((uint32_t)0x00000100)
+#define DSI_VVSACR_VSA9 ((uint32_t)0x00000200)
+
+/******************* Bit definition for DSI_VVBPCR register *************/
+#define DSI_VVBPCR_VBP ((uint32_t)0x000003FF) /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCR_VBP0 ((uint32_t)0x00000001)
+#define DSI_VVBPCR_VBP1 ((uint32_t)0x00000002)
+#define DSI_VVBPCR_VBP2 ((uint32_t)0x00000004)
+#define DSI_VVBPCR_VBP3 ((uint32_t)0x00000008)
+#define DSI_VVBPCR_VBP4 ((uint32_t)0x00000010)
+#define DSI_VVBPCR_VBP5 ((uint32_t)0x00000020)
+#define DSI_VVBPCR_VBP6 ((uint32_t)0x00000040)
+#define DSI_VVBPCR_VBP7 ((uint32_t)0x00000080)
+#define DSI_VVBPCR_VBP8 ((uint32_t)0x00000100)
+#define DSI_VVBPCR_VBP9 ((uint32_t)0x00000200)
+
+/******************* Bit definition for DSI_VVFPCR register *************/
+#define DSI_VVFPCR_VFP ((uint32_t)0x000003FF) /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCR_VFP0 ((uint32_t)0x00000001)
+#define DSI_VVFPCR_VFP1 ((uint32_t)0x00000002)
+#define DSI_VVFPCR_VFP2 ((uint32_t)0x00000004)
+#define DSI_VVFPCR_VFP3 ((uint32_t)0x00000008)
+#define DSI_VVFPCR_VFP4 ((uint32_t)0x00000010)
+#define DSI_VVFPCR_VFP5 ((uint32_t)0x00000020)
+#define DSI_VVFPCR_VFP6 ((uint32_t)0x00000040)
+#define DSI_VVFPCR_VFP7 ((uint32_t)0x00000080)
+#define DSI_VVFPCR_VFP8 ((uint32_t)0x00000100)
+#define DSI_VVFPCR_VFP9 ((uint32_t)0x00000200)
+
+/******************* Bit definition for DSI_VVACR register **************/
+#define DSI_VVACR_VA ((uint32_t)0x00003FFF) /*!< Vertical Active duration */
+#define DSI_VVACR_VA0 ((uint32_t)0x00000001)
+#define DSI_VVACR_VA1 ((uint32_t)0x00000002)
+#define DSI_VVACR_VA2 ((uint32_t)0x00000004)
+#define DSI_VVACR_VA3 ((uint32_t)0x00000008)
+#define DSI_VVACR_VA4 ((uint32_t)0x00000010)
+#define DSI_VVACR_VA5 ((uint32_t)0x00000020)
+#define DSI_VVACR_VA6 ((uint32_t)0x00000040)
+#define DSI_VVACR_VA7 ((uint32_t)0x00000080)
+#define DSI_VVACR_VA8 ((uint32_t)0x00000100)
+#define DSI_VVACR_VA9 ((uint32_t)0x00000200)
+#define DSI_VVACR_VA10 ((uint32_t)0x00000400)
+#define DSI_VVACR_VA11 ((uint32_t)0x00000800)
+#define DSI_VVACR_VA12 ((uint32_t)0x00001000)
+#define DSI_VVACR_VA13 ((uint32_t)0x00002000)
+
+/******************* Bit definition for DSI_LCCR register ***************/
+#define DSI_LCCR_CMDSIZE ((uint32_t)0x0000FFFF) /*!< Command Size */
+#define DSI_LCCR_CMDSIZE0 ((uint32_t)0x00000001)
+#define DSI_LCCR_CMDSIZE1 ((uint32_t)0x00000002)
+#define DSI_LCCR_CMDSIZE2 ((uint32_t)0x00000004)
+#define DSI_LCCR_CMDSIZE3 ((uint32_t)0x00000008)
+#define DSI_LCCR_CMDSIZE4 ((uint32_t)0x00000010)
+#define DSI_LCCR_CMDSIZE5 ((uint32_t)0x00000020)
+#define DSI_LCCR_CMDSIZE6 ((uint32_t)0x00000040)
+#define DSI_LCCR_CMDSIZE7 ((uint32_t)0x00000080)
+#define DSI_LCCR_CMDSIZE8 ((uint32_t)0x00000100)
+#define DSI_LCCR_CMDSIZE9 ((uint32_t)0x00000200)
+#define DSI_LCCR_CMDSIZE10 ((uint32_t)0x00000400)
+#define DSI_LCCR_CMDSIZE11 ((uint32_t)0x00000800)
+#define DSI_LCCR_CMDSIZE12 ((uint32_t)0x00001000)
+#define DSI_LCCR_CMDSIZE13 ((uint32_t)0x00002000)
+#define DSI_LCCR_CMDSIZE14 ((uint32_t)0x00004000)
+#define DSI_LCCR_CMDSIZE15 ((uint32_t)0x00008000)
+
+/******************* Bit definition for DSI_CMCR register ***************/
+#define DSI_CMCR_TEARE ((uint32_t)0x00000001) /*!< Tearing Effect Acknowledge Request Enable */
+#define DSI_CMCR_ARE ((uint32_t)0x00000002) /*!< Acknowledge Request Enable */
+#define DSI_CMCR_GSW0TX ((uint32_t)0x00000100) /*!< Generic Short Write Zero parameters Transmission */
+#define DSI_CMCR_GSW1TX ((uint32_t)0x00000200) /*!< Generic Short Write One parameters Transmission */
+#define DSI_CMCR_GSW2TX ((uint32_t)0x00000400) /*!< Generic Short Write Two parameters Transmission */
+#define DSI_CMCR_GSR0TX ((uint32_t)0x00000800) /*!< Generic Short Read Zero parameters Transmission */
+#define DSI_CMCR_GSR1TX ((uint32_t)0x00001000) /*!< Generic Short Read One parameters Transmission */
+#define DSI_CMCR_GSR2TX ((uint32_t)0x00002000) /*!< Generic Short Read Two parameters Transmission */
+#define DSI_CMCR_GLWTX ((uint32_t)0x00004000) /*!< Generic Long Write Transmission */
+#define DSI_CMCR_DSW0TX ((uint32_t)0x00010000) /*!< DCS Short Write Zero parameter Transmission */
+#define DSI_CMCR_DSW1TX ((uint32_t)0x00020000) /*!< DCS Short Read One parameter Transmission */
+#define DSI_CMCR_DSR0TX ((uint32_t)0x00040000) /*!< DCS Short Read Zero parameter Transmission */
+#define DSI_CMCR_DLWTX ((uint32_t)0x00080000) /*!< DCS Long Write Transmission */
+#define DSI_CMCR_MRDPS ((uint32_t)0x01000000) /*!< Maximum Read Packet Size */
+
+/******************* Bit definition for DSI_GHCR register ***************/
+#define DSI_GHCR_DT ((uint32_t)0x0000003F) /*!< Type */
+#define DSI_GHCR_DT0 ((uint32_t)0x00000001)
+#define DSI_GHCR_DT1 ((uint32_t)0x00000002)
+#define DSI_GHCR_DT2 ((uint32_t)0x00000004)
+#define DSI_GHCR_DT3 ((uint32_t)0x00000008)
+#define DSI_GHCR_DT4 ((uint32_t)0x00000010)
+#define DSI_GHCR_DT5 ((uint32_t)0x00000020)
+
+#define DSI_GHCR_VCID ((uint32_t)0x000000C0) /*!< Channel */
+#define DSI_GHCR_VCID0 ((uint32_t)0x00000040)
+#define DSI_GHCR_VCID1 ((uint32_t)0x00000080)
+
+#define DSI_GHCR_WCLSB ((uint32_t)0x0000FF00) /*!< WordCount LSB */
+#define DSI_GHCR_WCLSB0 ((uint32_t)0x00000100)
+#define DSI_GHCR_WCLSB1 ((uint32_t)0x00000200)
+#define DSI_GHCR_WCLSB2 ((uint32_t)0x00000400)
+#define DSI_GHCR_WCLSB3 ((uint32_t)0x00000800)
+#define DSI_GHCR_WCLSB4 ((uint32_t)0x00001000)
+#define DSI_GHCR_WCLSB5 ((uint32_t)0x00002000)
+#define DSI_GHCR_WCLSB6 ((uint32_t)0x00004000)
+#define DSI_GHCR_WCLSB7 ((uint32_t)0x00008000)
+
+#define DSI_GHCR_WCMSB ((uint32_t)0x00FF0000) /*!< WordCount MSB */
+#define DSI_GHCR_WCMSB0 ((uint32_t)0x00010000)
+#define DSI_GHCR_WCMSB1 ((uint32_t)0x00020000)
+#define DSI_GHCR_WCMSB2 ((uint32_t)0x00040000)
+#define DSI_GHCR_WCMSB3 ((uint32_t)0x00080000)
+#define DSI_GHCR_WCMSB4 ((uint32_t)0x00100000)
+#define DSI_GHCR_WCMSB5 ((uint32_t)0x00200000)
+#define DSI_GHCR_WCMSB6 ((uint32_t)0x00400000)
+#define DSI_GHCR_WCMSB7 ((uint32_t)0x00800000)
+
+/******************* Bit definition for DSI_GPDR register ***************/
+#define DSI_GPDR_DATA1 ((uint32_t)0x000000FF) /*!< Payload Byte 1 */
+#define DSI_GPDR_DATA1_0 ((uint32_t)0x00000001)
+#define DSI_GPDR_DATA1_1 ((uint32_t)0x00000002)
+#define DSI_GPDR_DATA1_2 ((uint32_t)0x00000004)
+#define DSI_GPDR_DATA1_3 ((uint32_t)0x00000008)
+#define DSI_GPDR_DATA1_4 ((uint32_t)0x00000010)
+#define DSI_GPDR_DATA1_5 ((uint32_t)0x00000020)
+#define DSI_GPDR_DATA1_6 ((uint32_t)0x00000040)
+#define DSI_GPDR_DATA1_7 ((uint32_t)0x00000080)
+
+#define DSI_GPDR_DATA2 ((uint32_t)0x0000FF00) /*!< Payload Byte 2 */
+#define DSI_GPDR_DATA2_0 ((uint32_t)0x00000100)
+#define DSI_GPDR_DATA2_1 ((uint32_t)0x00000200)
+#define DSI_GPDR_DATA2_2 ((uint32_t)0x00000400)
+#define DSI_GPDR_DATA2_3 ((uint32_t)0x00000800)
+#define DSI_GPDR_DATA2_4 ((uint32_t)0x00001000)
+#define DSI_GPDR_DATA2_5 ((uint32_t)0x00002000)
+#define DSI_GPDR_DATA2_6 ((uint32_t)0x00004000)
+#define DSI_GPDR_DATA2_7 ((uint32_t)0x00008000)
+
+#define DSI_GPDR_DATA3 ((uint32_t)0x00FF0000) /*!< Payload Byte 3 */
+#define DSI_GPDR_DATA3_0 ((uint32_t)0x00010000)
+#define DSI_GPDR_DATA3_1 ((uint32_t)0x00020000)
+#define DSI_GPDR_DATA3_2 ((uint32_t)0x00040000)
+#define DSI_GPDR_DATA3_3 ((uint32_t)0x00080000)
+#define DSI_GPDR_DATA3_4 ((uint32_t)0x00100000)
+#define DSI_GPDR_DATA3_5 ((uint32_t)0x00200000)
+#define DSI_GPDR_DATA3_6 ((uint32_t)0x00400000)
+#define DSI_GPDR_DATA3_7 ((uint32_t)0x00800000)
+
+#define DSI_GPDR_DATA4 ((uint32_t)0xFF000000) /*!< Payload Byte 4 */
+#define DSI_GPDR_DATA4_0 ((uint32_t)0x01000000)
+#define DSI_GPDR_DATA4_1 ((uint32_t)0x02000000)
+#define DSI_GPDR_DATA4_2 ((uint32_t)0x04000000)
+#define DSI_GPDR_DATA4_3 ((uint32_t)0x08000000)
+#define DSI_GPDR_DATA4_4 ((uint32_t)0x10000000)
+#define DSI_GPDR_DATA4_5 ((uint32_t)0x20000000)
+#define DSI_GPDR_DATA4_6 ((uint32_t)0x40000000)
+#define DSI_GPDR_DATA4_7 ((uint32_t)0x80000000)
+
+/******************* Bit definition for DSI_GPSR register ***************/
+#define DSI_GPSR_CMDFE ((uint32_t)0x00000001) /*!< Command FIFO Empty */
+#define DSI_GPSR_CMDFF ((uint32_t)0x00000002) /*!< Command FIFO Full */
+#define DSI_GPSR_PWRFE ((uint32_t)0x00000004) /*!< Payload Write FIFO Empty */
+#define DSI_GPSR_PWRFF ((uint32_t)0x00000008) /*!< Payload Write FIFO Full */
+#define DSI_GPSR_PRDFE ((uint32_t)0x00000010) /*!< Payload Read FIFO Empty */
+#define DSI_GPSR_PRDFF ((uint32_t)0x00000020) /*!< Payload Read FIFO Full */
+#define DSI_GPSR_RCB ((uint32_t)0x00000040) /*!< Read Command Busy */
+
+/******************* Bit definition for DSI_TCCR0 register **************/
+#define DSI_TCCR0_LPRX_TOCNT ((uint32_t)0x0000FFFF) /*!< Low-power Reception Timeout Counter */
+#define DSI_TCCR0_LPRX_TOCNT0 ((uint32_t)0x00000001)
+#define DSI_TCCR0_LPRX_TOCNT1 ((uint32_t)0x00000002)
+#define DSI_TCCR0_LPRX_TOCNT2 ((uint32_t)0x00000004)
+#define DSI_TCCR0_LPRX_TOCNT3 ((uint32_t)0x00000008)
+#define DSI_TCCR0_LPRX_TOCNT4 ((uint32_t)0x00000010)
+#define DSI_TCCR0_LPRX_TOCNT5 ((uint32_t)0x00000020)
+#define DSI_TCCR0_LPRX_TOCNT6 ((uint32_t)0x00000040)
+#define DSI_TCCR0_LPRX_TOCNT7 ((uint32_t)0x00000080)
+#define DSI_TCCR0_LPRX_TOCNT8 ((uint32_t)0x00000100)
+#define DSI_TCCR0_LPRX_TOCNT9 ((uint32_t)0x00000200)
+#define DSI_TCCR0_LPRX_TOCNT10 ((uint32_t)0x00000400)
+#define DSI_TCCR0_LPRX_TOCNT11 ((uint32_t)0x00000800)
+#define DSI_TCCR0_LPRX_TOCNT12 ((uint32_t)0x00001000)
+#define DSI_TCCR0_LPRX_TOCNT13 ((uint32_t)0x00002000)
+#define DSI_TCCR0_LPRX_TOCNT14 ((uint32_t)0x00004000)
+#define DSI_TCCR0_LPRX_TOCNT15 ((uint32_t)0x00008000)
+
+#define DSI_TCCR0_HSTX_TOCNT ((uint32_t)0xFFFF0000) /*!< High-Speed Transmission Timeout Counter */
+#define DSI_TCCR0_HSTX_TOCNT0 ((uint32_t)0x00010000)
+#define DSI_TCCR0_HSTX_TOCNT1 ((uint32_t)0x00020000)
+#define DSI_TCCR0_HSTX_TOCNT2 ((uint32_t)0x00040000)
+#define DSI_TCCR0_HSTX_TOCNT3 ((uint32_t)0x00080000)
+#define DSI_TCCR0_HSTX_TOCNT4 ((uint32_t)0x00100000)
+#define DSI_TCCR0_HSTX_TOCNT5 ((uint32_t)0x00200000)
+#define DSI_TCCR0_HSTX_TOCNT6 ((uint32_t)0x00400000)
+#define DSI_TCCR0_HSTX_TOCNT7 ((uint32_t)0x00800000)
+#define DSI_TCCR0_HSTX_TOCNT8 ((uint32_t)0x01000000)
+#define DSI_TCCR0_HSTX_TOCNT9 ((uint32_t)0x02000000)
+#define DSI_TCCR0_HSTX_TOCNT10 ((uint32_t)0x04000000)
+#define DSI_TCCR0_HSTX_TOCNT11 ((uint32_t)0x08000000)
+#define DSI_TCCR0_HSTX_TOCNT12 ((uint32_t)0x10000000)
+#define DSI_TCCR0_HSTX_TOCNT13 ((uint32_t)0x20000000)
+#define DSI_TCCR0_HSTX_TOCNT14 ((uint32_t)0x40000000)
+#define DSI_TCCR0_HSTX_TOCNT15 ((uint32_t)0x80000000)
+
+/******************* Bit definition for DSI_TCCR1 register **************/
+#define DSI_TCCR1_HSRD_TOCNT ((uint32_t)0x0000FFFF) /*!< High-Speed Read Timeout Counter */
+#define DSI_TCCR1_HSRD_TOCNT0 ((uint32_t)0x00000001)
+#define DSI_TCCR1_HSRD_TOCNT1 ((uint32_t)0x00000002)
+#define DSI_TCCR1_HSRD_TOCNT2 ((uint32_t)0x00000004)
+#define DSI_TCCR1_HSRD_TOCNT3 ((uint32_t)0x00000008)
+#define DSI_TCCR1_HSRD_TOCNT4 ((uint32_t)0x00000010)
+#define DSI_TCCR1_HSRD_TOCNT5 ((uint32_t)0x00000020)
+#define DSI_TCCR1_HSRD_TOCNT6 ((uint32_t)0x00000040)
+#define DSI_TCCR1_HSRD_TOCNT7 ((uint32_t)0x00000080)
+#define DSI_TCCR1_HSRD_TOCNT8 ((uint32_t)0x00000100)
+#define DSI_TCCR1_HSRD_TOCNT9 ((uint32_t)0x00000200)
+#define DSI_TCCR1_HSRD_TOCNT10 ((uint32_t)0x00000400)
+#define DSI_TCCR1_HSRD_TOCNT11 ((uint32_t)0x00000800)
+#define DSI_TCCR1_HSRD_TOCNT12 ((uint32_t)0x00001000)
+#define DSI_TCCR1_HSRD_TOCNT13 ((uint32_t)0x00002000)
+#define DSI_TCCR1_HSRD_TOCNT14 ((uint32_t)0x00004000)
+#define DSI_TCCR1_HSRD_TOCNT15 ((uint32_t)0x00008000)
+
+/******************* Bit definition for DSI_TCCR2 register **************/
+#define DSI_TCCR2_LPRD_TOCNT ((uint32_t)0x0000FFFF) /*!< Low-Power Read Timeout Counter */
+#define DSI_TCCR2_LPRD_TOCNT0 ((uint32_t)0x00000001)
+#define DSI_TCCR2_LPRD_TOCNT1 ((uint32_t)0x00000002)
+#define DSI_TCCR2_LPRD_TOCNT2 ((uint32_t)0x00000004)
+#define DSI_TCCR2_LPRD_TOCNT3 ((uint32_t)0x00000008)
+#define DSI_TCCR2_LPRD_TOCNT4 ((uint32_t)0x00000010)
+#define DSI_TCCR2_LPRD_TOCNT5 ((uint32_t)0x00000020)
+#define DSI_TCCR2_LPRD_TOCNT6 ((uint32_t)0x00000040)
+#define DSI_TCCR2_LPRD_TOCNT7 ((uint32_t)0x00000080)
+#define DSI_TCCR2_LPRD_TOCNT8 ((uint32_t)0x00000100)
+#define DSI_TCCR2_LPRD_TOCNT9 ((uint32_t)0x00000200)
+#define DSI_TCCR2_LPRD_TOCNT10 ((uint32_t)0x00000400)
+#define DSI_TCCR2_LPRD_TOCNT11 ((uint32_t)0x00000800)
+#define DSI_TCCR2_LPRD_TOCNT12 ((uint32_t)0x00001000)
+#define DSI_TCCR2_LPRD_TOCNT13 ((uint32_t)0x00002000)
+#define DSI_TCCR2_LPRD_TOCNT14 ((uint32_t)0x00004000)
+#define DSI_TCCR2_LPRD_TOCNT15 ((uint32_t)0x00008000)
+
+/******************* Bit definition for DSI_TCCR3 register **************/
+#define DSI_TCCR3_HSWR_TOCNT ((uint32_t)0x0000FFFF) /*!< High-Speed Write Timeout Counter */
+#define DSI_TCCR3_HSWR_TOCNT0 ((uint32_t)0x00000001)
+#define DSI_TCCR3_HSWR_TOCNT1 ((uint32_t)0x00000002)
+#define DSI_TCCR3_HSWR_TOCNT2 ((uint32_t)0x00000004)
+#define DSI_TCCR3_HSWR_TOCNT3 ((uint32_t)0x00000008)
+#define DSI_TCCR3_HSWR_TOCNT4 ((uint32_t)0x00000010)
+#define DSI_TCCR3_HSWR_TOCNT5 ((uint32_t)0x00000020)
+#define DSI_TCCR3_HSWR_TOCNT6 ((uint32_t)0x00000040)
+#define DSI_TCCR3_HSWR_TOCNT7 ((uint32_t)0x00000080)
+#define DSI_TCCR3_HSWR_TOCNT8 ((uint32_t)0x00000100)
+#define DSI_TCCR3_HSWR_TOCNT9 ((uint32_t)0x00000200)
+#define DSI_TCCR3_HSWR_TOCNT10 ((uint32_t)0x00000400)
+#define DSI_TCCR3_HSWR_TOCNT11 ((uint32_t)0x00000800)
+#define DSI_TCCR3_HSWR_TOCNT12 ((uint32_t)0x00001000)
+#define DSI_TCCR3_HSWR_TOCNT13 ((uint32_t)0x00002000)
+#define DSI_TCCR3_HSWR_TOCNT14 ((uint32_t)0x00004000)
+#define DSI_TCCR3_HSWR_TOCNT15 ((uint32_t)0x00008000)
+
+#define DSI_TCCR3_PM ((uint32_t)0x01000000) /*!< Presp Mode */
+
+/******************* Bit definition for DSI_TCCR4 register **************/
+#define DSI_TCCR4_LPWR_TOCNT ((uint32_t)0x0000FFFF) /*!< Low-Power Write Timeout Counter */
+#define DSI_TCCR4_LPWR_TOCNT0 ((uint32_t)0x00000001)
+#define DSI_TCCR4_LPWR_TOCNT1 ((uint32_t)0x00000002)
+#define DSI_TCCR4_LPWR_TOCNT2 ((uint32_t)0x00000004)
+#define DSI_TCCR4_LPWR_TOCNT3 ((uint32_t)0x00000008)
+#define DSI_TCCR4_LPWR_TOCNT4 ((uint32_t)0x00000010)
+#define DSI_TCCR4_LPWR_TOCNT5 ((uint32_t)0x00000020)
+#define DSI_TCCR4_LPWR_TOCNT6 ((uint32_t)0x00000040)
+#define DSI_TCCR4_LPWR_TOCNT7 ((uint32_t)0x00000080)
+#define DSI_TCCR4_LPWR_TOCNT8 ((uint32_t)0x00000100)
+#define DSI_TCCR4_LPWR_TOCNT9 ((uint32_t)0x00000200)
+#define DSI_TCCR4_LPWR_TOCNT10 ((uint32_t)0x00000400)
+#define DSI_TCCR4_LPWR_TOCNT11 ((uint32_t)0x00000800)
+#define DSI_TCCR4_LPWR_TOCNT12 ((uint32_t)0x00001000)
+#define DSI_TCCR4_LPWR_TOCNT13 ((uint32_t)0x00002000)
+#define DSI_TCCR4_LPWR_TOCNT14 ((uint32_t)0x00004000)
+#define DSI_TCCR4_LPWR_TOCNT15 ((uint32_t)0x00008000)
+
+/******************* Bit definition for DSI_TCCR5 register **************/
+#define DSI_TCCR5_BTA_TOCNT ((uint32_t)0x0000FFFF) /*!< Bus-Turn-Around Timeout Counter */
+#define DSI_TCCR5_BTA_TOCNT0 ((uint32_t)0x00000001)
+#define DSI_TCCR5_BTA_TOCNT1 ((uint32_t)0x00000002)
+#define DSI_TCCR5_BTA_TOCNT2 ((uint32_t)0x00000004)
+#define DSI_TCCR5_BTA_TOCNT3 ((uint32_t)0x00000008)
+#define DSI_TCCR5_BTA_TOCNT4 ((uint32_t)0x00000010)
+#define DSI_TCCR5_BTA_TOCNT5 ((uint32_t)0x00000020)
+#define DSI_TCCR5_BTA_TOCNT6 ((uint32_t)0x00000040)
+#define DSI_TCCR5_BTA_TOCNT7 ((uint32_t)0x00000080)
+#define DSI_TCCR5_BTA_TOCNT8 ((uint32_t)0x00000100)
+#define DSI_TCCR5_BTA_TOCNT9 ((uint32_t)0x00000200)
+#define DSI_TCCR5_BTA_TOCNT10 ((uint32_t)0x00000400)
+#define DSI_TCCR5_BTA_TOCNT11 ((uint32_t)0x00000800)
+#define DSI_TCCR5_BTA_TOCNT12 ((uint32_t)0x00001000)
+#define DSI_TCCR5_BTA_TOCNT13 ((uint32_t)0x00002000)
+#define DSI_TCCR5_BTA_TOCNT14 ((uint32_t)0x00004000)
+#define DSI_TCCR5_BTA_TOCNT15 ((uint32_t)0x00008000)
+
+/******************* Bit definition for DSI_TDCR register ***************/
+#define DSI_TDCR_3DM ((uint32_t)0x00000003) /*!< 3D Mode */
+#define DSI_TDCR_3DM0 ((uint32_t)0x00000001)
+#define DSI_TDCR_3DM1 ((uint32_t)0x00000002)
+
+#define DSI_TDCR_3DF ((uint32_t)0x0000000C) /*!< 3D Format */
+#define DSI_TDCR_3DF0 ((uint32_t)0x00000004)
+#define DSI_TDCR_3DF1 ((uint32_t)0x00000008)
+
+#define DSI_TDCR_SVS ((uint32_t)0x00000010) /*!< Second VSYNC */
+#define DSI_TDCR_RF ((uint32_t)0x00000020) /*!< Right First */
+#define DSI_TDCR_S3DC ((uint32_t)0x00010000) /*!< Send 3D Control */
+
+/******************* Bit definition for DSI_CLCR register ***************/
+#define DSI_CLCR_DPCC ((uint32_t)0x00000001) /*!< D-PHY Clock Control */
+#define DSI_CLCR_ACR ((uint32_t)0x00000002) /*!< Automatic Clocklane Control */
+
+/******************* Bit definition for DSI_CLTCR register **************/
+#define DSI_CLTCR_LP2HS_TIME ((uint32_t)0x000003FF) /*!< Low-Power to High-Speed Time */
+#define DSI_CLTCR_LP2HS_TIME0 ((uint32_t)0x00000001)
+#define DSI_CLTCR_LP2HS_TIME1 ((uint32_t)0x00000002)
+#define DSI_CLTCR_LP2HS_TIME2 ((uint32_t)0x00000004)
+#define DSI_CLTCR_LP2HS_TIME3 ((uint32_t)0x00000008)
+#define DSI_CLTCR_LP2HS_TIME4 ((uint32_t)0x00000010)
+#define DSI_CLTCR_LP2HS_TIME5 ((uint32_t)0x00000020)
+#define DSI_CLTCR_LP2HS_TIME6 ((uint32_t)0x00000040)
+#define DSI_CLTCR_LP2HS_TIME7 ((uint32_t)0x00000080)
+#define DSI_CLTCR_LP2HS_TIME8 ((uint32_t)0x00000100)
+#define DSI_CLTCR_LP2HS_TIME9 ((uint32_t)0x00000200)
+
+#define DSI_CLTCR_HS2LP_TIME ((uint32_t)0x03FF0000) /*!< High-Speed to Low-Power Time */
+#define DSI_CLTCR_HS2LP_TIME0 ((uint32_t)0x00010000)
+#define DSI_CLTCR_HS2LP_TIME1 ((uint32_t)0x00020000)
+#define DSI_CLTCR_HS2LP_TIME2 ((uint32_t)0x00040000)
+#define DSI_CLTCR_HS2LP_TIME3 ((uint32_t)0x00080000)
+#define DSI_CLTCR_HS2LP_TIME4 ((uint32_t)0x00100000)
+#define DSI_CLTCR_HS2LP_TIME5 ((uint32_t)0x00200000)
+#define DSI_CLTCR_HS2LP_TIME6 ((uint32_t)0x00400000)
+#define DSI_CLTCR_HS2LP_TIME7 ((uint32_t)0x00800000)
+#define DSI_CLTCR_HS2LP_TIME8 ((uint32_t)0x01000000)
+#define DSI_CLTCR_HS2LP_TIME9 ((uint32_t)0x02000000)
+
+/******************* Bit definition for DSI_DLTCR register **************/
+#define DSI_DLTCR_MRD_TIME ((uint32_t)0x00007FFF) /*!< Maximum Read Time */
+#define DSI_DLTCR_MRD_TIME0 ((uint32_t)0x00000001)
+#define DSI_DLTCR_MRD_TIME1 ((uint32_t)0x00000002)
+#define DSI_DLTCR_MRD_TIME2 ((uint32_t)0x00000004)
+#define DSI_DLTCR_MRD_TIME3 ((uint32_t)0x00000008)
+#define DSI_DLTCR_MRD_TIME4 ((uint32_t)0x00000010)
+#define DSI_DLTCR_MRD_TIME5 ((uint32_t)0x00000020)
+#define DSI_DLTCR_MRD_TIME6 ((uint32_t)0x00000040)
+#define DSI_DLTCR_MRD_TIME7 ((uint32_t)0x00000080)
+#define DSI_DLTCR_MRD_TIME8 ((uint32_t)0x00000100)
+#define DSI_DLTCR_MRD_TIME9 ((uint32_t)0x00000200)
+#define DSI_DLTCR_MRD_TIME10 ((uint32_t)0x00000400)
+#define DSI_DLTCR_MRD_TIME11 ((uint32_t)0x00000800)
+#define DSI_DLTCR_MRD_TIME12 ((uint32_t)0x00001000)
+#define DSI_DLTCR_MRD_TIME13 ((uint32_t)0x00002000)
+#define DSI_DLTCR_MRD_TIME14 ((uint32_t)0x00004000)
+
+#define DSI_DLTCR_LP2HS_TIME ((uint32_t)0x00FF0000) /*!< Low-Power To High-Speed Time */
+#define DSI_DLTCR_LP2HS_TIME0 ((uint32_t)0x00010000)
+#define DSI_DLTCR_LP2HS_TIME1 ((uint32_t)0x00020000)
+#define DSI_DLTCR_LP2HS_TIME2 ((uint32_t)0x00040000)
+#define DSI_DLTCR_LP2HS_TIME3 ((uint32_t)0x00080000)
+#define DSI_DLTCR_LP2HS_TIME4 ((uint32_t)0x00100000)
+#define DSI_DLTCR_LP2HS_TIME5 ((uint32_t)0x00200000)
+#define DSI_DLTCR_LP2HS_TIME6 ((uint32_t)0x00400000)
+#define DSI_DLTCR_LP2HS_TIME7 ((uint32_t)0x00800000)
+
+#define DSI_DLTCR_HS2LP_TIME ((uint32_t)0xFF000000) /*!< High-Speed To Low-Power Time */
+#define DSI_DLTCR_HS2LP_TIME0 ((uint32_t)0x01000000)
+#define DSI_DLTCR_HS2LP_TIME1 ((uint32_t)0x02000000)
+#define DSI_DLTCR_HS2LP_TIME2 ((uint32_t)0x04000000)
+#define DSI_DLTCR_HS2LP_TIME3 ((uint32_t)0x08000000)
+#define DSI_DLTCR_HS2LP_TIME4 ((uint32_t)0x10000000)
+#define DSI_DLTCR_HS2LP_TIME5 ((uint32_t)0x20000000)
+#define DSI_DLTCR_HS2LP_TIME6 ((uint32_t)0x40000000)
+#define DSI_DLTCR_HS2LP_TIME7 ((uint32_t)0x80000000)
+
+/******************* Bit definition for DSI_PCTLR register **************/
+#define DSI_PCTLR_DEN ((uint32_t)0x00000002) /*!< Digital Enable */
+#define DSI_PCTLR_CKE ((uint32_t)0x00000004) /*!< Clock Enable */
+
+/******************* Bit definition for DSI_PCONFR register *************/
+#define DSI_PCONFR_NL ((uint32_t)0x00000003) /*!< Number of Lanes */
+#define DSI_PCONFR_NL0 ((uint32_t)0x00000001)
+#define DSI_PCONFR_NL1 ((uint32_t)0x00000002)
+
+#define DSI_PCONFR_SW_TIME ((uint32_t)0x0000FF00) /*!< Stop Wait Time */
+#define DSI_PCONFR_SW_TIME0 ((uint32_t)0x00000100)
+#define DSI_PCONFR_SW_TIME1 ((uint32_t)0x00000200)
+#define DSI_PCONFR_SW_TIME2 ((uint32_t)0x00000400)
+#define DSI_PCONFR_SW_TIME3 ((uint32_t)0x00000800)
+#define DSI_PCONFR_SW_TIME4 ((uint32_t)0x00001000)
+#define DSI_PCONFR_SW_TIME5 ((uint32_t)0x00002000)
+#define DSI_PCONFR_SW_TIME6 ((uint32_t)0x00004000)
+#define DSI_PCONFR_SW_TIME7 ((uint32_t)0x00008000)
+
+/******************* Bit definition for DSI_PUCR register ***************/
+#define DSI_PUCR_URCL ((uint32_t)0x00000001) /*!< ULPS Request on Clock Lane */
+#define DSI_PUCR_UECL ((uint32_t)0x00000002) /*!< ULPS Exit on Clock Lane */
+#define DSI_PUCR_URDL ((uint32_t)0x00000004) /*!< ULPS Request on Data Lane */
+#define DSI_PUCR_UEDL ((uint32_t)0x00000008) /*!< ULPS Exit on Data Lane */
+
+/******************* Bit definition for DSI_PTTCR register **************/
+#define DSI_PTTCR_TX_TRIG ((uint32_t)0x0000000F) /*!< Transmission Trigger */
+#define DSI_PTTCR_TX_TRIG0 ((uint32_t)0x00000001)
+#define DSI_PTTCR_TX_TRIG1 ((uint32_t)0x00000002)
+#define DSI_PTTCR_TX_TRIG2 ((uint32_t)0x00000004)
+#define DSI_PTTCR_TX_TRIG3 ((uint32_t)0x00000008)
+
+/******************* Bit definition for DSI_PSR register ****************/
+#define DSI_PSR_PD ((uint32_t)0x00000002) /*!< PHY Direction */
+#define DSI_PSR_PSSC ((uint32_t)0x00000004) /*!< PHY Stop State Clock lane */
+#define DSI_PSR_UANC ((uint32_t)0x00000008) /*!< ULPS Active Not Clock lane */
+#define DSI_PSR_PSS0 ((uint32_t)0x00000010) /*!< PHY Stop State lane 0 */
+#define DSI_PSR_UAN0 ((uint32_t)0x00000020) /*!< ULPS Active Not lane 0 */
+#define DSI_PSR_RUE0 ((uint32_t)0x00000040) /*!< RX ULPS Escape lane 0 */
+#define DSI_PSR_PSS1 ((uint32_t)0x00000080) /*!< PHY Stop State lane 1 */
+#define DSI_PSR_UAN1 ((uint32_t)0x00000100) /*!< ULPS Active Not lane 1 */
+
+/******************* Bit definition for DSI_ISR0 register ***************/
+#define DSI_ISR0_AE0 ((uint32_t)0x00000001) /*!< Acknowledge Error 0 */
+#define DSI_ISR0_AE1 ((uint32_t)0x00000002) /*!< Acknowledge Error 1 */
+#define DSI_ISR0_AE2 ((uint32_t)0x00000004) /*!< Acknowledge Error 2 */
+#define DSI_ISR0_AE3 ((uint32_t)0x00000008) /*!< Acknowledge Error 3 */
+#define DSI_ISR0_AE4 ((uint32_t)0x00000010) /*!< Acknowledge Error 4 */
+#define DSI_ISR0_AE5 ((uint32_t)0x00000020) /*!< Acknowledge Error 5 */
+#define DSI_ISR0_AE6 ((uint32_t)0x00000040) /*!< Acknowledge Error 6 */
+#define DSI_ISR0_AE7 ((uint32_t)0x00000080) /*!< Acknowledge Error 7 */
+#define DSI_ISR0_AE8 ((uint32_t)0x00000100) /*!< Acknowledge Error 8 */
+#define DSI_ISR0_AE9 ((uint32_t)0x00000200) /*!< Acknowledge Error 9 */
+#define DSI_ISR0_AE10 ((uint32_t)0x00000400) /*!< Acknowledge Error 10 */
+#define DSI_ISR0_AE11 ((uint32_t)0x00000800) /*!< Acknowledge Error 11 */
+#define DSI_ISR0_AE12 ((uint32_t)0x00001000) /*!< Acknowledge Error 12 */
+#define DSI_ISR0_AE13 ((uint32_t)0x00002000) /*!< Acknowledge Error 13 */
+#define DSI_ISR0_AE14 ((uint32_t)0x00004000) /*!< Acknowledge Error 14 */
+#define DSI_ISR0_AE15 ((uint32_t)0x00008000) /*!< Acknowledge Error 15 */
+#define DSI_ISR0_PE0 ((uint32_t)0x00010000) /*!< PHY Error 0 */
+#define DSI_ISR0_PE1 ((uint32_t)0x00020000) /*!< PHY Error 1 */
+#define DSI_ISR0_PE2 ((uint32_t)0x00040000) /*!< PHY Error 2 */
+#define DSI_ISR0_PE3 ((uint32_t)0x00080000) /*!< PHY Error 3 */
+#define DSI_ISR0_PE4 ((uint32_t)0x00100000) /*!< PHY Error 4 */
+
+/******************* Bit definition for DSI_ISR1 register ***************/
+#define DSI_ISR1_TOHSTX ((uint32_t)0x00000001) /*!< Timeout High-Speed Transmission */
+#define DSI_ISR1_TOLPRX ((uint32_t)0x00000002) /*!< Timeout Low-Power Reception */
+#define DSI_ISR1_ECCSE ((uint32_t)0x00000004) /*!< ECC Single-bit Error */
+#define DSI_ISR1_ECCME ((uint32_t)0x00000008) /*!< ECC Multi-bit Error */
+#define DSI_ISR1_CRCE ((uint32_t)0x00000010) /*!< CRC Error */
+#define DSI_ISR1_PSE ((uint32_t)0x00000020) /*!< Packet Size Error */
+#define DSI_ISR1_EOTPE ((uint32_t)0x00000040) /*!< EoTp Error */
+#define DSI_ISR1_LPWRE ((uint32_t)0x00000080) /*!< LTDC Payload Write Error */
+#define DSI_ISR1_GCWRE ((uint32_t)0x00000100) /*!< Generic Command Write Error */
+#define DSI_ISR1_GPWRE ((uint32_t)0x00000200) /*!< Generic Payload Write Error */
+#define DSI_ISR1_GPTXE ((uint32_t)0x00000400) /*!< Generic Payload Transmit Error */
+#define DSI_ISR1_GPRDE ((uint32_t)0x00000800) /*!< Generic Payload Read Error */
+#define DSI_ISR1_GPRXE ((uint32_t)0x00001000) /*!< Generic Payload Receive Error */
+
+/******************* Bit definition for DSI_IER0 register ***************/
+#define DSI_IER0_AE0IE ((uint32_t)0x00000001) /*!< Acknowledge Error 0 Interrupt Enable */
+#define DSI_IER0_AE1IE ((uint32_t)0x00000002) /*!< Acknowledge Error 1 Interrupt Enable */
+#define DSI_IER0_AE2IE ((uint32_t)0x00000004) /*!< Acknowledge Error 2 Interrupt Enable */
+#define DSI_IER0_AE3IE ((uint32_t)0x00000008) /*!< Acknowledge Error 3 Interrupt Enable */
+#define DSI_IER0_AE4IE ((uint32_t)0x00000010) /*!< Acknowledge Error 4 Interrupt Enable */
+#define DSI_IER0_AE5IE ((uint32_t)0x00000020) /*!< Acknowledge Error 5 Interrupt Enable */
+#define DSI_IER0_AE6IE ((uint32_t)0x00000040) /*!< Acknowledge Error 6 Interrupt Enable */
+#define DSI_IER0_AE7IE ((uint32_t)0x00000080) /*!< Acknowledge Error 7 Interrupt Enable */
+#define DSI_IER0_AE8IE ((uint32_t)0x00000100) /*!< Acknowledge Error 8 Interrupt Enable */
+#define DSI_IER0_AE9IE ((uint32_t)0x00000200) /*!< Acknowledge Error 9 Interrupt Enable */
+#define DSI_IER0_AE10IE ((uint32_t)0x00000400) /*!< Acknowledge Error 10 Interrupt Enable */
+#define DSI_IER0_AE11IE ((uint32_t)0x00000800) /*!< Acknowledge Error 11 Interrupt Enable */
+#define DSI_IER0_AE12IE ((uint32_t)0x00001000) /*!< Acknowledge Error 12 Interrupt Enable */
+#define DSI_IER0_AE13IE ((uint32_t)0x00002000) /*!< Acknowledge Error 13 Interrupt Enable */
+#define DSI_IER0_AE14IE ((uint32_t)0x00004000) /*!< Acknowledge Error 14 Interrupt Enable */
+#define DSI_IER0_AE15IE ((uint32_t)0x00008000) /*!< Acknowledge Error 15 Interrupt Enable */
+#define DSI_IER0_PE0IE ((uint32_t)0x00010000) /*!< PHY Error 0 Interrupt Enable */
+#define DSI_IER0_PE1IE ((uint32_t)0x00020000) /*!< PHY Error 1 Interrupt Enable */
+#define DSI_IER0_PE2IE ((uint32_t)0x00040000) /*!< PHY Error 2 Interrupt Enable */
+#define DSI_IER0_PE3IE ((uint32_t)0x00080000) /*!< PHY Error 3 Interrupt Enable */
+#define DSI_IER0_PE4IE ((uint32_t)0x00100000) /*!< PHY Error 4 Interrupt Enable */
+
+/******************* Bit definition for DSI_IER1 register ***************/
+#define DSI_IER1_TOHSTXIE ((uint32_t)0x00000001) /*!< Timeout High-Speed Transmission Interrupt Enable */
+#define DSI_IER1_TOLPRXIE ((uint32_t)0x00000002) /*!< Timeout Low-Power Reception Interrupt Enable */
+#define DSI_IER1_ECCSEIE ((uint32_t)0x00000004) /*!< ECC Single-bit Error Interrupt Enable */
+#define DSI_IER1_ECCMEIE ((uint32_t)0x00000008) /*!< ECC Multi-bit Error Interrupt Enable */
+#define DSI_IER1_CRCEIE ((uint32_t)0x00000010) /*!< CRC Error Interrupt Enable */
+#define DSI_IER1_PSEIE ((uint32_t)0x00000020) /*!< Packet Size Error Interrupt Enable */
+#define DSI_IER1_EOTPEIE ((uint32_t)0x00000040) /*!< EoTp Error Interrupt Enable */
+#define DSI_IER1_LPWREIE ((uint32_t)0x00000080) /*!< LTDC Payload Write Error Interrupt Enable */
+#define DSI_IER1_GCWREIE ((uint32_t)0x00000100) /*!< Generic Command Write Error Interrupt Enable */
+#define DSI_IER1_GPWREIE ((uint32_t)0x00000200) /*!< Generic Payload Write Error Interrupt Enable */
+#define DSI_IER1_GPTXEIE ((uint32_t)0x00000400) /*!< Generic Payload Transmit Error Interrupt Enable */
+#define DSI_IER1_GPRDEIE ((uint32_t)0x00000800) /*!< Generic Payload Read Error Interrupt Enable */
+#define DSI_IER1_GPRXEIE ((uint32_t)0x00001000) /*!< Generic Payload Receive Error Interrupt Enable */
+
+/******************* Bit definition for DSI_FIR0 register ***************/
+#define DSI_FIR0_FAE0 ((uint32_t)0x00000001) /*!< Force Acknowledge Error 0 */
+#define DSI_FIR0_FAE1 ((uint32_t)0x00000002) /*!< Force Acknowledge Error 1 */
+#define DSI_FIR0_FAE2 ((uint32_t)0x00000004) /*!< Force Acknowledge Error 2 */
+#define DSI_FIR0_FAE3 ((uint32_t)0x00000008) /*!< Force Acknowledge Error 3 */
+#define DSI_FIR0_FAE4 ((uint32_t)0x00000010) /*!< Force Acknowledge Error 4 */
+#define DSI_FIR0_FAE5 ((uint32_t)0x00000020) /*!< Force Acknowledge Error 5 */
+#define DSI_FIR0_FAE6 ((uint32_t)0x00000040) /*!< Force Acknowledge Error 6 */
+#define DSI_FIR0_FAE7 ((uint32_t)0x00000080) /*!< Force Acknowledge Error 7 */
+#define DSI_FIR0_FAE8 ((uint32_t)0x00000100) /*!< Force Acknowledge Error 8 */
+#define DSI_FIR0_FAE9 ((uint32_t)0x00000200) /*!< Force Acknowledge Error 9 */
+#define DSI_FIR0_FAE10 ((uint32_t)0x00000400) /*!< Force Acknowledge Error 10 */
+#define DSI_FIR0_FAE11 ((uint32_t)0x00000800) /*!< Force Acknowledge Error 11 */
+#define DSI_FIR0_FAE12 ((uint32_t)0x00001000) /*!< Force Acknowledge Error 12 */
+#define DSI_FIR0_FAE13 ((uint32_t)0x00002000) /*!< Force Acknowledge Error 13 */
+#define DSI_FIR0_FAE14 ((uint32_t)0x00004000) /*!< Force Acknowledge Error 14 */
+#define DSI_FIR0_FAE15 ((uint32_t)0x00008000) /*!< Force Acknowledge Error 15 */
+#define DSI_FIR0_FPE0 ((uint32_t)0x00010000) /*!< Force PHY Error 0 */
+#define DSI_FIR0_FPE1 ((uint32_t)0x00020000) /*!< Force PHY Error 1 */
+#define DSI_FIR0_FPE2 ((uint32_t)0x00040000) /*!< Force PHY Error 2 */
+#define DSI_FIR0_FPE3 ((uint32_t)0x00080000) /*!< Force PHY Error 3 */
+#define DSI_FIR0_FPE4 ((uint32_t)0x00100000) /*!< Force PHY Error 4 */
+
+/******************* Bit definition for DSI_FIR1 register ***************/
+#define DSI_FIR1_FTOHSTX ((uint32_t)0x00000001) /*!< Force Timeout High-Speed Transmission */
+#define DSI_FIR1_FTOLPRX ((uint32_t)0x00000002) /*!< Force Timeout Low-Power Reception */
+#define DSI_FIR1_FECCSE ((uint32_t)0x00000004) /*!< Force ECC Single-bit Error */
+#define DSI_FIR1_FECCME ((uint32_t)0x00000008) /*!< Force ECC Multi-bit Error */
+#define DSI_FIR1_FCRCE ((uint32_t)0x00000010) /*!< Force CRC Error */
+#define DSI_FIR1_FPSE ((uint32_t)0x00000020) /*!< Force Packet Size Error */
+#define DSI_FIR1_FEOTPE ((uint32_t)0x00000040) /*!< Force EoTp Error */
+#define DSI_FIR1_FLPWRE ((uint32_t)0x00000080) /*!< Force LTDC Payload Write Error */
+#define DSI_FIR1_FGCWRE ((uint32_t)0x00000100) /*!< Force Generic Command Write Error */
+#define DSI_FIR1_FGPWRE ((uint32_t)0x00000200) /*!< Force Generic Payload Write Error */
+#define DSI_FIR1_FGPTXE ((uint32_t)0x00000400) /*!< Force Generic Payload Transmit Error */
+#define DSI_FIR1_FGPRDE ((uint32_t)0x00000800) /*!< Force Generic Payload Read Error */
+#define DSI_FIR1_FGPRXE ((uint32_t)0x00001000) /*!< Force Generic Payload Receive Error */
+
+/******************* Bit definition for DSI_VSCR register ***************/
+#define DSI_VSCR_EN ((uint32_t)0x00000001) /*!< Enable */
+#define DSI_VSCR_UR ((uint32_t)0x00000100) /*!< Update Register */
+
+/******************* Bit definition for DSI_LCVCIDR register ************/
+#define DSI_LCVCIDR_VCID ((uint32_t)0x00000003) /*!< Virtual Channel ID */
+#define DSI_LCVCIDR_VCID0 ((uint32_t)0x00000001)
+#define DSI_LCVCIDR_VCID1 ((uint32_t)0x00000002)
+
+/******************* Bit definition for DSI_LCCCR register **************/
+#define DSI_LCCCR_COLC ((uint32_t)0x0000000F) /*!< Color Coding */
+#define DSI_LCCCR_COLC0 ((uint32_t)0x00000001)
+#define DSI_LCCCR_COLC1 ((uint32_t)0x00000002)
+#define DSI_LCCCR_COLC2 ((uint32_t)0x00000004)
+#define DSI_LCCCR_COLC3 ((uint32_t)0x00000008)
+
+#define DSI_LCCCR_LPE ((uint32_t)0x00000100) /*!< Loosely Packed Enable */
+
+/******************* Bit definition for DSI_LPMCCR register *************/
+#define DSI_LPMCCR_VLPSIZE ((uint32_t)0x000000FF) /*!< VACT Largest Packet Size */
+#define DSI_LPMCCR_VLPSIZE0 ((uint32_t)0x00000001)
+#define DSI_LPMCCR_VLPSIZE1 ((uint32_t)0x00000002)
+#define DSI_LPMCCR_VLPSIZE2 ((uint32_t)0x00000004)
+#define DSI_LPMCCR_VLPSIZE3 ((uint32_t)0x00000008)
+#define DSI_LPMCCR_VLPSIZE4 ((uint32_t)0x00000010)
+#define DSI_LPMCCR_VLPSIZE5 ((uint32_t)0x00000020)
+#define DSI_LPMCCR_VLPSIZE6 ((uint32_t)0x00000040)
+#define DSI_LPMCCR_VLPSIZE7 ((uint32_t)0x00000080)
+
+#define DSI_LPMCCR_LPSIZE ((uint32_t)0x00FF0000) /*!< Largest Packet Size */
+#define DSI_LPMCCR_LPSIZE0 ((uint32_t)0x00010000)
+#define DSI_LPMCCR_LPSIZE1 ((uint32_t)0x00020000)
+#define DSI_LPMCCR_LPSIZE2 ((uint32_t)0x00040000)
+#define DSI_LPMCCR_LPSIZE3 ((uint32_t)0x00080000)
+#define DSI_LPMCCR_LPSIZE4 ((uint32_t)0x00100000)
+#define DSI_LPMCCR_LPSIZE5 ((uint32_t)0x00200000)
+#define DSI_LPMCCR_LPSIZE6 ((uint32_t)0x00400000)
+#define DSI_LPMCCR_LPSIZE7 ((uint32_t)0x00800000)
+
+/******************* Bit definition for DSI_VMCCR register **************/
+#define DSI_VMCCR_VMT ((uint32_t)0x00000003) /*!< Video Mode Type */
+#define DSI_VMCCR_VMT0 ((uint32_t)0x00000001)
+#define DSI_VMCCR_VMT1 ((uint32_t)0x00000002)
+
+#define DSI_VMCCR_LPVSAE ((uint32_t)0x00000100) /*!< Low-power Vertical Sync time Enable */
+#define DSI_VMCCR_LPVBPE ((uint32_t)0x00000200) /*!< Low-power Vertical Back-porch Enable */
+#define DSI_VMCCR_LPVFPE ((uint32_t)0x00000400) /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCCR_LPVAE ((uint32_t)0x00000800) /*!< Low-power Vertical Active Enable */
+#define DSI_VMCCR_LPHBPE ((uint32_t)0x00001000) /*!< Low-power Horizontal Back-porch Enable */
+#define DSI_VMCCR_LPHFE ((uint32_t)0x00002000) /*!< Low-power Horizontal Front-porch Enable */
+#define DSI_VMCCR_FBTAAE ((uint32_t)0x00004000) /*!< Frame BTA Acknowledge Enable */
+#define DSI_VMCCR_LPCE ((uint32_t)0x00008000) /*!< Low-power Command Enable */
+
+/******************* Bit definition for DSI_VPCCR register **************/
+#define DSI_VPCCR_VPSIZE ((uint32_t)0x00003FFF) /*!< Video Packet Size */
+#define DSI_VPCCR_VPSIZE0 ((uint32_t)0x00000001)
+#define DSI_VPCCR_VPSIZE1 ((uint32_t)0x00000002)
+#define DSI_VPCCR_VPSIZE2 ((uint32_t)0x00000004)
+#define DSI_VPCCR_VPSIZE3 ((uint32_t)0x00000008)
+#define DSI_VPCCR_VPSIZE4 ((uint32_t)0x00000010)
+#define DSI_VPCCR_VPSIZE5 ((uint32_t)0x00000020)
+#define DSI_VPCCR_VPSIZE6 ((uint32_t)0x00000040)
+#define DSI_VPCCR_VPSIZE7 ((uint32_t)0x00000080)
+#define DSI_VPCCR_VPSIZE8 ((uint32_t)0x00000100)
+#define DSI_VPCCR_VPSIZE9 ((uint32_t)0x00000200)
+#define DSI_VPCCR_VPSIZE10 ((uint32_t)0x00000400)
+#define DSI_VPCCR_VPSIZE11 ((uint32_t)0x00000800)
+#define DSI_VPCCR_VPSIZE12 ((uint32_t)0x00001000)
+#define DSI_VPCCR_VPSIZE13 ((uint32_t)0x00002000)
+
+/******************* Bit definition for DSI_VCCCR register **************/
+#define DSI_VCCCR_NUMC ((uint32_t)0x00001FFF) /*!< Number of Chunks */
+#define DSI_VCCCR_NUMC0 ((uint32_t)0x00000001)
+#define DSI_VCCCR_NUMC1 ((uint32_t)0x00000002)
+#define DSI_VCCCR_NUMC2 ((uint32_t)0x00000004)
+#define DSI_VCCCR_NUMC3 ((uint32_t)0x00000008)
+#define DSI_VCCCR_NUMC4 ((uint32_t)0x00000010)
+#define DSI_VCCCR_NUMC5 ((uint32_t)0x00000020)
+#define DSI_VCCCR_NUMC6 ((uint32_t)0x00000040)
+#define DSI_VCCCR_NUMC7 ((uint32_t)0x00000080)
+#define DSI_VCCCR_NUMC8 ((uint32_t)0x00000100)
+#define DSI_VCCCR_NUMC9 ((uint32_t)0x00000200)
+#define DSI_VCCCR_NUMC10 ((uint32_t)0x00000400)
+#define DSI_VCCCR_NUMC11 ((uint32_t)0x00000800)
+#define DSI_VCCCR_NUMC12 ((uint32_t)0x00001000)
+
+/******************* Bit definition for DSI_VNPCCR register *************/
+#define DSI_VNPCCR_NPSIZE ((uint32_t)0x00001FFF) /*!< Number of Chunks */
+#define DSI_VNPCCR_NPSIZE0 ((uint32_t)0x00000001)
+#define DSI_VNPCCR_NPSIZE1 ((uint32_t)0x00000002)
+#define DSI_VNPCCR_NPSIZE2 ((uint32_t)0x00000004)
+#define DSI_VNPCCR_NPSIZE3 ((uint32_t)0x00000008)
+#define DSI_VNPCCR_NPSIZE4 ((uint32_t)0x00000010)
+#define DSI_VNPCCR_NPSIZE5 ((uint32_t)0x00000020)
+#define DSI_VNPCCR_NPSIZE6 ((uint32_t)0x00000040)
+#define DSI_VNPCCR_NPSIZE7 ((uint32_t)0x00000080)
+#define DSI_VNPCCR_NPSIZE8 ((uint32_t)0x00000100)
+#define DSI_VNPCCR_NPSIZE9 ((uint32_t)0x00000200)
+#define DSI_VNPCCR_NPSIZE10 ((uint32_t)0x00000400)
+#define DSI_VNPCCR_NPSIZE11 ((uint32_t)0x00000800)
+#define DSI_VNPCCR_NPSIZE12 ((uint32_t)0x00001000)
+
+/******************* Bit definition for DSI_VHSACCR register ************/
+#define DSI_VHSACCR_HSA ((uint32_t)0x00000FFF) /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACCR_HSA0 ((uint32_t)0x00000001)
+#define DSI_VHSACCR_HSA1 ((uint32_t)0x00000002)
+#define DSI_VHSACCR_HSA2 ((uint32_t)0x00000004)
+#define DSI_VHSACCR_HSA3 ((uint32_t)0x00000008)
+#define DSI_VHSACCR_HSA4 ((uint32_t)0x00000010)
+#define DSI_VHSACCR_HSA5 ((uint32_t)0x00000020)
+#define DSI_VHSACCR_HSA6 ((uint32_t)0x00000040)
+#define DSI_VHSACCR_HSA7 ((uint32_t)0x00000080)
+#define DSI_VHSACCR_HSA8 ((uint32_t)0x00000100)
+#define DSI_VHSACCR_HSA9 ((uint32_t)0x00000200)
+#define DSI_VHSACCR_HSA10 ((uint32_t)0x00000400)
+#define DSI_VHSACCR_HSA11 ((uint32_t)0x00000800)
+
+/******************* Bit definition for DSI_VHBPCCR register ************/
+#define DSI_VHBPCCR_HBP ((uint32_t)0x00000FFF) /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCCR_HBP0 ((uint32_t)0x00000001)
+#define DSI_VHBPCCR_HBP1 ((uint32_t)0x00000002)
+#define DSI_VHBPCCR_HBP2 ((uint32_t)0x00000004)
+#define DSI_VHBPCCR_HBP3 ((uint32_t)0x00000008)
+#define DSI_VHBPCCR_HBP4 ((uint32_t)0x00000010)
+#define DSI_VHBPCCR_HBP5 ((uint32_t)0x00000020)
+#define DSI_VHBPCCR_HBP6 ((uint32_t)0x00000040)
+#define DSI_VHBPCCR_HBP7 ((uint32_t)0x00000080)
+#define DSI_VHBPCCR_HBP8 ((uint32_t)0x00000100)
+#define DSI_VHBPCCR_HBP9 ((uint32_t)0x00000200)
+#define DSI_VHBPCCR_HBP10 ((uint32_t)0x00000400)
+#define DSI_VHBPCCR_HBP11 ((uint32_t)0x00000800)
+
+/******************* Bit definition for DSI_VLCCR register **************/
+#define DSI_VLCCR_HLINE ((uint32_t)0x00007FFF) /*!< Horizontal Line duration */
+#define DSI_VLCCR_HLINE0 ((uint32_t)0x00000001)
+#define DSI_VLCCR_HLINE1 ((uint32_t)0x00000002)
+#define DSI_VLCCR_HLINE2 ((uint32_t)0x00000004)
+#define DSI_VLCCR_HLINE3 ((uint32_t)0x00000008)
+#define DSI_VLCCR_HLINE4 ((uint32_t)0x00000010)
+#define DSI_VLCCR_HLINE5 ((uint32_t)0x00000020)
+#define DSI_VLCCR_HLINE6 ((uint32_t)0x00000040)
+#define DSI_VLCCR_HLINE7 ((uint32_t)0x00000080)
+#define DSI_VLCCR_HLINE8 ((uint32_t)0x00000100)
+#define DSI_VLCCR_HLINE9 ((uint32_t)0x00000200)
+#define DSI_VLCCR_HLINE10 ((uint32_t)0x00000400)
+#define DSI_VLCCR_HLINE11 ((uint32_t)0x00000800)
+#define DSI_VLCCR_HLINE12 ((uint32_t)0x00001000)
+#define DSI_VLCCR_HLINE13 ((uint32_t)0x00002000)
+#define DSI_VLCCR_HLINE14 ((uint32_t)0x00004000)
+
+/******************* Bit definition for DSI_VVSACCR register ***************/
+#define DSI_VVSACCR_VSA ((uint32_t)0x000003FF) /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACCR_VSA0 ((uint32_t)0x00000001)
+#define DSI_VVSACCR_VSA1 ((uint32_t)0x00000002)
+#define DSI_VVSACCR_VSA2 ((uint32_t)0x00000004)
+#define DSI_VVSACCR_VSA3 ((uint32_t)0x00000008)
+#define DSI_VVSACCR_VSA4 ((uint32_t)0x00000010)
+#define DSI_VVSACCR_VSA5 ((uint32_t)0x00000020)
+#define DSI_VVSACCR_VSA6 ((uint32_t)0x00000040)
+#define DSI_VVSACCR_VSA7 ((uint32_t)0x00000080)
+#define DSI_VVSACCR_VSA8 ((uint32_t)0x00000100)
+#define DSI_VVSACCR_VSA9 ((uint32_t)0x00000200)
+
+/******************* Bit definition for DSI_VVBPCCR register ************/
+#define DSI_VVBPCCR_VBP ((uint32_t)0x000003FF) /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCCR_VBP0 ((uint32_t)0x00000001)
+#define DSI_VVBPCCR_VBP1 ((uint32_t)0x00000002)
+#define DSI_VVBPCCR_VBP2 ((uint32_t)0x00000004)
+#define DSI_VVBPCCR_VBP3 ((uint32_t)0x00000008)
+#define DSI_VVBPCCR_VBP4 ((uint32_t)0x00000010)
+#define DSI_VVBPCCR_VBP5 ((uint32_t)0x00000020)
+#define DSI_VVBPCCR_VBP6 ((uint32_t)0x00000040)
+#define DSI_VVBPCCR_VBP7 ((uint32_t)0x00000080)
+#define DSI_VVBPCCR_VBP8 ((uint32_t)0x00000100)
+#define DSI_VVBPCCR_VBP9 ((uint32_t)0x00000200)
+
+/******************* Bit definition for DSI_VVFPCCR register ************/
+#define DSI_VVFPCCR_VFP ((uint32_t)0x000003FF) /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCCR_VFP0 ((uint32_t)0x00000001)
+#define DSI_VVFPCCR_VFP1 ((uint32_t)0x00000002)
+#define DSI_VVFPCCR_VFP2 ((uint32_t)0x00000004)
+#define DSI_VVFPCCR_VFP3 ((uint32_t)0x00000008)
+#define DSI_VVFPCCR_VFP4 ((uint32_t)0x00000010)
+#define DSI_VVFPCCR_VFP5 ((uint32_t)0x00000020)
+#define DSI_VVFPCCR_VFP6 ((uint32_t)0x00000040)
+#define DSI_VVFPCCR_VFP7 ((uint32_t)0x00000080)
+#define DSI_VVFPCCR_VFP8 ((uint32_t)0x00000100)
+#define DSI_VVFPCCR_VFP9 ((uint32_t)0x00000200)
+
+/******************* Bit definition for DSI_VVACCR register *************/
+#define DSI_VVACCR_VA ((uint32_t)0x00003FFF) /*!< Vertical Active duration */
+#define DSI_VVACCR_VA0 ((uint32_t)0x00000001)
+#define DSI_VVACCR_VA1 ((uint32_t)0x00000002)
+#define DSI_VVACCR_VA2 ((uint32_t)0x00000004)
+#define DSI_VVACCR_VA3 ((uint32_t)0x00000008)
+#define DSI_VVACCR_VA4 ((uint32_t)0x00000010)
+#define DSI_VVACCR_VA5 ((uint32_t)0x00000020)
+#define DSI_VVACCR_VA6 ((uint32_t)0x00000040)
+#define DSI_VVACCR_VA7 ((uint32_t)0x00000080)
+#define DSI_VVACCR_VA8 ((uint32_t)0x00000100)
+#define DSI_VVACCR_VA9 ((uint32_t)0x00000200)
+#define DSI_VVACCR_VA10 ((uint32_t)0x00000400)
+#define DSI_VVACCR_VA11 ((uint32_t)0x00000800)
+#define DSI_VVACCR_VA12 ((uint32_t)0x00001000)
+#define DSI_VVACCR_VA13 ((uint32_t)0x00002000)
+
+/******************* Bit definition for DSI_TDCCR register **************/
+#define DSI_TDCCR_3DM ((uint32_t)0x00000003) /*!< 3D Mode */
+#define DSI_TDCCR_3DM0 ((uint32_t)0x00000001)
+#define DSI_TDCCR_3DM1 ((uint32_t)0x00000002)
+
+#define DSI_TDCCR_3DF ((uint32_t)0x0000000C) /*!< 3D Format */
+#define DSI_TDCCR_3DF0 ((uint32_t)0x00000004)
+#define DSI_TDCCR_3DF1 ((uint32_t)0x00000008)
+
+#define DSI_TDCCR_SVS ((uint32_t)0x00000010) /*!< Second VSYNC */
+#define DSI_TDCCR_RF ((uint32_t)0x00000020) /*!< Right First */
+#define DSI_TDCCR_S3DC ((uint32_t)0x00010000) /*!< Send 3D Control */
+
+/******************* Bit definition for DSI_WCFGR register ***************/
+#define DSI_WCFGR_DSIM ((uint32_t)0x00000001) /*!< DSI Mode */
+#define DSI_WCFGR_COLMUX ((uint32_t)0x0000000E) /*!< Color Multiplexing */
+#define DSI_WCFGR_COLMUX0 ((uint32_t)0x00000002)
+#define DSI_WCFGR_COLMUX1 ((uint32_t)0x00000004)
+#define DSI_WCFGR_COLMUX2 ((uint32_t)0x00000008)
+
+#define DSI_WCFGR_TESRC ((uint32_t)0x00000010) /*!< Tearing Effect Source */
+#define DSI_WCFGR_TEPOL ((uint32_t)0x00000020) /*!< Tearing Effect Polarity */
+#define DSI_WCFGR_AR ((uint32_t)0x00000040) /*!< Automatic Refresh */
+#define DSI_WCFGR_VSPOL ((uint32_t)0x00000080) /*!< VSync Polarity */
+
+/******************* Bit definition for DSI_WCR register *****************/
+#define DSI_WCR_COLM ((uint32_t)0x00000001) /*!< Color Mode */
+#define DSI_WCR_SHTDN ((uint32_t)0x00000002) /*!< Shutdown */
+#define DSI_WCR_LTDCEN ((uint32_t)0x00000004) /*!< LTDC Enable */
+#define DSI_WCR_DSIEN ((uint32_t)0x00000008) /*!< DSI Enable */
+
+/******************* Bit definition for DSI_WIER register ****************/
+#define DSI_WIER_TEIE ((uint32_t)0x00000001) /*!< Tearing Effect Interrupt Enable */
+#define DSI_WIER_ERIE ((uint32_t)0x00000002) /*!< End of Refresh Interrupt Enable */
+#define DSI_WIER_PLLLIE ((uint32_t)0x00000200) /*!< PLL Lock Interrupt Enable */
+#define DSI_WIER_PLLUIE ((uint32_t)0x00000400) /*!< PLL Unlock Interrupt Enable */
+#define DSI_WIER_RRIE ((uint32_t)0x00002000) /*!< Regulator Ready Interrupt Enable */
+
+/******************* Bit definition for DSI_WISR register ****************/
+#define DSI_WISR_TEIF ((uint32_t)0x00000001) /*!< Tearing Effect Interrupt Flag */
+#define DSI_WISR_ERIF ((uint32_t)0x00000002) /*!< End of Refresh Interrupt Flag */
+#define DSI_WISR_BUSY ((uint32_t)0x00000004) /*!< Busy Flag */
+#define DSI_WISR_PLLLS ((uint32_t)0x00000100) /*!< PLL Lock Status */
+#define DSI_WISR_PLLLIF ((uint32_t)0x00000200) /*!< PLL Lock Interrupt Flag */
+#define DSI_WISR_PLLUIF ((uint32_t)0x00000400) /*!< PLL Unlock Interrupt Flag */
+#define DSI_WISR_RRS ((uint32_t)0x00001000) /*!< Regulator Ready Flag */
+#define DSI_WISR_RRIF ((uint32_t)0x00002000) /*!< Regulator Ready Interrupt Flag */
+
+/******************* Bit definition for DSI_WIFCR register ***************/
+#define DSI_WIFCR_CTEIF ((uint32_t)0x00000001) /*!< Clear Tearing Effect Interrupt Flag */
+#define DSI_WIFCR_CERIF ((uint32_t)0x00000002) /*!< Clear End of Refresh Interrupt Flag */
+#define DSI_WIFCR_CPLLLIF ((uint32_t)0x00000200) /*!< Clear PLL Lock Interrupt Flag */
+#define DSI_WIFCR_CPLLUIF ((uint32_t)0x00000400) /*!< Clear PLL Unlock Interrupt Flag */
+#define DSI_WIFCR_CRRIF ((uint32_t)0x00002000) /*!< Clear Regulator Ready Interrupt Flag */
+
+/******************* Bit definition for DSI_WPCR0 register ***************/
+#define DSI_WPCR0_UIX4 ((uint32_t)0x0000003F) /*!< Unit Interval multiplied by 4 */
+#define DSI_WPCR0_UIX4_0 ((uint32_t)0x00000001)
+#define DSI_WPCR0_UIX4_1 ((uint32_t)0x00000002)
+#define DSI_WPCR0_UIX4_2 ((uint32_t)0x00000004)
+#define DSI_WPCR0_UIX4_3 ((uint32_t)0x00000008)
+#define DSI_WPCR0_UIX4_4 ((uint32_t)0x00000010)
+#define DSI_WPCR0_UIX4_5 ((uint32_t)0x00000020)
+
+#define DSI_WPCR0_SWCL ((uint32_t)0x00000040) /*!< Swap pins on clock lane */
+#define DSI_WPCR0_SWDL0 ((uint32_t)0x00000080) /*!< Swap pins on data lane 1 */
+#define DSI_WPCR0_SWDL1 ((uint32_t)0x00000100) /*!< Swap pins on data lane 2 */
+#define DSI_WPCR0_HSICL ((uint32_t)0x00000200) /*!< Invert the high-speed data signal on clock lane */
+#define DSI_WPCR0_HSIDL0 ((uint32_t)0x00000400) /*!< Invert the high-speed data signal on lane 1 */
+#define DSI_WPCR0_HSIDL1 ((uint32_t)0x00000800) /*!< Invert the high-speed data signal on lane 2 */
+#define DSI_WPCR0_FTXSMCL ((uint32_t)0x00001000) /*!< Force clock lane in TX stop mode */
+#define DSI_WPCR0_FTXSMDL ((uint32_t)0x00002000) /*!< Force data lanes in TX stop mode */
+#define DSI_WPCR0_CDOFFDL ((uint32_t)0x00004000) /*!< Contention detection OFF */
+#define DSI_WPCR0_TDDL ((uint32_t)0x00010000) /*!< Turn Disable Data Lanes */
+#define DSI_WPCR0_PDEN ((uint32_t)0x00040000) /*!< Pull-Down Enable */
+#define DSI_WPCR0_TCLKPREPEN ((uint32_t)0x00080000) /*!< Timer for t-CLKPREP Enable */
+#define DSI_WPCR0_TCLKZEROEN ((uint32_t)0x00100000) /*!< Timer for t-CLKZERO Enable */
+#define DSI_WPCR0_THSPREPEN ((uint32_t)0x00200000) /*!< Timer for t-HSPREP Enable */
+#define DSI_WPCR0_THSTRAILEN ((uint32_t)0x00400000) /*!< Timer for t-HSTRAIL Enable */
+#define DSI_WPCR0_THSZEROEN ((uint32_t)0x00800000) /*!< Timer for t-HSZERO Enable */
+#define DSI_WPCR0_TLPXDEN ((uint32_t)0x01000000) /*!< Timer for t-LPXD Enable */
+#define DSI_WPCR0_THSEXITEN ((uint32_t)0x02000000) /*!< Timer for t-HSEXIT Enable */
+#define DSI_WPCR0_TLPXCEN ((uint32_t)0x04000000) /*!< Timer for t-LPXC Enable */
+#define DSI_WPCR0_TCLKPOSTEN ((uint32_t)0x08000000) /*!< Timer for t-CLKPOST Enable */
+
+/******************* Bit definition for DSI_WPCR1 register ***************/
+#define DSI_WPCR1_HSTXDCL ((uint32_t)0x00000003) /*!< High-Speed Transmission Delay on Clock Lane */
+#define DSI_WPCR1_HSTXDCL0 ((uint32_t)0x00000001)
+#define DSI_WPCR1_HSTXDCL1 ((uint32_t)0x00000002)
+
+#define DSI_WPCR1_HSTXDDL ((uint32_t)0x0000000C) /*!< High-Speed Transmission Delay on Data Lane */
+#define DSI_WPCR1_HSTXDDL0 ((uint32_t)0x00000004)
+#define DSI_WPCR1_HSTXDDL1 ((uint32_t)0x00000008)
+
+#define DSI_WPCR1_LPSRCCL ((uint32_t)0x000000C0) /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
+#define DSI_WPCR1_LPSRCCL0 ((uint32_t)0x00000040)
+#define DSI_WPCR1_LPSRCCL1 ((uint32_t)0x00000080)
+
+#define DSI_WPCR1_LPSRCDL ((uint32_t)0x00000300) /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
+#define DSI_WPCR1_LPSRCDL0 ((uint32_t)0x00000100)
+#define DSI_WPCR1_LPSRCDL1 ((uint32_t)0x00000200)
+
+#define DSI_WPCR1_SDDC ((uint32_t)0x00001000) /*!< SDD Control */
+
+#define DSI_WPCR1_LPRXVCDL ((uint32_t)0x0000C000) /*!< Low-Power Reception V-IL Compensation on Data Lanes */
+#define DSI_WPCR1_LPRXVCDL0 ((uint32_t)0x00004000)
+#define DSI_WPCR1_LPRXVCDL1 ((uint32_t)0x00008000)
+
+#define DSI_WPCR1_HSTXSRCCL ((uint32_t)0x00030000) /*!< High-Speed Transmission Delay on Clock Lane */
+#define DSI_WPCR1_HSTXSRCCL0 ((uint32_t)0x00010000)
+#define DSI_WPCR1_HSTXSRCCL1 ((uint32_t)0x00020000)
+
+#define DSI_WPCR1_HSTXSRCDL ((uint32_t)0x000C0000) /*!< High-Speed Transmission Delay on Data Lane */
+#define DSI_WPCR1_HSTXSRCDL0 ((uint32_t)0x00040000)
+#define DSI_WPCR1_HSTXSRCDL1 ((uint32_t)0x00080000)
+
+#define DSI_WPCR1_FLPRXLPM ((uint32_t)0x00400000) /*!< Forces LP Receiver in Low-Power Mode */
+
+#define DSI_WPCR1_LPRXFT ((uint32_t)0x06000000) /*!< Low-Power RX low-pass Filtering Tuning */
+#define DSI_WPCR1_LPRXFT0 ((uint32_t)0x02000000)
+#define DSI_WPCR1_LPRXFT1 ((uint32_t)0x04000000)
+
+/******************* Bit definition for DSI_WPCR2 register ***************/
+#define DSI_WPCR2_TCLKPREP ((uint32_t)0x000000FF) /*!< t-CLKPREP */
+#define DSI_WPCR2_TCLKPREP0 ((uint32_t)0x00000001)
+#define DSI_WPCR2_TCLKPREP1 ((uint32_t)0x00000002)
+#define DSI_WPCR2_TCLKPREP2 ((uint32_t)0x00000004)
+#define DSI_WPCR2_TCLKPREP3 ((uint32_t)0x00000008)
+#define DSI_WPCR2_TCLKPREP4 ((uint32_t)0x00000010)
+#define DSI_WPCR2_TCLKPREP5 ((uint32_t)0x00000020)
+#define DSI_WPCR2_TCLKPREP6 ((uint32_t)0x00000040)
+#define DSI_WPCR2_TCLKPREP7 ((uint32_t)0x00000080)
+
+#define DSI_WPCR2_TCLKZERO ((uint32_t)0x0000FF00) /*!< t-CLKZERO */
+#define DSI_WPCR2_TCLKZERO0 ((uint32_t)0x00000100)
+#define DSI_WPCR2_TCLKZERO1 ((uint32_t)0x00000200)
+#define DSI_WPCR2_TCLKZERO2 ((uint32_t)0x00000400)
+#define DSI_WPCR2_TCLKZERO3 ((uint32_t)0x00000800)
+#define DSI_WPCR2_TCLKZERO4 ((uint32_t)0x00001000)
+#define DSI_WPCR2_TCLKZERO5 ((uint32_t)0x00002000)
+#define DSI_WPCR2_TCLKZERO6 ((uint32_t)0x00004000)
+#define DSI_WPCR2_TCLKZERO7 ((uint32_t)0x00008000)
+
+#define DSI_WPCR2_THSPREP ((uint32_t)0x00FF0000) /*!< t-HSPREP */
+#define DSI_WPCR2_THSPREP0 ((uint32_t)0x00010000)
+#define DSI_WPCR2_THSPREP1 ((uint32_t)0x00020000)
+#define DSI_WPCR2_THSPREP2 ((uint32_t)0x00040000)
+#define DSI_WPCR2_THSPREP3 ((uint32_t)0x00080000)
+#define DSI_WPCR2_THSPREP4 ((uint32_t)0x00100000)
+#define DSI_WPCR2_THSPREP5 ((uint32_t)0x00200000)
+#define DSI_WPCR2_THSPREP6 ((uint32_t)0x00400000)
+#define DSI_WPCR2_THSPREP7 ((uint32_t)0x00800000)
+
+#define DSI_WPCR2_THSTRAIL ((uint32_t)0xFF000000) /*!< t-HSTRAIL */
+#define DSI_WPCR2_THSTRAIL0 ((uint32_t)0x01000000)
+#define DSI_WPCR2_THSTRAIL1 ((uint32_t)0x02000000)
+#define DSI_WPCR2_THSTRAIL2 ((uint32_t)0x04000000)
+#define DSI_WPCR2_THSTRAIL3 ((uint32_t)0x08000000)
+#define DSI_WPCR2_THSTRAIL4 ((uint32_t)0x10000000)
+#define DSI_WPCR2_THSTRAIL5 ((uint32_t)0x20000000)
+#define DSI_WPCR2_THSTRAIL6 ((uint32_t)0x40000000)
+#define DSI_WPCR2_THSTRAIL7 ((uint32_t)0x80000000)
+
+/******************* Bit definition for DSI_WPCR3 register ***************/
+#define DSI_WPCR3_THSZERO ((uint32_t)0x000000FF) /*!< t-HSZERO */
+#define DSI_WPCR3_THSZERO0 ((uint32_t)0x00000001)
+#define DSI_WPCR3_THSZERO1 ((uint32_t)0x00000002)
+#define DSI_WPCR3_THSZERO2 ((uint32_t)0x00000004)
+#define DSI_WPCR3_THSZERO3 ((uint32_t)0x00000008)
+#define DSI_WPCR3_THSZERO4 ((uint32_t)0x00000010)
+#define DSI_WPCR3_THSZERO5 ((uint32_t)0x00000020)
+#define DSI_WPCR3_THSZERO6 ((uint32_t)0x00000040)
+#define DSI_WPCR3_THSZERO7 ((uint32_t)0x00000080)
+
+#define DSI_WPCR3_TLPXD ((uint32_t)0x0000FF00) /*!< t-LPXD */
+#define DSI_WPCR3_TLPXD0 ((uint32_t)0x00000100)
+#define DSI_WPCR3_TLPXD1 ((uint32_t)0x00000200)
+#define DSI_WPCR3_TLPXD2 ((uint32_t)0x00000400)
+#define DSI_WPCR3_TLPXD3 ((uint32_t)0x00000800)
+#define DSI_WPCR3_TLPXD4 ((uint32_t)0x00001000)
+#define DSI_WPCR3_TLPXD5 ((uint32_t)0x00002000)
+#define DSI_WPCR3_TLPXD6 ((uint32_t)0x00004000)
+#define DSI_WPCR3_TLPXD7 ((uint32_t)0x00008000)
+
+#define DSI_WPCR3_THSEXIT ((uint32_t)0x00FF0000) /*!< t-HSEXIT */
+#define DSI_WPCR3_THSEXIT0 ((uint32_t)0x00010000)
+#define DSI_WPCR3_THSEXIT1 ((uint32_t)0x00020000)
+#define DSI_WPCR3_THSEXIT2 ((uint32_t)0x00040000)
+#define DSI_WPCR3_THSEXIT3 ((uint32_t)0x00080000)
+#define DSI_WPCR3_THSEXIT4 ((uint32_t)0x00100000)
+#define DSI_WPCR3_THSEXIT5 ((uint32_t)0x00200000)
+#define DSI_WPCR3_THSEXIT6 ((uint32_t)0x00400000)
+#define DSI_WPCR3_THSEXIT7 ((uint32_t)0x00800000)
+
+#define DSI_WPCR3_TLPXC ((uint32_t)0xFF000000) /*!< t-LPXC */
+#define DSI_WPCR3_TLPXC0 ((uint32_t)0x01000000)
+#define DSI_WPCR3_TLPXC1 ((uint32_t)0x02000000)
+#define DSI_WPCR3_TLPXC2 ((uint32_t)0x04000000)
+#define DSI_WPCR3_TLPXC3 ((uint32_t)0x08000000)
+#define DSI_WPCR3_TLPXC4 ((uint32_t)0x10000000)
+#define DSI_WPCR3_TLPXC5 ((uint32_t)0x20000000)
+#define DSI_WPCR3_TLPXC6 ((uint32_t)0x40000000)
+#define DSI_WPCR3_TLPXC7 ((uint32_t)0x80000000)
+
+/******************* Bit definition for DSI_WPCR4 register ***************/
+#define DSI_WPCR4_TCLKPOST ((uint32_t)0x000000FF) /*!< t-CLKPOST */
+#define DSI_WPCR4_TCLKPOST0 ((uint32_t)0x00000001)
+#define DSI_WPCR4_TCLKPOST1 ((uint32_t)0x00000002)
+#define DSI_WPCR4_TCLKPOST2 ((uint32_t)0x00000004)
+#define DSI_WPCR4_TCLKPOST3 ((uint32_t)0x00000008)
+#define DSI_WPCR4_TCLKPOST4 ((uint32_t)0x00000010)
+#define DSI_WPCR4_TCLKPOST5 ((uint32_t)0x00000020)
+#define DSI_WPCR4_TCLKPOST6 ((uint32_t)0x00000040)
+#define DSI_WPCR4_TCLKPOST7 ((uint32_t)0x00000080)
+
+/******************* Bit definition for DSI_WRPCR register ***************/
+#define DSI_WRPCR_PLLEN ((uint32_t)0x00000001) /*!< PLL Enable */
+#define DSI_WRPCR_PLL_NDIV ((uint32_t)0x000001FC) /*!< PLL Loop Division Factor */
+#define DSI_WRPCR_PLL_NDIV0 ((uint32_t)0x00000004)
+#define DSI_WRPCR_PLL_NDIV1 ((uint32_t)0x00000008)
+#define DSI_WRPCR_PLL_NDIV2 ((uint32_t)0x00000010)
+#define DSI_WRPCR_PLL_NDIV3 ((uint32_t)0x00000020)
+#define DSI_WRPCR_PLL_NDIV4 ((uint32_t)0x00000040)
+#define DSI_WRPCR_PLL_NDIV5 ((uint32_t)0x00000080)
+#define DSI_WRPCR_PLL_NDIV6 ((uint32_t)0x00000100)
+
+#define DSI_WRPCR_PLL_IDF ((uint32_t)0x00007800) /*!< PLL Input Division Factor */
+#define DSI_WRPCR_PLL_IDF0 ((uint32_t)0x00000800)
+#define DSI_WRPCR_PLL_IDF1 ((uint32_t)0x00001000)
+#define DSI_WRPCR_PLL_IDF2 ((uint32_t)0x00002000)
+#define DSI_WRPCR_PLL_IDF3 ((uint32_t)0x00004000)
+
+#define DSI_WRPCR_PLL_ODF ((uint32_t)0x00030000) /*!< PLL Output Division Factor */
+#define DSI_WRPCR_PLL_ODF0 ((uint32_t)0x00010000)
+#define DSI_WRPCR_PLL_ODF1 ((uint32_t)0x00020000)
+
+#define DSI_WRPCR_REGEN ((uint32_t)0x01000000) /*!< Regulator Enable */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
+#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
+#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
+#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
+#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
+#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
+#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
+#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
+#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
+#define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
+#define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
+#define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
+#define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
+#define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
+#define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
+#define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
+#define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
+#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
+#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
+#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
+#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
+#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
+#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP ((uint32_t)0x00000001)
+#define FLASH_SR_SOP ((uint32_t)0x00000002)
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
+#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
+#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
+#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
+#define FLASH_SR_BSY ((uint32_t)0x00010000)
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001)
+#define FLASH_CR_SER ((uint32_t)0x00000002)
+#define FLASH_CR_MER ((uint32_t)0x00000004)
+#define FLASH_CR_MER1 FLASH_CR_MER
+#define FLASH_CR_SNB ((uint32_t)0x000000F8)
+#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
+#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
+#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
+#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
+#define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
+#define FLASH_CR_PSIZE ((uint32_t)0x00000300)
+#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
+#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
+#define FLASH_CR_MER2 ((uint32_t)0x00008000)
+#define FLASH_CR_STRT ((uint32_t)0x00010000)
+#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
+#define FLASH_CR_LOCK ((uint32_t)0x80000000)
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
+#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
+#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
+#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
+#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
+#define FLASH_OPTCR_BFB2 ((uint32_t)0x00000010)
+#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
+#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
+#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
+#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
+#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
+#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
+#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
+#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
+#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
+#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
+#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
+#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
+#define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
+#define FLASH_OPTCR_DB1M ((uint32_t)0x40000000)
+#define FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000)
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR1_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
+#define FMC_BCR1_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BCR1_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BCR1_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
+#define FMC_BCR1_WFDIS ((uint32_t)0x00200000) /*!<Write FIFO Disable */
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_PCR register *******************/
+#define FMC_PCR_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FMC_PCR_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FMC_PCR_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_PCR_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_PCR_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FMC_PCR_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FMC_PCR_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_PCR_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FMC_PCR_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FMC_PCR_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FMC_PCR_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/******************* Bit definition for FMC_SR register *******************/
+#define FMC_SR_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FMC_SR_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FMC_SR_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FMC_SR_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FMC_SR_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEM register ******************/
+#define FMC_PMEM_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PMEM_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PMEM_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PMEM_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PMEM_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PMEM_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PMEM_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PMEM_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PMEM_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PMEM_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PMEM_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PMEM_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PMEM_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PMEM_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PMEM_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PMEM_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PMEM_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PMEM_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PMEM_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PMEM_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PMEM_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PMEM_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PMEM_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PMEM_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PMEM_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PMEM_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PMEM_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PMEM_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PMEM_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PMEM_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PMEM_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PMEM_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT register ******************/
+#define FMC_PATT_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PATT_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PATT_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PATT_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PATT_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PATT_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PATT_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PATT_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PATT_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PATT_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PATT_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PATT_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PATT_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PATT_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PATT_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PATT_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PATT_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PATT_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PATT_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PATT_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PATT_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PATT_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PATT_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PATT_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PATT_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PATT_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PATT_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PATT_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PATT_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PATT_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PATT_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PATT_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_ECCR register ******************/
+#define FMC_ECCR_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
+
+/****************** Bit definition for FMC_SDCR1 register ******************/
+#define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
+
+#define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+
+#define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
+
+#define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
+#define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
+
+#define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
+#define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDCR2 register ******************/
+#define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
+
+#define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+
+#define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
+
+#define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
+
+#define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
+#define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDTR1 register ******************/
+#define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+
+#define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+
+#define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDTR2 register ******************/
+#define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+
+#define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+
+#define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDCMR register ******************/
+#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+
+#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+
+#define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
+
+/****************** Bit definition for FMC_SDRTR register ******************/
+#define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
+
+/****************** Bit definition for FMC_SDSR register ******************/
+#define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+
+#define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
+#define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
+#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
+#define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
+#define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
+#define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
+#define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
+#define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
+#define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
+#define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
+#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
+#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
+#define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
+#define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
+#define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
+#define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* LCD-TFT Display Controller (LTDC) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for LTDC_SSCR register *****************/
+
+#define LTDC_SSCR_VSH ((uint32_t)0x000007FF) /*!< Vertical Synchronization Height */
+#define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /*!< Horizontal Synchronization Width */
+
+/******************** Bit definition for LTDC_BPCR register *****************/
+
+#define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) /*!< Accumulated Vertical Back Porch */
+#define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /*!< Accumulated Horizontal Back Porch */
+
+/******************** Bit definition for LTDC_AWCR register *****************/
+
+#define LTDC_AWCR_AAH ((uint32_t)0x000007FF) /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /*!< Accumulated Active Width */
+
+/******************** Bit definition for LTDC_TWCR register *****************/
+
+#define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /*!< Total Width */
+
+/******************** Bit definition for LTDC_GCR register ******************/
+
+#define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) /*!< LCD-TFT controller enable bit */
+#define LTDC_GCR_DBW ((uint32_t)0x00000070) /*!< Dither Blue Width */
+#define LTDC_GCR_DGW ((uint32_t)0x00000700) /*!< Dither Green Width */
+#define LTDC_GCR_DRW ((uint32_t)0x00007000) /*!< Dither Red Width */
+#define LTDC_GCR_DTEN ((uint32_t)0x00010000) /*!< Dither Enable */
+#define LTDC_GCR_PCPOL ((uint32_t)0x10000000) /*!< Pixel Clock Polarity */
+#define LTDC_GCR_DEPOL ((uint32_t)0x20000000) /*!< Data Enable Polarity */
+#define LTDC_GCR_VSPOL ((uint32_t)0x40000000) /*!< Vertical Synchronization Polarity */
+#define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /*!< Horizontal Synchronization Polarity */
+
+/******************** Bit definition for LTDC_SRCR register *****************/
+
+#define LTDC_SRCR_IMR ((uint32_t)0x00000001) /*!< Immediate Reload */
+#define LTDC_SRCR_VBR ((uint32_t)0x00000002) /*!< Vertical Blanking Reload */
+
+/******************** Bit definition for LTDC_BCCR register *****************/
+
+#define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) /*!< Background Blue value */
+#define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) /*!< Background Green value */
+#define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /*!< Background Red value */
+
+/******************** Bit definition for LTDC_IER register ******************/
+
+#define LTDC_IER_LIE ((uint32_t)0x00000001) /*!< Line Interrupt Enable */
+#define LTDC_IER_FUIE ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Enable */
+#define LTDC_IER_TERRIE ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Enable */
+#define LTDC_IER_RRIE ((uint32_t)0x00000008) /*!< Register Reload interrupt enable */
+
+/******************** Bit definition for LTDC_ISR register ******************/
+
+#define LTDC_ISR_LIF ((uint32_t)0x00000001) /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF ((uint32_t)0x00000008) /*!< Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_ICR register ******************/
+
+#define LTDC_ICR_CLIF ((uint32_t)0x00000001) /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF ((uint32_t)0x00000002) /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /*!< Clears Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_LIPCR register ****************/
+
+#define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /*!< Line Interrupt Position */
+
+/******************** Bit definition for LTDC_CPSR register *****************/
+
+#define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /*!< Current X Position */
+
+/******************** Bit definition for LTDC_CDSR register *****************/
+
+#define LTDC_CDSR_VDES ((uint32_t)0x00000001) /*!< Vertical Data Enable Status */
+#define LTDC_CDSR_HDES ((uint32_t)0x00000002) /*!< Horizontal Data Enable Status */
+#define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) /*!< Vertical Synchronization Status */
+#define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /*!< Horizontal Synchronization Status */
+
+/******************** Bit definition for LTDC_LxCR register *****************/
+
+#define LTDC_LxCR_LEN ((uint32_t)0x00000001) /*!< Layer Enable */
+#define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) /*!< Color Keying Enable */
+#define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) /*!< Color Lockup Table Enable */
+
+/******************** Bit definition for LTDC_LxWHPCR register **************/
+
+#define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) /*!< Window Horizontal Stop Position */
+
+/******************** Bit definition for LTDC_LxWVPCR register **************/
+
+#define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) /*!< Window Vertical Stop Position */
+
+/******************** Bit definition for LTDC_LxCKCR register ***************/
+
+#define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) /*!< Color Key Blue value */
+#define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) /*!< Color Key Red value */
+
+/******************** Bit definition for LTDC_LxPFCR register ***************/
+
+#define LTDC_LxPFCR_PF ((uint32_t)0x00000007) /*!< Pixel Format */
+
+/******************** Bit definition for LTDC_LxCACR register ***************/
+
+#define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) /*!< Constant Alpha */
+
+/******************** Bit definition for LTDC_LxDCCR register ***************/
+
+#define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) /*!< Default Color Blue */
+#define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) /*!< Default Color Red */
+#define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) /*!< Default Color Alpha */
+
+/******************** Bit definition for LTDC_LxBFCR register ***************/
+
+#define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) /*!< Blending Factor 1 */
+
+/******************** Bit definition for LTDC_LxCFBAR register **************/
+
+#define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /*!< Color Frame Buffer Start Address */
+
+/******************** Bit definition for LTDC_LxCFBLR register **************/
+
+#define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) /*!< Color Frame Buffer Line Length */
+#define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) /*!< Color Frame Buffer Pitch in bytes */
+
+/******************** Bit definition for LTDC_LxCFBLNR register *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) /*!< Frame Buffer Line Number */
+
+/******************** Bit definition for LTDC_LxCLUTWR register *************/
+
+#define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) /*!< Blue value */
+#define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) /*!< Green value */
+#define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /*!< Red value */
+#define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /*!< CLUT address */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define PWR_CR_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */
+#define PWR_CR_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */
+#define PWR_CR_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */
+#define PWR_CR_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define PWR_CR_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+#define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
+#define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
+#define PWR_CSR_WUPP ((uint32_t)0x00000080) /*!< WKUP pin Polarity */
+#define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
+#define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
+#define PWR_CSR_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */
+#define PWR_CSR_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */
+#define PWR_CSR_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* QUADSPI */
+/* */
+/******************************************************************************/
+/***************** Bit definition for QUADSPI_CR register *******************/
+#define QUADSPI_CR_EN ((uint32_t)0x00000001) /*!< Enable */
+#define QUADSPI_CR_ABORT ((uint32_t)0x00000002) /*!< Abort request */
+#define QUADSPI_CR_DMAEN ((uint32_t)0x00000004) /*!< DMA Enable */
+#define QUADSPI_CR_TCEN ((uint32_t)0x00000008) /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010) /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM ((uint32_t)0x00000040) /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL ((uint32_t)0x00000080) /*!< Flash Select */
+#define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00) /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define QUADSPI_CR_FTHRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define QUADSPI_CR_FTHRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define QUADSPI_CR_FTHRES_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define QUADSPI_CR_TEIE ((uint32_t)0x00010000) /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE ((uint32_t)0x00020000) /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE ((uint32_t)0x00040000) /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE ((uint32_t)0x00080000) /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE ((uint32_t)0x00100000) /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS ((uint32_t)0x00400000) /*!< Bit 1 */
+#define QUADSPI_CR_PMM ((uint32_t)0x00800000) /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000) /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define QUADSPI_CR_PRESCALER_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define QUADSPI_CR_PRESCALER_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define QUADSPI_CR_PRESCALER_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define QUADSPI_CR_PRESCALER_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define QUADSPI_CR_PRESCALER_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define QUADSPI_CR_PRESCALER_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define QUADSPI_CR_PRESCALER_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/***************** Bit definition for QUADSPI_DCR register ******************/
+#define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001) /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT ((uint32_t)0x00000700) /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000) /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define QUADSPI_DCR_FSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define QUADSPI_DCR_FSIZE_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define QUADSPI_DCR_FSIZE_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define QUADSPI_DCR_FSIZE_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+
+/****************** Bit definition for QUADSPI_SR register *******************/
+#define QUADSPI_SR_TEF ((uint32_t)0x00000001) /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF ((uint32_t)0x00000002) /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF ((uint32_t)0x00000004) /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF ((uint32_t)0x00000008) /*!< Status Match Flag */
+#define QUADSPI_SR_TOF ((uint32_t)0x00000010) /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY ((uint32_t)0x00000020) /*!< Busy */
+#define QUADSPI_SR_FLEVEL ((uint32_t)0x00003F00) /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define QUADSPI_SR_FLEVEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define QUADSPI_SR_FLEVEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define QUADSPI_SR_FLEVEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define QUADSPI_SR_FLEVEL_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define QUADSPI_SR_FLEVEL_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+
+/****************** Bit definition for QUADSPI_FCR register ******************/
+#define QUADSPI_FCR_CTEF ((uint32_t)0x00000001) /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF ((uint32_t)0x00000002) /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF ((uint32_t)0x00000008) /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF ((uint32_t)0x00000010) /*!< Clear Timeout Flag */
+
+/****************** Bit definition for QUADSPI_DLR register ******************/
+#define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFF) /*!< DL[31:0]: Data Length */
+
+/****************** Bit definition for QUADSPI_CCR register ******************/
+#define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define QUADSPI_CCR_INSTRUCTION_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define QUADSPI_CCR_INSTRUCTION_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define QUADSPI_CCR_INSTRUCTION_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define QUADSPI_CCR_INSTRUCTION_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define QUADSPI_CCR_INSTRUCTION_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define QUADSPI_CCR_INSTRUCTION_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define QUADSPI_CCR_INSTRUCTION_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define QUADSPI_CCR_IMODE ((uint32_t)0x00000300) /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00) /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000) /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000) /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000) /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000) /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define QUADSPI_CCR_DCYC_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define QUADSPI_CCR_DCYC_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define QUADSPI_CCR_DCYC_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+#define QUADSPI_CCR_DCYC_4 ((uint32_t)0x00400000) /*!< Bit 4 */
+#define QUADSPI_CCR_DMODE ((uint32_t)0x03000000) /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000) /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define QUADSPI_CCR_SIOO ((uint32_t)0x10000000) /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC ((uint32_t)0x40000000) /*!< DHHC: Delay Half Hclk Cycle */
+#define QUADSPI_CCR_DDRM ((uint32_t)0x80000000) /*!< DDRM: Double Data Rate Mode */
+/****************** Bit definition for QUADSPI_AR register *******************/
+#define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< ADDRESS[31:0]: Address */
+
+/****************** Bit definition for QUADSPI_ABR register ******************/
+#define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/****************** Bit definition for QUADSPI_DR register *******************/
+#define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFF) /*!< DATA[31:0]: Data */
+
+/****************** Bit definition for QUADSPI_PSMKR register ****************/
+#define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) /*!< MASK[31:0]: Status Mask */
+
+/****************** Bit definition for QUADSPI_PSMAR register ****************/
+#define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) /*!< MATCH[31:0]: Status Match */
+
+/****************** Bit definition for QUADSPI_PIR register *****************/
+#define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFF) /*!< INTERVAL[15:0]: Polling Interval */
+
+/****************** Bit definition for QUADSPI_LPTR register *****************/
+#define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFF) /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001)
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000)
+#define RCC_CR_HSERDY ((uint32_t)0x00020000)
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
+#define RCC_CR_CSSON ((uint32_t)0x00080000)
+#define RCC_CR_PLLON ((uint32_t)0x01000000)
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
+#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
+#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
+#define RCC_CR_PLLSAION ((uint32_t)0x10000000)
+#define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
+#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
+#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
+#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
+#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
+#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
+#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
+
+#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
+#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
+#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
+#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
+#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
+#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
+#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
+#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
+#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
+#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
+#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
+#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
+
+#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
+
+#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
+#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
+#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
+#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
+#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
+
+#define RCC_PLLCFGR_PLLR ((uint32_t)0x70000000)
+#define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x10000000)
+#define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x20000000)
+#define RCC_PLLCFGR_PLLR_2 ((uint32_t)0x40000000)
+
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
+#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
+#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
+#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
+#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
+#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
+#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
+#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
+
+#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
+
+#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
+#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
+#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
+#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
+
+#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
+#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
+#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
+#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
+
+#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
+#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
+#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
+#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
+#define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
+#define RCC_CIR_CSSF ((uint32_t)0x00000080)
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
+#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
+#define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
+#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
+#define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
+#define RCC_CIR_CSSC ((uint32_t)0x00800000)
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
+#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
+#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
+#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
+#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
+#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
+#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
+#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
+#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
+#define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
+#define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
+#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
+#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
+#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
+#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
+#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
+#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
+#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
+#define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
+#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
+#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
+#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
+#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
+#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
+#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
+#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
+#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
+#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
+#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
+#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
+#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
+#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
+#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
+#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
+#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
+#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
+#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
+#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
+#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
+#define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
+#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
+#define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
+#define RCC_APB2RSTR_DSIRST ((uint32_t)0x08000000)
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
+#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
+#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
+#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
+#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
+#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
+#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
+#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
+#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
+#define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
+#define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
+
+#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
+#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
+#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
+#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
+#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
+#define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)
+
+#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
+#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
+#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
+#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
+#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
+#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
+#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
+#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
+#define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
+#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
+#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
+#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
+#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
+#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
+#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
+#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
+#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
+#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
+#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
+#define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
+#define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
+#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
+#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
+#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
+#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
+#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
+#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
+#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
+#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
+#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
+#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
+#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
+#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
+#define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)
+#define RCC_APB2ENR_DSIEN ((uint32_t)0x08000000)
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
+#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
+#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
+#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
+#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
+#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
+#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
+#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
+#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
+#define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
+#define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
+
+#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
+#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
+#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
+#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
+#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
+#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
+#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
+#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
+#define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
+
+#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
+#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
+#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
+#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
+#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
+#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
+#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
+#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
+#define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002)
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
+#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
+#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
+#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
+#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
+#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
+#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
+#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
+#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
+#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
+#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
+#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
+#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
+#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
+#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
+#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
+#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
+#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
+#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
+#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
+#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
+#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
+#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
+#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
+#define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
+#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
+#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
+#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
+#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
+#define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
+#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
+#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
+#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
+#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
+#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
+#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
+#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
+#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
+#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
+#define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
+#define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
+#define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)
+#define RCC_APB2LPENR_DSILPEN ((uint32_t)0x08000000)
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
+#define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001)
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
+#define RCC_CSR_RMVF ((uint32_t)0x01000000)
+#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
+#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
+#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
+#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
+#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
+#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
+#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
+#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
+#define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
+#define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
+#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
+#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
+#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
+#define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
+#define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
+
+#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
+
+
+/******************** Bit definition for RCC_PLLSAICFGR register ************/
+#define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
+#define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
+#define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
+#define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
+#define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
+#define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
+#define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
+#define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
+#define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
+#define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)
+#define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)
+#define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)
+
+#define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
+#define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
+#define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)
+#define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
+#define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
+
+#define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)
+#define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)
+#define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)
+#define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)
+#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
+#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
+#define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
+#define RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000)
+#define RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000)
+#define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
+#define RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000)
+#define RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000)
+#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
+#define RCC_DCKCFGR_CK48MSEL ((uint32_t)0x08000000)
+#define RCC_DCKCFGR_SDIOSEL ((uint32_t)0x10000000)
+#define RCC_DCKCFGR_DSISEL ((uint32_t)0x20000000)
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN ((uint32_t)0x00000004)
+#define RNG_CR_IE ((uint32_t)0x00000008)
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY ((uint32_t)0x00000001)
+#define RNG_SR_CECS ((uint32_t)0x00000002)
+#define RNG_SR_SECS ((uint32_t)0x00000004)
+#define RNG_SR_CEIS ((uint32_t)0x00000020)
+#define RNG_SR_SEIS ((uint32_t)0x00000040)
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_DCE ((uint32_t)0x00000080)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
+#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
+#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+#define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+#define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */
+#define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+#define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+
+#define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */
+#define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */
+
+#define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */
+#define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */
+#define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */
+#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
+#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
+
+#define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+#define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */
+#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+
+#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
+#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */
+#define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */
+
+#define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+#define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */
+#define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */
+#define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */
+#define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */
+
+#define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */
+
+#define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+#define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */
+#define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */
+#define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+
+#define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */
+#define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+#define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */
+#define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */
+#define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+
+#define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+#define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */
+
+/******************* Bit definition for SAI_xIMR register *******************/
+#define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */
+#define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */
+#define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */
+#define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */
+#define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */
+#define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */
+#define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */
+
+/******************** Bit definition for SAI_xSR register *******************/
+#define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */
+#define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */
+#define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */
+#define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */
+#define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */
+#define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */
+#define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */
+
+#define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
+#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
+#define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */
+#define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */
+#define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */
+#define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */
+#define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */
+#define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */
+
+/****************** Bit definition for SAI_xDR register ******************/
+#define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
+
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
+#define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+#define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x00001000) /*!<Asynchronous start enable */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
+#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
+#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
+
+#define SYSCFG_MEMRMP_UFB_MODE ((uint32_t)0x00000100) /*!< User Flash Bank mode */
+#define SYSCFG_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC memory mapping swap */
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
+
+#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /*!<PK[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /*!<PK[1] pin */
+
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /*!<PK[2] pin */
+
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /*!<PK[3] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /*!<PK[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /*!<PK[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /*!<PK[6] pin */
+
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /*!<PK[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /*!<PJ[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /*!<PJ[9] pin */
+
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /*!<PJ[10] pin */
+
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /*!<PJ[11] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /*!<PJ[12] pin */
+
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /*!<PJ[13] pin */
+
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /*!<PJ[14] pin */
+
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /*!<PJ[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
+
+#define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
+#define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
+#define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
+#define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
+#define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
+#define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
+#define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
+#define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
+#define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
+#define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
+#define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
+#define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
+#define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
+#define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
+#define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
+#define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
+
+#define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
+
+/******************************************************************************/
+/* */
+/* Ethernet MAC Registers bits definitions */
+/* */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
+#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
+#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
+ #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
+ #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
+ #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
+ #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
+ #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
+ #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
+ #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
+#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
+#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
+#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
+#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
+#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
+#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+ #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
+ #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
+ #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
+ #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
+#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
+#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
+#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
+#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
+#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
+#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
+#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
+ #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
+ #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
+#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
+#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
+#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
+#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
+#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
+ #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+ #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+ #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+ #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+ #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
+#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
+#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
+ #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
+ #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
+ #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
+ #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
+#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
+#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
+#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
+#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
+#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
+#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
+#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+ #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
+#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
+#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
+ #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
+#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
+#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
+ #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
+#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
+#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
+#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
+#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
+#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
+#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
+#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
+ #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+ #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+ #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+ #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
+#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
+ #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+ #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+ #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+ #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
+#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
+#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
+#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
+#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+ #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
+ #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
+ #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
+ #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
+ #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
+ #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
+ #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
+ #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
+ #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
+ #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
+ #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
+ #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
+ #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
+ #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
+ #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
+#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
+#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
+#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
+#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
+#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
+#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
+#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
+#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
+#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
+#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
+#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
+#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
+ #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+ #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+ #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+ #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+ #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+ #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+ #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+ #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
+#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
+ #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
+ #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
+ #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
+ #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
+#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008) /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010) /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020) /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040) /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080) /*!< B-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN ((uint32_t)0x00001000) /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER ((uint32_t)0x00100000) /*!< OTG version */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
+#define USB_OTG_GOTGINT_IDCHNG ((uint32_t)0x00100000) /*!< Change in ID pin input value */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_RSTDET ((uint32_t)0x00800000) /*!< Reset detected interrupt */
+#define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000) /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_RSTDEM ((uint32_t)0x00800000) /*!< Reset detected interrupt mask */
+#define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000) /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
+#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
+
+#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
+#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
+#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+
+#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
+#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
+#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
+
+#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
+#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
+#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+
+#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
+#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
+#define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /*!< USB VBUS Detection Enable */
+
+/******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
+#define USB_OTG_GPWRDN_ADPMEN ((uint32_t)0x00000001) /*!< ADP module enable */
+#define USB_OTG_GPWRDN_ADPIF ((uint32_t)0x00800000) /*!< ADP Interrupt flag */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
+#define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001) /*!< LPM support enable */
+#define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002) /*!< LPM Token acknowledge enable */
+#define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003C) /*!< BESL value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040) /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080) /*!< L1 shallow sleep enable */
+#define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00) /*!< BESL threshold */
+#define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000) /*!< L1 deep sleep enable */
+#define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000) /*!< LPM response */
+#define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000) /*!< Port sleep status */
+#define USB_OTG_GLPMCFG_L1RSMOK ((uint32_t)0x00010000) /*!< Sleep State Resume OK */
+#define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000) /*!< LPM Channel Index */
+#define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000) /*!< LPM retry count */
+#define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000) /*!< Send LPM transaction */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /*!< LPM retry count status */
+#define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /*!< Enable best effort service latency */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
+#define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
+#define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI) || \
+ ((INSTANCE) == GPIOJ) || \
+ ((INSTANCE) == GPIOK))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+ ((PERIPH) == SAI1_Block_B))
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6))
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** QSPI Instances ********************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 8 /* Including EP0 */
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 8 /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F469xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/include/devices/stm32f479xx.h b/f4/include/devices/stm32f479xx.h
new file mode 100644
index 0000000..d1b82db
--- /dev/null
+++ b/f4/include/devices/stm32f479xx.h
@@ -0,0 +1,10331 @@
+/**
+ ******************************************************************************
+ * @file stm32f479xx.h
+ * @author MCD Application Team
+ * @version V2.4.1
+ * @date 09-October-2015
+ * @brief CMSIS STM32F479xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f479xx
+ * @{
+ */
+
+#ifndef __STM32F479xx_H
+#define __STM32F479xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ UART7_IRQn = 82, /*!< UART7 global interrupt */
+ UART8_IRQn = 83, /*!< UART8 global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ LTDC_IRQn = 88, /*!< LTDC global Interrupt */
+ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
+ DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
+ QUADSPI_IRQn = 91, /*!< QUADSPI global Interrupt */
+ DSI_IRQn = 92 /*!< DSI global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief DMA2D Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+/**
+ * @brief DSI Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
+ __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
+ __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
+ __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
+ __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
+ __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
+ uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
+ __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
+ __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
+ __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
+ __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
+ __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
+ __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
+ __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
+ __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
+ __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
+ __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
+ __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
+ __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
+ __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
+ __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
+ __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
+ __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
+ __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
+ __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
+ __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
+ __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
+ __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
+ __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
+ __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
+ __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
+ __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
+ __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
+ __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
+ __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
+ __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
+ __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
+ __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
+ uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
+ __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
+ uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
+ __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
+ uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
+ __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
+ __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
+ uint32_t RESERVED5; /*!< Reserved, 0x114 */
+ __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
+ uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
+ __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
+ __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
+ __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
+ __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
+ __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
+ __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
+ __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
+ __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
+ __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
+ __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
+ __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
+ uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
+ __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
+ uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
+ __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
+ __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
+ __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
+ __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
+ __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
+ uint32_t RESERVED9; /*!< Reserved, 0x414 */
+ __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
+ uint32_t RESERVED10; /*!< Reserved, 0x42C */
+ __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
+} DSI_TypeDef;
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1[2];
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ __IO uint32_t RESERVED8;
+ __IO uint32_t PTPTSSR;
+ uint32_t RESERVED9[565];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ __IO uint32_t DMARSWTR;
+ uint32_t RESERVED10[8];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank3
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+ uint32_t RESERVED; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank5_6
+ */
+
+typedef struct
+{
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief LCD-TFT Display Controller
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
+ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
+ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
+ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
+ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
+ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
+ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
+ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
+ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
+ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
+ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
+ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
+ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
+ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
+ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
+} LTDC_TypeDef;
+
+/**
+ * @brief LCD-TFT Display layer x Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
+ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
+ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
+ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
+ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
+ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
+ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
+ uint32_t RESERVED0[2]; /*!< Reserved */
+ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
+ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
+ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
+ uint32_t RESERVED1[3]; /*!< Reserved */
+ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief QUAD Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief Crypto Processor
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
+ __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
+ __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
+ __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
+ __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
+ __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
+ __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
+ __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
+ __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
+ __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
+ __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
+ __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
+ __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
+ __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
+ __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
+ __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
+ __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
+ __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
+ __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
+ __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
+ __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
+ __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
+ __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
+ __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
+ __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
+ __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
+ __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
+ __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
+ __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
+ __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
+ __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
+ __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
+ __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
+ __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
+} CRYP_TypeDef;
+
+/**
+ * @brief HASH
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
+ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
+ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
+ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
+ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
+ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
+ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
+ __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
+} HASH_TypeDef;
+
+/**
+ * @brief HASH_DIGEST
+ */
+
+typedef struct
+{
+ __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
+} HASH_DIGEST_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
+ uint32_t Reserved6; /*!< Reserved 050h */
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
+ __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
+ __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
+ uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
+#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(160 KB) base address in the alias region */
+#define SRAM2_BASE ((uint32_t)0x20028000) /*!< SRAM2(32 KB) base address in the alias region */
+#define SRAM3_BASE ((uint32_t)0x20030000) /*!< SRAM3(128 KB) base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
+#define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< QuadSPI registers base address */
+#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x22500000) /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE ((uint32_t)0x22600000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
+#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800)
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
+#define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
+#define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
+#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
+#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
+#define DSI_BASE (APB2PERIPH_BASE + 0x6C00)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
+#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
+#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000)
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
+#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
+#define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
+#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t )0xE0042000)
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
+#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
+
+#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
+#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
+#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
+#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
+#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
+#define USB_OTG_HOST_BASE ((uint32_t )0x400)
+#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
+#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
+#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
+#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
+#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
+#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define UART7 ((USART_TypeDef *) UART7_BASE)
+#define UART8 ((USART_TypeDef *) UART8_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+#define DSI ((DSI_TypeDef *)DSI_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
+#define HASH ((HASH_TypeDef *) HASH_BASE)
+#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
+#define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
+#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
+#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
+#define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
+#define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
+#define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
+#define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
+#define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
+
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
+#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
+
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Crypto Processor */
+/* */
+/******************************************************************************/
+/******************* Bits definition for CRYP_CR register ********************/
+#define CRYP_CR_ALGODIR ((uint32_t)0x00000004)
+
+#define CRYP_CR_ALGOMODE ((uint32_t)0x00080038)
+#define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)
+#define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)
+#define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)
+#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)
+#define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)
+#define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)
+#define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)
+#define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)
+#define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)
+#define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)
+
+#define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)
+#define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)
+#define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)
+#define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)
+#define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)
+#define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)
+#define CRYP_CR_FFLUSH ((uint32_t)0x00004000)
+#define CRYP_CR_CRYPEN ((uint32_t)0x00008000)
+
+#define CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000)
+#define CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000)
+#define CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000)
+#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
+
+/****************** Bits definition for CRYP_SR register *********************/
+#define CRYP_SR_IFEM ((uint32_t)0x00000001)
+#define CRYP_SR_IFNF ((uint32_t)0x00000002)
+#define CRYP_SR_OFNE ((uint32_t)0x00000004)
+#define CRYP_SR_OFFU ((uint32_t)0x00000008)
+#define CRYP_SR_BUSY ((uint32_t)0x00000010)
+/****************** Bits definition for CRYP_DMACR register ******************/
+#define CRYP_DMACR_DIEN ((uint32_t)0x00000001)
+#define CRYP_DMACR_DOEN ((uint32_t)0x00000002)
+/***************** Bits definition for CRYP_IMSCR register ******************/
+#define CRYP_IMSCR_INIM ((uint32_t)0x00000001)
+#define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)
+/****************** Bits definition for CRYP_RISR register *******************/
+#define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)
+#define CRYP_RISR_INRIS ((uint32_t)0x00000002)
+/****************** Bits definition for CRYP_MISR register *******************/
+#define CRYP_MISR_INMIS ((uint32_t)0x00000001)
+#define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
+#define DCMI_CR_CM ((uint32_t)0x00000002)
+#define DCMI_CR_CROP ((uint32_t)0x00000004)
+#define DCMI_CR_JPEG ((uint32_t)0x00000008)
+#define DCMI_CR_ESS ((uint32_t)0x00000010)
+#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
+#define DCMI_CR_HSPOL ((uint32_t)0x00000040)
+#define DCMI_CR_VSPOL ((uint32_t)0x00000080)
+#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
+#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
+#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
+#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
+#define DCMI_CR_OUTEN ((uint32_t)0x00002000)
+#define DCMI_CR_ENABLE ((uint32_t)0x00004000)
+#define DCMI_CR_BSM_0 ((uint32_t)0x00010000)
+#define DCMI_CR_BSM_1 ((uint32_t)0x00020000)
+#define DCMI_CR_OEBS ((uint32_t)0x00040000)
+#define DCMI_CR_LSM ((uint32_t)0x00080000)
+#define DCMI_CR_OELS ((uint32_t)0x00100000)
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC ((uint32_t)0x00000001)
+#define DCMI_SR_VSYNC ((uint32_t)0x00000002)
+#define DCMI_SR_FNE ((uint32_t)0x00000004)
+
+/******************** Bits definition for DCMI_RISR register ****************/
+#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
+#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
+#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
+#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
+#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
+#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
+#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
+#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
+#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
+
+/******************** Bits definition for DCMI_MISR register ****************/
+#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
+#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
+#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
+#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
+#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
+#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
+#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
+#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
+#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
+#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
+#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
+#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
+#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
+#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
+#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
+#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
+#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
+#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
+#define DMA_SxCR_ACK ((uint32_t)0x00100000)
+#define DMA_SxCR_CT ((uint32_t)0x00080000)
+#define DMA_SxCR_DBM ((uint32_t)0x00040000)
+#define DMA_SxCR_PL ((uint32_t)0x00030000)
+#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
+#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
+#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
+#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
+#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
+#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
+#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
+#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
+#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
+#define DMA_SxCR_MINC ((uint32_t)0x00000400)
+#define DMA_SxCR_PINC ((uint32_t)0x00000200)
+#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
+#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
+#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
+#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
+#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
+#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
+#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
+#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
+#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
+#define DMA_SxCR_EN ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT ((uint32_t)0x0000FFFF)
+#define DMA_SxNDT_0 ((uint32_t)0x00000001)
+#define DMA_SxNDT_1 ((uint32_t)0x00000002)
+#define DMA_SxNDT_2 ((uint32_t)0x00000004)
+#define DMA_SxNDT_3 ((uint32_t)0x00000008)
+#define DMA_SxNDT_4 ((uint32_t)0x00000010)
+#define DMA_SxNDT_5 ((uint32_t)0x00000020)
+#define DMA_SxNDT_6 ((uint32_t)0x00000040)
+#define DMA_SxNDT_7 ((uint32_t)0x00000080)
+#define DMA_SxNDT_8 ((uint32_t)0x00000100)
+#define DMA_SxNDT_9 ((uint32_t)0x00000200)
+#define DMA_SxNDT_10 ((uint32_t)0x00000400)
+#define DMA_SxNDT_11 ((uint32_t)0x00000800)
+#define DMA_SxNDT_12 ((uint32_t)0x00001000)
+#define DMA_SxNDT_13 ((uint32_t)0x00002000)
+#define DMA_SxNDT_14 ((uint32_t)0x00004000)
+#define DMA_SxNDT_15 ((uint32_t)0x00008000)
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
+#define DMA_SxFCR_FS ((uint32_t)0x00000038)
+#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
+#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
+#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
+#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
+#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
+#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
+#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
+#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
+#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
+#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
+#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
+#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
+#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
+#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
+#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
+#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
+#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
+#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
+#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
+#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
+#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
+#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
+#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
+#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
+#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
+#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
+#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
+#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
+#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
+#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
+#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
+#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
+#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
+#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
+#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
+#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
+#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
+#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
+#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
+#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
+#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
+#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
+#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
+#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
+#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
+#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
+#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
+#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
+#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
+#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
+#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
+#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
+#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
+#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
+#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
+#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
+#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
+#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
+#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
+#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
+#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
+#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
+#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
+#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
+#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
+#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
+#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
+#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
+#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
+#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
+#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
+#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
+#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
+#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
+#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
+#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
+#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
+#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
+#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
+#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
+#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
+#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
+#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
+
+
+/******************************************************************************/
+/* */
+/* AHB Master DMA2D Controller (DMA2D) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DMA2D_CR register ******************/
+
+#define DMA2D_CR_START ((uint32_t)0x00000001) /*!< Start transfer */
+#define DMA2D_CR_SUSP ((uint32_t)0x00000002) /*!< Suspend transfer */
+#define DMA2D_CR_ABORT ((uint32_t)0x00000004) /*!< Abort transfer */
+#define DMA2D_CR_TEIE ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE ((uint32_t)0x00030000) /*!< DMA2D Mode */
+
+/******************** Bit definition for DMA2D_ISR register *****************/
+
+#define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_IFSR register ****************/
+
+#define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_FGMAR register ***************/
+
+#define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_FGOR register ****************/
+
+#define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_BGMAR register ***************/
+
+#define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGOR register ****************/
+
+#define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_FGPFCCR register *************/
+
+#define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
+#define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
+#define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha mode */
+#define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
+
+/******************** Bit definition for DMA2D_FGCOLR register **************/
+
+#define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
+#define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
+
+/******************** Bit definition for DMA2D_BGPFCCR register *************/
+
+#define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
+#define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
+#define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha Mode */
+#define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
+
+/******************** Bit definition for DMA2D_BGCOLR register **************/
+
+#define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
+#define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
+
+/******************** Bit definition for DMA2D_FGCMAR register **************/
+
+#define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGCMAR register **************/
+
+#define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OPFCCR register **************/
+
+#define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /*!< Color mode */
+
+/******************** Bit definition for DMA2D_OCOLR register ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /*!< Alpha Channel Value */
+
+/******************** Bit definition for DMA2D_OMAR register ****************/
+
+#define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OOR register *****************/
+
+#define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_NLR register *****************/
+
+#define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /*!< Number of Lines */
+#define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */
+
+/******************** Bit definition for DMA2D_LWR register *****************/
+
+#define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /*!< Line Watermark */
+
+/******************** Bit definition for DMA2D_AMTCR register ***************/
+
+#define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /*!< Enable */
+#define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /*!< Dead Time */
+
+
+/******************** Bit definition for DMA2D_FGCLUT register **************/
+
+/******************** Bit definition for DMA2D_BGCLUT register **************/
+
+
+/******************************************************************************/
+/* */
+/* Display Serial Interface (DSI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DSI_VR register *****************/
+#define DSI_VR ((uint32_t)0x3133302A) /*!< DSI Host Version */
+
+/******************* Bit definition for DSI_CR register *****************/
+#define DSI_CR_EN ((uint32_t)0x00000001) /*!< DSI Host power up and reset */
+
+/******************* Bit definition for DSI_CCR register ****************/
+#define DSI_CCR_TXECKDIV ((uint32_t)0x000000FF) /*!< TX Escape Clock Division */
+#define DSI_CCR_TXECKDIV0 ((uint32_t)0x00000001)
+#define DSI_CCR_TXECKDIV1 ((uint32_t)0x00000002)
+#define DSI_CCR_TXECKDIV2 ((uint32_t)0x00000004)
+#define DSI_CCR_TXECKDIV3 ((uint32_t)0x00000008)
+#define DSI_CCR_TXECKDIV4 ((uint32_t)0x00000010)
+#define DSI_CCR_TXECKDIV5 ((uint32_t)0x00000020)
+#define DSI_CCR_TXECKDIV6 ((uint32_t)0x00000040)
+#define DSI_CCR_TXECKDIV7 ((uint32_t)0x00000080)
+
+#define DSI_CCR_TOCKDIV ((uint32_t)0x0000FF00) /*!< Timeout Clock Division */
+#define DSI_CCR_TOCKDIV0 ((uint32_t)0x00000100)
+#define DSI_CCR_TOCKDIV1 ((uint32_t)0x00000200)
+#define DSI_CCR_TOCKDIV2 ((uint32_t)0x00000400)
+#define DSI_CCR_TOCKDIV3 ((uint32_t)0x00000800)
+#define DSI_CCR_TOCKDIV4 ((uint32_t)0x00001000)
+#define DSI_CCR_TOCKDIV5 ((uint32_t)0x00002000)
+#define DSI_CCR_TOCKDIV6 ((uint32_t)0x00004000)
+#define DSI_CCR_TOCKDIV7 ((uint32_t)0x00008000)
+
+/******************* Bit definition for DSI_LVCIDR register *************/
+#define DSI_LVCIDR_VCID ((uint32_t)0x00000003) /*!< Virtual Channel ID */
+#define DSI_LVCIDR_VCID0 ((uint32_t)0x00000001)
+#define DSI_LVCIDR_VCID1 ((uint32_t)0x00000002)
+
+/******************* Bit definition for DSI_LCOLCR register *************/
+#define DSI_LCOLCR_COLC ((uint32_t)0x0000000F) /*!< Color Coding */
+#define DSI_LCOLCR_COLC0 ((uint32_t)0x00000001)
+#define DSI_LCOLCR_COLC1 ((uint32_t)0x00000020)
+#define DSI_LCOLCR_COLC2 ((uint32_t)0x00000040)
+#define DSI_LCOLCR_COLC3 ((uint32_t)0x00000080)
+
+#define DSI_LCOLCR_LPE ((uint32_t)0x00000100) /*!< Loosly Packet Enable */
+
+/******************* Bit definition for DSI_LPCR register ***************/
+#define DSI_LPCR_DEP ((uint32_t)0x00000001) /*!< Data Enable Polarity */
+#define DSI_LPCR_VSP ((uint32_t)0x00000002) /*!< VSYNC Polarity */
+#define DSI_LPCR_HSP ((uint32_t)0x00000004) /*!< HSYNC Polarity */
+
+/******************* Bit definition for DSI_LPMCR register **************/
+#define DSI_LPMCR_VLPSIZE ((uint32_t)0x000000FF) /*!< VACT Largest Packet Size */
+#define DSI_LPMCR_VLPSIZE0 ((uint32_t)0x00000001)
+#define DSI_LPMCR_VLPSIZE1 ((uint32_t)0x00000002)
+#define DSI_LPMCR_VLPSIZE2 ((uint32_t)0x00000004)
+#define DSI_LPMCR_VLPSIZE3 ((uint32_t)0x00000008)
+#define DSI_LPMCR_VLPSIZE4 ((uint32_t)0x00000010)
+#define DSI_LPMCR_VLPSIZE5 ((uint32_t)0x00000020)
+#define DSI_LPMCR_VLPSIZE6 ((uint32_t)0x00000040)
+#define DSI_LPMCR_VLPSIZE7 ((uint32_t)0x00000080)
+
+#define DSI_LPMCR_LPSIZE ((uint32_t)0x00FF0000) /*!< Largest Packet Size */
+#define DSI_LPMCR_LPSIZE0 ((uint32_t)0x00010000)
+#define DSI_LPMCR_LPSIZE1 ((uint32_t)0x00020000)
+#define DSI_LPMCR_LPSIZE2 ((uint32_t)0x00040000)
+#define DSI_LPMCR_LPSIZE3 ((uint32_t)0x00080000)
+#define DSI_LPMCR_LPSIZE4 ((uint32_t)0x00100000)
+#define DSI_LPMCR_LPSIZE5 ((uint32_t)0x00200000)
+#define DSI_LPMCR_LPSIZE6 ((uint32_t)0x00400000)
+#define DSI_LPMCR_LPSIZE7 ((uint32_t)0x00800000)
+
+/******************* Bit definition for DSI_PCR register ****************/
+#define DSI_PCR_ETTXE ((uint32_t)0x00000001) /*!< EoTp Transmission Enable */
+#define DSI_PCR_ETRXE ((uint32_t)0x00000002) /*!< EoTp Reception Enable */
+#define DSI_PCR_BTAE ((uint32_t)0x00000004) /*!< Bus Turn Around Enable */
+#define DSI_PCR_ECCRXE ((uint32_t)0x00000008) /*!< ECC Reception Enable */
+#define DSI_PCR_CRCRXE ((uint32_t)0x00000010) /*!< CRC Reception Enable */
+
+/******************* Bit definition for DSI_GVCIDR register *************/
+#define DSI_GVCIDR_VCID ((uint32_t)0x00000003) /*!< Virtual Channel ID */
+#define DSI_GVCIDR_VCID0 ((uint32_t)0x00000001)
+#define DSI_GVCIDR_VCID1 ((uint32_t)0x00000002)
+
+/******************* Bit definition for DSI_MCR register ****************/
+#define DSI_MCR_CMDM ((uint32_t)0x00000001) /*!< Command Mode */
+
+/******************* Bit definition for DSI_VMCR register ***************/
+#define DSI_VMCR_VMT ((uint32_t)0x00000003) /*!< Video Mode Type */
+#define DSI_VMCR_VMT0 ((uint32_t)0x00000001)
+#define DSI_VMCR_VMT1 ((uint32_t)0x00000002)
+
+#define DSI_VMCR_LPVSAE ((uint32_t)0x00000100) /*!< Low-Power Vertical Sync Active Enable */
+#define DSI_VMCR_LPVBPE ((uint32_t)0x00000200) /*!< Low-power Vertical Back-Porch Enable */
+#define DSI_VMCR_LPVFPE ((uint32_t)0x00000400) /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCR_LPVAE ((uint32_t)0x00000800) /*!< Low-Power Vertical Active Enable */
+#define DSI_VMCR_LPHBPE ((uint32_t)0x00001000) /*!< Low-Power Horizontal Back-Porch Enable */
+#define DSI_VMCR_LPHFPE ((uint32_t)0x00002000) /*!< Low-Power Horizontal Front-Porch Enable */
+#define DSI_VMCR_FBTAAE ((uint32_t)0x00004000) /*!< Frame Bus-Turn-Around Acknowledge Enable */
+#define DSI_VMCR_LPCE ((uint32_t)0x00008000) /*!< Low-Power Command Enable */
+#define DSI_VMCR_PGE ((uint32_t)0x00010000) /*!< Pattern Generator Enable */
+#define DSI_VMCR_PGM ((uint32_t)0x00100000) /*!< Pattern Generator Mode */
+#define DSI_VMCR_PGO ((uint32_t)0x01000000) /*!< Pattern Generator Orientation */
+
+/******************* Bit definition for DSI_VPCR register ***************/
+#define DSI_VPCR_VPSIZE ((uint32_t)0x00003FFF) /*!< Video Packet Size */
+#define DSI_VPCR_VPSIZE0 ((uint32_t)0x00000001)
+#define DSI_VPCR_VPSIZE1 ((uint32_t)0x00000002)
+#define DSI_VPCR_VPSIZE2 ((uint32_t)0x00000004)
+#define DSI_VPCR_VPSIZE3 ((uint32_t)0x00000008)
+#define DSI_VPCR_VPSIZE4 ((uint32_t)0x00000010)
+#define DSI_VPCR_VPSIZE5 ((uint32_t)0x00000020)
+#define DSI_VPCR_VPSIZE6 ((uint32_t)0x00000040)
+#define DSI_VPCR_VPSIZE7 ((uint32_t)0x00000080)
+#define DSI_VPCR_VPSIZE8 ((uint32_t)0x00000100)
+#define DSI_VPCR_VPSIZE9 ((uint32_t)0x00000200)
+#define DSI_VPCR_VPSIZE10 ((uint32_t)0x00000400)
+#define DSI_VPCR_VPSIZE11 ((uint32_t)0x00000800)
+#define DSI_VPCR_VPSIZE12 ((uint32_t)0x00001000)
+#define DSI_VPCR_VPSIZE13 ((uint32_t)0x00002000)
+
+/******************* Bit definition for DSI_VCCR register ***************/
+#define DSI_VCCR_NUMC ((uint32_t)0x00001FFF) /*!< Number of Chunks */
+#define DSI_VCCR_NUMC0 ((uint32_t)0x00000001)
+#define DSI_VCCR_NUMC1 ((uint32_t)0x00000002)
+#define DSI_VCCR_NUMC2 ((uint32_t)0x00000004)
+#define DSI_VCCR_NUMC3 ((uint32_t)0x00000008)
+#define DSI_VCCR_NUMC4 ((uint32_t)0x00000010)
+#define DSI_VCCR_NUMC5 ((uint32_t)0x00000020)
+#define DSI_VCCR_NUMC6 ((uint32_t)0x00000040)
+#define DSI_VCCR_NUMC7 ((uint32_t)0x00000080)
+#define DSI_VCCR_NUMC8 ((uint32_t)0x00000100)
+#define DSI_VCCR_NUMC9 ((uint32_t)0x00000200)
+#define DSI_VCCR_NUMC10 ((uint32_t)0x00000400)
+#define DSI_VCCR_NUMC11 ((uint32_t)0x00000800)
+#define DSI_VCCR_NUMC12 ((uint32_t)0x00001000)
+
+/******************* Bit definition for DSI_VNPCR register **************/
+#define DSI_VNPCR_NPSIZE ((uint32_t)0x00001FFF) /*!< Null Packet Size */
+#define DSI_VNPCR_NPSIZE0 ((uint32_t)0x00000001)
+#define DSI_VNPCR_NPSIZE1 ((uint32_t)0x00000002)
+#define DSI_VNPCR_NPSIZE2 ((uint32_t)0x00000004)
+#define DSI_VNPCR_NPSIZE3 ((uint32_t)0x00000008)
+#define DSI_VNPCR_NPSIZE4 ((uint32_t)0x00000010)
+#define DSI_VNPCR_NPSIZE5 ((uint32_t)0x00000020)
+#define DSI_VNPCR_NPSIZE6 ((uint32_t)0x00000040)
+#define DSI_VNPCR_NPSIZE7 ((uint32_t)0x00000080)
+#define DSI_VNPCR_NPSIZE8 ((uint32_t)0x00000100)
+#define DSI_VNPCR_NPSIZE9 ((uint32_t)0x00000200)
+#define DSI_VNPCR_NPSIZE10 ((uint32_t)0x00000400)
+#define DSI_VNPCR_NPSIZE11 ((uint32_t)0x00000800)
+#define DSI_VNPCR_NPSIZE12 ((uint32_t)0x00001000)
+
+/******************* Bit definition for DSI_VHSACR register *************/
+#define DSI_VHSACR_HSA ((uint32_t)0x00000FFF) /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACR_HSA0 ((uint32_t)0x00000001)
+#define DSI_VHSACR_HSA1 ((uint32_t)0x00000002)
+#define DSI_VHSACR_HSA2 ((uint32_t)0x00000004)
+#define DSI_VHSACR_HSA3 ((uint32_t)0x00000008)
+#define DSI_VHSACR_HSA4 ((uint32_t)0x00000010)
+#define DSI_VHSACR_HSA5 ((uint32_t)0x00000020)
+#define DSI_VHSACR_HSA6 ((uint32_t)0x00000040)
+#define DSI_VHSACR_HSA7 ((uint32_t)0x00000080)
+#define DSI_VHSACR_HSA8 ((uint32_t)0x00000100)
+#define DSI_VHSACR_HSA9 ((uint32_t)0x00000200)
+#define DSI_VHSACR_HSA10 ((uint32_t)0x00000400)
+#define DSI_VHSACR_HSA11 ((uint32_t)0x00000800)
+
+/******************* Bit definition for DSI_VHBPCR register *************/
+#define DSI_VHBPCR_HBP ((uint32_t)0x00000FFF) /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCR_HBP0 ((uint32_t)0x00000001)
+#define DSI_VHBPCR_HBP1 ((uint32_t)0x00000002)
+#define DSI_VHBPCR_HBP2 ((uint32_t)0x00000004)
+#define DSI_VHBPCR_HBP3 ((uint32_t)0x00000008)
+#define DSI_VHBPCR_HBP4 ((uint32_t)0x00000010)
+#define DSI_VHBPCR_HBP5 ((uint32_t)0x00000020)
+#define DSI_VHBPCR_HBP6 ((uint32_t)0x00000040)
+#define DSI_VHBPCR_HBP7 ((uint32_t)0x00000080)
+#define DSI_VHBPCR_HBP8 ((uint32_t)0x00000100)
+#define DSI_VHBPCR_HBP9 ((uint32_t)0x00000200)
+#define DSI_VHBPCR_HBP10 ((uint32_t)0x00000400)
+#define DSI_VHBPCR_HBP11 ((uint32_t)0x00000800)
+
+/******************* Bit definition for DSI_VLCR register ***************/
+#define DSI_VLCR_HLINE ((uint32_t)0x00007FFF) /*!< Horizontal Line duration */
+#define DSI_VLCR_HLINE0 ((uint32_t)0x00000001)
+#define DSI_VLCR_HLINE1 ((uint32_t)0x00000002)
+#define DSI_VLCR_HLINE2 ((uint32_t)0x00000004)
+#define DSI_VLCR_HLINE3 ((uint32_t)0x00000008)
+#define DSI_VLCR_HLINE4 ((uint32_t)0x00000010)
+#define DSI_VLCR_HLINE5 ((uint32_t)0x00000020)
+#define DSI_VLCR_HLINE6 ((uint32_t)0x00000040)
+#define DSI_VLCR_HLINE7 ((uint32_t)0x00000080)
+#define DSI_VLCR_HLINE8 ((uint32_t)0x00000100)
+#define DSI_VLCR_HLINE9 ((uint32_t)0x00000200)
+#define DSI_VLCR_HLINE10 ((uint32_t)0x00000400)
+#define DSI_VLCR_HLINE11 ((uint32_t)0x00000800)
+#define DSI_VLCR_HLINE12 ((uint32_t)0x00001000)
+#define DSI_VLCR_HLINE13 ((uint32_t)0x00002000)
+#define DSI_VLCR_HLINE14 ((uint32_t)0x00004000)
+
+/******************* Bit definition for DSI_VVSACR register *************/
+#define DSI_VVSACR_VSA ((uint32_t)0x000003FF) /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACR_VSA0 ((uint32_t)0x00000001)
+#define DSI_VVSACR_VSA1 ((uint32_t)0x00000002)
+#define DSI_VVSACR_VSA2 ((uint32_t)0x00000004)
+#define DSI_VVSACR_VSA3 ((uint32_t)0x00000008)
+#define DSI_VVSACR_VSA4 ((uint32_t)0x00000010)
+#define DSI_VVSACR_VSA5 ((uint32_t)0x00000020)
+#define DSI_VVSACR_VSA6 ((uint32_t)0x00000040)
+#define DSI_VVSACR_VSA7 ((uint32_t)0x00000080)
+#define DSI_VVSACR_VSA8 ((uint32_t)0x00000100)
+#define DSI_VVSACR_VSA9 ((uint32_t)0x00000200)
+
+/******************* Bit definition for DSI_VVBPCR register *************/
+#define DSI_VVBPCR_VBP ((uint32_t)0x000003FF) /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCR_VBP0 ((uint32_t)0x00000001)
+#define DSI_VVBPCR_VBP1 ((uint32_t)0x00000002)
+#define DSI_VVBPCR_VBP2 ((uint32_t)0x00000004)
+#define DSI_VVBPCR_VBP3 ((uint32_t)0x00000008)
+#define DSI_VVBPCR_VBP4 ((uint32_t)0x00000010)
+#define DSI_VVBPCR_VBP5 ((uint32_t)0x00000020)
+#define DSI_VVBPCR_VBP6 ((uint32_t)0x00000040)
+#define DSI_VVBPCR_VBP7 ((uint32_t)0x00000080)
+#define DSI_VVBPCR_VBP8 ((uint32_t)0x00000100)
+#define DSI_VVBPCR_VBP9 ((uint32_t)0x00000200)
+
+/******************* Bit definition for DSI_VVFPCR register *************/
+#define DSI_VVFPCR_VFP ((uint32_t)0x000003FF) /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCR_VFP0 ((uint32_t)0x00000001)
+#define DSI_VVFPCR_VFP1 ((uint32_t)0x00000002)
+#define DSI_VVFPCR_VFP2 ((uint32_t)0x00000004)
+#define DSI_VVFPCR_VFP3 ((uint32_t)0x00000008)
+#define DSI_VVFPCR_VFP4 ((uint32_t)0x00000010)
+#define DSI_VVFPCR_VFP5 ((uint32_t)0x00000020)
+#define DSI_VVFPCR_VFP6 ((uint32_t)0x00000040)
+#define DSI_VVFPCR_VFP7 ((uint32_t)0x00000080)
+#define DSI_VVFPCR_VFP8 ((uint32_t)0x00000100)
+#define DSI_VVFPCR_VFP9 ((uint32_t)0x00000200)
+
+/******************* Bit definition for DSI_VVACR register **************/
+#define DSI_VVACR_VA ((uint32_t)0x00003FFF) /*!< Vertical Active duration */
+#define DSI_VVACR_VA0 ((uint32_t)0x00000001)
+#define DSI_VVACR_VA1 ((uint32_t)0x00000002)
+#define DSI_VVACR_VA2 ((uint32_t)0x00000004)
+#define DSI_VVACR_VA3 ((uint32_t)0x00000008)
+#define DSI_VVACR_VA4 ((uint32_t)0x00000010)
+#define DSI_VVACR_VA5 ((uint32_t)0x00000020)
+#define DSI_VVACR_VA6 ((uint32_t)0x00000040)
+#define DSI_VVACR_VA7 ((uint32_t)0x00000080)
+#define DSI_VVACR_VA8 ((uint32_t)0x00000100)
+#define DSI_VVACR_VA9 ((uint32_t)0x00000200)
+#define DSI_VVACR_VA10 ((uint32_t)0x00000400)
+#define DSI_VVACR_VA11 ((uint32_t)0x00000800)
+#define DSI_VVACR_VA12 ((uint32_t)0x00001000)
+#define DSI_VVACR_VA13 ((uint32_t)0x00002000)
+
+/******************* Bit definition for DSI_LCCR register ***************/
+#define DSI_LCCR_CMDSIZE ((uint32_t)0x0000FFFF) /*!< Command Size */
+#define DSI_LCCR_CMDSIZE0 ((uint32_t)0x00000001)
+#define DSI_LCCR_CMDSIZE1 ((uint32_t)0x00000002)
+#define DSI_LCCR_CMDSIZE2 ((uint32_t)0x00000004)
+#define DSI_LCCR_CMDSIZE3 ((uint32_t)0x00000008)
+#define DSI_LCCR_CMDSIZE4 ((uint32_t)0x00000010)
+#define DSI_LCCR_CMDSIZE5 ((uint32_t)0x00000020)
+#define DSI_LCCR_CMDSIZE6 ((uint32_t)0x00000040)
+#define DSI_LCCR_CMDSIZE7 ((uint32_t)0x00000080)
+#define DSI_LCCR_CMDSIZE8 ((uint32_t)0x00000100)
+#define DSI_LCCR_CMDSIZE9 ((uint32_t)0x00000200)
+#define DSI_LCCR_CMDSIZE10 ((uint32_t)0x00000400)
+#define DSI_LCCR_CMDSIZE11 ((uint32_t)0x00000800)
+#define DSI_LCCR_CMDSIZE12 ((uint32_t)0x00001000)
+#define DSI_LCCR_CMDSIZE13 ((uint32_t)0x00002000)
+#define DSI_LCCR_CMDSIZE14 ((uint32_t)0x00004000)
+#define DSI_LCCR_CMDSIZE15 ((uint32_t)0x00008000)
+
+/******************* Bit definition for DSI_CMCR register ***************/
+#define DSI_CMCR_TEARE ((uint32_t)0x00000001) /*!< Tearing Effect Acknowledge Request Enable */
+#define DSI_CMCR_ARE ((uint32_t)0x00000002) /*!< Acknowledge Request Enable */
+#define DSI_CMCR_GSW0TX ((uint32_t)0x00000100) /*!< Generic Short Write Zero parameters Transmission */
+#define DSI_CMCR_GSW1TX ((uint32_t)0x00000200) /*!< Generic Short Write One parameters Transmission */
+#define DSI_CMCR_GSW2TX ((uint32_t)0x00000400) /*!< Generic Short Write Two parameters Transmission */
+#define DSI_CMCR_GSR0TX ((uint32_t)0x00000800) /*!< Generic Short Read Zero parameters Transmission */
+#define DSI_CMCR_GSR1TX ((uint32_t)0x00001000) /*!< Generic Short Read One parameters Transmission */
+#define DSI_CMCR_GSR2TX ((uint32_t)0x00002000) /*!< Generic Short Read Two parameters Transmission */
+#define DSI_CMCR_GLWTX ((uint32_t)0x00004000) /*!< Generic Long Write Transmission */
+#define DSI_CMCR_DSW0TX ((uint32_t)0x00010000) /*!< DCS Short Write Zero parameter Transmission */
+#define DSI_CMCR_DSW1TX ((uint32_t)0x00020000) /*!< DCS Short Read One parameter Transmission */
+#define DSI_CMCR_DSR0TX ((uint32_t)0x00040000) /*!< DCS Short Read Zero parameter Transmission */
+#define DSI_CMCR_DLWTX ((uint32_t)0x00080000) /*!< DCS Long Write Transmission */
+#define DSI_CMCR_MRDPS ((uint32_t)0x01000000) /*!< Maximum Read Packet Size */
+
+/******************* Bit definition for DSI_GHCR register ***************/
+#define DSI_GHCR_DT ((uint32_t)0x0000003F) /*!< Type */
+#define DSI_GHCR_DT0 ((uint32_t)0x00000001)
+#define DSI_GHCR_DT1 ((uint32_t)0x00000002)
+#define DSI_GHCR_DT2 ((uint32_t)0x00000004)
+#define DSI_GHCR_DT3 ((uint32_t)0x00000008)
+#define DSI_GHCR_DT4 ((uint32_t)0x00000010)
+#define DSI_GHCR_DT5 ((uint32_t)0x00000020)
+
+#define DSI_GHCR_VCID ((uint32_t)0x000000C0) /*!< Channel */
+#define DSI_GHCR_VCID0 ((uint32_t)0x00000040)
+#define DSI_GHCR_VCID1 ((uint32_t)0x00000080)
+
+#define DSI_GHCR_WCLSB ((uint32_t)0x0000FF00) /*!< WordCount LSB */
+#define DSI_GHCR_WCLSB0 ((uint32_t)0x00000100)
+#define DSI_GHCR_WCLSB1 ((uint32_t)0x00000200)
+#define DSI_GHCR_WCLSB2 ((uint32_t)0x00000400)
+#define DSI_GHCR_WCLSB3 ((uint32_t)0x00000800)
+#define DSI_GHCR_WCLSB4 ((uint32_t)0x00001000)
+#define DSI_GHCR_WCLSB5 ((uint32_t)0x00002000)
+#define DSI_GHCR_WCLSB6 ((uint32_t)0x00004000)
+#define DSI_GHCR_WCLSB7 ((uint32_t)0x00008000)
+
+#define DSI_GHCR_WCMSB ((uint32_t)0x00FF0000) /*!< WordCount MSB */
+#define DSI_GHCR_WCMSB0 ((uint32_t)0x00010000)
+#define DSI_GHCR_WCMSB1 ((uint32_t)0x00020000)
+#define DSI_GHCR_WCMSB2 ((uint32_t)0x00040000)
+#define DSI_GHCR_WCMSB3 ((uint32_t)0x00080000)
+#define DSI_GHCR_WCMSB4 ((uint32_t)0x00100000)
+#define DSI_GHCR_WCMSB5 ((uint32_t)0x00200000)
+#define DSI_GHCR_WCMSB6 ((uint32_t)0x00400000)
+#define DSI_GHCR_WCMSB7 ((uint32_t)0x00800000)
+
+/******************* Bit definition for DSI_GPDR register ***************/
+#define DSI_GPDR_DATA1 ((uint32_t)0x000000FF) /*!< Payload Byte 1 */
+#define DSI_GPDR_DATA1_0 ((uint32_t)0x00000001)
+#define DSI_GPDR_DATA1_1 ((uint32_t)0x00000002)
+#define DSI_GPDR_DATA1_2 ((uint32_t)0x00000004)
+#define DSI_GPDR_DATA1_3 ((uint32_t)0x00000008)
+#define DSI_GPDR_DATA1_4 ((uint32_t)0x00000010)
+#define DSI_GPDR_DATA1_5 ((uint32_t)0x00000020)
+#define DSI_GPDR_DATA1_6 ((uint32_t)0x00000040)
+#define DSI_GPDR_DATA1_7 ((uint32_t)0x00000080)
+
+#define DSI_GPDR_DATA2 ((uint32_t)0x0000FF00) /*!< Payload Byte 2 */
+#define DSI_GPDR_DATA2_0 ((uint32_t)0x00000100)
+#define DSI_GPDR_DATA2_1 ((uint32_t)0x00000200)
+#define DSI_GPDR_DATA2_2 ((uint32_t)0x00000400)
+#define DSI_GPDR_DATA2_3 ((uint32_t)0x00000800)
+#define DSI_GPDR_DATA2_4 ((uint32_t)0x00001000)
+#define DSI_GPDR_DATA2_5 ((uint32_t)0x00002000)
+#define DSI_GPDR_DATA2_6 ((uint32_t)0x00004000)
+#define DSI_GPDR_DATA2_7 ((uint32_t)0x00008000)
+
+#define DSI_GPDR_DATA3 ((uint32_t)0x00FF0000) /*!< Payload Byte 3 */
+#define DSI_GPDR_DATA3_0 ((uint32_t)0x00010000)
+#define DSI_GPDR_DATA3_1 ((uint32_t)0x00020000)
+#define DSI_GPDR_DATA3_2 ((uint32_t)0x00040000)
+#define DSI_GPDR_DATA3_3 ((uint32_t)0x00080000)
+#define DSI_GPDR_DATA3_4 ((uint32_t)0x00100000)
+#define DSI_GPDR_DATA3_5 ((uint32_t)0x00200000)
+#define DSI_GPDR_DATA3_6 ((uint32_t)0x00400000)
+#define DSI_GPDR_DATA3_7 ((uint32_t)0x00800000)
+
+#define DSI_GPDR_DATA4 ((uint32_t)0xFF000000) /*!< Payload Byte 4 */
+#define DSI_GPDR_DATA4_0 ((uint32_t)0x01000000)
+#define DSI_GPDR_DATA4_1 ((uint32_t)0x02000000)
+#define DSI_GPDR_DATA4_2 ((uint32_t)0x04000000)
+#define DSI_GPDR_DATA4_3 ((uint32_t)0x08000000)
+#define DSI_GPDR_DATA4_4 ((uint32_t)0x10000000)
+#define DSI_GPDR_DATA4_5 ((uint32_t)0x20000000)
+#define DSI_GPDR_DATA4_6 ((uint32_t)0x40000000)
+#define DSI_GPDR_DATA4_7 ((uint32_t)0x80000000)
+
+/******************* Bit definition for DSI_GPSR register ***************/
+#define DSI_GPSR_CMDFE ((uint32_t)0x00000001) /*!< Command FIFO Empty */
+#define DSI_GPSR_CMDFF ((uint32_t)0x00000002) /*!< Command FIFO Full */
+#define DSI_GPSR_PWRFE ((uint32_t)0x00000004) /*!< Payload Write FIFO Empty */
+#define DSI_GPSR_PWRFF ((uint32_t)0x00000008) /*!< Payload Write FIFO Full */
+#define DSI_GPSR_PRDFE ((uint32_t)0x00000010) /*!< Payload Read FIFO Empty */
+#define DSI_GPSR_PRDFF ((uint32_t)0x00000020) /*!< Payload Read FIFO Full */
+#define DSI_GPSR_RCB ((uint32_t)0x00000040) /*!< Read Command Busy */
+
+/******************* Bit definition for DSI_TCCR0 register **************/
+#define DSI_TCCR0_LPRX_TOCNT ((uint32_t)0x0000FFFF) /*!< Low-power Reception Timeout Counter */
+#define DSI_TCCR0_LPRX_TOCNT0 ((uint32_t)0x00000001)
+#define DSI_TCCR0_LPRX_TOCNT1 ((uint32_t)0x00000002)
+#define DSI_TCCR0_LPRX_TOCNT2 ((uint32_t)0x00000004)
+#define DSI_TCCR0_LPRX_TOCNT3 ((uint32_t)0x00000008)
+#define DSI_TCCR0_LPRX_TOCNT4 ((uint32_t)0x00000010)
+#define DSI_TCCR0_LPRX_TOCNT5 ((uint32_t)0x00000020)
+#define DSI_TCCR0_LPRX_TOCNT6 ((uint32_t)0x00000040)
+#define DSI_TCCR0_LPRX_TOCNT7 ((uint32_t)0x00000080)
+#define DSI_TCCR0_LPRX_TOCNT8 ((uint32_t)0x00000100)
+#define DSI_TCCR0_LPRX_TOCNT9 ((uint32_t)0x00000200)
+#define DSI_TCCR0_LPRX_TOCNT10 ((uint32_t)0x00000400)
+#define DSI_TCCR0_LPRX_TOCNT11 ((uint32_t)0x00000800)
+#define DSI_TCCR0_LPRX_TOCNT12 ((uint32_t)0x00001000)
+#define DSI_TCCR0_LPRX_TOCNT13 ((uint32_t)0x00002000)
+#define DSI_TCCR0_LPRX_TOCNT14 ((uint32_t)0x00004000)
+#define DSI_TCCR0_LPRX_TOCNT15 ((uint32_t)0x00008000)
+
+#define DSI_TCCR0_HSTX_TOCNT ((uint32_t)0xFFFF0000) /*!< High-Speed Transmission Timeout Counter */
+#define DSI_TCCR0_HSTX_TOCNT0 ((uint32_t)0x00010000)
+#define DSI_TCCR0_HSTX_TOCNT1 ((uint32_t)0x00020000)
+#define DSI_TCCR0_HSTX_TOCNT2 ((uint32_t)0x00040000)
+#define DSI_TCCR0_HSTX_TOCNT3 ((uint32_t)0x00080000)
+#define DSI_TCCR0_HSTX_TOCNT4 ((uint32_t)0x00100000)
+#define DSI_TCCR0_HSTX_TOCNT5 ((uint32_t)0x00200000)
+#define DSI_TCCR0_HSTX_TOCNT6 ((uint32_t)0x00400000)
+#define DSI_TCCR0_HSTX_TOCNT7 ((uint32_t)0x00800000)
+#define DSI_TCCR0_HSTX_TOCNT8 ((uint32_t)0x01000000)
+#define DSI_TCCR0_HSTX_TOCNT9 ((uint32_t)0x02000000)
+#define DSI_TCCR0_HSTX_TOCNT10 ((uint32_t)0x04000000)
+#define DSI_TCCR0_HSTX_TOCNT11 ((uint32_t)0x08000000)
+#define DSI_TCCR0_HSTX_TOCNT12 ((uint32_t)0x10000000)
+#define DSI_TCCR0_HSTX_TOCNT13 ((uint32_t)0x20000000)
+#define DSI_TCCR0_HSTX_TOCNT14 ((uint32_t)0x40000000)
+#define DSI_TCCR0_HSTX_TOCNT15 ((uint32_t)0x80000000)
+
+/******************* Bit definition for DSI_TCCR1 register **************/
+#define DSI_TCCR1_HSRD_TOCNT ((uint32_t)0x0000FFFF) /*!< High-Speed Read Timeout Counter */
+#define DSI_TCCR1_HSRD_TOCNT0 ((uint32_t)0x00000001)
+#define DSI_TCCR1_HSRD_TOCNT1 ((uint32_t)0x00000002)
+#define DSI_TCCR1_HSRD_TOCNT2 ((uint32_t)0x00000004)
+#define DSI_TCCR1_HSRD_TOCNT3 ((uint32_t)0x00000008)
+#define DSI_TCCR1_HSRD_TOCNT4 ((uint32_t)0x00000010)
+#define DSI_TCCR1_HSRD_TOCNT5 ((uint32_t)0x00000020)
+#define DSI_TCCR1_HSRD_TOCNT6 ((uint32_t)0x00000040)
+#define DSI_TCCR1_HSRD_TOCNT7 ((uint32_t)0x00000080)
+#define DSI_TCCR1_HSRD_TOCNT8 ((uint32_t)0x00000100)
+#define DSI_TCCR1_HSRD_TOCNT9 ((uint32_t)0x00000200)
+#define DSI_TCCR1_HSRD_TOCNT10 ((uint32_t)0x00000400)
+#define DSI_TCCR1_HSRD_TOCNT11 ((uint32_t)0x00000800)
+#define DSI_TCCR1_HSRD_TOCNT12 ((uint32_t)0x00001000)
+#define DSI_TCCR1_HSRD_TOCNT13 ((uint32_t)0x00002000)
+#define DSI_TCCR1_HSRD_TOCNT14 ((uint32_t)0x00004000)
+#define DSI_TCCR1_HSRD_TOCNT15 ((uint32_t)0x00008000)
+
+/******************* Bit definition for DSI_TCCR2 register **************/
+#define DSI_TCCR2_LPRD_TOCNT ((uint32_t)0x0000FFFF) /*!< Low-Power Read Timeout Counter */
+#define DSI_TCCR2_LPRD_TOCNT0 ((uint32_t)0x00000001)
+#define DSI_TCCR2_LPRD_TOCNT1 ((uint32_t)0x00000002)
+#define DSI_TCCR2_LPRD_TOCNT2 ((uint32_t)0x00000004)
+#define DSI_TCCR2_LPRD_TOCNT3 ((uint32_t)0x00000008)
+#define DSI_TCCR2_LPRD_TOCNT4 ((uint32_t)0x00000010)
+#define DSI_TCCR2_LPRD_TOCNT5 ((uint32_t)0x00000020)
+#define DSI_TCCR2_LPRD_TOCNT6 ((uint32_t)0x00000040)
+#define DSI_TCCR2_LPRD_TOCNT7 ((uint32_t)0x00000080)
+#define DSI_TCCR2_LPRD_TOCNT8 ((uint32_t)0x00000100)
+#define DSI_TCCR2_LPRD_TOCNT9 ((uint32_t)0x00000200)
+#define DSI_TCCR2_LPRD_TOCNT10 ((uint32_t)0x00000400)
+#define DSI_TCCR2_LPRD_TOCNT11 ((uint32_t)0x00000800)
+#define DSI_TCCR2_LPRD_TOCNT12 ((uint32_t)0x00001000)
+#define DSI_TCCR2_LPRD_TOCNT13 ((uint32_t)0x00002000)
+#define DSI_TCCR2_LPRD_TOCNT14 ((uint32_t)0x00004000)
+#define DSI_TCCR2_LPRD_TOCNT15 ((uint32_t)0x00008000)
+
+/******************* Bit definition for DSI_TCCR3 register **************/
+#define DSI_TCCR3_HSWR_TOCNT ((uint32_t)0x0000FFFF) /*!< High-Speed Write Timeout Counter */
+#define DSI_TCCR3_HSWR_TOCNT0 ((uint32_t)0x00000001)
+#define DSI_TCCR3_HSWR_TOCNT1 ((uint32_t)0x00000002)
+#define DSI_TCCR3_HSWR_TOCNT2 ((uint32_t)0x00000004)
+#define DSI_TCCR3_HSWR_TOCNT3 ((uint32_t)0x00000008)
+#define DSI_TCCR3_HSWR_TOCNT4 ((uint32_t)0x00000010)
+#define DSI_TCCR3_HSWR_TOCNT5 ((uint32_t)0x00000020)
+#define DSI_TCCR3_HSWR_TOCNT6 ((uint32_t)0x00000040)
+#define DSI_TCCR3_HSWR_TOCNT7 ((uint32_t)0x00000080)
+#define DSI_TCCR3_HSWR_TOCNT8 ((uint32_t)0x00000100)
+#define DSI_TCCR3_HSWR_TOCNT9 ((uint32_t)0x00000200)
+#define DSI_TCCR3_HSWR_TOCNT10 ((uint32_t)0x00000400)
+#define DSI_TCCR3_HSWR_TOCNT11 ((uint32_t)0x00000800)
+#define DSI_TCCR3_HSWR_TOCNT12 ((uint32_t)0x00001000)
+#define DSI_TCCR3_HSWR_TOCNT13 ((uint32_t)0x00002000)
+#define DSI_TCCR3_HSWR_TOCNT14 ((uint32_t)0x00004000)
+#define DSI_TCCR3_HSWR_TOCNT15 ((uint32_t)0x00008000)
+
+#define DSI_TCCR3_PM ((uint32_t)0x01000000) /*!< Presp Mode */
+
+/******************* Bit definition for DSI_TCCR4 register **************/
+#define DSI_TCCR4_LPWR_TOCNT ((uint32_t)0x0000FFFF) /*!< Low-Power Write Timeout Counter */
+#define DSI_TCCR4_LPWR_TOCNT0 ((uint32_t)0x00000001)
+#define DSI_TCCR4_LPWR_TOCNT1 ((uint32_t)0x00000002)
+#define DSI_TCCR4_LPWR_TOCNT2 ((uint32_t)0x00000004)
+#define DSI_TCCR4_LPWR_TOCNT3 ((uint32_t)0x00000008)
+#define DSI_TCCR4_LPWR_TOCNT4 ((uint32_t)0x00000010)
+#define DSI_TCCR4_LPWR_TOCNT5 ((uint32_t)0x00000020)
+#define DSI_TCCR4_LPWR_TOCNT6 ((uint32_t)0x00000040)
+#define DSI_TCCR4_LPWR_TOCNT7 ((uint32_t)0x00000080)
+#define DSI_TCCR4_LPWR_TOCNT8 ((uint32_t)0x00000100)
+#define DSI_TCCR4_LPWR_TOCNT9 ((uint32_t)0x00000200)
+#define DSI_TCCR4_LPWR_TOCNT10 ((uint32_t)0x00000400)
+#define DSI_TCCR4_LPWR_TOCNT11 ((uint32_t)0x00000800)
+#define DSI_TCCR4_LPWR_TOCNT12 ((uint32_t)0x00001000)
+#define DSI_TCCR4_LPWR_TOCNT13 ((uint32_t)0x00002000)
+#define DSI_TCCR4_LPWR_TOCNT14 ((uint32_t)0x00004000)
+#define DSI_TCCR4_LPWR_TOCNT15 ((uint32_t)0x00008000)
+
+/******************* Bit definition for DSI_TCCR5 register **************/
+#define DSI_TCCR5_BTA_TOCNT ((uint32_t)0x0000FFFF) /*!< Bus-Turn-Around Timeout Counter */
+#define DSI_TCCR5_BTA_TOCNT0 ((uint32_t)0x00000001)
+#define DSI_TCCR5_BTA_TOCNT1 ((uint32_t)0x00000002)
+#define DSI_TCCR5_BTA_TOCNT2 ((uint32_t)0x00000004)
+#define DSI_TCCR5_BTA_TOCNT3 ((uint32_t)0x00000008)
+#define DSI_TCCR5_BTA_TOCNT4 ((uint32_t)0x00000010)
+#define DSI_TCCR5_BTA_TOCNT5 ((uint32_t)0x00000020)
+#define DSI_TCCR5_BTA_TOCNT6 ((uint32_t)0x00000040)
+#define DSI_TCCR5_BTA_TOCNT7 ((uint32_t)0x00000080)
+#define DSI_TCCR5_BTA_TOCNT8 ((uint32_t)0x00000100)
+#define DSI_TCCR5_BTA_TOCNT9 ((uint32_t)0x00000200)
+#define DSI_TCCR5_BTA_TOCNT10 ((uint32_t)0x00000400)
+#define DSI_TCCR5_BTA_TOCNT11 ((uint32_t)0x00000800)
+#define DSI_TCCR5_BTA_TOCNT12 ((uint32_t)0x00001000)
+#define DSI_TCCR5_BTA_TOCNT13 ((uint32_t)0x00002000)
+#define DSI_TCCR5_BTA_TOCNT14 ((uint32_t)0x00004000)
+#define DSI_TCCR5_BTA_TOCNT15 ((uint32_t)0x00008000)
+
+/******************* Bit definition for DSI_TDCR register ***************/
+#define DSI_TDCR_3DM ((uint32_t)0x00000003) /*!< 3D Mode */
+#define DSI_TDCR_3DM0 ((uint32_t)0x00000001)
+#define DSI_TDCR_3DM1 ((uint32_t)0x00000002)
+
+#define DSI_TDCR_3DF ((uint32_t)0x0000000C) /*!< 3D Format */
+#define DSI_TDCR_3DF0 ((uint32_t)0x00000004)
+#define DSI_TDCR_3DF1 ((uint32_t)0x00000008)
+
+#define DSI_TDCR_SVS ((uint32_t)0x00000010) /*!< Second VSYNC */
+#define DSI_TDCR_RF ((uint32_t)0x00000020) /*!< Right First */
+#define DSI_TDCR_S3DC ((uint32_t)0x00010000) /*!< Send 3D Control */
+
+/******************* Bit definition for DSI_CLCR register ***************/
+#define DSI_CLCR_DPCC ((uint32_t)0x00000001) /*!< D-PHY Clock Control */
+#define DSI_CLCR_ACR ((uint32_t)0x00000002) /*!< Automatic Clocklane Control */
+
+/******************* Bit definition for DSI_CLTCR register **************/
+#define DSI_CLTCR_LP2HS_TIME ((uint32_t)0x000003FF) /*!< Low-Power to High-Speed Time */
+#define DSI_CLTCR_LP2HS_TIME0 ((uint32_t)0x00000001)
+#define DSI_CLTCR_LP2HS_TIME1 ((uint32_t)0x00000002)
+#define DSI_CLTCR_LP2HS_TIME2 ((uint32_t)0x00000004)
+#define DSI_CLTCR_LP2HS_TIME3 ((uint32_t)0x00000008)
+#define DSI_CLTCR_LP2HS_TIME4 ((uint32_t)0x00000010)
+#define DSI_CLTCR_LP2HS_TIME5 ((uint32_t)0x00000020)
+#define DSI_CLTCR_LP2HS_TIME6 ((uint32_t)0x00000040)
+#define DSI_CLTCR_LP2HS_TIME7 ((uint32_t)0x00000080)
+#define DSI_CLTCR_LP2HS_TIME8 ((uint32_t)0x00000100)
+#define DSI_CLTCR_LP2HS_TIME9 ((uint32_t)0x00000200)
+
+#define DSI_CLTCR_HS2LP_TIME ((uint32_t)0x03FF0000) /*!< High-Speed to Low-Power Time */
+#define DSI_CLTCR_HS2LP_TIME0 ((uint32_t)0x00010000)
+#define DSI_CLTCR_HS2LP_TIME1 ((uint32_t)0x00020000)
+#define DSI_CLTCR_HS2LP_TIME2 ((uint32_t)0x00040000)
+#define DSI_CLTCR_HS2LP_TIME3 ((uint32_t)0x00080000)
+#define DSI_CLTCR_HS2LP_TIME4 ((uint32_t)0x00100000)
+#define DSI_CLTCR_HS2LP_TIME5 ((uint32_t)0x00200000)
+#define DSI_CLTCR_HS2LP_TIME6 ((uint32_t)0x00400000)
+#define DSI_CLTCR_HS2LP_TIME7 ((uint32_t)0x00800000)
+#define DSI_CLTCR_HS2LP_TIME8 ((uint32_t)0x01000000)
+#define DSI_CLTCR_HS2LP_TIME9 ((uint32_t)0x02000000)
+
+/******************* Bit definition for DSI_DLTCR register **************/
+#define DSI_DLTCR_MRD_TIME ((uint32_t)0x00007FFF) /*!< Maximum Read Time */
+#define DSI_DLTCR_MRD_TIME0 ((uint32_t)0x00000001)
+#define DSI_DLTCR_MRD_TIME1 ((uint32_t)0x00000002)
+#define DSI_DLTCR_MRD_TIME2 ((uint32_t)0x00000004)
+#define DSI_DLTCR_MRD_TIME3 ((uint32_t)0x00000008)
+#define DSI_DLTCR_MRD_TIME4 ((uint32_t)0x00000010)
+#define DSI_DLTCR_MRD_TIME5 ((uint32_t)0x00000020)
+#define DSI_DLTCR_MRD_TIME6 ((uint32_t)0x00000040)
+#define DSI_DLTCR_MRD_TIME7 ((uint32_t)0x00000080)
+#define DSI_DLTCR_MRD_TIME8 ((uint32_t)0x00000100)
+#define DSI_DLTCR_MRD_TIME9 ((uint32_t)0x00000200)
+#define DSI_DLTCR_MRD_TIME10 ((uint32_t)0x00000400)
+#define DSI_DLTCR_MRD_TIME11 ((uint32_t)0x00000800)
+#define DSI_DLTCR_MRD_TIME12 ((uint32_t)0x00001000)
+#define DSI_DLTCR_MRD_TIME13 ((uint32_t)0x00002000)
+#define DSI_DLTCR_MRD_TIME14 ((uint32_t)0x00004000)
+
+#define DSI_DLTCR_LP2HS_TIME ((uint32_t)0x00FF0000) /*!< Low-Power To High-Speed Time */
+#define DSI_DLTCR_LP2HS_TIME0 ((uint32_t)0x00010000)
+#define DSI_DLTCR_LP2HS_TIME1 ((uint32_t)0x00020000)
+#define DSI_DLTCR_LP2HS_TIME2 ((uint32_t)0x00040000)
+#define DSI_DLTCR_LP2HS_TIME3 ((uint32_t)0x00080000)
+#define DSI_DLTCR_LP2HS_TIME4 ((uint32_t)0x00100000)
+#define DSI_DLTCR_LP2HS_TIME5 ((uint32_t)0x00200000)
+#define DSI_DLTCR_LP2HS_TIME6 ((uint32_t)0x00400000)
+#define DSI_DLTCR_LP2HS_TIME7 ((uint32_t)0x00800000)
+
+#define DSI_DLTCR_HS2LP_TIME ((uint32_t)0xFF000000) /*!< High-Speed To Low-Power Time */
+#define DSI_DLTCR_HS2LP_TIME0 ((uint32_t)0x01000000)
+#define DSI_DLTCR_HS2LP_TIME1 ((uint32_t)0x02000000)
+#define DSI_DLTCR_HS2LP_TIME2 ((uint32_t)0x04000000)
+#define DSI_DLTCR_HS2LP_TIME3 ((uint32_t)0x08000000)
+#define DSI_DLTCR_HS2LP_TIME4 ((uint32_t)0x10000000)
+#define DSI_DLTCR_HS2LP_TIME5 ((uint32_t)0x20000000)
+#define DSI_DLTCR_HS2LP_TIME6 ((uint32_t)0x40000000)
+#define DSI_DLTCR_HS2LP_TIME7 ((uint32_t)0x80000000)
+
+/******************* Bit definition for DSI_PCTLR register **************/
+#define DSI_PCTLR_DEN ((uint32_t)0x00000002) /*!< Digital Enable */
+#define DSI_PCTLR_CKE ((uint32_t)0x00000004) /*!< Clock Enable */
+
+/******************* Bit definition for DSI_PCONFR register *************/
+#define DSI_PCONFR_NL ((uint32_t)0x00000003) /*!< Number of Lanes */
+#define DSI_PCONFR_NL0 ((uint32_t)0x00000001)
+#define DSI_PCONFR_NL1 ((uint32_t)0x00000002)
+
+#define DSI_PCONFR_SW_TIME ((uint32_t)0x0000FF00) /*!< Stop Wait Time */
+#define DSI_PCONFR_SW_TIME0 ((uint32_t)0x00000100)
+#define DSI_PCONFR_SW_TIME1 ((uint32_t)0x00000200)
+#define DSI_PCONFR_SW_TIME2 ((uint32_t)0x00000400)
+#define DSI_PCONFR_SW_TIME3 ((uint32_t)0x00000800)
+#define DSI_PCONFR_SW_TIME4 ((uint32_t)0x00001000)
+#define DSI_PCONFR_SW_TIME5 ((uint32_t)0x00002000)
+#define DSI_PCONFR_SW_TIME6 ((uint32_t)0x00004000)
+#define DSI_PCONFR_SW_TIME7 ((uint32_t)0x00008000)
+
+/******************* Bit definition for DSI_PUCR register ***************/
+#define DSI_PUCR_URCL ((uint32_t)0x00000001) /*!< ULPS Request on Clock Lane */
+#define DSI_PUCR_UECL ((uint32_t)0x00000002) /*!< ULPS Exit on Clock Lane */
+#define DSI_PUCR_URDL ((uint32_t)0x00000004) /*!< ULPS Request on Data Lane */
+#define DSI_PUCR_UEDL ((uint32_t)0x00000008) /*!< ULPS Exit on Data Lane */
+
+/******************* Bit definition for DSI_PTTCR register **************/
+#define DSI_PTTCR_TX_TRIG ((uint32_t)0x0000000F) /*!< Transmission Trigger */
+#define DSI_PTTCR_TX_TRIG0 ((uint32_t)0x00000001)
+#define DSI_PTTCR_TX_TRIG1 ((uint32_t)0x00000002)
+#define DSI_PTTCR_TX_TRIG2 ((uint32_t)0x00000004)
+#define DSI_PTTCR_TX_TRIG3 ((uint32_t)0x00000008)
+
+/******************* Bit definition for DSI_PSR register ****************/
+#define DSI_PSR_PD ((uint32_t)0x00000002) /*!< PHY Direction */
+#define DSI_PSR_PSSC ((uint32_t)0x00000004) /*!< PHY Stop State Clock lane */
+#define DSI_PSR_UANC ((uint32_t)0x00000008) /*!< ULPS Active Not Clock lane */
+#define DSI_PSR_PSS0 ((uint32_t)0x00000010) /*!< PHY Stop State lane 0 */
+#define DSI_PSR_UAN0 ((uint32_t)0x00000020) /*!< ULPS Active Not lane 0 */
+#define DSI_PSR_RUE0 ((uint32_t)0x00000040) /*!< RX ULPS Escape lane 0 */
+#define DSI_PSR_PSS1 ((uint32_t)0x00000080) /*!< PHY Stop State lane 1 */
+#define DSI_PSR_UAN1 ((uint32_t)0x00000100) /*!< ULPS Active Not lane 1 */
+
+/******************* Bit definition for DSI_ISR0 register ***************/
+#define DSI_ISR0_AE0 ((uint32_t)0x00000001) /*!< Acknowledge Error 0 */
+#define DSI_ISR0_AE1 ((uint32_t)0x00000002) /*!< Acknowledge Error 1 */
+#define DSI_ISR0_AE2 ((uint32_t)0x00000004) /*!< Acknowledge Error 2 */
+#define DSI_ISR0_AE3 ((uint32_t)0x00000008) /*!< Acknowledge Error 3 */
+#define DSI_ISR0_AE4 ((uint32_t)0x00000010) /*!< Acknowledge Error 4 */
+#define DSI_ISR0_AE5 ((uint32_t)0x00000020) /*!< Acknowledge Error 5 */
+#define DSI_ISR0_AE6 ((uint32_t)0x00000040) /*!< Acknowledge Error 6 */
+#define DSI_ISR0_AE7 ((uint32_t)0x00000080) /*!< Acknowledge Error 7 */
+#define DSI_ISR0_AE8 ((uint32_t)0x00000100) /*!< Acknowledge Error 8 */
+#define DSI_ISR0_AE9 ((uint32_t)0x00000200) /*!< Acknowledge Error 9 */
+#define DSI_ISR0_AE10 ((uint32_t)0x00000400) /*!< Acknowledge Error 10 */
+#define DSI_ISR0_AE11 ((uint32_t)0x00000800) /*!< Acknowledge Error 11 */
+#define DSI_ISR0_AE12 ((uint32_t)0x00001000) /*!< Acknowledge Error 12 */
+#define DSI_ISR0_AE13 ((uint32_t)0x00002000) /*!< Acknowledge Error 13 */
+#define DSI_ISR0_AE14 ((uint32_t)0x00004000) /*!< Acknowledge Error 14 */
+#define DSI_ISR0_AE15 ((uint32_t)0x00008000) /*!< Acknowledge Error 15 */
+#define DSI_ISR0_PE0 ((uint32_t)0x00010000) /*!< PHY Error 0 */
+#define DSI_ISR0_PE1 ((uint32_t)0x00020000) /*!< PHY Error 1 */
+#define DSI_ISR0_PE2 ((uint32_t)0x00040000) /*!< PHY Error 2 */
+#define DSI_ISR0_PE3 ((uint32_t)0x00080000) /*!< PHY Error 3 */
+#define DSI_ISR0_PE4 ((uint32_t)0x00100000) /*!< PHY Error 4 */
+
+/******************* Bit definition for DSI_ISR1 register ***************/
+#define DSI_ISR1_TOHSTX ((uint32_t)0x00000001) /*!< Timeout High-Speed Transmission */
+#define DSI_ISR1_TOLPRX ((uint32_t)0x00000002) /*!< Timeout Low-Power Reception */
+#define DSI_ISR1_ECCSE ((uint32_t)0x00000004) /*!< ECC Single-bit Error */
+#define DSI_ISR1_ECCME ((uint32_t)0x00000008) /*!< ECC Multi-bit Error */
+#define DSI_ISR1_CRCE ((uint32_t)0x00000010) /*!< CRC Error */
+#define DSI_ISR1_PSE ((uint32_t)0x00000020) /*!< Packet Size Error */
+#define DSI_ISR1_EOTPE ((uint32_t)0x00000040) /*!< EoTp Error */
+#define DSI_ISR1_LPWRE ((uint32_t)0x00000080) /*!< LTDC Payload Write Error */
+#define DSI_ISR1_GCWRE ((uint32_t)0x00000100) /*!< Generic Command Write Error */
+#define DSI_ISR1_GPWRE ((uint32_t)0x00000200) /*!< Generic Payload Write Error */
+#define DSI_ISR1_GPTXE ((uint32_t)0x00000400) /*!< Generic Payload Transmit Error */
+#define DSI_ISR1_GPRDE ((uint32_t)0x00000800) /*!< Generic Payload Read Error */
+#define DSI_ISR1_GPRXE ((uint32_t)0x00001000) /*!< Generic Payload Receive Error */
+
+/******************* Bit definition for DSI_IER0 register ***************/
+#define DSI_IER0_AE0IE ((uint32_t)0x00000001) /*!< Acknowledge Error 0 Interrupt Enable */
+#define DSI_IER0_AE1IE ((uint32_t)0x00000002) /*!< Acknowledge Error 1 Interrupt Enable */
+#define DSI_IER0_AE2IE ((uint32_t)0x00000004) /*!< Acknowledge Error 2 Interrupt Enable */
+#define DSI_IER0_AE3IE ((uint32_t)0x00000008) /*!< Acknowledge Error 3 Interrupt Enable */
+#define DSI_IER0_AE4IE ((uint32_t)0x00000010) /*!< Acknowledge Error 4 Interrupt Enable */
+#define DSI_IER0_AE5IE ((uint32_t)0x00000020) /*!< Acknowledge Error 5 Interrupt Enable */
+#define DSI_IER0_AE6IE ((uint32_t)0x00000040) /*!< Acknowledge Error 6 Interrupt Enable */
+#define DSI_IER0_AE7IE ((uint32_t)0x00000080) /*!< Acknowledge Error 7 Interrupt Enable */
+#define DSI_IER0_AE8IE ((uint32_t)0x00000100) /*!< Acknowledge Error 8 Interrupt Enable */
+#define DSI_IER0_AE9IE ((uint32_t)0x00000200) /*!< Acknowledge Error 9 Interrupt Enable */
+#define DSI_IER0_AE10IE ((uint32_t)0x00000400) /*!< Acknowledge Error 10 Interrupt Enable */
+#define DSI_IER0_AE11IE ((uint32_t)0x00000800) /*!< Acknowledge Error 11 Interrupt Enable */
+#define DSI_IER0_AE12IE ((uint32_t)0x00001000) /*!< Acknowledge Error 12 Interrupt Enable */
+#define DSI_IER0_AE13IE ((uint32_t)0x00002000) /*!< Acknowledge Error 13 Interrupt Enable */
+#define DSI_IER0_AE14IE ((uint32_t)0x00004000) /*!< Acknowledge Error 14 Interrupt Enable */
+#define DSI_IER0_AE15IE ((uint32_t)0x00008000) /*!< Acknowledge Error 15 Interrupt Enable */
+#define DSI_IER0_PE0IE ((uint32_t)0x00010000) /*!< PHY Error 0 Interrupt Enable */
+#define DSI_IER0_PE1IE ((uint32_t)0x00020000) /*!< PHY Error 1 Interrupt Enable */
+#define DSI_IER0_PE2IE ((uint32_t)0x00040000) /*!< PHY Error 2 Interrupt Enable */
+#define DSI_IER0_PE3IE ((uint32_t)0x00080000) /*!< PHY Error 3 Interrupt Enable */
+#define DSI_IER0_PE4IE ((uint32_t)0x00100000) /*!< PHY Error 4 Interrupt Enable */
+
+/******************* Bit definition for DSI_IER1 register ***************/
+#define DSI_IER1_TOHSTXIE ((uint32_t)0x00000001) /*!< Timeout High-Speed Transmission Interrupt Enable */
+#define DSI_IER1_TOLPRXIE ((uint32_t)0x00000002) /*!< Timeout Low-Power Reception Interrupt Enable */
+#define DSI_IER1_ECCSEIE ((uint32_t)0x00000004) /*!< ECC Single-bit Error Interrupt Enable */
+#define DSI_IER1_ECCMEIE ((uint32_t)0x00000008) /*!< ECC Multi-bit Error Interrupt Enable */
+#define DSI_IER1_CRCEIE ((uint32_t)0x00000010) /*!< CRC Error Interrupt Enable */
+#define DSI_IER1_PSEIE ((uint32_t)0x00000020) /*!< Packet Size Error Interrupt Enable */
+#define DSI_IER1_EOTPEIE ((uint32_t)0x00000040) /*!< EoTp Error Interrupt Enable */
+#define DSI_IER1_LPWREIE ((uint32_t)0x00000080) /*!< LTDC Payload Write Error Interrupt Enable */
+#define DSI_IER1_GCWREIE ((uint32_t)0x00000100) /*!< Generic Command Write Error Interrupt Enable */
+#define DSI_IER1_GPWREIE ((uint32_t)0x00000200) /*!< Generic Payload Write Error Interrupt Enable */
+#define DSI_IER1_GPTXEIE ((uint32_t)0x00000400) /*!< Generic Payload Transmit Error Interrupt Enable */
+#define DSI_IER1_GPRDEIE ((uint32_t)0x00000800) /*!< Generic Payload Read Error Interrupt Enable */
+#define DSI_IER1_GPRXEIE ((uint32_t)0x00001000) /*!< Generic Payload Receive Error Interrupt Enable */
+
+/******************* Bit definition for DSI_FIR0 register ***************/
+#define DSI_FIR0_FAE0 ((uint32_t)0x00000001) /*!< Force Acknowledge Error 0 */
+#define DSI_FIR0_FAE1 ((uint32_t)0x00000002) /*!< Force Acknowledge Error 1 */
+#define DSI_FIR0_FAE2 ((uint32_t)0x00000004) /*!< Force Acknowledge Error 2 */
+#define DSI_FIR0_FAE3 ((uint32_t)0x00000008) /*!< Force Acknowledge Error 3 */
+#define DSI_FIR0_FAE4 ((uint32_t)0x00000010) /*!< Force Acknowledge Error 4 */
+#define DSI_FIR0_FAE5 ((uint32_t)0x00000020) /*!< Force Acknowledge Error 5 */
+#define DSI_FIR0_FAE6 ((uint32_t)0x00000040) /*!< Force Acknowledge Error 6 */
+#define DSI_FIR0_FAE7 ((uint32_t)0x00000080) /*!< Force Acknowledge Error 7 */
+#define DSI_FIR0_FAE8 ((uint32_t)0x00000100) /*!< Force Acknowledge Error 8 */
+#define DSI_FIR0_FAE9 ((uint32_t)0x00000200) /*!< Force Acknowledge Error 9 */
+#define DSI_FIR0_FAE10 ((uint32_t)0x00000400) /*!< Force Acknowledge Error 10 */
+#define DSI_FIR0_FAE11 ((uint32_t)0x00000800) /*!< Force Acknowledge Error 11 */
+#define DSI_FIR0_FAE12 ((uint32_t)0x00001000) /*!< Force Acknowledge Error 12 */
+#define DSI_FIR0_FAE13 ((uint32_t)0x00002000) /*!< Force Acknowledge Error 13 */
+#define DSI_FIR0_FAE14 ((uint32_t)0x00004000) /*!< Force Acknowledge Error 14 */
+#define DSI_FIR0_FAE15 ((uint32_t)0x00008000) /*!< Force Acknowledge Error 15 */
+#define DSI_FIR0_FPE0 ((uint32_t)0x00010000) /*!< Force PHY Error 0 */
+#define DSI_FIR0_FPE1 ((uint32_t)0x00020000) /*!< Force PHY Error 1 */
+#define DSI_FIR0_FPE2 ((uint32_t)0x00040000) /*!< Force PHY Error 2 */
+#define DSI_FIR0_FPE3 ((uint32_t)0x00080000) /*!< Force PHY Error 3 */
+#define DSI_FIR0_FPE4 ((uint32_t)0x00100000) /*!< Force PHY Error 4 */
+
+/******************* Bit definition for DSI_FIR1 register ***************/
+#define DSI_FIR1_FTOHSTX ((uint32_t)0x00000001) /*!< Force Timeout High-Speed Transmission */
+#define DSI_FIR1_FTOLPRX ((uint32_t)0x00000002) /*!< Force Timeout Low-Power Reception */
+#define DSI_FIR1_FECCSE ((uint32_t)0x00000004) /*!< Force ECC Single-bit Error */
+#define DSI_FIR1_FECCME ((uint32_t)0x00000008) /*!< Force ECC Multi-bit Error */
+#define DSI_FIR1_FCRCE ((uint32_t)0x00000010) /*!< Force CRC Error */
+#define DSI_FIR1_FPSE ((uint32_t)0x00000020) /*!< Force Packet Size Error */
+#define DSI_FIR1_FEOTPE ((uint32_t)0x00000040) /*!< Force EoTp Error */
+#define DSI_FIR1_FLPWRE ((uint32_t)0x00000080) /*!< Force LTDC Payload Write Error */
+#define DSI_FIR1_FGCWRE ((uint32_t)0x00000100) /*!< Force Generic Command Write Error */
+#define DSI_FIR1_FGPWRE ((uint32_t)0x00000200) /*!< Force Generic Payload Write Error */
+#define DSI_FIR1_FGPTXE ((uint32_t)0x00000400) /*!< Force Generic Payload Transmit Error */
+#define DSI_FIR1_FGPRDE ((uint32_t)0x00000800) /*!< Force Generic Payload Read Error */
+#define DSI_FIR1_FGPRXE ((uint32_t)0x00001000) /*!< Force Generic Payload Receive Error */
+
+/******************* Bit definition for DSI_VSCR register ***************/
+#define DSI_VSCR_EN ((uint32_t)0x00000001) /*!< Enable */
+#define DSI_VSCR_UR ((uint32_t)0x00000100) /*!< Update Register */
+
+/******************* Bit definition for DSI_LCVCIDR register ************/
+#define DSI_LCVCIDR_VCID ((uint32_t)0x00000003) /*!< Virtual Channel ID */
+#define DSI_LCVCIDR_VCID0 ((uint32_t)0x00000001)
+#define DSI_LCVCIDR_VCID1 ((uint32_t)0x00000002)
+
+/******************* Bit definition for DSI_LCCCR register **************/
+#define DSI_LCCCR_COLC ((uint32_t)0x0000000F) /*!< Color Coding */
+#define DSI_LCCCR_COLC0 ((uint32_t)0x00000001)
+#define DSI_LCCCR_COLC1 ((uint32_t)0x00000002)
+#define DSI_LCCCR_COLC2 ((uint32_t)0x00000004)
+#define DSI_LCCCR_COLC3 ((uint32_t)0x00000008)
+
+#define DSI_LCCCR_LPE ((uint32_t)0x00000100) /*!< Loosely Packed Enable */
+
+/******************* Bit definition for DSI_LPMCCR register *************/
+#define DSI_LPMCCR_VLPSIZE ((uint32_t)0x000000FF) /*!< VACT Largest Packet Size */
+#define DSI_LPMCCR_VLPSIZE0 ((uint32_t)0x00000001)
+#define DSI_LPMCCR_VLPSIZE1 ((uint32_t)0x00000002)
+#define DSI_LPMCCR_VLPSIZE2 ((uint32_t)0x00000004)
+#define DSI_LPMCCR_VLPSIZE3 ((uint32_t)0x00000008)
+#define DSI_LPMCCR_VLPSIZE4 ((uint32_t)0x00000010)
+#define DSI_LPMCCR_VLPSIZE5 ((uint32_t)0x00000020)
+#define DSI_LPMCCR_VLPSIZE6 ((uint32_t)0x00000040)
+#define DSI_LPMCCR_VLPSIZE7 ((uint32_t)0x00000080)
+
+#define DSI_LPMCCR_LPSIZE ((uint32_t)0x00FF0000) /*!< Largest Packet Size */
+#define DSI_LPMCCR_LPSIZE0 ((uint32_t)0x00010000)
+#define DSI_LPMCCR_LPSIZE1 ((uint32_t)0x00020000)
+#define DSI_LPMCCR_LPSIZE2 ((uint32_t)0x00040000)
+#define DSI_LPMCCR_LPSIZE3 ((uint32_t)0x00080000)
+#define DSI_LPMCCR_LPSIZE4 ((uint32_t)0x00100000)
+#define DSI_LPMCCR_LPSIZE5 ((uint32_t)0x00200000)
+#define DSI_LPMCCR_LPSIZE6 ((uint32_t)0x00400000)
+#define DSI_LPMCCR_LPSIZE7 ((uint32_t)0x00800000)
+
+/******************* Bit definition for DSI_VMCCR register **************/
+#define DSI_VMCCR_VMT ((uint32_t)0x00000003) /*!< Video Mode Type */
+#define DSI_VMCCR_VMT0 ((uint32_t)0x00000001)
+#define DSI_VMCCR_VMT1 ((uint32_t)0x00000002)
+
+#define DSI_VMCCR_LPVSAE ((uint32_t)0x00000100) /*!< Low-power Vertical Sync time Enable */
+#define DSI_VMCCR_LPVBPE ((uint32_t)0x00000200) /*!< Low-power Vertical Back-porch Enable */
+#define DSI_VMCCR_LPVFPE ((uint32_t)0x00000400) /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCCR_LPVAE ((uint32_t)0x00000800) /*!< Low-power Vertical Active Enable */
+#define DSI_VMCCR_LPHBPE ((uint32_t)0x00001000) /*!< Low-power Horizontal Back-porch Enable */
+#define DSI_VMCCR_LPHFE ((uint32_t)0x00002000) /*!< Low-power Horizontal Front-porch Enable */
+#define DSI_VMCCR_FBTAAE ((uint32_t)0x00004000) /*!< Frame BTA Acknowledge Enable */
+#define DSI_VMCCR_LPCE ((uint32_t)0x00008000) /*!< Low-power Command Enable */
+
+/******************* Bit definition for DSI_VPCCR register **************/
+#define DSI_VPCCR_VPSIZE ((uint32_t)0x00003FFF) /*!< Video Packet Size */
+#define DSI_VPCCR_VPSIZE0 ((uint32_t)0x00000001)
+#define DSI_VPCCR_VPSIZE1 ((uint32_t)0x00000002)
+#define DSI_VPCCR_VPSIZE2 ((uint32_t)0x00000004)
+#define DSI_VPCCR_VPSIZE3 ((uint32_t)0x00000008)
+#define DSI_VPCCR_VPSIZE4 ((uint32_t)0x00000010)
+#define DSI_VPCCR_VPSIZE5 ((uint32_t)0x00000020)
+#define DSI_VPCCR_VPSIZE6 ((uint32_t)0x00000040)
+#define DSI_VPCCR_VPSIZE7 ((uint32_t)0x00000080)
+#define DSI_VPCCR_VPSIZE8 ((uint32_t)0x00000100)
+#define DSI_VPCCR_VPSIZE9 ((uint32_t)0x00000200)
+#define DSI_VPCCR_VPSIZE10 ((uint32_t)0x00000400)
+#define DSI_VPCCR_VPSIZE11 ((uint32_t)0x00000800)
+#define DSI_VPCCR_VPSIZE12 ((uint32_t)0x00001000)
+#define DSI_VPCCR_VPSIZE13 ((uint32_t)0x00002000)
+
+/******************* Bit definition for DSI_VCCCR register **************/
+#define DSI_VCCCR_NUMC ((uint32_t)0x00001FFF) /*!< Number of Chunks */
+#define DSI_VCCCR_NUMC0 ((uint32_t)0x00000001)
+#define DSI_VCCCR_NUMC1 ((uint32_t)0x00000002)
+#define DSI_VCCCR_NUMC2 ((uint32_t)0x00000004)
+#define DSI_VCCCR_NUMC3 ((uint32_t)0x00000008)
+#define DSI_VCCCR_NUMC4 ((uint32_t)0x00000010)
+#define DSI_VCCCR_NUMC5 ((uint32_t)0x00000020)
+#define DSI_VCCCR_NUMC6 ((uint32_t)0x00000040)
+#define DSI_VCCCR_NUMC7 ((uint32_t)0x00000080)
+#define DSI_VCCCR_NUMC8 ((uint32_t)0x00000100)
+#define DSI_VCCCR_NUMC9 ((uint32_t)0x00000200)
+#define DSI_VCCCR_NUMC10 ((uint32_t)0x00000400)
+#define DSI_VCCCR_NUMC11 ((uint32_t)0x00000800)
+#define DSI_VCCCR_NUMC12 ((uint32_t)0x00001000)
+
+/******************* Bit definition for DSI_VNPCCR register *************/
+#define DSI_VNPCCR_NPSIZE ((uint32_t)0x00001FFF) /*!< Number of Chunks */
+#define DSI_VNPCCR_NPSIZE0 ((uint32_t)0x00000001)
+#define DSI_VNPCCR_NPSIZE1 ((uint32_t)0x00000002)
+#define DSI_VNPCCR_NPSIZE2 ((uint32_t)0x00000004)
+#define DSI_VNPCCR_NPSIZE3 ((uint32_t)0x00000008)
+#define DSI_VNPCCR_NPSIZE4 ((uint32_t)0x00000010)
+#define DSI_VNPCCR_NPSIZE5 ((uint32_t)0x00000020)
+#define DSI_VNPCCR_NPSIZE6 ((uint32_t)0x00000040)
+#define DSI_VNPCCR_NPSIZE7 ((uint32_t)0x00000080)
+#define DSI_VNPCCR_NPSIZE8 ((uint32_t)0x00000100)
+#define DSI_VNPCCR_NPSIZE9 ((uint32_t)0x00000200)
+#define DSI_VNPCCR_NPSIZE10 ((uint32_t)0x00000400)
+#define DSI_VNPCCR_NPSIZE11 ((uint32_t)0x00000800)
+#define DSI_VNPCCR_NPSIZE12 ((uint32_t)0x00001000)
+
+/******************* Bit definition for DSI_VHSACCR register ************/
+#define DSI_VHSACCR_HSA ((uint32_t)0x00000FFF) /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACCR_HSA0 ((uint32_t)0x00000001)
+#define DSI_VHSACCR_HSA1 ((uint32_t)0x00000002)
+#define DSI_VHSACCR_HSA2 ((uint32_t)0x00000004)
+#define DSI_VHSACCR_HSA3 ((uint32_t)0x00000008)
+#define DSI_VHSACCR_HSA4 ((uint32_t)0x00000010)
+#define DSI_VHSACCR_HSA5 ((uint32_t)0x00000020)
+#define DSI_VHSACCR_HSA6 ((uint32_t)0x00000040)
+#define DSI_VHSACCR_HSA7 ((uint32_t)0x00000080)
+#define DSI_VHSACCR_HSA8 ((uint32_t)0x00000100)
+#define DSI_VHSACCR_HSA9 ((uint32_t)0x00000200)
+#define DSI_VHSACCR_HSA10 ((uint32_t)0x00000400)
+#define DSI_VHSACCR_HSA11 ((uint32_t)0x00000800)
+
+/******************* Bit definition for DSI_VHBPCCR register ************/
+#define DSI_VHBPCCR_HBP ((uint32_t)0x00000FFF) /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCCR_HBP0 ((uint32_t)0x00000001)
+#define DSI_VHBPCCR_HBP1 ((uint32_t)0x00000002)
+#define DSI_VHBPCCR_HBP2 ((uint32_t)0x00000004)
+#define DSI_VHBPCCR_HBP3 ((uint32_t)0x00000008)
+#define DSI_VHBPCCR_HBP4 ((uint32_t)0x00000010)
+#define DSI_VHBPCCR_HBP5 ((uint32_t)0x00000020)
+#define DSI_VHBPCCR_HBP6 ((uint32_t)0x00000040)
+#define DSI_VHBPCCR_HBP7 ((uint32_t)0x00000080)
+#define DSI_VHBPCCR_HBP8 ((uint32_t)0x00000100)
+#define DSI_VHBPCCR_HBP9 ((uint32_t)0x00000200)
+#define DSI_VHBPCCR_HBP10 ((uint32_t)0x00000400)
+#define DSI_VHBPCCR_HBP11 ((uint32_t)0x00000800)
+
+/******************* Bit definition for DSI_VLCCR register **************/
+#define DSI_VLCCR_HLINE ((uint32_t)0x00007FFF) /*!< Horizontal Line duration */
+#define DSI_VLCCR_HLINE0 ((uint32_t)0x00000001)
+#define DSI_VLCCR_HLINE1 ((uint32_t)0x00000002)
+#define DSI_VLCCR_HLINE2 ((uint32_t)0x00000004)
+#define DSI_VLCCR_HLINE3 ((uint32_t)0x00000008)
+#define DSI_VLCCR_HLINE4 ((uint32_t)0x00000010)
+#define DSI_VLCCR_HLINE5 ((uint32_t)0x00000020)
+#define DSI_VLCCR_HLINE6 ((uint32_t)0x00000040)
+#define DSI_VLCCR_HLINE7 ((uint32_t)0x00000080)
+#define DSI_VLCCR_HLINE8 ((uint32_t)0x00000100)
+#define DSI_VLCCR_HLINE9 ((uint32_t)0x00000200)
+#define DSI_VLCCR_HLINE10 ((uint32_t)0x00000400)
+#define DSI_VLCCR_HLINE11 ((uint32_t)0x00000800)
+#define DSI_VLCCR_HLINE12 ((uint32_t)0x00001000)
+#define DSI_VLCCR_HLINE13 ((uint32_t)0x00002000)
+#define DSI_VLCCR_HLINE14 ((uint32_t)0x00004000)
+
+/******************* Bit definition for DSI_VVSACCR register ***************/
+#define DSI_VVSACCR_VSA ((uint32_t)0x000003FF) /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACCR_VSA0 ((uint32_t)0x00000001)
+#define DSI_VVSACCR_VSA1 ((uint32_t)0x00000002)
+#define DSI_VVSACCR_VSA2 ((uint32_t)0x00000004)
+#define DSI_VVSACCR_VSA3 ((uint32_t)0x00000008)
+#define DSI_VVSACCR_VSA4 ((uint32_t)0x00000010)
+#define DSI_VVSACCR_VSA5 ((uint32_t)0x00000020)
+#define DSI_VVSACCR_VSA6 ((uint32_t)0x00000040)
+#define DSI_VVSACCR_VSA7 ((uint32_t)0x00000080)
+#define DSI_VVSACCR_VSA8 ((uint32_t)0x00000100)
+#define DSI_VVSACCR_VSA9 ((uint32_t)0x00000200)
+
+/******************* Bit definition for DSI_VVBPCCR register ************/
+#define DSI_VVBPCCR_VBP ((uint32_t)0x000003FF) /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCCR_VBP0 ((uint32_t)0x00000001)
+#define DSI_VVBPCCR_VBP1 ((uint32_t)0x00000002)
+#define DSI_VVBPCCR_VBP2 ((uint32_t)0x00000004)
+#define DSI_VVBPCCR_VBP3 ((uint32_t)0x00000008)
+#define DSI_VVBPCCR_VBP4 ((uint32_t)0x00000010)
+#define DSI_VVBPCCR_VBP5 ((uint32_t)0x00000020)
+#define DSI_VVBPCCR_VBP6 ((uint32_t)0x00000040)
+#define DSI_VVBPCCR_VBP7 ((uint32_t)0x00000080)
+#define DSI_VVBPCCR_VBP8 ((uint32_t)0x00000100)
+#define DSI_VVBPCCR_VBP9 ((uint32_t)0x00000200)
+
+/******************* Bit definition for DSI_VVFPCCR register ************/
+#define DSI_VVFPCCR_VFP ((uint32_t)0x000003FF) /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCCR_VFP0 ((uint32_t)0x00000001)
+#define DSI_VVFPCCR_VFP1 ((uint32_t)0x00000002)
+#define DSI_VVFPCCR_VFP2 ((uint32_t)0x00000004)
+#define DSI_VVFPCCR_VFP3 ((uint32_t)0x00000008)
+#define DSI_VVFPCCR_VFP4 ((uint32_t)0x00000010)
+#define DSI_VVFPCCR_VFP5 ((uint32_t)0x00000020)
+#define DSI_VVFPCCR_VFP6 ((uint32_t)0x00000040)
+#define DSI_VVFPCCR_VFP7 ((uint32_t)0x00000080)
+#define DSI_VVFPCCR_VFP8 ((uint32_t)0x00000100)
+#define DSI_VVFPCCR_VFP9 ((uint32_t)0x00000200)
+
+/******************* Bit definition for DSI_VVACCR register *************/
+#define DSI_VVACCR_VA ((uint32_t)0x00003FFF) /*!< Vertical Active duration */
+#define DSI_VVACCR_VA0 ((uint32_t)0x00000001)
+#define DSI_VVACCR_VA1 ((uint32_t)0x00000002)
+#define DSI_VVACCR_VA2 ((uint32_t)0x00000004)
+#define DSI_VVACCR_VA3 ((uint32_t)0x00000008)
+#define DSI_VVACCR_VA4 ((uint32_t)0x00000010)
+#define DSI_VVACCR_VA5 ((uint32_t)0x00000020)
+#define DSI_VVACCR_VA6 ((uint32_t)0x00000040)
+#define DSI_VVACCR_VA7 ((uint32_t)0x00000080)
+#define DSI_VVACCR_VA8 ((uint32_t)0x00000100)
+#define DSI_VVACCR_VA9 ((uint32_t)0x00000200)
+#define DSI_VVACCR_VA10 ((uint32_t)0x00000400)
+#define DSI_VVACCR_VA11 ((uint32_t)0x00000800)
+#define DSI_VVACCR_VA12 ((uint32_t)0x00001000)
+#define DSI_VVACCR_VA13 ((uint32_t)0x00002000)
+
+/******************* Bit definition for DSI_TDCCR register **************/
+#define DSI_TDCCR_3DM ((uint32_t)0x00000003) /*!< 3D Mode */
+#define DSI_TDCCR_3DM0 ((uint32_t)0x00000001)
+#define DSI_TDCCR_3DM1 ((uint32_t)0x00000002)
+
+#define DSI_TDCCR_3DF ((uint32_t)0x0000000C) /*!< 3D Format */
+#define DSI_TDCCR_3DF0 ((uint32_t)0x00000004)
+#define DSI_TDCCR_3DF1 ((uint32_t)0x00000008)
+
+#define DSI_TDCCR_SVS ((uint32_t)0x00000010) /*!< Second VSYNC */
+#define DSI_TDCCR_RF ((uint32_t)0x00000020) /*!< Right First */
+#define DSI_TDCCR_S3DC ((uint32_t)0x00010000) /*!< Send 3D Control */
+
+/******************* Bit definition for DSI_WCFGR register ***************/
+#define DSI_WCFGR_DSIM ((uint32_t)0x00000001) /*!< DSI Mode */
+#define DSI_WCFGR_COLMUX ((uint32_t)0x0000000E) /*!< Color Multiplexing */
+#define DSI_WCFGR_COLMUX0 ((uint32_t)0x00000002)
+#define DSI_WCFGR_COLMUX1 ((uint32_t)0x00000004)
+#define DSI_WCFGR_COLMUX2 ((uint32_t)0x00000008)
+
+#define DSI_WCFGR_TESRC ((uint32_t)0x00000010) /*!< Tearing Effect Source */
+#define DSI_WCFGR_TEPOL ((uint32_t)0x00000020) /*!< Tearing Effect Polarity */
+#define DSI_WCFGR_AR ((uint32_t)0x00000040) /*!< Automatic Refresh */
+#define DSI_WCFGR_VSPOL ((uint32_t)0x00000080) /*!< VSync Polarity */
+
+/******************* Bit definition for DSI_WCR register *****************/
+#define DSI_WCR_COLM ((uint32_t)0x00000001) /*!< Color Mode */
+#define DSI_WCR_SHTDN ((uint32_t)0x00000002) /*!< Shutdown */
+#define DSI_WCR_LTDCEN ((uint32_t)0x00000004) /*!< LTDC Enable */
+#define DSI_WCR_DSIEN ((uint32_t)0x00000008) /*!< DSI Enable */
+
+/******************* Bit definition for DSI_WIER register ****************/
+#define DSI_WIER_TEIE ((uint32_t)0x00000001) /*!< Tearing Effect Interrupt Enable */
+#define DSI_WIER_ERIE ((uint32_t)0x00000002) /*!< End of Refresh Interrupt Enable */
+#define DSI_WIER_PLLLIE ((uint32_t)0x00000200) /*!< PLL Lock Interrupt Enable */
+#define DSI_WIER_PLLUIE ((uint32_t)0x00000400) /*!< PLL Unlock Interrupt Enable */
+#define DSI_WIER_RRIE ((uint32_t)0x00002000) /*!< Regulator Ready Interrupt Enable */
+
+/******************* Bit definition for DSI_WISR register ****************/
+#define DSI_WISR_TEIF ((uint32_t)0x00000001) /*!< Tearing Effect Interrupt Flag */
+#define DSI_WISR_ERIF ((uint32_t)0x00000002) /*!< End of Refresh Interrupt Flag */
+#define DSI_WISR_BUSY ((uint32_t)0x00000004) /*!< Busy Flag */
+#define DSI_WISR_PLLLS ((uint32_t)0x00000100) /*!< PLL Lock Status */
+#define DSI_WISR_PLLLIF ((uint32_t)0x00000200) /*!< PLL Lock Interrupt Flag */
+#define DSI_WISR_PLLUIF ((uint32_t)0x00000400) /*!< PLL Unlock Interrupt Flag */
+#define DSI_WISR_RRS ((uint32_t)0x00001000) /*!< Regulator Ready Flag */
+#define DSI_WISR_RRIF ((uint32_t)0x00002000) /*!< Regulator Ready Interrupt Flag */
+
+/******************* Bit definition for DSI_WIFCR register ***************/
+#define DSI_WIFCR_CTEIF ((uint32_t)0x00000001) /*!< Clear Tearing Effect Interrupt Flag */
+#define DSI_WIFCR_CERIF ((uint32_t)0x00000002) /*!< Clear End of Refresh Interrupt Flag */
+#define DSI_WIFCR_CPLLLIF ((uint32_t)0x00000200) /*!< Clear PLL Lock Interrupt Flag */
+#define DSI_WIFCR_CPLLUIF ((uint32_t)0x00000400) /*!< Clear PLL Unlock Interrupt Flag */
+#define DSI_WIFCR_CRRIF ((uint32_t)0x00002000) /*!< Clear Regulator Ready Interrupt Flag */
+
+/******************* Bit definition for DSI_WPCR0 register ***************/
+#define DSI_WPCR0_UIX4 ((uint32_t)0x0000003F) /*!< Unit Interval multiplied by 4 */
+#define DSI_WPCR0_UIX4_0 ((uint32_t)0x00000001)
+#define DSI_WPCR0_UIX4_1 ((uint32_t)0x00000002)
+#define DSI_WPCR0_UIX4_2 ((uint32_t)0x00000004)
+#define DSI_WPCR0_UIX4_3 ((uint32_t)0x00000008)
+#define DSI_WPCR0_UIX4_4 ((uint32_t)0x00000010)
+#define DSI_WPCR0_UIX4_5 ((uint32_t)0x00000020)
+
+#define DSI_WPCR0_SWCL ((uint32_t)0x00000040) /*!< Swap pins on clock lane */
+#define DSI_WPCR0_SWDL0 ((uint32_t)0x00000080) /*!< Swap pins on data lane 1 */
+#define DSI_WPCR0_SWDL1 ((uint32_t)0x00000100) /*!< Swap pins on data lane 2 */
+#define DSI_WPCR0_HSICL ((uint32_t)0x00000200) /*!< Invert the high-speed data signal on clock lane */
+#define DSI_WPCR0_HSIDL0 ((uint32_t)0x00000400) /*!< Invert the high-speed data signal on lane 1 */
+#define DSI_WPCR0_HSIDL1 ((uint32_t)0x00000800) /*!< Invert the high-speed data signal on lane 2 */
+#define DSI_WPCR0_FTXSMCL ((uint32_t)0x00001000) /*!< Force clock lane in TX stop mode */
+#define DSI_WPCR0_FTXSMDL ((uint32_t)0x00002000) /*!< Force data lanes in TX stop mode */
+#define DSI_WPCR0_CDOFFDL ((uint32_t)0x00004000) /*!< Contention detection OFF */
+#define DSI_WPCR0_TDDL ((uint32_t)0x00010000) /*!< Turn Disable Data Lanes */
+#define DSI_WPCR0_PDEN ((uint32_t)0x00040000) /*!< Pull-Down Enable */
+#define DSI_WPCR0_TCLKPREPEN ((uint32_t)0x00080000) /*!< Timer for t-CLKPREP Enable */
+#define DSI_WPCR0_TCLKZEROEN ((uint32_t)0x00100000) /*!< Timer for t-CLKZERO Enable */
+#define DSI_WPCR0_THSPREPEN ((uint32_t)0x00200000) /*!< Timer for t-HSPREP Enable */
+#define DSI_WPCR0_THSTRAILEN ((uint32_t)0x00400000) /*!< Timer for t-HSTRAIL Enable */
+#define DSI_WPCR0_THSZEROEN ((uint32_t)0x00800000) /*!< Timer for t-HSZERO Enable */
+#define DSI_WPCR0_TLPXDEN ((uint32_t)0x01000000) /*!< Timer for t-LPXD Enable */
+#define DSI_WPCR0_THSEXITEN ((uint32_t)0x02000000) /*!< Timer for t-HSEXIT Enable */
+#define DSI_WPCR0_TLPXCEN ((uint32_t)0x04000000) /*!< Timer for t-LPXC Enable */
+#define DSI_WPCR0_TCLKPOSTEN ((uint32_t)0x08000000) /*!< Timer for t-CLKPOST Enable */
+
+/******************* Bit definition for DSI_WPCR1 register ***************/
+#define DSI_WPCR1_HSTXDCL ((uint32_t)0x00000003) /*!< High-Speed Transmission Delay on Clock Lane */
+#define DSI_WPCR1_HSTXDCL0 ((uint32_t)0x00000001)
+#define DSI_WPCR1_HSTXDCL1 ((uint32_t)0x00000002)
+
+#define DSI_WPCR1_HSTXDDL ((uint32_t)0x0000000C) /*!< High-Speed Transmission Delay on Data Lane */
+#define DSI_WPCR1_HSTXDDL0 ((uint32_t)0x00000004)
+#define DSI_WPCR1_HSTXDDL1 ((uint32_t)0x00000008)
+
+#define DSI_WPCR1_LPSRCCL ((uint32_t)0x000000C0) /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
+#define DSI_WPCR1_LPSRCCL0 ((uint32_t)0x00000040)
+#define DSI_WPCR1_LPSRCCL1 ((uint32_t)0x00000080)
+
+#define DSI_WPCR1_LPSRCDL ((uint32_t)0x00000300) /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
+#define DSI_WPCR1_LPSRCDL0 ((uint32_t)0x00000100)
+#define DSI_WPCR1_LPSRCDL1 ((uint32_t)0x00000200)
+
+#define DSI_WPCR1_SDDC ((uint32_t)0x00001000) /*!< SDD Control */
+
+#define DSI_WPCR1_LPRXVCDL ((uint32_t)0x0000C000) /*!< Low-Power Reception V-IL Compensation on Data Lanes */
+#define DSI_WPCR1_LPRXVCDL0 ((uint32_t)0x00004000)
+#define DSI_WPCR1_LPRXVCDL1 ((uint32_t)0x00008000)
+
+#define DSI_WPCR1_HSTXSRCCL ((uint32_t)0x00030000) /*!< High-Speed Transmission Delay on Clock Lane */
+#define DSI_WPCR1_HSTXSRCCL0 ((uint32_t)0x00010000)
+#define DSI_WPCR1_HSTXSRCCL1 ((uint32_t)0x00020000)
+
+#define DSI_WPCR1_HSTXSRCDL ((uint32_t)0x000C0000) /*!< High-Speed Transmission Delay on Data Lane */
+#define DSI_WPCR1_HSTXSRCDL0 ((uint32_t)0x00040000)
+#define DSI_WPCR1_HSTXSRCDL1 ((uint32_t)0x00080000)
+
+#define DSI_WPCR1_FLPRXLPM ((uint32_t)0x00400000) /*!< Forces LP Receiver in Low-Power Mode */
+
+#define DSI_WPCR1_LPRXFT ((uint32_t)0x06000000) /*!< Low-Power RX low-pass Filtering Tuning */
+#define DSI_WPCR1_LPRXFT0 ((uint32_t)0x02000000)
+#define DSI_WPCR1_LPRXFT1 ((uint32_t)0x04000000)
+
+/******************* Bit definition for DSI_WPCR2 register ***************/
+#define DSI_WPCR2_TCLKPREP ((uint32_t)0x000000FF) /*!< t-CLKPREP */
+#define DSI_WPCR2_TCLKPREP0 ((uint32_t)0x00000001)
+#define DSI_WPCR2_TCLKPREP1 ((uint32_t)0x00000002)
+#define DSI_WPCR2_TCLKPREP2 ((uint32_t)0x00000004)
+#define DSI_WPCR2_TCLKPREP3 ((uint32_t)0x00000008)
+#define DSI_WPCR2_TCLKPREP4 ((uint32_t)0x00000010)
+#define DSI_WPCR2_TCLKPREP5 ((uint32_t)0x00000020)
+#define DSI_WPCR2_TCLKPREP6 ((uint32_t)0x00000040)
+#define DSI_WPCR2_TCLKPREP7 ((uint32_t)0x00000080)
+
+#define DSI_WPCR2_TCLKZERO ((uint32_t)0x0000FF00) /*!< t-CLKZERO */
+#define DSI_WPCR2_TCLKZERO0 ((uint32_t)0x00000100)
+#define DSI_WPCR2_TCLKZERO1 ((uint32_t)0x00000200)
+#define DSI_WPCR2_TCLKZERO2 ((uint32_t)0x00000400)
+#define DSI_WPCR2_TCLKZERO3 ((uint32_t)0x00000800)
+#define DSI_WPCR2_TCLKZERO4 ((uint32_t)0x00001000)
+#define DSI_WPCR2_TCLKZERO5 ((uint32_t)0x00002000)
+#define DSI_WPCR2_TCLKZERO6 ((uint32_t)0x00004000)
+#define DSI_WPCR2_TCLKZERO7 ((uint32_t)0x00008000)
+
+#define DSI_WPCR2_THSPREP ((uint32_t)0x00FF0000) /*!< t-HSPREP */
+#define DSI_WPCR2_THSPREP0 ((uint32_t)0x00010000)
+#define DSI_WPCR2_THSPREP1 ((uint32_t)0x00020000)
+#define DSI_WPCR2_THSPREP2 ((uint32_t)0x00040000)
+#define DSI_WPCR2_THSPREP3 ((uint32_t)0x00080000)
+#define DSI_WPCR2_THSPREP4 ((uint32_t)0x00100000)
+#define DSI_WPCR2_THSPREP5 ((uint32_t)0x00200000)
+#define DSI_WPCR2_THSPREP6 ((uint32_t)0x00400000)
+#define DSI_WPCR2_THSPREP7 ((uint32_t)0x00800000)
+
+#define DSI_WPCR2_THSTRAIL ((uint32_t)0xFF000000) /*!< t-HSTRAIL */
+#define DSI_WPCR2_THSTRAIL0 ((uint32_t)0x01000000)
+#define DSI_WPCR2_THSTRAIL1 ((uint32_t)0x02000000)
+#define DSI_WPCR2_THSTRAIL2 ((uint32_t)0x04000000)
+#define DSI_WPCR2_THSTRAIL3 ((uint32_t)0x08000000)
+#define DSI_WPCR2_THSTRAIL4 ((uint32_t)0x10000000)
+#define DSI_WPCR2_THSTRAIL5 ((uint32_t)0x20000000)
+#define DSI_WPCR2_THSTRAIL6 ((uint32_t)0x40000000)
+#define DSI_WPCR2_THSTRAIL7 ((uint32_t)0x80000000)
+
+/******************* Bit definition for DSI_WPCR3 register ***************/
+#define DSI_WPCR3_THSZERO ((uint32_t)0x000000FF) /*!< t-HSZERO */
+#define DSI_WPCR3_THSZERO0 ((uint32_t)0x00000001)
+#define DSI_WPCR3_THSZERO1 ((uint32_t)0x00000002)
+#define DSI_WPCR3_THSZERO2 ((uint32_t)0x00000004)
+#define DSI_WPCR3_THSZERO3 ((uint32_t)0x00000008)
+#define DSI_WPCR3_THSZERO4 ((uint32_t)0x00000010)
+#define DSI_WPCR3_THSZERO5 ((uint32_t)0x00000020)
+#define DSI_WPCR3_THSZERO6 ((uint32_t)0x00000040)
+#define DSI_WPCR3_THSZERO7 ((uint32_t)0x00000080)
+
+#define DSI_WPCR3_TLPXD ((uint32_t)0x0000FF00) /*!< t-LPXD */
+#define DSI_WPCR3_TLPXD0 ((uint32_t)0x00000100)
+#define DSI_WPCR3_TLPXD1 ((uint32_t)0x00000200)
+#define DSI_WPCR3_TLPXD2 ((uint32_t)0x00000400)
+#define DSI_WPCR3_TLPXD3 ((uint32_t)0x00000800)
+#define DSI_WPCR3_TLPXD4 ((uint32_t)0x00001000)
+#define DSI_WPCR3_TLPXD5 ((uint32_t)0x00002000)
+#define DSI_WPCR3_TLPXD6 ((uint32_t)0x00004000)
+#define DSI_WPCR3_TLPXD7 ((uint32_t)0x00008000)
+
+#define DSI_WPCR3_THSEXIT ((uint32_t)0x00FF0000) /*!< t-HSEXIT */
+#define DSI_WPCR3_THSEXIT0 ((uint32_t)0x00010000)
+#define DSI_WPCR3_THSEXIT1 ((uint32_t)0x00020000)
+#define DSI_WPCR3_THSEXIT2 ((uint32_t)0x00040000)
+#define DSI_WPCR3_THSEXIT3 ((uint32_t)0x00080000)
+#define DSI_WPCR3_THSEXIT4 ((uint32_t)0x00100000)
+#define DSI_WPCR3_THSEXIT5 ((uint32_t)0x00200000)
+#define DSI_WPCR3_THSEXIT6 ((uint32_t)0x00400000)
+#define DSI_WPCR3_THSEXIT7 ((uint32_t)0x00800000)
+
+#define DSI_WPCR3_TLPXC ((uint32_t)0xFF000000) /*!< t-LPXC */
+#define DSI_WPCR3_TLPXC0 ((uint32_t)0x01000000)
+#define DSI_WPCR3_TLPXC1 ((uint32_t)0x02000000)
+#define DSI_WPCR3_TLPXC2 ((uint32_t)0x04000000)
+#define DSI_WPCR3_TLPXC3 ((uint32_t)0x08000000)
+#define DSI_WPCR3_TLPXC4 ((uint32_t)0x10000000)
+#define DSI_WPCR3_TLPXC5 ((uint32_t)0x20000000)
+#define DSI_WPCR3_TLPXC6 ((uint32_t)0x40000000)
+#define DSI_WPCR3_TLPXC7 ((uint32_t)0x80000000)
+
+/******************* Bit definition for DSI_WPCR4 register ***************/
+#define DSI_WPCR4_TCLKPOST ((uint32_t)0x000000FF) /*!< t-CLKPOST */
+#define DSI_WPCR4_TCLKPOST0 ((uint32_t)0x00000001)
+#define DSI_WPCR4_TCLKPOST1 ((uint32_t)0x00000002)
+#define DSI_WPCR4_TCLKPOST2 ((uint32_t)0x00000004)
+#define DSI_WPCR4_TCLKPOST3 ((uint32_t)0x00000008)
+#define DSI_WPCR4_TCLKPOST4 ((uint32_t)0x00000010)
+#define DSI_WPCR4_TCLKPOST5 ((uint32_t)0x00000020)
+#define DSI_WPCR4_TCLKPOST6 ((uint32_t)0x00000040)
+#define DSI_WPCR4_TCLKPOST7 ((uint32_t)0x00000080)
+
+/******************* Bit definition for DSI_WRPCR register ***************/
+#define DSI_WRPCR_PLLEN ((uint32_t)0x00000001) /*!< PLL Enable */
+#define DSI_WRPCR_PLL_NDIV ((uint32_t)0x000001FC) /*!< PLL Loop Division Factor */
+#define DSI_WRPCR_PLL_NDIV0 ((uint32_t)0x00000004)
+#define DSI_WRPCR_PLL_NDIV1 ((uint32_t)0x00000008)
+#define DSI_WRPCR_PLL_NDIV2 ((uint32_t)0x00000010)
+#define DSI_WRPCR_PLL_NDIV3 ((uint32_t)0x00000020)
+#define DSI_WRPCR_PLL_NDIV4 ((uint32_t)0x00000040)
+#define DSI_WRPCR_PLL_NDIV5 ((uint32_t)0x00000080)
+#define DSI_WRPCR_PLL_NDIV6 ((uint32_t)0x00000100)
+
+#define DSI_WRPCR_PLL_IDF ((uint32_t)0x00007800) /*!< PLL Input Division Factor */
+#define DSI_WRPCR_PLL_IDF0 ((uint32_t)0x00000800)
+#define DSI_WRPCR_PLL_IDF1 ((uint32_t)0x00001000)
+#define DSI_WRPCR_PLL_IDF2 ((uint32_t)0x00002000)
+#define DSI_WRPCR_PLL_IDF3 ((uint32_t)0x00004000)
+
+#define DSI_WRPCR_PLL_ODF ((uint32_t)0x00030000) /*!< PLL Output Division Factor */
+#define DSI_WRPCR_PLL_ODF0 ((uint32_t)0x00010000)
+#define DSI_WRPCR_PLL_ODF1 ((uint32_t)0x00020000)
+
+#define DSI_WRPCR_REGEN ((uint32_t)0x01000000) /*!< Regulator Enable */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
+#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
+#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
+#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
+#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
+#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
+#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
+#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
+#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
+#define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
+#define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
+#define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
+#define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
+#define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
+#define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
+#define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
+#define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
+#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
+#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
+#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
+#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
+#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
+#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP ((uint32_t)0x00000001)
+#define FLASH_SR_SOP ((uint32_t)0x00000002)
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
+#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
+#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
+#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
+#define FLASH_SR_BSY ((uint32_t)0x00010000)
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001)
+#define FLASH_CR_SER ((uint32_t)0x00000002)
+#define FLASH_CR_MER ((uint32_t)0x00000004)
+#define FLASH_CR_MER1 FLASH_CR_MER
+#define FLASH_CR_SNB ((uint32_t)0x000000F8)
+#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
+#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
+#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
+#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
+#define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
+#define FLASH_CR_PSIZE ((uint32_t)0x00000300)
+#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
+#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
+#define FLASH_CR_MER2 ((uint32_t)0x00008000)
+#define FLASH_CR_STRT ((uint32_t)0x00010000)
+#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
+#define FLASH_CR_LOCK ((uint32_t)0x80000000)
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
+#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
+#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
+#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
+#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
+#define FLASH_OPTCR_BFB2 ((uint32_t)0x00000010)
+#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
+#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
+#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
+#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
+#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
+#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
+#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
+#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
+#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
+#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
+#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
+#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
+#define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
+#define FLASH_OPTCR_DB1M ((uint32_t)0x40000000)
+#define FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000)
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR1_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
+#define FMC_BCR1_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BCR1_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BCR1_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
+#define FMC_BCR1_WFDIS ((uint32_t)0x00200000) /*!<Write FIFO Disable */
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_PCR register *******************/
+#define FMC_PCR_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FMC_PCR_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FMC_PCR_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_PCR_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_PCR_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FMC_PCR_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FMC_PCR_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_PCR_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FMC_PCR_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FMC_PCR_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FMC_PCR_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/******************* Bit definition for FMC_SR register *******************/
+#define FMC_SR_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FMC_SR_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FMC_SR_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FMC_SR_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FMC_SR_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEM register ******************/
+#define FMC_PMEM_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PMEM_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PMEM_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PMEM_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PMEM_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PMEM_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PMEM_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PMEM_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PMEM_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PMEM_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PMEM_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PMEM_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PMEM_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PMEM_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PMEM_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PMEM_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PMEM_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PMEM_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PMEM_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PMEM_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PMEM_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PMEM_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PMEM_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PMEM_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PMEM_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PMEM_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PMEM_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PMEM_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PMEM_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PMEM_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PMEM_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PMEM_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT register ******************/
+#define FMC_PATT_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PATT_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PATT_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PATT_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PATT_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PATT_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PATT_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PATT_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PATT_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PATT_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PATT_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PATT_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PATT_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PATT_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PATT_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PATT_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PATT_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PATT_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PATT_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PATT_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PATT_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PATT_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PATT_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PATT_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PATT_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PATT_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PATT_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PATT_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PATT_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PATT_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PATT_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PATT_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_ECCR register ******************/
+#define FMC_ECCR_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
+
+/****************** Bit definition for FMC_SDCR1 register ******************/
+#define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
+
+#define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+
+#define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
+
+#define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
+#define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
+
+#define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
+#define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDCR2 register ******************/
+#define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
+
+#define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+
+#define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
+
+#define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
+
+#define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
+#define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDTR1 register ******************/
+#define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+
+#define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+
+#define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDTR2 register ******************/
+#define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+
+#define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+
+#define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDCMR register ******************/
+#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+
+#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+
+#define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
+
+/****************** Bit definition for FMC_SDRTR register ******************/
+#define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
+
+/****************** Bit definition for FMC_SDSR register ******************/
+#define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+
+#define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/******************************************************************************/
+/* */
+/* HASH */
+/* */
+/******************************************************************************/
+/****************** Bits definition for HASH_CR register ********************/
+#define HASH_CR_INIT ((uint32_t)0x00000004)
+#define HASH_CR_DMAE ((uint32_t)0x00000008)
+#define HASH_CR_DATATYPE ((uint32_t)0x00000030)
+#define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)
+#define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)
+#define HASH_CR_MODE ((uint32_t)0x00000040)
+#define HASH_CR_ALGO ((uint32_t)0x00040080)
+#define HASH_CR_ALGO_0 ((uint32_t)0x00000080)
+#define HASH_CR_ALGO_1 ((uint32_t)0x00040000)
+#define HASH_CR_NBW ((uint32_t)0x00000F00)
+#define HASH_CR_NBW_0 ((uint32_t)0x00000100)
+#define HASH_CR_NBW_1 ((uint32_t)0x00000200)
+#define HASH_CR_NBW_2 ((uint32_t)0x00000400)
+#define HASH_CR_NBW_3 ((uint32_t)0x00000800)
+#define HASH_CR_DINNE ((uint32_t)0x00001000)
+#define HASH_CR_MDMAT ((uint32_t)0x00002000)
+#define HASH_CR_LKEY ((uint32_t)0x00010000)
+
+/****************** Bits definition for HASH_STR register *******************/
+#define HASH_STR_NBLW ((uint32_t)0x0000001F)
+#define HASH_STR_NBLW_0 ((uint32_t)0x00000001)
+#define HASH_STR_NBLW_1 ((uint32_t)0x00000002)
+#define HASH_STR_NBLW_2 ((uint32_t)0x00000004)
+#define HASH_STR_NBLW_3 ((uint32_t)0x00000008)
+#define HASH_STR_NBLW_4 ((uint32_t)0x00000010)
+#define HASH_STR_DCAL ((uint32_t)0x00000100)
+/* Aliases for HASH_STR register */
+#define HASH_STR_NBW HASH_STR_NBLW
+#define HASH_STR_NBW_0 HASH_STR_NBLW_0
+#define HASH_STR_NBW_1 HASH_STR_NBLW_1
+#define HASH_STR_NBW_2 HASH_STR_NBLW_2
+#define HASH_STR_NBW_3 HASH_STR_NBLW_3
+#define HASH_STR_NBW_4 HASH_STR_NBLW_4
+
+/****************** Bits definition for HASH_IMR register *******************/
+#define HASH_IMR_DINIE ((uint32_t)0x00000001)
+#define HASH_IMR_DCIE ((uint32_t)0x00000002)
+/* Aliases for HASH_IMR register */
+#define HASH_IMR_DINIM HASH_IMR_DINIE
+#define HASH_IMR_DCIM HASH_IMR_DCIE
+
+/****************** Bits definition for HASH_SR register ********************/
+#define HASH_SR_DINIS ((uint32_t)0x00000001)
+#define HASH_SR_DCIS ((uint32_t)0x00000002)
+#define HASH_SR_DMAS ((uint32_t)0x00000004)
+#define HASH_SR_BUSY ((uint32_t)0x00000008)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
+#define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
+#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
+#define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
+#define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
+#define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
+#define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
+#define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
+#define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
+#define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
+#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
+#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
+#define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
+#define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
+#define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
+#define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* LCD-TFT Display Controller (LTDC) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for LTDC_SSCR register *****************/
+
+#define LTDC_SSCR_VSH ((uint32_t)0x000007FF) /*!< Vertical Synchronization Height */
+#define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /*!< Horizontal Synchronization Width */
+
+/******************** Bit definition for LTDC_BPCR register *****************/
+
+#define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) /*!< Accumulated Vertical Back Porch */
+#define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /*!< Accumulated Horizontal Back Porch */
+
+/******************** Bit definition for LTDC_AWCR register *****************/
+
+#define LTDC_AWCR_AAH ((uint32_t)0x000007FF) /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /*!< Accumulated Active Width */
+
+/******************** Bit definition for LTDC_TWCR register *****************/
+
+#define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /*!< Total Width */
+
+/******************** Bit definition for LTDC_GCR register ******************/
+
+#define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) /*!< LCD-TFT controller enable bit */
+#define LTDC_GCR_DBW ((uint32_t)0x00000070) /*!< Dither Blue Width */
+#define LTDC_GCR_DGW ((uint32_t)0x00000700) /*!< Dither Green Width */
+#define LTDC_GCR_DRW ((uint32_t)0x00007000) /*!< Dither Red Width */
+#define LTDC_GCR_DTEN ((uint32_t)0x00010000) /*!< Dither Enable */
+#define LTDC_GCR_PCPOL ((uint32_t)0x10000000) /*!< Pixel Clock Polarity */
+#define LTDC_GCR_DEPOL ((uint32_t)0x20000000) /*!< Data Enable Polarity */
+#define LTDC_GCR_VSPOL ((uint32_t)0x40000000) /*!< Vertical Synchronization Polarity */
+#define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /*!< Horizontal Synchronization Polarity */
+
+/******************** Bit definition for LTDC_SRCR register *****************/
+
+#define LTDC_SRCR_IMR ((uint32_t)0x00000001) /*!< Immediate Reload */
+#define LTDC_SRCR_VBR ((uint32_t)0x00000002) /*!< Vertical Blanking Reload */
+
+/******************** Bit definition for LTDC_BCCR register *****************/
+
+#define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) /*!< Background Blue value */
+#define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) /*!< Background Green value */
+#define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /*!< Background Red value */
+
+/******************** Bit definition for LTDC_IER register ******************/
+
+#define LTDC_IER_LIE ((uint32_t)0x00000001) /*!< Line Interrupt Enable */
+#define LTDC_IER_FUIE ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Enable */
+#define LTDC_IER_TERRIE ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Enable */
+#define LTDC_IER_RRIE ((uint32_t)0x00000008) /*!< Register Reload interrupt enable */
+
+/******************** Bit definition for LTDC_ISR register ******************/
+
+#define LTDC_ISR_LIF ((uint32_t)0x00000001) /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF ((uint32_t)0x00000008) /*!< Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_ICR register ******************/
+
+#define LTDC_ICR_CLIF ((uint32_t)0x00000001) /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF ((uint32_t)0x00000002) /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /*!< Clears Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_LIPCR register ****************/
+
+#define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /*!< Line Interrupt Position */
+
+/******************** Bit definition for LTDC_CPSR register *****************/
+
+#define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /*!< Current X Position */
+
+/******************** Bit definition for LTDC_CDSR register *****************/
+
+#define LTDC_CDSR_VDES ((uint32_t)0x00000001) /*!< Vertical Data Enable Status */
+#define LTDC_CDSR_HDES ((uint32_t)0x00000002) /*!< Horizontal Data Enable Status */
+#define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) /*!< Vertical Synchronization Status */
+#define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /*!< Horizontal Synchronization Status */
+
+/******************** Bit definition for LTDC_LxCR register *****************/
+
+#define LTDC_LxCR_LEN ((uint32_t)0x00000001) /*!< Layer Enable */
+#define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) /*!< Color Keying Enable */
+#define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) /*!< Color Lockup Table Enable */
+
+/******************** Bit definition for LTDC_LxWHPCR register **************/
+
+#define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) /*!< Window Horizontal Stop Position */
+
+/******************** Bit definition for LTDC_LxWVPCR register **************/
+
+#define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) /*!< Window Vertical Stop Position */
+
+/******************** Bit definition for LTDC_LxCKCR register ***************/
+
+#define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) /*!< Color Key Blue value */
+#define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) /*!< Color Key Red value */
+
+/******************** Bit definition for LTDC_LxPFCR register ***************/
+
+#define LTDC_LxPFCR_PF ((uint32_t)0x00000007) /*!< Pixel Format */
+
+/******************** Bit definition for LTDC_LxCACR register ***************/
+
+#define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) /*!< Constant Alpha */
+
+/******************** Bit definition for LTDC_LxDCCR register ***************/
+
+#define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) /*!< Default Color Blue */
+#define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) /*!< Default Color Red */
+#define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) /*!< Default Color Alpha */
+
+/******************** Bit definition for LTDC_LxBFCR register ***************/
+
+#define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) /*!< Blending Factor 1 */
+
+/******************** Bit definition for LTDC_LxCFBAR register **************/
+
+#define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /*!< Color Frame Buffer Start Address */
+
+/******************** Bit definition for LTDC_LxCFBLR register **************/
+
+#define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) /*!< Color Frame Buffer Line Length */
+#define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) /*!< Color Frame Buffer Pitch in bytes */
+
+/******************** Bit definition for LTDC_LxCFBLNR register *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) /*!< Frame Buffer Line Number */
+
+/******************** Bit definition for LTDC_LxCLUTWR register *************/
+
+#define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) /*!< Blue value */
+#define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) /*!< Green value */
+#define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /*!< Red value */
+#define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /*!< CLUT address */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define PWR_CR_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */
+#define PWR_CR_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */
+#define PWR_CR_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */
+#define PWR_CR_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define PWR_CR_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+#define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
+#define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
+#define PWR_CSR_WUPP ((uint32_t)0x00000080) /*!< WKUP pin Polarity */
+#define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
+#define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
+#define PWR_CSR_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */
+#define PWR_CSR_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */
+#define PWR_CSR_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* QUADSPI */
+/* */
+/******************************************************************************/
+/***************** Bit definition for QUADSPI_CR register *******************/
+#define QUADSPI_CR_EN ((uint32_t)0x00000001) /*!< Enable */
+#define QUADSPI_CR_ABORT ((uint32_t)0x00000002) /*!< Abort request */
+#define QUADSPI_CR_DMAEN ((uint32_t)0x00000004) /*!< DMA Enable */
+#define QUADSPI_CR_TCEN ((uint32_t)0x00000008) /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010) /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM ((uint32_t)0x00000040) /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL ((uint32_t)0x00000080) /*!< Flash Select */
+#define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00) /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define QUADSPI_CR_FTHRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define QUADSPI_CR_FTHRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define QUADSPI_CR_FTHRES_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define QUADSPI_CR_TEIE ((uint32_t)0x00010000) /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE ((uint32_t)0x00020000) /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE ((uint32_t)0x00040000) /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE ((uint32_t)0x00080000) /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE ((uint32_t)0x00100000) /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS ((uint32_t)0x00400000) /*!< Bit 1 */
+#define QUADSPI_CR_PMM ((uint32_t)0x00800000) /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000) /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define QUADSPI_CR_PRESCALER_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define QUADSPI_CR_PRESCALER_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define QUADSPI_CR_PRESCALER_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define QUADSPI_CR_PRESCALER_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define QUADSPI_CR_PRESCALER_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define QUADSPI_CR_PRESCALER_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define QUADSPI_CR_PRESCALER_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/***************** Bit definition for QUADSPI_DCR register ******************/
+#define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001) /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT ((uint32_t)0x00000700) /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000) /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define QUADSPI_DCR_FSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define QUADSPI_DCR_FSIZE_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define QUADSPI_DCR_FSIZE_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define QUADSPI_DCR_FSIZE_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+
+/****************** Bit definition for QUADSPI_SR register *******************/
+#define QUADSPI_SR_TEF ((uint32_t)0x00000001) /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF ((uint32_t)0x00000002) /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF ((uint32_t)0x00000004) /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF ((uint32_t)0x00000008) /*!< Status Match Flag */
+#define QUADSPI_SR_TOF ((uint32_t)0x00000010) /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY ((uint32_t)0x00000020) /*!< Busy */
+#define QUADSPI_SR_FLEVEL ((uint32_t)0x00003F00) /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define QUADSPI_SR_FLEVEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define QUADSPI_SR_FLEVEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define QUADSPI_SR_FLEVEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define QUADSPI_SR_FLEVEL_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define QUADSPI_SR_FLEVEL_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+
+/****************** Bit definition for QUADSPI_FCR register ******************/
+#define QUADSPI_FCR_CTEF ((uint32_t)0x00000001) /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF ((uint32_t)0x00000002) /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF ((uint32_t)0x00000008) /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF ((uint32_t)0x00000010) /*!< Clear Timeout Flag */
+
+/****************** Bit definition for QUADSPI_DLR register ******************/
+#define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFF) /*!< DL[31:0]: Data Length */
+
+/****************** Bit definition for QUADSPI_CCR register ******************/
+#define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define QUADSPI_CCR_INSTRUCTION_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define QUADSPI_CCR_INSTRUCTION_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define QUADSPI_CCR_INSTRUCTION_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define QUADSPI_CCR_INSTRUCTION_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define QUADSPI_CCR_INSTRUCTION_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define QUADSPI_CCR_INSTRUCTION_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define QUADSPI_CCR_INSTRUCTION_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define QUADSPI_CCR_IMODE ((uint32_t)0x00000300) /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00) /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000) /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000) /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000) /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000) /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define QUADSPI_CCR_DCYC_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define QUADSPI_CCR_DCYC_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define QUADSPI_CCR_DCYC_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+#define QUADSPI_CCR_DCYC_4 ((uint32_t)0x00400000) /*!< Bit 4 */
+#define QUADSPI_CCR_DMODE ((uint32_t)0x03000000) /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000) /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define QUADSPI_CCR_SIOO ((uint32_t)0x10000000) /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC ((uint32_t)0x40000000) /*!< DHHC: Delay Half Hclk Cycle */
+#define QUADSPI_CCR_DDRM ((uint32_t)0x80000000) /*!< DDRM: Double Data Rate Mode */
+/****************** Bit definition for QUADSPI_AR register *******************/
+#define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< ADDRESS[31:0]: Address */
+
+/****************** Bit definition for QUADSPI_ABR register ******************/
+#define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/****************** Bit definition for QUADSPI_DR register *******************/
+#define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFF) /*!< DATA[31:0]: Data */
+
+/****************** Bit definition for QUADSPI_PSMKR register ****************/
+#define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) /*!< MASK[31:0]: Status Mask */
+
+/****************** Bit definition for QUADSPI_PSMAR register ****************/
+#define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) /*!< MATCH[31:0]: Status Match */
+
+/****************** Bit definition for QUADSPI_PIR register *****************/
+#define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFF) /*!< INTERVAL[15:0]: Polling Interval */
+
+/****************** Bit definition for QUADSPI_LPTR register *****************/
+#define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFF) /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001)
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000)
+#define RCC_CR_HSERDY ((uint32_t)0x00020000)
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
+#define RCC_CR_CSSON ((uint32_t)0x00080000)
+#define RCC_CR_PLLON ((uint32_t)0x01000000)
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
+#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
+#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
+#define RCC_CR_PLLSAION ((uint32_t)0x10000000)
+#define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
+#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
+#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
+#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
+#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
+#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
+#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
+
+#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
+#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
+#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
+#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
+#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
+#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
+#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
+#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
+#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
+#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
+#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
+#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
+
+#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
+
+#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
+#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
+#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
+#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
+#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
+
+#define RCC_PLLCFGR_PLLR ((uint32_t)0x70000000)
+#define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x10000000)
+#define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x20000000)
+#define RCC_PLLCFGR_PLLR_2 ((uint32_t)0x40000000)
+
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
+#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
+#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
+#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
+#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
+#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
+#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
+#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
+
+#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
+
+#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
+#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
+#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
+#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
+
+#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
+#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
+#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
+#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
+
+#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
+#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
+#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
+#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
+#define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
+#define RCC_CIR_CSSF ((uint32_t)0x00000080)
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
+#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
+#define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
+#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
+#define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
+#define RCC_CIR_CSSC ((uint32_t)0x00800000)
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
+#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
+#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
+#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
+#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
+#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
+#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
+#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
+#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
+#define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
+#define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
+#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
+#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
+#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
+#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
+#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
+#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
+#define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)
+ /* maintained for legacy purpose */
+#define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
+#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
+#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
+#define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
+#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
+#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
+#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
+#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
+#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
+#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
+#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
+#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
+#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
+#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
+#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
+#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
+#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
+#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
+#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
+#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
+#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
+#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
+#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
+#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
+#define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
+#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
+#define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
+#define RCC_APB2RSTR_DSIRST ((uint32_t)0x08000000)
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
+#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
+#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
+#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
+#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
+#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
+#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
+#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
+#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
+#define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
+#define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
+
+#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
+#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
+#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
+#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
+#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
+#define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)
+
+#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
+#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
+#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
+#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
+#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
+#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
+#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
+#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
+#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
+#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
+#define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
+#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
+#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
+#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
+#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
+#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
+#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
+#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
+#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
+#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
+#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
+#define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
+#define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
+#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
+#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
+#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
+#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
+#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
+#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
+#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
+#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
+#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
+#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
+#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
+#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
+#define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)
+#define RCC_APB2ENR_DSIEN ((uint32_t)0x08000000)
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
+#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
+#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
+#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
+#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
+#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
+#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
+#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
+#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
+#define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
+#define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
+
+#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
+#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
+#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
+#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
+#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
+#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
+#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
+#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
+#define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
+
+#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
+#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
+#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
+#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
+#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
+#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
+#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
+#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
+#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
+#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
+#define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002)
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
+#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
+#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
+#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
+#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
+#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
+#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
+#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
+#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
+#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
+#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
+#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
+#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
+#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
+#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
+#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
+#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
+#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
+#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
+#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
+#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
+#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
+#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
+#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
+#define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
+#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
+#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
+#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
+#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
+#define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
+#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
+#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
+#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
+#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
+#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
+#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
+#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
+#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
+#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
+#define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
+#define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
+#define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)
+#define RCC_APB2LPENR_DSILPEN ((uint32_t)0x08000000)
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
+#define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001)
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
+#define RCC_CSR_RMVF ((uint32_t)0x01000000)
+#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
+#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
+#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
+#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
+#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
+#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
+#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
+#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
+#define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
+#define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
+#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
+#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
+#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
+#define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
+#define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
+
+#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
+
+
+/******************** Bit definition for RCC_PLLSAICFGR register ************/
+#define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
+#define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
+#define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
+#define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
+#define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
+#define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
+#define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
+#define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
+#define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
+#define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)
+#define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)
+#define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)
+
+#define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
+#define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
+#define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)
+#define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
+#define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
+
+#define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)
+#define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)
+#define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)
+#define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)
+#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
+#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
+#define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
+#define RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000)
+#define RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000)
+#define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
+#define RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000)
+#define RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000)
+#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
+#define RCC_DCKCFGR_CK48MSEL ((uint32_t)0x08000000)
+#define RCC_DCKCFGR_SDIOSEL ((uint32_t)0x10000000)
+#define RCC_DCKCFGR_DSISEL ((uint32_t)0x20000000)
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN ((uint32_t)0x00000004)
+#define RNG_CR_IE ((uint32_t)0x00000008)
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY ((uint32_t)0x00000001)
+#define RNG_SR_CECS ((uint32_t)0x00000002)
+#define RNG_SR_SECS ((uint32_t)0x00000004)
+#define RNG_SR_CEIS ((uint32_t)0x00000020)
+#define RNG_SR_SEIS ((uint32_t)0x00000040)
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_DCE ((uint32_t)0x00000080)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
+#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
+#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+#define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+#define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */
+#define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+#define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+
+#define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */
+#define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */
+
+#define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */
+#define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */
+#define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */
+#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
+#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
+
+#define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+#define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */
+#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+
+#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
+#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */
+#define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */
+
+#define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+#define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */
+#define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */
+#define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */
+#define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */
+
+#define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */
+
+#define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+#define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */
+#define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */
+#define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+
+#define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */
+#define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+#define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */
+#define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */
+#define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+
+#define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+#define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */
+
+/******************* Bit definition for SAI_xIMR register *******************/
+#define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */
+#define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */
+#define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */
+#define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */
+#define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */
+#define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */
+#define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */
+
+/******************** Bit definition for SAI_xSR register *******************/
+#define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */
+#define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */
+#define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */
+#define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */
+#define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */
+#define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */
+#define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */
+
+#define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
+#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
+#define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */
+#define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */
+#define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */
+#define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */
+#define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */
+#define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */
+
+/****************** Bit definition for SAI_xDR register ******************/
+#define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
+
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
+#define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+#define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x00001000) /*!<Asynchronous start enable */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
+#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
+#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
+
+#define SYSCFG_MEMRMP_UFB_MODE ((uint32_t)0x00000100) /*!< User Flash Bank mode */
+#define SYSCFG_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC memory mapping swap */
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
+
+#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /*!<PK[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /*!<PK[1] pin */
+
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /*!<PK[2] pin */
+
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /*!<PK[3] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /*!<PK[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /*!<PK[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /*!<PK[6] pin */
+
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /*!<PK[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /*!<PJ[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /*!<PJ[9] pin */
+
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /*!<PJ[10] pin */
+
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /*!<PJ[11] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /*!<PJ[12] pin */
+
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /*!<PJ[13] pin */
+
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /*!<PJ[14] pin */
+
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /*!<PJ[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
+
+#define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
+#define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
+#define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
+#define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
+#define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
+#define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
+#define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
+#define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
+#define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
+#define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
+#define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
+#define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
+#define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
+#define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
+#define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
+#define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
+
+#define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
+
+/******************************************************************************/
+/* */
+/* Ethernet MAC Registers bits definitions */
+/* */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
+#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
+#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
+ #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
+ #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
+ #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
+ #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
+ #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
+ #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
+ #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
+#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
+#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
+#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
+#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
+#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
+#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+ #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
+ #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
+ #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
+ #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
+#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
+#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
+#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
+#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
+#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
+#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
+#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
+ #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
+ #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
+#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
+#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
+#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
+#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
+#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
+ #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+ #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+ #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+ #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+ #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
+#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
+#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
+ #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
+ #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
+ #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
+ #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
+#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
+#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
+#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
+#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
+#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
+#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
+#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+ #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
+#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
+#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
+ #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
+#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
+#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
+ #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
+#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
+#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
+#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
+#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
+#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
+#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
+#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
+ #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+ #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+ #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+ #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
+#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
+ #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+ #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+ #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+ #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
+#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
+#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
+#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
+#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+ #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
+ #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
+ #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
+ #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
+ #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
+ #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
+ #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
+ #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
+ #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
+ #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
+ #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
+ #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
+ #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
+ #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
+ #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
+#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
+#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
+#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
+#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
+#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
+#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
+#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
+#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
+#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
+#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
+#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
+#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
+ #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+ #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+ #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+ #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+ #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+ #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+ #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+ #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
+#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
+ #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
+ #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
+ #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
+ #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
+#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008) /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010) /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020) /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040) /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080) /*!< B-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN ((uint32_t)0x00001000) /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER ((uint32_t)0x00100000) /*!< OTG version */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
+#define USB_OTG_GOTGINT_IDCHNG ((uint32_t)0x00100000) /*!< Change in ID pin input value */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_RSTDET ((uint32_t)0x00800000) /*!< Reset detected interrupt */
+#define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000) /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_RSTDEM ((uint32_t)0x00800000) /*!< Reset detected interrupt mask */
+#define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000) /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
+#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
+
+#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
+#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
+#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+
+#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
+#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
+#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
+
+#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
+#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
+#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+
+#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
+#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
+#define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /*!< USB VBUS Detection Enable */
+
+/******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
+#define USB_OTG_GPWRDN_ADPMEN ((uint32_t)0x00000001) /*!< ADP module enable */
+#define USB_OTG_GPWRDN_ADPIF ((uint32_t)0x00800000) /*!< ADP Interrupt flag */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
+#define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001) /*!< LPM support enable */
+#define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002) /*!< LPM Token acknowledge enable */
+#define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003C) /*!< BESL value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040) /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080) /*!< L1 shallow sleep enable */
+#define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00) /*!< BESL threshold */
+#define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000) /*!< L1 deep sleep enable */
+#define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000) /*!< LPM response */
+#define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000) /*!< Port sleep status */
+#define USB_OTG_GLPMCFG_L1RSMOK ((uint32_t)0x00010000) /*!< Sleep State Resume OK */
+#define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000) /*!< LPM Channel Index */
+#define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000) /*!< LPM retry count */
+#define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000) /*!< Send LPM transaction */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /*!< LPM retry count status */
+#define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /*!< Enable best effort service latency */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
+#define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
+#define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI) || \
+ ((INSTANCE) == GPIOJ) || \
+ ((INSTANCE) == GPIOK))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+ ((PERIPH) == SAI1_Block_B))
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6))
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** QSPI Instances ********************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 6 /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 8 /* Including EP0 */
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 8 /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F479xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/include/devices/stm32f4xx.h b/f4/include/devices/stm32f4xx.h
index 8ab7163..c747b5c 100755
--- a/f4/include/devices/stm32f4xx.h
+++ b/f4/include/devices/stm32f4xx.h
@@ -2,9 +2,9 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 15-December-2014
- * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ * @version V2.4.1
+ * @date 09-October-2015
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -76,7 +76,9 @@
*/
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
- !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE)
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@@ -89,7 +91,16 @@
STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
- /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -105,17 +116,17 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.2.0
+ * @brief CMSIS Device version number V2.4.1
*/
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
|(__STM32F4xx_CMSIS_DEVICE_VERSION))
-
+
/**
* @}
*/
@@ -144,8 +155,20 @@
#include "stm32f401xc.h"
#elif defined(STM32F401xE)
#include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+ #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+ #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+ #include "stm32f410rx.h"
#elif defined(STM32F411xE)
#include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+ #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+ #include "stm32f479xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif
diff --git a/f4/include/devices/system_stm32f4xx.h b/f4/include/devices/system_stm32f4xx.h
index d0cc157..cdad85a 100755
--- a/f4/include/devices/system_stm32f4xx.h
+++ b/f4/include/devices/system_stm32f4xx.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 15-December-2014
+ * @version V2.4.1
+ * @date 09-October-2015
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
diff --git a/f4/include/stm32f4xx_hal.h b/f4/include/stm32f4xx_hal.h
index 022ea2b..58348c1 100755
--- a/f4/include/stm32f4xx_hal.h
+++ b/f4/include/stm32f4xx_hal.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_hal.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -134,7 +134,8 @@
}while(0);
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
*/
#define __HAL_SYSCFG_REMAPMEMORY_FMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
@@ -146,7 +147,37 @@
#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\
}while(0);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
+ * @{
+ */
+/** @brief SYSCFG Break Lockup lock
+ * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input
+ * @note The selected configuration is locked and can be unlocked by system reset
+ */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
+ SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
+ }while(0)
+/**
+ * @}
+ */
+
+/** @defgroup PVD_Lock_Enable PVD Lock
+ * @{
+ */
+/** @brief SYSCFG Break PVD lock
+ * Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
+ * @note The selected configuration is locked and can be unlocked by system reset
+ */
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
+ SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
+ }while(0)
+/**
+ * @}
+ */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
/**
* @}
*/
@@ -188,10 +219,11 @@ void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void);
void HAL_EnableCompensationCell(void);
void HAL_DisableCompensationCell(void);
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
void HAL_EnableMemorySwappingBank(void);
void HAL_DisableMemorySwappingBank(void);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
diff --git a/f4/include/stm32f4xx_hal_adc.h b/f4/include/stm32f4xx_hal_adc.h
index edbb60a..6e3b2b8 100755
--- a/f4/include/stm32f4xx_hal_adc.h
+++ b/f4/include/stm32f4xx_hal_adc.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_adc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
- * @brief Header file of ADC HAL extension module.
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief Header file containing functions prototypes of ADC HAL library.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -97,7 +97,11 @@ typedef struct
This parameter can be set to ENABLE or DISABLE */
uint32_t EOCSelection; /*!< Specifies whether the EOC flag is set
at the end of single channel conversion or at the end of all conversions.
- This parameter can be a value of @ref ADC_EOCSelection */
+ This parameter can be a value of @ref ADC_EOCSelection
+ Note: Impact on overrun when not using DMA: When EOCSelection is set to ADC_EOC_SINGLE_CONV,
+ overrun detection is automatically enabled, in this case each conversion data must be read.
+ To perform ADC conversions without having to read all conversion data, this parameter must
+ be set to ADC_EOC_SEQ_CONV */
uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests is performed in Continuous or in Single mode.
@@ -111,10 +115,14 @@ typedef struct
uint32_t NbrOfDiscConversion; /*!< Specifies the number of ADC discontinuous conversions that will be done
using the sequencer for regular channel group.
This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
- uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger of a regular group.
- This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
- uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion of a regular group.
- This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
+ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
+ If set to ADC_SOFTWARE_START, external triggers are disabled.
+ This parameter can be a value of @ref ADC_External_trigger_Source_Regular
+ Note: This parameter can be modified only if there is no conversion is ongoing. */
+ uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
+ If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
+ This parameter can be a value of @ref ADC_External_trigger_edge_Regular
+ Note: This parameter can be modified only if there is no conversion is ongoing. */
}ADC_InitTypeDef;
/**
@@ -193,10 +201,10 @@ typedef struct
/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
* @{
*/
-#define ADC_CLOCKPRESCALER_PCLK_DIV2 ((uint32_t)0x00000000)
-#define ADC_CLOCKPRESCALER_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
-#define ADC_CLOCKPRESCALER_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
-#define ADC_CLOCKPRESCALER_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
+#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000)
+#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
+#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
+#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
/**
* @}
*/
@@ -248,7 +256,9 @@ typedef struct
/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
* @{
- */
+ */
+/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
+/* compatibility with other STM32 devices. */
#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000)
#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
@@ -265,6 +275,7 @@ typedef struct
#define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
#define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
+#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1)
/**
* @}
*/
@@ -439,7 +450,7 @@ typedef struct
* @param __INTERRUPT__: specifies the ADC interrupt source to check.
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Clear the ADC's pending flags.
@@ -538,7 +549,14 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/** @defgroup ADC_Private_Constants ADC Private Constants
* @{
*/
-
+/* Delay for ADC stabilization time. */
+/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
+/* Unit: us */
+#define ADC_STAB_DELAY_US ((uint32_t) 3)
+/* Delay for temperature sensor stabilization time. */
+/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
+/* Unit: us */
+#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
/**
* @}
*/
@@ -547,10 +565,10 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/** @defgroup ADC_Private_Macros ADC Private Macros
* @{
*/
-#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV2) || \
- ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV4) || \
- ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV6) || \
- ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV8))
+#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8))
#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
@@ -590,28 +608,10 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11))
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \
+ ((REGTRIG) == ADC_SOFTWARE_START))
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
((ALIGN) == ADC_DATAALIGN_LEFT))
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
- ((CHANNEL) == ADC_CHANNEL_1) || \
- ((CHANNEL) == ADC_CHANNEL_2) || \
- ((CHANNEL) == ADC_CHANNEL_3) || \
- ((CHANNEL) == ADC_CHANNEL_4) || \
- ((CHANNEL) == ADC_CHANNEL_5) || \
- ((CHANNEL) == ADC_CHANNEL_6) || \
- ((CHANNEL) == ADC_CHANNEL_7) || \
- ((CHANNEL) == ADC_CHANNEL_8) || \
- ((CHANNEL) == ADC_CHANNEL_9) || \
- ((CHANNEL) == ADC_CHANNEL_10) || \
- ((CHANNEL) == ADC_CHANNEL_11) || \
- ((CHANNEL) == ADC_CHANNEL_12) || \
- ((CHANNEL) == ADC_CHANNEL_13) || \
- ((CHANNEL) == ADC_CHANNEL_14) || \
- ((CHANNEL) == ADC_CHANNEL_15) || \
- ((CHANNEL) == ADC_CHANNEL_16) || \
- ((CHANNEL) == ADC_CHANNEL_17) || \
- ((CHANNEL) == ADC_CHANNEL_18))
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \
((TIME) == ADC_SAMPLETIME_15CYCLES) || \
((TIME) == ADC_SAMPLETIME_28CYCLES) || \
@@ -705,7 +705,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
* @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
* @retval None
*/
-#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << 13)
+#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
/**
* @brief Enable ADC scan mode.
diff --git a/f4/include/stm32f4xx_hal_adc_ex.h b/f4/include/stm32f4xx_hal_adc_ex.h
index ed85869..8ffa409 100755
--- a/f4/include/stm32f4xx_hal_adc_ex.h
+++ b/f4/include/stm32f4xx_hal_adc_ex.h
@@ -1,14 +1,14 @@
/**
******************************************************************************
- * @file stm32f4xx_hal_adc.h
+ * @file stm32f4xx_hal_adc_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -168,6 +168,7 @@ typedef struct
#define ADC_EXTERNALTRIGINJECCONV_T8_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ((uint32_t)ADC_CR2_JEXTSEL)
+#define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1)
/**
* @}
*/
@@ -187,14 +188,16 @@ typedef struct
* @{
*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
+ defined(STM32F410Rx) || defined(STM32F412xG)
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F412xG */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F411xE) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT ((uint32_t)0x10000000) /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F411xE || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
@@ -223,11 +226,11 @@ typedef struct
*/
/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
@@ -260,6 +263,18 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
/** @defgroup ADCEx_Private_Macros ADC Private Macros
* @{
*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412xG)
+#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412xG */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \
+ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
@@ -296,7 +311,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3) || \
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15))
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)|| \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START))
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)4)))
diff --git a/f4/include/stm32f4xx_hal_can.h b/f4/include/stm32f4xx_hal_can.h
index 31a614b..c7c46ac 100755
--- a/f4/include/stm32f4xx_hal_can.h
+++ b/f4/include/stm32f4xx_hal_can.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_can.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,9 @@
extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -180,7 +182,7 @@ typedef struct
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
- uint32_t Data[8]; /*!< Contains the data to be transmitted.
+ uint8_t Data[8]; /*!< Contains the data to be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
}CanTxMsgTypeDef;
@@ -205,7 +207,7 @@ typedef struct
uint32_t DLC; /*!< Specifies the length of the frame that will be received.
This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
- uint32_t Data[8]; /*!< Contains the data to be received.
+ uint8_t Data[8]; /*!< Contains the data to be received.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
@@ -753,7 +755,8 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
diff --git a/f4/include/stm32f4xx_hal_cec.h b/f4/include/stm32f4xx_hal_cec.h
new file mode 100644
index 0000000..634e8d7
--- /dev/null
+++ b/f4/include/stm32f4xx_hal_cec.h
@@ -0,0 +1,681 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_cec.h
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief Header file of CEC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CEC_H
+#define __STM32F4xx_HAL_CEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F446xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CEC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CEC_Exported_Types CEC Exported Types
+ * @{
+ */
+
+/**
+ * @brief CEC Init Structure definition
+ */
+typedef struct
+{
+ uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
+ It can be one of @ref CEC_Signal_Free_Time
+ and belongs to the set {0,...,7} where
+ 0x0 is the default configuration
+ else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
+
+ uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
+ it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
+ or CEC_EXTENDED_TOLERANCE */
+
+ uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
+ CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
+ CEC_RX_STOP_ON_BRE: reception is stopped. */
+
+ uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
+ CEC line upon Bit Rising Error detection.
+ CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
+ CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
+
+ uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
+ CEC line upon Long Bit Period Error detection.
+ CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
+ CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
+
+ uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
+ upon an error detected on a broadcast message.
+
+ It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
+
+ 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
+ a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
+ and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
+ b) LBPE detection: error-bit generation on the CEC line
+ if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
+
+ 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
+ no error-bit generation in case neither a) nor b) are satisfied. Additionally,
+ there is no error-bit generation in case of Short Bit Period Error detection in
+ a broadcast message while LSTN bit is set. */
+
+ uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
+ CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
+ CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
+
+ uint32_t OwnAddress; /*!< Set OAR field, specifies CEC device address within a 15-bit long field */
+
+ uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
+
+ CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
+ own address (OAR). Messages addressed to different destination are ignored.
+ Broadcast messages are always received.
+
+ CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
+ address (OAR) with positive acknowledge. Messages addressed to different destination
+ are received, but without interfering with the CEC bus: no acknowledge sent. */
+
+ uint8_t InitiatorAddress; /* Initiator address (source logical address, sent in each header) */
+
+}CEC_InitTypeDef;
+
+/**
+ * @brief HAL CEC State structures definition
+ */
+typedef enum
+{
+ HAL_CEC_STATE_RESET = 0x00, /*!< Peripheral Reset state */
+ HAL_CEC_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_CEC_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_CEC_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
+ HAL_CEC_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
+ HAL_CEC_STATE_STANDBY_RX = 0x05, /*!< IP ready to receive, doesn't prevent IP to transmit */
+ HAL_CEC_STATE_TIMEOUT = 0x06, /*!< Timeout state */
+ HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */
+}HAL_CEC_StateTypeDef;
+
+/**
+ * @brief CEC handle Structure definition
+ */
+typedef struct
+{
+ CEC_TypeDef *Instance; /* CEC registers base address */
+
+ CEC_InitTypeDef Init; /* CEC communication parameters */
+
+ uint8_t *pTxBuffPtr; /* Pointer to CEC Tx transfer Buffer */
+
+ uint16_t TxXferCount; /* CEC Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /* Pointer to CEC Rx transfer Buffer */
+
+ uint16_t RxXferSize; /* CEC Rx Transfer size, 0: header received only */
+
+ uint32_t ErrorCode; /* For errors handling purposes, copy of ISR register
+ in case error is reported */
+
+ HAL_LockTypeDef Lock; /* Locking object */
+
+ HAL_CEC_StateTypeDef State; /* CEC communication state */
+
+}CEC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CEC_Exported_Constants CEC Exported Constants
+ * @{
+ */
+
+/** @defgroup CEC_Error_Code CEC Error Code
+ * @{
+ */
+#define HAL_CEC_ERROR_NONE (uint32_t) 0x0 /*!< no error */
+#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
+#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
+#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
+#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
+#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
+#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
+#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
+#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
+#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
+ * @{
+ */
+#define CEC_DEFAULT_SFT ((uint32_t)0x00000000)
+#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001)
+#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002)
+#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003)
+#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004)
+#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005)
+#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006)
+#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Tolerance CEC Receiver Tolerance
+ * @{
+ */
+#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000)
+#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
+ * @{
+ */
+#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000)
+#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
+ * @{
+ */
+#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
+#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
+ * @{
+ */
+#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
+#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
+ * @{
+ */
+#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000)
+#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
+ * @{
+ */
+#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000)
+#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Listening_Mode CEC Listening mode option
+ * @{
+ */
+#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000)
+#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
+ * @{
+ */
+#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
+ * @{
+ */
+#define CEC_INITIATOR_LSB_POS ((uint32_t) 4)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
+ * @{
+ */
+#define CEC_IT_TXACKE CEC_IER_TXACKEIE
+#define CEC_IT_TXERR CEC_IER_TXERRIE
+#define CEC_IT_TXUDR CEC_IER_TXUDRIE
+#define CEC_IT_TXEND CEC_IER_TXENDIE
+#define CEC_IT_TXBR CEC_IER_TXBRIE
+#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
+#define CEC_IT_RXACKE CEC_IER_RXACKEIE
+#define CEC_IT_LBPE CEC_IER_LBPEIE
+#define CEC_IT_SBPE CEC_IER_SBPEIE
+#define CEC_IT_BRE CEC_IER_BREIE
+#define CEC_IT_RXOVR CEC_IER_RXOVRIE
+#define CEC_IT_RXEND CEC_IER_RXENDIE
+#define CEC_IT_RXBR CEC_IER_RXBRIE
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Flags_Definitions CEC Flags definition
+ * @{
+ */
+#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
+#define CEC_FLAG_TXERR CEC_ISR_TXERR
+#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
+#define CEC_FLAG_TXEND CEC_ISR_TXEND
+#define CEC_FLAG_TXBR CEC_ISR_TXBR
+#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
+#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
+#define CEC_FLAG_LBPE CEC_ISR_LBPE
+#define CEC_FLAG_SBPE CEC_ISR_SBPE
+#define CEC_FLAG_BRE CEC_ISR_BRE
+#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
+#define CEC_FLAG_RXEND CEC_ISR_RXEND
+#define CEC_FLAG_RXBR CEC_ISR_RXBR
+/**
+ * @}
+ */
+
+/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
+ * @{
+ */
+#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
+ CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
+ * @{
+ */
+#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
+ * @{
+ */
+#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CEC_Exported_Macros CEC Exported Macros
+ * @{
+ */
+
+/** @brief Reset CEC handle state
+ * @param __HANDLE__: CEC handle.
+ * @retval None
+ */
+#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
+
+/** @brief Checks whether or not the specified CEC interrupt flag is set.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __FLAG__: specifies the interrupt to check.
+ * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
+ * @arg CEC_FLAG_TXERR: Tx Error.
+ * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
+ * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
+ * @arg CEC_FLAG_TXBR: Tx-Byte Request.
+ * @arg CEC_FLAG_ARBLST: Arbitration Lost
+ * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
+ * @arg CEC_FLAG_LBPE: Rx Long period Error
+ * @arg CEC_FLAG_SBPE: Rx Short period Error
+ * @arg CEC_FLAG_BRE: Rx Bit Rissing Error
+ * @arg CEC_FLAG_RXOVR: Rx Overrun.
+ * @arg CEC_FLAG_RXEND: End Of Reception.
+ * @arg CEC_FLAG_RXBR: Rx-Byte Received.
+ * @retval ITStatus
+ */
+#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+
+/** @brief Clears the interrupt or status flag when raised (write at 1)
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __FLAG__: specifies the interrupt/status flag to clear.
+ * This parameter can be one of the following values:
+ * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
+ * @arg CEC_FLAG_TXERR: Tx Error.
+ * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
+ * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
+ * @arg CEC_FLAG_TXBR: Tx-Byte Request.
+ * @arg CEC_FLAG_ARBLST: Arbitration Lost
+ * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
+ * @arg CEC_FLAG_LBPE: Rx Long period Error
+ * @arg CEC_FLAG_SBPE: Rx Short period Error
+ * @arg CEC_FLAG_BRE: Rx Bit Rissing Error
+ * @arg CEC_FLAG_RXOVR: Rx Overrun.
+ * @arg CEC_FLAG_RXEND: End Of Reception.
+ * @arg CEC_FLAG_RXBR: Rx-Byte Received.
+ * @retval none
+ */
+#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
+
+/** @brief Enables the specified CEC interrupt.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __INTERRUPT__: specifies the CEC interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @retval none
+ */
+#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/** @brief Disables the specified CEC interrupt.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __INTERRUPT__: specifies the CEC interrupt to disable.
+ * This parameter can be one of the following values:
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @retval none
+ */
+#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
+
+/** @brief Checks whether or not the specified CEC interrupt is enabled.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __INTERRUPT__: specifies the CEC interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
+
+/** @brief Enables the CEC device
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
+
+/** @brief Disables the CEC device
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
+
+/** @brief Set Transmission Start flag
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
+
+/** @brief Set Transmission End flag
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
+ */
+#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
+
+/** @brief Get Transmission Start flag
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
+
+/** @brief Get Transmission End flag
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
+
+/** @brief Clear OAR register
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
+
+/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
+ * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position)
+ * @retval none
+ */
+#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CEC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
+void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
+void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
+HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
+uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec);
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
+void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
+void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
+void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions ************************************************/
+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CEC_Private_Types CEC Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Variables CEC Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Constants CEC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CEC_Private_Macros CEC Private Macros
+ * @{
+ */
+
+#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
+
+#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
+ ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
+
+#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
+ ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
+
+#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
+
+#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
+
+#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
+
+#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
+ ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
+
+#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
+ ((__MODE__) == CEC_FULL_LISTENING_MODE))
+
+/** @brief Check CEC device Own Address Register (OAR) setting.
+ * OAR address is written in a 15-bit field within CEC_CFGR register.
+ * @param __ADDRESS__: CEC own address.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF)
+
+/** @brief Check CEC initiator or destination logical address setting.
+ * Initiator and destination addresses are coded over 4 bits.
+ * @param __ADDRESS__: CEC initiator or logical address.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
+
+/** @brief Check CEC message size.
+ * The message size is the payload size: without counting the header,
+ * it varies from 0 byte (ping operation, one header only, no payload) to
+ * 15 bytes (1 opcode and up to 14 operands following the header).
+ * @param __SIZE__: CEC message size.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Functions CEC Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CEC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/include/stm32f4xx_hal_cortex.h b/f4/include/stm32f4xx_hal_cortex.h
index 0208de3..441a409 100755
--- a/f4/include/stm32f4xx_hal_cortex.h
+++ b/f4/include/stm32f4xx_hal_cortex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_cortex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,6 +54,48 @@
* @{
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+ * @brief MPU Region initialization structure
+ * @{
+ */
+typedef struct
+{
+ uint8_t Enable; /*!< Specifies the status of the region.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
+ uint8_t Number; /*!< Specifies the number of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Number */
+ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
+ uint8_t Size; /*!< Specifies the size of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Size */
+ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint8_t TypeExtField; /*!< Specifies the TEX field level.
+ This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
+ uint8_t AccessPermission; /*!< Specifies the region access permission type.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
+ uint8_t DisableExec; /*!< Specifies the instruction access status.
+ This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
+ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
+ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
+ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
+}MPU_Region_InitTypeDef;
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
@@ -87,6 +129,137 @@
* @}
*/
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
+ * @{
+ */
+#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
+#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
+#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
+#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+ * @{
+ */
+#define MPU_REGION_ENABLE ((uint8_t)0x01)
+#define MPU_REGION_DISABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+ * @{
+ */
+#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
+#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+ * @{
+ */
+#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+ * @{
+ */
+#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+ * @{
+ */
+#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
+ * @{
+ */
+#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
+#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
+#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+ * @{
+ */
+#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
+#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
+#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
+#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
+#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
+#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
+#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+ * @{
+ */
+#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
+#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
+#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
+#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+ * @{
+ */
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
+#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
+#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
+#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
/**
* @}
*/
@@ -140,6 +313,9 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
* @{
*/
/* Peripheral Control functions ***********************************************/
+#if (__MPU_PRESENT == 1)
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
@@ -178,9 +354,123 @@ void HAL_SYSTICK_Callback(void);
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+ ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
+ ((TYPE) == MPU_TEX_LEVEL1) || \
+ ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
+ ((TYPE) == MPU_REGION_PRIV_RW) || \
+ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+ ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+ ((TYPE) == MPU_REGION_PRIV_RO) || \
+ ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
+ ((NUMBER) == MPU_REGION_NUMBER1) || \
+ ((NUMBER) == MPU_REGION_NUMBER2) || \
+ ((NUMBER) == MPU_REGION_NUMBER3) || \
+ ((NUMBER) == MPU_REGION_NUMBER4) || \
+ ((NUMBER) == MPU_REGION_NUMBER5) || \
+ ((NUMBER) == MPU_REGION_NUMBER6) || \
+ ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
+ ((SIZE) == MPU_REGION_SIZE_64B) || \
+ ((SIZE) == MPU_REGION_SIZE_128B) || \
+ ((SIZE) == MPU_REGION_SIZE_256B) || \
+ ((SIZE) == MPU_REGION_SIZE_512B) || \
+ ((SIZE) == MPU_REGION_SIZE_1KB) || \
+ ((SIZE) == MPU_REGION_SIZE_2KB) || \
+ ((SIZE) == MPU_REGION_SIZE_4KB) || \
+ ((SIZE) == MPU_REGION_SIZE_8KB) || \
+ ((SIZE) == MPU_REGION_SIZE_16KB) || \
+ ((SIZE) == MPU_REGION_SIZE_32KB) || \
+ ((SIZE) == MPU_REGION_SIZE_64KB) || \
+ ((SIZE) == MPU_REGION_SIZE_128KB) || \
+ ((SIZE) == MPU_REGION_SIZE_256KB) || \
+ ((SIZE) == MPU_REGION_SIZE_512KB) || \
+ ((SIZE) == MPU_REGION_SIZE_1MB) || \
+ ((SIZE) == MPU_REGION_SIZE_2MB) || \
+ ((SIZE) == MPU_REGION_SIZE_4MB) || \
+ ((SIZE) == MPU_REGION_SIZE_8MB) || \
+ ((SIZE) == MPU_REGION_SIZE_16MB) || \
+ ((SIZE) == MPU_REGION_SIZE_32MB) || \
+ ((SIZE) == MPU_REGION_SIZE_64MB) || \
+ ((SIZE) == MPU_REGION_SIZE_128MB) || \
+ ((SIZE) == MPU_REGION_SIZE_256MB) || \
+ ((SIZE) == MPU_REGION_SIZE_512MB) || \
+ ((SIZE) == MPU_REGION_SIZE_1GB) || \
+ ((SIZE) == MPU_REGION_SIZE_2GB) || \
+ ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
+ * @brief CORTEX private functions
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1)
+/**
+ * @brief Disables the MPU
+ * @retval None
+ */
+__STATIC_INLINE void HAL_MPU_Disable(void)
+{
+ /* Disable fault exceptions */
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
+ /* Disable the MPU */
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/**
+ * @brief Enables the MPU
+ * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
+ * NMI, FAULTMASK and privileged access to the default memory
+ * This parameter can be one of the following values:
+ * @arg MPU_HFNMI_PRIVDEF_NONE
+ * @arg MPU_HARDFAULT_NMI
+ * @arg MPU_PRIVILEGED_DEFAULT
+ * @arg MPU_HFNMI_PRIVDEF
+ * @retval None
+ */
+__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+ /* Enable the MPU */
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+ /* Enable fault exceptions */
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+}
+#endif /* __MPU_PRESENT */
+
/**
* @}
- */
+ */
/**
* @}
diff --git a/f4/include/stm32f4xx_hal_crc.h b/f4/include/stm32f4xx_hal_crc.h
index 1b881f7..1434a0d 100755
--- a/f4/include/stm32f4xx_hal_crc.h
+++ b/f4/include/stm32f4xx_hal_crc.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_crc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -121,7 +121,7 @@ typedef struct
* @param __VALUE__: 8-bit value to be stored in the ID register
* @retval None
*/
-#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__))
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
/**
* @brief Returns the 8-bit data stored in the Independent Data(ID) register.
diff --git a/f4/include/stm32f4xx_hal_cryp.h b/f4/include/stm32f4xx_hal_cryp.h
index c164c67..d61fe1b 100755
--- a/f4/include/stm32f4xx_hal_cryp.h
+++ b/f4/include/stm32f4xx_hal_cryp.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_cryp.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,7 @@
extern "C" {
#endif
-#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx)
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -139,6 +139,8 @@ typedef enum
typedef struct
{
+ CRYP_TypeDef *Instance; /*!< CRYP registers base address */
+
CRYP_InitTypeDef Init; /*!< CRYP required parameters */
uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
@@ -263,25 +265,29 @@ typedef struct
/**
* @brief Enable/Disable the CRYP peripheral.
+ * @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#define __HAL_CRYP_ENABLE() (CRYP->CR |= CRYP_CR_CRYPEN)
-#define __HAL_CRYP_DISABLE() (CRYP->CR &= ~CRYP_CR_CRYPEN)
+#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
+#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
/**
* @brief Flush the data FIFO.
+ * @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#define __HAL_CRYP_FIFO_FLUSH() (CRYP->CR |= CRYP_CR_FFLUSH)
+#define __HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
/**
* @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC.
+ * @param __HANDLE__: specifies the CRYP handle.
* @param MODE: The algorithm mode.
* @retval None
*/
-#define __HAL_CRYP_SET_MODE(MODE) CRYP->CR |= (uint32_t)(MODE)
+#define __HAL_CRYP_SET_MODE(__HANDLE__, MODE) ((__HANDLE__)->Instance->CR |= (uint32_t)(MODE))
/** @brief Check whether the specified CRYP flag is set or not.
+ * @param __HANDLE__: specifies the CRYP handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
@@ -295,31 +301,34 @@ typedef struct
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_CRYP_GET_FLAG(__FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01)?(((CRYP->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
- (((CRYP->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
+#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
+ ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
/** @brief Check whether the specified CRYP interrupt is set or not.
+ * @param __HANDLE__: specifies the CRYP handle.
* @param __INTERRUPT__: specifies the interrupt to check.
* This parameter can be one of the following values:
* @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending
* @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_CRYP_GET_IT(__INTERRUPT__) ((CRYP->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Enable the CRYP interrupt.
+ * @param __HANDLE__: specifies the CRYP handle.
* @param __INTERRUPT__: CRYP Interrupt.
* @retval None
*/
-#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((CRYP->IMSCR) |= (__INTERRUPT__))
+#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
/**
* @brief Disable the CRYP interrupt.
+ * @param __HANDLE__: specifies the CRYP handle.
* @param __INTERRUPT__: CRYP interrupt.
* @retval None
*/
-#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((CRYP->IMSCR) &= ~(__INTERRUPT__))
+#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
/**
* @}
@@ -508,7 +517,7 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
* @}
*/
-#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx || STM32F479xx */
/**
* @}
diff --git a/f4/include/stm32f4xx_hal_cryp_ex.h b/f4/include/stm32f4xx_hal_cryp_ex.h
index f3f5866..dde1357 100755
--- a/f4/include/stm32f4xx_hal_cryp_ex.h
+++ b/f4/include/stm32f4xx_hal_cryp_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_cryp_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of CRYP HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,7 @@
extern "C" {
#endif
-#if defined(STM32F437xx) || defined(STM32F439xx)
+#if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -98,12 +98,13 @@
/**
* @brief Set the phase: Init, header, payload, final.
* This is relevant only for GCM and CCM modes.
+ * @param __HANDLE__: specifies the CRYP handle.
* @param __PHASE__: The phase.
* @retval None
*/
-#define __HAL_CRYP_SET_PHASE(__PHASE__) do{CRYP->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
- CRYP->CR |= (uint32_t)(__PHASE__);\
- }while(0)
+#define __HAL_CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
+ (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
+ }while(0)
/**
* @}
@@ -202,7 +203,7 @@ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);
* @}
*/
-#endif /* STM32F437xx || STM32F439xx */
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
/**
* @}
*/
diff --git a/f4/include/stm32f4xx_hal_dac.h b/f4/include/stm32f4xx_hal_dac.h
index cc7f39b..e0ff166 100755
--- a/f4/include/stm32f4xx_hal_dac.h
+++ b/f4/include/stm32f4xx_hal_dac.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_dac.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,10 @@
extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -208,16 +211,14 @@ typedef struct
* @param __DAC_Channel__: specifies the DAC channel
* @retval None
*/
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
/** @brief Disable the DAC channel
* @param __HANDLE__: specifies the DAC handle
* @param __DAC_Channel__: specifies the DAC channel.
* @retval None
*/
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
/** @brief Enable the DAC interrupt
* @param __HANDLE__: specifies the DAC handle
@@ -233,6 +234,16 @@ typedef struct
*/
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+/** @brief Checks if the specified DAC interrupt source is enabled or disabled.
+ * @param __HANDLE__: DAC handle
+ * @param __INTERRUPT__: DAC interrupt source to check
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+
/** @brief Get the selected DAC's flag status.
* @param __HANDLE__: specifies the DAC handle.
* @param __FLAG__: specifies the flag to clear.
@@ -381,7 +392,9 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
diff --git a/f4/include/stm32f4xx_hal_dac_ex.h b/f4/include/stm32f4xx_hal_dac_ex.h
index b9ded57..06f187d 100755
--- a/f4/include/stm32f4xx_hal_dac_ex.h
+++ b/f4/include/stm32f4xx_hal_dac_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_dac.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,10 @@
extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -61,16 +64,6 @@
/** @defgroup DACEx_Exported_Constants DAC Exported Constants
* @{
*/
-
-/** @defgroup DACEx_wave_generation DAC Wave Generation
- * @{
- */
-#define DAC_WAVEGENERATION_NONE ((uint32_t)0x00000000)
-#define DAC_WAVEGENERATION_NOISE ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVEGENERATION_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
-/**
- * @}
- */
/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude
* @{
@@ -103,18 +96,10 @@
* @}
*/
-/** @defgroup DACEx_wave_Format DAC Wave Format
- * @{
- */
-#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
/**
* @}
*/
-/**
- * @}
- */
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DACEx_Exported_Functions
@@ -156,9 +141,6 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
/** @defgroup DACEx_Private_Macros DAC Private Macros
* @{
*/
-#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WAVEGENERATION_NONE) || \
- ((WAVE) == DAC_WAVEGENERATION_NOISE) || \
- ((WAVE) == DAC_WAVEGENERATION_TRIANGLE))
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
@@ -183,8 +165,6 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || \
- ((WAVE) == DAC_WAVE_TRIANGLE))
/**
* @}
*/
@@ -199,7 +179,9 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
diff --git a/f4/include/stm32f4xx_hal_dcmi.h b/f4/include/stm32f4xx_hal_dcmi.h
index c7c22ed..d095525 100755
--- a/f4/include/stm32f4xx_hal_dcmi.h
+++ b/f4/include/stm32f4xx_hal_dcmi.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_dcmi.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of DCMI HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,10 +43,15 @@
extern "C" {
#endif
-#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+/* Include DCMI HAL Extended module */
+/* (include on top of file since DCMI structures are defined in extended file) */
+#include "stm32f4xx_hal_dcmi_ex.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
@@ -70,46 +75,6 @@ typedef enum
DCMI_OVERRUN = 2, /*!< DCMI Overrun */
}DCMI_ErrorTypeDef;
-/**
- * @brief DCMI Embedded Synchronisation CODE Init structure definition
- */
-typedef struct
-{
- uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
- uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
- uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
- uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
-}DCMI_CodesInitTypeDef;
-
-/**
- * @brief DCMI Init structure definition
- */
-typedef struct
-{
- uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
- This parameter can be a value of @ref DCMI_Synchronization_Mode */
-
- uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
- This parameter can be a value of @ref DCMI_PIXCK_Polarity */
-
- uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
- This parameter can be a value of @ref DCMI_VSYNC_Polarity */
-
- uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
- This parameter can be a value of @ref DCMI_HSYNC_Polarity */
-
- uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
- This parameter can be a value of @ref DCMI_Capture_Rate */
-
- uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
- This parameter can be a value of @ref DCMI_Extended_Data_Mode */
-
- DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the frame start delimiter. */
-
- uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
- This parameter can be a value of @ref DCMI_MODE_JPEG */
-
-}DCMI_InitTypeDef;
/**
* @brief HAL DCMI State structures definition
@@ -531,7 +496,9 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
+ STM32F479xx */
/**
* @}
diff --git a/f4/include/stm32f4xx_hal_dcmi_ex.h b/f4/include/stm32f4xx_hal_dcmi_ex.h
new file mode 100644
index 0000000..877023c
--- /dev/null
+++ b/f4/include/stm32f4xx_hal_dcmi_ex.h
@@ -0,0 +1,223 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dcmi_ex.h
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief Header file of DCMI Extension HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DCMI_EX_H
+#define __STM32F4xx_HAL_DCMI_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DCMIEx
+ * @brief DCMI HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DCMIEx_Exported_Types DCMI Extended Exported Types
+ * @{
+ */
+/**
+ * @brief DCMIEx Embedded Synchronisation CODE Init structure definition
+ */
+typedef struct
+{
+ uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
+ uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
+ uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
+ uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
+}DCMI_CodesInitTypeDef;
+
+/**
+ * @brief DCMI Init structure definition
+ */
+typedef struct
+{
+ uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
+ This parameter can be a value of @ref DCMI_Synchronization_Mode */
+
+ uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
+ This parameter can be a value of @ref DCMI_PIXCK_Polarity */
+
+ uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
+ This parameter can be a value of @ref DCMI_VSYNC_Polarity */
+
+ uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
+ This parameter can be a value of @ref DCMI_HSYNC_Polarity */
+
+ uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
+ This parameter can be a value of @ref DCMI_Capture_Rate */
+
+ uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
+ This parameter can be a value of @ref DCMI_Extended_Data_Mode */
+
+ DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the frame start delimiter. */
+
+ uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
+ This parameter can be a value of @ref DCMI_MODE_JPEG */
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface
+ This parameter can be a value of @ref DCMIEx_Byte_Select_Mode */
+
+ uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd
+ This parameter can be a value of @ref DCMIEx_Byte_Select_Start */
+
+ uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface
+ This parameter can be a value of @ref DCMIEx_Line_Select_Mode */
+
+ uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd
+ This parameter can be a value of @ref DCMIEx_Line_Select_Start */
+
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+}DCMI_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup DCMIEx_Exported_Constants DCMI Exported Constants
+ * @{
+ */
+
+/** @defgroup DCMIEx_Byte_Select_Mode DCMI Byte Select Mode
+ * @{
+ */
+#define DCMI_BSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received data */
+#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */
+#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
+#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMIEx_Byte_Select_Start DCMI Byte Select Start
+ * @{
+ */
+#define DCMI_OEBS_ODD ((uint32_t)0x00000000) /*!< Interface captures first data from the frame/line start, second one being dropped */
+#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMIEx_Line_Select_Mode DCMI Line Select Mode
+ * @{
+ */
+#define DCMI_LSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received lines */
+#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMIEx_Line_Select_Start DCMI Line Select Start
+ * @{
+ */
+#define DCMI_OELS_ODD ((uint32_t)0x00000000) /*!< Interface captures first line from the frame start, second one being dropped */
+#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup DCMIEx_Private_Macros DCMI Extended Private Macros
+ * @{
+ */
+#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \
+ ((MODE) == DCMI_BSM_OTHER) || \
+ ((MODE) == DCMI_BSM_ALTERNATE_4) || \
+ ((MODE) == DCMI_BSM_ALTERNATE_2))
+
+#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
+ ((POLARITY) == DCMI_OEBS_EVEN))
+
+#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
+ ((MODE) == DCMI_LSM_ALTERNATE_2))
+
+#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
+ ((POLARITY) == DCMI_OELS_EVEN))
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+#endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
+ STM32F479xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DCMI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/include/stm32f4xx_hal_def.h b/f4/include/stm32f4xx_hal_def.h
index 038aaf4..e72e7dd 100755
--- a/f4/include/stm32f4xx_hal_def.h
+++ b/f4/include/stm32f4xx_hal_def.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_hal_def.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -47,6 +47,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
#include "Legacy/stm32_hal_legacy.h"
+#include <stdio.h>
/* Exported types ------------------------------------------------------------*/
@@ -71,10 +72,6 @@ typedef enum
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/
-#ifndef NULL
- #define NULL 0
-#endif
-
#define HAL_MAX_DELAY 0xFFFFFFFF
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
diff --git a/f4/include/stm32f4xx_hal_dma.h b/f4/include/stm32f4xx_hal_dma.h
index f97b4a6..a59d8da 100755
--- a/f4/include/stm32f4xx_hal_dma.h
+++ b/f4/include/stm32f4xx_hal_dma.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_dma.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -165,7 +165,11 @@ typedef struct __DMA_HandleTypeDef
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
- __IO uint32_t ErrorCode; /*!< DMA Error code */
+ __IO uint32_t ErrorCode; /*!< DMA Error code */
+
+ uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
+
+ uint32_t StreamIndex; /*!< DMA Stream Index */
}DMA_HandleTypeDef;
/**
@@ -580,7 +584,7 @@ typedef struct __DMA_HandleTypeDef
((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
/**
- * @brief Check whether the specified DMA Stream interrupt has occurred or not.
+ * @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
* @param __HANDLE__: DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
diff --git a/f4/include/stm32f4xx_hal_dma2d.h b/f4/include/stm32f4xx_hal_dma2d.h
index 8012dc9..c9b2eeb 100755
--- a/f4/include/stm32f4xx_hal_dma2d.h
+++ b/f4/include/stm32f4xx_hal_dma2d.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_dma2d.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of DMA2D HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,8 @@
extern "C" {
#endif
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -543,7 +544,7 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
* @}
*/
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#ifdef __cplusplus
}
diff --git a/f4/include/stm32f4xx_hal_dma_ex.h b/f4/include/stm32f4xx_hal_dma_ex.h
index 996282d..08a37cb 100755
--- a/f4/include/stm32f4xx_hal_dma_ex.h
+++ b/f4/include/stm32f4xx_hal_dma_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_dma_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
diff --git a/f4/include/stm32f4xx_hal_dsi.h b/f4/include/stm32f4xx_hal_dsi.h
new file mode 100644
index 0000000..ef1f917
--- /dev/null
+++ b/f4/include/stm32f4xx_hal_dsi.h
@@ -0,0 +1,1242 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dsi.h
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief Header file of DSI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DSI_H
+#define __STM32F4xx_HAL_DSI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DSI DSI
+ * @brief DSI HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/**
+ * @brief DSI Init Structure definition
+ */
+typedef struct
+{
+ uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control
+ This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */
+
+ uint32_t TXEscapeCkdiv; /*!< TX Escape clock division
+ The values 0 and 1 stop the TX_ESC clock generation */
+
+ uint32_t NumberOfLanes; /*!< Number of lanes
+ This parameter can be any value of @ref DSI_Number_Of_Lanes */
+
+}DSI_InitTypeDef;
+
+/**
+ * @brief DSI PLL Clock structure definition
+ */
+typedef struct
+{
+ uint32_t PLLNDIV; /*!< PLL Loop Division Factor
+ This parameter must be a value between 10 and 125 */
+
+ uint32_t PLLIDF; /*!< PLL Input Division Factor
+ This parameter can be any value of @ref DSI_PLL_IDF */
+
+ uint32_t PLLODF; /*!< PLL Output Division Factor
+ This parameter can be any value of @ref DSI_PLL_ODF */
+
+}DSI_PLLInitTypeDef;
+
+/**
+ * @brief DSI Video mode configuration
+ */
+typedef struct
+{
+ uint32_t VirtualChannelID; /*!< Virtual channel ID */
+
+ uint32_t ColorCoding; /*!< Color coding for LTDC interface
+ This parameter can be any value of @ref DSI_Color_Coding */
+
+ uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using
+ 18-bit configuration).
+ This parameter can be any value of @ref DSI_LooselyPacked */
+
+ uint32_t Mode; /*!< Video mode type
+ This parameter can be any value of @ref DSI_Video_Mode_Type */
+
+ uint32_t PacketSize; /*!< Video packet size */
+
+ uint32_t NumberOfChunks; /*!< Number of chunks */
+
+ uint32_t NullPacketSize; /*!< Null packet size */
+
+ uint32_t HSPolarity; /*!< HSYNC pin polarity
+ This parameter can be any value of @ref DSI_HSYNC_Polarity */
+
+ uint32_t VSPolarity; /*!< VSYNC pin polarity
+ This parameter can be any value of @ref DSI_VSYNC_Polarity */
+
+ uint32_t DEPolarity; /*!< Data Enable pin polarity
+ This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
+
+ uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */
+
+ uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */
+
+ uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */
+
+ uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */
+
+ uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */
+
+ uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */
+
+ uint32_t VerticalActive; /*!< Vertical active duration */
+
+ uint32_t LPCommandEnable; /*!< Low-power command enable
+ This parameter can be any value of @ref DSI_LP_Command */
+
+ uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
+ can fit in a line during VSA, VBP and VFP regions */
+
+ uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
+ can fit in a line during VACT region */
+
+ uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable
+ This parameter can be any value of @ref DSI_LP_HFP */
+
+ uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable
+ This parameter can be any value of @ref DSI_LP_HBP */
+
+ uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable
+ This parameter can be any value of @ref DSI_LP_VACT */
+
+ uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable
+ This parameter can be any value of @ref DSI_LP_VFP */
+
+ uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable
+ This parameter can be any value of @ref DSI_LP_VBP */
+
+ uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable
+ This parameter can be any value of @ref DSI_LP_VSYNC */
+
+ uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable
+ This parameter can be any value of @ref DSI_FBTA_acknowledge */
+
+}DSI_VidCfgTypeDef;
+
+/**
+ * @brief DSI Adapted command mode configuration
+ */
+typedef struct
+{
+ uint32_t VirtualChannelID; /*!< Virtual channel ID */
+
+ uint32_t ColorCoding; /*!< Color coding for LTDC interface
+ This parameter can be any value of @ref DSI_Color_Coding */
+
+ uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in
+ pixels. This parameter can be any value between 0x00 and 0xFFFF */
+
+ uint32_t TearingEffectSource; /*!< Tearing effect source
+ This parameter can be any value of @ref DSI_TearingEffectSource */
+
+ uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity
+ This parameter can be any value of @ref DSI_TearingEffectPolarity */
+
+ uint32_t HSPolarity; /*!< HSYNC pin polarity
+ This parameter can be any value of @ref DSI_HSYNC_Polarity */
+
+ uint32_t VSPolarity; /*!< VSYNC pin polarity
+ This parameter can be any value of @ref DSI_VSYNC_Polarity */
+
+ uint32_t DEPolarity; /*!< Data Enable pin polarity
+ This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
+
+ uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted
+ This parameter can be any value of @ref DSI_Vsync_Polarity */
+
+ uint32_t AutomaticRefresh; /*!< Automatic refresh mode
+ This parameter can be any value of @ref DSI_AutomaticRefresh */
+
+ uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable
+ This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
+
+}DSI_CmdCfgTypeDef;
+
+/**
+ * @brief DSI command transmission mode configuration
+ */
+typedef struct
+{
+ uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */
+
+ uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */
+
+ uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */
+
+ uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */
+
+ uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */
+
+ uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */
+
+ uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenLongWrite */
+
+ uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission
+ This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */
+
+ uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission
+ This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */
+
+ uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission
+ This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */
+
+ uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission
+ This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */
+
+ uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission
+ This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */
+
+ uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable
+ This parameter can be any value of @ref DSI_AcknowledgeRequest */
+
+}DSI_LPCmdTypeDef;
+
+/**
+ * @brief DSI PHY Timings definition
+ */
+typedef struct
+{
+ uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
+ to low-power transmission */
+
+ uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power
+ to high-speed transmission */
+
+ uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed
+ to low-power transmission */
+
+ uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power
+ to high-speed transmission */
+
+ uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */
+
+ uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the
+ Stop state */
+
+}DSI_PHY_TimerTypeDef;
+
+/**
+ * @brief DSI HOST Timeouts definition
+ */
+typedef struct
+{
+ uint32_t TimeoutCkdiv; /*!< Time-out clock division */
+
+ uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */
+
+ uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */
+
+ uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */
+
+ uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */
+
+ uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */
+
+ uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode
+ This parameter can be any value of @ref DSI_HS_PrespMode */
+
+ uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */
+
+ uint32_t BTATimeout; /*!< BTA time-out */
+
+}DSI_HOST_TimeoutTypeDef;
+
+/**
+ * @brief DSI States Structure definition
+ */
+typedef enum
+{
+ HAL_DSI_STATE_RESET = 0x00,
+ HAL_DSI_STATE_READY = 0x01,
+ HAL_DSI_STATE_ERROR = 0x02,
+ HAL_DSI_STATE_BUSY = 0x03,
+ HAL_DSI_STATE_TIMEOUT = 0x04
+}HAL_DSI_StateTypeDef;
+
+/**
+ * @brief DSI Handle Structure definition
+ */
+typedef struct
+{
+ DSI_TypeDef *Instance; /*!< Register base address */
+ DSI_InitTypeDef Init; /*!< DSI required parameters */
+ HAL_LockTypeDef Lock; /*!< DSI peripheral status */
+ __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */
+ __IO uint32_t ErrorCode; /*!< DSI Error code */
+ uint32_t ErrorMsk; /*!< DSI Error monitoring mask */
+}DSI_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DSI_DCS_Command DSI DCS Command
+ * @{
+ */
+#define DSI_ENTER_IDLE_MODE 0x39
+#define DSI_ENTER_INVERT_MODE 0x21
+#define DSI_ENTER_NORMAL_MODE 0x13
+#define DSI_ENTER_PARTIAL_MODE 0x12
+#define DSI_ENTER_SLEEP_MODE 0x10
+#define DSI_EXIT_IDLE_MODE 0x38
+#define DSI_EXIT_INVERT_MODE 0x20
+#define DSI_EXIT_SLEEP_MODE 0x11
+#define DSI_GET_3D_CONTROL 0x3F
+#define DSI_GET_ADDRESS_MODE 0x0B
+#define DSI_GET_BLUE_CHANNEL 0x08
+#define DSI_GET_DIAGNOSTIC_RESULT 0x0F
+#define DSI_GET_DISPLAY_MODE 0x0D
+#define DSI_GET_GREEN_CHANNEL 0x07
+#define DSI_GET_PIXEL_FORMAT 0x0C
+#define DSI_GET_POWER_MODE 0x0A
+#define DSI_GET_RED_CHANNEL 0x06
+#define DSI_GET_SCANLINE 0x45
+#define DSI_GET_SIGNAL_MODE 0x0E
+#define DSI_NOP 0x00
+#define DSI_READ_DDB_CONTINUE 0xA8
+#define DSI_READ_DDB_START 0xA1
+#define DSI_READ_MEMORY_CONTINUE 0x3E
+#define DSI_READ_MEMORY_START 0x2E
+#define DSI_SET_3D_CONTROL 0x3D
+#define DSI_SET_ADDRESS_MODE 0x36
+#define DSI_SET_COLUMN_ADDRESS 0x2A
+#define DSI_SET_DISPLAY_OFF 0x28
+#define DSI_SET_DISPLAY_ON 0x29
+#define DSI_SET_GAMMA_CURVE 0x26
+#define DSI_SET_PAGE_ADDRESS 0x2B
+#define DSI_SET_PARTIAL_COLUMNS 0x31
+#define DSI_SET_PARTIAL_ROWS 0x30
+#define DSI_SET_PIXEL_FORMAT 0x3A
+#define DSI_SET_SCROLL_AREA 0x33
+#define DSI_SET_SCROLL_START 0x37
+#define DSI_SET_TEAR_OFF 0x34
+#define DSI_SET_TEAR_ON 0x35
+#define DSI_SET_TEAR_SCANLINE 0x44
+#define DSI_SET_VSYNC_TIMING 0x40
+#define DSI_SOFT_RESET 0x01
+#define DSI_WRITE_LUT 0x2D
+#define DSI_WRITE_MEMORY_CONTINUE 0x3C
+#define DSI_WRITE_MEMORY_START 0x2C
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Video_Mode_Type DSI Video Mode Type
+ * @{
+ */
+#define DSI_VID_MODE_NB_PULSES 0
+#define DSI_VID_MODE_NB_EVENTS 1
+#define DSI_VID_MODE_BURST 2
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Color_Mode DSI Color Mode
+ * @{
+ */
+#define DSI_COLOR_MODE_FULL 0
+#define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
+/**
+ * @}
+ */
+
+/** @defgroup DSI_ShutDown DSI ShutDown
+ * @{
+ */
+#define DSI_DISPLAY_ON 0
+#define DSI_DISPLAY_OFF DSI_WCR_SHTDN
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_Command DSI LP Command
+ * @{
+ */
+#define DSI_LP_COMMAND_DISABLE 0
+#define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_HFP DSI LP HFP
+ * @{
+ */
+#define DSI_LP_HFP_DISABLE 0
+#define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_HBP DSI LP HBP
+ * @{
+ */
+#define DSI_LP_HBP_DISABLE 0
+#define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_VACT DSI LP VACT
+ * @{
+ */
+#define DSI_LP_VACT_DISABLE 0
+#define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_VFP DSI LP VFP
+ * @{
+ */
+#define DSI_LP_VFP_DISABLE 0
+#define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_VBP DSI LP VBP
+ * @{
+ */
+#define DSI_LP_VBP_DISABLE 0
+#define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_VSYNC DSI LP VSYNC
+ * @{
+ */
+#define DSI_LP_VSYNC_DISABLE 0
+#define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge
+ * @{
+ */
+#define DSI_FBTAA_DISABLE 0
+#define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source
+ * @{
+ */
+#define DSI_TE_DSILINK 0
+#define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
+/**
+ * @}
+ */
+
+/** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity
+ * @{
+ */
+#define DSI_TE_RISING_EDGE 0
+#define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity
+ * @{
+ */
+#define DSI_VSYNC_FALLING 0
+#define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
+/**
+ * @}
+ */
+
+/** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh
+ * @{
+ */
+#define DSI_AR_DISABLE 0
+#define DSI_AR_ENABLE DSI_WCFGR_AR
+/**
+ * @}
+ */
+
+/** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request
+ * @{
+ */
+#define DSI_TE_ACKNOWLEDGE_DISABLE 0
+#define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request
+ * @{
+ */
+#define DSI_ACKNOWLEDGE_DISABLE 0
+#define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP
+ * @{
+ */
+#define DSI_LP_GSW0P_DISABLE 0
+#define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP
+ * @{
+ */
+#define DSI_LP_GSW1P_DISABLE 0
+#define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP
+ * @{
+ */
+#define DSI_LP_GSW2P_DISABLE 0
+#define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP
+ * @{
+ */
+#define DSI_LP_GSR0P_DISABLE 0
+#define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP
+ * @{
+ */
+#define DSI_LP_GSR1P_DISABLE 0
+#define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP
+ * @{
+ */
+#define DSI_LP_GSR2P_DISABLE 0
+#define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite
+ * @{
+ */
+#define DSI_LP_GLW_DISABLE 0
+#define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP
+ * @{
+ */
+#define DSI_LP_DSW0P_DISABLE 0
+#define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP
+ * @{
+ */
+#define DSI_LP_DSW1P_DISABLE 0
+#define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP
+ * @{
+ */
+#define DSI_LP_DSR0P_DISABLE 0
+#define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write
+ * @{
+ */
+#define DSI_LP_DLW_DISABLE 0
+#define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet
+ * @{
+ */
+#define DSI_LP_MRDP_DISABLE 0
+#define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
+/**
+ * @}
+ */
+
+/** @defgroup DSI_HS_PrespMode DSI HS Presp Mode
+ * @{
+ */
+#define DSI_HS_PM_DISABLE 0
+#define DSI_HS_PM_ENABLE DSI_TCCR3_PM
+/**
+ * @}
+ */
+
+
+/** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control
+ * @{
+ */
+#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0
+#define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes
+ * @{
+ */
+#define DSI_ONE_DATA_LANE 0
+#define DSI_TWO_DATA_LANES 1
+/**
+ * @}
+ */
+
+/** @defgroup DSI_FlowControl DSI Flow Control
+ * @{
+ */
+#define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
+#define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
+#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
+#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
+#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
+#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
+ DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
+ DSI_FLOW_CONTROL_EOTP_TX)
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Color_Coding DSI Color Coding
+ * @{
+ */
+#define DSI_RGB565 ((uint32_t)0x00000000) /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */
+#define DSI_RGB666 ((uint32_t)0x00000003) /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */
+#define DSI_RGB888 ((uint32_t)0x00000005)
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LooselyPacked DSI Loosely Packed
+ * @{
+ */
+#define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE
+#define DSI_LOOSELY_PACKED_DISABLE 0
+/**
+ * @}
+ */
+
+/** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity
+ * @{
+ */
+#define DSI_HSYNC_ACTIVE_HIGH 0
+#define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP
+/**
+ * @}
+ */
+
+/** @defgroup DSI_VSYNC_Polarity DSI VSYNC Polarity
+ * @{
+ */
+#define DSI_VSYNC_ACTIVE_HIGH 0
+#define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP
+/**
+ * @}
+ */
+
+/** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity
+ * @{
+ */
+#define DSI_DATA_ENABLE_ACTIVE_HIGH 0
+#define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP
+/**
+ * @}
+ */
+
+/** @defgroup DSI_PLL_IDF DSI PLL IDF
+ * @{
+ */
+#define DSI_PLL_IN_DIV1 ((uint32_t)0x00000001)
+#define DSI_PLL_IN_DIV2 ((uint32_t)0x00000002)
+#define DSI_PLL_IN_DIV3 ((uint32_t)0x00000003)
+#define DSI_PLL_IN_DIV4 ((uint32_t)0x00000004)
+#define DSI_PLL_IN_DIV5 ((uint32_t)0x00000005)
+#define DSI_PLL_IN_DIV6 ((uint32_t)0x00000006)
+#define DSI_PLL_IN_DIV7 ((uint32_t)0x00000007)
+/**
+ * @}
+ */
+
+/** @defgroup DSI_PLL_ODF DSI PLL ODF
+ * @{
+ */
+#define DSI_PLL_OUT_DIV1 ((uint32_t)0x00000000)
+#define DSI_PLL_OUT_DIV2 ((uint32_t)0x00000001)
+#define DSI_PLL_OUT_DIV4 ((uint32_t)0x00000002)
+#define DSI_PLL_OUT_DIV8 ((uint32_t)0x00000003)
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Flags DSI Flags
+ * @{
+ */
+#define DSI_FLAG_TE DSI_WISR_TEIF
+#define DSI_FLAG_ER DSI_WISR_ERIF
+#define DSI_FLAG_BUSY DSI_WISR_BUSY
+#define DSI_FLAG_PLLLS DSI_WISR_PLLLS
+#define DSI_FLAG_PLLL DSI_WISR_PLLLIF
+#define DSI_FLAG_PLLU DSI_WISR_PLLUIF
+#define DSI_FLAG_RRS DSI_WISR_RRS
+#define DSI_FLAG_RR DSI_WISR_RRIF
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Interrupts DSI Interrupts
+ * @{
+ */
+#define DSI_IT_TE DSI_WIER_TEIE
+#define DSI_IT_ER DSI_WIER_ERIE
+#define DSI_IT_PLLL DSI_WIER_PLLLIE
+#define DSI_IT_PLLU DSI_WIER_PLLUIE
+#define DSI_IT_RR DSI_WIER_RRIE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type
+ * @{
+ */
+#define DSI_DCS_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000005) /*!< DCS short write, no parameters */
+#define DSI_DCS_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000015) /*!< DCS short write, one parameter */
+#define DSI_GEN_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000003) /*!< Generic short write, no parameters */
+#define DSI_GEN_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000013) /*!< Generic short write, one parameter */
+#define DSI_GEN_SHORT_PKT_WRITE_P2 ((uint32_t)0x00000023) /*!< Generic short write, two parameters */
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type
+ * @{
+ */
+#define DSI_DCS_LONG_PKT_WRITE ((uint32_t)0x00000039) /*!< DCS long write */
+#define DSI_GEN_LONG_PKT_WRITE ((uint32_t)0x00000029) /*!< Generic long write */
+/**
+ * @}
+ */
+
+/** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type
+ * @{
+ */
+#define DSI_DCS_SHORT_PKT_READ ((uint32_t)0x00000006) /*!< DCS short read */
+#define DSI_GEN_SHORT_PKT_READ_P0 ((uint32_t)0x00000004) /*!< Generic short read, no parameters */
+#define DSI_GEN_SHORT_PKT_READ_P1 ((uint32_t)0x00000014) /*!< Generic short read, one parameter */
+#define DSI_GEN_SHORT_PKT_READ_P2 ((uint32_t)0x00000024) /*!< Generic short read, two parameters */
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Error_Data_Type DSI Error Data Type
+ * @{
+ */
+#define HAL_DSI_ERROR_NONE 0
+#define HAL_DSI_ERROR_ACK ((uint32_t)0x00000001) /*!< acknowledge errors */
+#define HAL_DSI_ERROR_PHY ((uint32_t)0x00000002) /*!< PHY related errors */
+#define HAL_DSI_ERROR_TX ((uint32_t)0x00000004) /*!< transmission error */
+#define HAL_DSI_ERROR_RX ((uint32_t)0x00000008) /*!< reception error */
+#define HAL_DSI_ERROR_ECC ((uint32_t)0x00000010) /*!< ECC errors */
+#define HAL_DSI_ERROR_CRC ((uint32_t)0x00000020) /*!< CRC error */
+#define HAL_DSI_ERROR_PSE ((uint32_t)0x00000040) /*!< Packet Size error */
+#define HAL_DSI_ERROR_EOT ((uint32_t)0x00000080) /*!< End Of Transmission error */
+#define HAL_DSI_ERROR_OVF ((uint32_t)0x00000100) /*!< FIFO overflow error */
+#define HAL_DSI_ERROR_GEN ((uint32_t)0x00000200) /*!< Generic FIFO related errors */
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Lane_Group DSI Lane Group
+ * @{
+ */
+#define DSI_CLOCK_LANE ((uint32_t)0x00000000)
+#define DSI_DATA_LANES ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Communication_Delay DSI Communication Delay
+ * @{
+ */
+#define DSI_SLEW_RATE_HSTX ((uint32_t)0x00000000)
+#define DSI_SLEW_RATE_LPTX ((uint32_t)0x00000001)
+#define DSI_HS_DELAY ((uint32_t)0x00000002)
+/**
+ * @}
+ */
+
+/** @defgroup DSI_CustomLane DSI CustomLane
+ * @{
+ */
+#define DSI_SWAP_LANE_PINS ((uint32_t)0x00000000)
+#define DSI_INVERT_HS_SIGNAL ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Lane_Select DSI Lane Select
+ * @{
+ */
+#define DSI_CLOCK_LANE ((uint32_t)0x00000000)
+#define DSI_DATA_LANE0 ((uint32_t)0x00000001)
+#define DSI_DATA_LANE1 ((uint32_t)0x00000002)
+/**
+ * @}
+ */
+
+/** @defgroup DSI_PHY_Timing DSI PHY Timing
+ * @{
+ */
+#define DSI_TCLK_POST ((uint32_t)0x00000000)
+#define DSI_TLPX_CLK ((uint32_t)0x00000001)
+#define DSI_THS_EXIT ((uint32_t)0x00000002)
+#define DSI_TLPX_DATA ((uint32_t)0x00000003)
+#define DSI_THS_ZERO ((uint32_t)0x00000004)
+#define DSI_THS_TRAIL ((uint32_t)0x00000005)
+#define DSI_THS_PREPARE ((uint32_t)0x00000006)
+#define DSI_TCLK_ZERO ((uint32_t)0x00000007)
+#define DSI_TCLK_PREPARE ((uint32_t)0x00000008)
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/**
+ * @brief Enables the DSI host.
+ * @param __HANDLE__: DSI handle
+ * @retval None.
+ */
+#define __HAL_DSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DSI_CR_EN)
+
+/**
+ * @brief Disables the DSI host.
+ * @param __HANDLE__: DSI handle
+ * @retval None.
+ */
+#define __HAL_DSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DSI_CR_EN)
+
+/**
+ * @brief Enables the DSI wrapper.
+ * @param __HANDLE__: DSI handle
+ * @retval None.
+ */
+#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR |= DSI_WCR_DSIEN)
+
+/**
+ * @brief Disable the DSI wrapper.
+ * @param __HANDLE__: DSI handle
+ * @retval None.
+ */
+#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR &= ~DSI_WCR_DSIEN)
+
+/**
+ * @brief Enables the DSI PLL.
+ * @param __HANDLE__: DSI handle
+ * @retval None.
+ */
+#define __HAL_DSI_PLL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_PLLEN)
+
+/**
+ * @brief Disables the DSI PLL.
+ * @param __HANDLE__: DSI handle
+ * @retval None.
+ */
+#define __HAL_DSI_PLL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_PLLEN)
+
+/**
+ * @brief Enables the DSI regulator.
+ * @param __HANDLE__: DSI handle
+ * @retval None.
+ */
+#define __HAL_DSI_REG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_REGEN)
+
+/**
+ * @brief Disables the DSI regulator.
+ * @param __HANDLE__: DSI handle
+ * @retval None.
+ */
+#define __HAL_DSI_REG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_REGEN)
+
+/**
+ * @brief Get the DSI pending flags.
+ * @param __HANDLE__: DSI handle.
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
+ * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
+ * @arg DSI_FLAG_BUSY : Busy Flag
+ * @arg DSI_FLAG_PLLLS: PLL Lock Status
+ * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
+ * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
+ * @arg DSI_FLAG_RRS : Regulator Ready Flag
+ * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))
+
+/**
+ * @brief Clears the DSI pending flags.
+ * @param __HANDLE__: DSI handle.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
+ * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
+ * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
+ * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
+ * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
+ * @retval None
+ */
+#define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))
+
+/**
+ * @brief Enables the specified DSI interrupts.
+ * @param __HANDLE__: DSI handle.
+ * @param __INTERRUPT__: specifies the DSI interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg DSI_IT_TE : Tearing Effect Interrupt
+ * @arg DSI_IT_ER : End of Refresh Interrupt
+ * @arg DSI_IT_PLLL: PLL Lock Interrupt
+ * @arg DSI_IT_PLLU: PLL Unlock Interrupt
+ * @arg DSI_IT_RR : Regulator Ready Interrupt
+ * @retval None
+ */
+#define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified DSI interrupts.
+ * @param __HANDLE__: DSI handle
+ * @param __INTERRUPT__: specifies the DSI interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DSI_IT_TE : Tearing Effect Interrupt
+ * @arg DSI_IT_ER : End of Refresh Interrupt
+ * @arg DSI_IT_PLLL: PLL Lock Interrupt
+ * @arg DSI_IT_PLLU: PLL Unlock Interrupt
+ * @arg DSI_IT_RR : Regulator Ready Interrupt
+ * @retval None
+ */
+#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified DSI interrupt has occurred or not.
+ * @param __HANDLE__: DSI handle
+ * @param __INTERRUPT__: specifies the DSI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DSI_IT_TE : Tearing Effect Interrupt
+ * @arg DSI_IT_ER : End of Refresh Interrupt
+ * @arg DSI_IT_PLLL: PLL Lock Interrupt
+ * @arg DSI_IT_PLLU: PLL Unlock Interrupt
+ * @arg DSI_IT_RR : Regulator Ready Interrupt
+ * @retval The state of INTERRUPT (SET or RESET).
+ */
+#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WISR & (__INTERRUPT__))
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DSI_Exported_Functions DSI Exported Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
+HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
+
+void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
+
+HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
+HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
+HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
+HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd);
+HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
+HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimings);
+HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts);
+HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);
+HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);
+HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
+ uint32_t ChannelID,
+ uint32_t Mode,
+ uint32_t Param1,
+ uint32_t Param2);
+HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
+ uint32_t ChannelID,
+ uint32_t Mode,
+ uint32_t Nbparams,
+ uint32_t Param1,
+ uint8_t* ParametersTable);
+HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
+ uint32_t ChannelNbr,
+ uint8_t* Array,
+ uint32_t Size,
+ uint32_t Mode,
+ uint32_t DCSCmd,
+ uint8_t* ParametersTable);
+HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
+
+HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
+HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
+
+HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value);
+HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
+HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value);
+HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
+
+uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
+HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup DSI_Private_Types DSI Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup DSI_Private_Defines DSI Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DSI_Private_Variables DSI Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DSI_Private_Constants DSI Private Constants
+ * @{
+ */
+#define DSI_MAX_RETURN_PKT_SIZE ((uint32_t)0x00000037) /*!< Maximum return packet configuration */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DSI_Private_Macros DSI Private Macros
+ * @{
+ */
+#define IS_DSI_PLL_NDIV(NDIV) ((10 <= (NDIV)) && ((NDIV) <= 125))
+#define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \
+ ((IDF) == DSI_PLL_IN_DIV2) || \
+ ((IDF) == DSI_PLL_IN_DIV3) || \
+ ((IDF) == DSI_PLL_IN_DIV4) || \
+ ((IDF) == DSI_PLL_IN_DIV5) || \
+ ((IDF) == DSI_PLL_IN_DIV6) || \
+ ((IDF) == DSI_PLL_IN_DIV7))
+#define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \
+ ((ODF) == DSI_PLL_OUT_DIV2) || \
+ ((ODF) == DSI_PLL_OUT_DIV4) || \
+ ((ODF) == DSI_PLL_OUT_DIV8))
+#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
+#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
+#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
+#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5)
+#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
+#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
+#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
+#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
+#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
+ ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
+ ((VideoModeType) == DSI_VID_MODE_BURST))
+#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
+#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
+#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
+#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
+#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
+#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
+#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
+#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
+#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
+#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
+#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
+#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
+#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
+#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
+#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
+#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
+#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
+#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
+#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
+#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
+#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
+#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
+#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
+#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
+#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
+#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
+#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
+#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
+#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
+ ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
+ ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
+ ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \
+ ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
+#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \
+ ((MODE) == DSI_GEN_LONG_PKT_WRITE))
+#define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \
+ ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
+ ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
+ ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
+#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
+#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
+#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
+#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
+#define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \
+ ((Timing) == DSI_TLPX_CLK ) || \
+ ((Timing) == DSI_THS_EXIT ) || \
+ ((Timing) == DSI_TLPX_DATA ) || \
+ ((Timing) == DSI_THS_ZERO ) || \
+ ((Timing) == DSI_THS_TRAIL ) || \
+ ((Timing) == DSI_THS_PREPARE ) || \
+ ((Timing) == DSI_TCLK_ZERO ) || \
+ ((Timing) == DSI_TCLK_PREPARE))
+
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DSI_Private_Functions DSI Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F469xx || STM32F479xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DSI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/include/stm32f4xx_hal_eth.h b/f4/include/stm32f4xx_hal_eth.h
index 19d8e0c..e7f54b3 100755
--- a/f4/include/stm32f4xx_hal_eth.h
+++ b/f4/include/stm32f4xx_hal_eth.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_eth.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of ETH HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,8 @@
extern "C" {
#endif
-#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -65,14 +66,8 @@
((SPEED) == ETH_SPEED_100M))
#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
((MODE) == ETH_MODE_HALFDUPLEX))
-#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
- ((MODE) == ETH_MODE_HALFDUPLEX))
#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
((MODE) == ETH_RXINTERRUPT_MODE))
-#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
- ((MODE) == ETH_RXINTERRUPT_MODE))
-#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
- ((MODE) == ETH_RXINTERRUPT_MODE))
#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
@@ -1258,10 +1253,10 @@ typedef struct
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
-#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
@@ -2211,7 +2206,8 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
+ STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#ifdef __cplusplus
}
diff --git a/f4/include/stm32f4xx_hal_flash.h b/f4/include/stm32f4xx_hal_flash.h
index 90f13d9..50758e4 100755
--- a/f4/include/stm32f4xx_hal_flash.h
+++ b/f4/include/stm32f4xx_hal_flash.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_flash.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -187,12 +187,19 @@ typedef struct
*/
/**
* @brief Set the FLASH Latency.
- * @param __LATENCY__: FLASH Latency
+ * @param __LATENCY__: FLASH Latency
* The value of this parameter depend on device used within the same series
* @retval none
*/
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))
+/**
+ * @brief Get the FLASH Latency.
+ * @retval FLASH Latency
+ * The value of this parameter depend on device used within the same series
+ */
+#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
/**
* @brief Enable the FLASH prefetch buffer.
* @retval none
@@ -234,15 +241,18 @@ typedef struct
* @note This function must be used only when the Instruction Cache is disabled.
* @retval None
*/
-#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() (FLASH->ACR |= FLASH_ACR_ICRST)
+#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST; \
+ FLASH->ACR &= ~FLASH_ACR_ICRST; \
+ }while(0)
/**
* @brief Resets the FLASH data Cache.
* @note This function must be used only when the data Cache is disabled.
* @retval None
*/
-#define __HAL_FLASH_DATA_CACHE_RESET() (FLASH->ACR |= FLASH_ACR_DCRST)
-
+#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST; \
+ FLASH->ACR &= ~FLASH_ACR_DCRST; \
+ }while(0)
/**
* @brief Enable the specified FLASH interrupt.
* @param __INTERRUPT__ : FLASH interrupt
diff --git a/f4/include/stm32f4xx_hal_flash_ex.h b/f4/include/stm32f4xx_hal_flash_ex.h
index b69df38..f9d2d07 100755
--- a/f4/include/stm32f4xx_hal_flash_ex.h
+++ b/f4/include/stm32f4xx_hal_flash_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_flash_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of FLASH HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -111,8 +111,10 @@ typedef struct
/**
* @brief FLASH Advanced Option Bytes Program structure definition
*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
typedef struct
{
uint32_t OptionType; /*!< Option byte to be configured for extension.
@@ -121,12 +123,12 @@ typedef struct
uint32_t PCROPState; /*!< PCROP activation or deactivation.
This parameter can be a value of @ref FLASHEx_PCROP_State */
-#if defined (STM32F401xC) || defined (STM32F401xE) || defined (STM32F411xE)
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
uint16_t Sectors; /*!< specifies the sector(s) set for PCROP.
This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
uint32_t Banks; /*!< Select banks for PCROP activation/deactivation of all sectors.
This parameter must be a value of @ref FLASHEx_Banks */
@@ -139,9 +141,9 @@ typedef struct
uint8_t BootConfig; /*!< Specifies Option bytes for boot config.
This parameter can be a value of @ref FLASHEx_Dual_Boot */
-#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
} FLASH_AdvOBProgramInitTypeDef;
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
@@ -197,8 +199,8 @@ typedef struct
*/
#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
#define OB_RDP_LEVEL_1 ((uint8_t)0x55)
-/*#define OB_RDP_LEVEL_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2
- it s no more possible to go back to level 1 or 0 */
+#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2
+ it s no more possible to go back to level 1 or 0 */
/**
* @}
*/
@@ -243,7 +245,9 @@ typedef struct
*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
/** @defgroup FLASHEx_PCROP_State FLASH PCROP State
* @{
*/
@@ -252,19 +256,22 @@ typedef struct
/**
* @}
*/
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+ STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
/** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type
* @{
*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
#define OPTIONBYTE_PCROP ((uint32_t)0x01) /*!< PCROP option byte configuration */
#define OPTIONBYTE_BOOTCONFIG ((uint32_t)0x02) /*!< BOOTConfig option byte configuration */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
#define OPTIONBYTE_PCROP ((uint32_t)0x01) /*!<PCROP option byte configuration */
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
/**
* @}
*/
@@ -272,8 +279,9 @@ typedef struct
/** @defgroup FLASH_Latency FLASH Latency
* @{
*/
-/*------------------------------------------- STM32F42xxx/STM32F43xxx------------------------------------------*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+/*------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx ----------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
@@ -290,12 +298,14 @@ typedef struct
#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */
#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */
#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
/*--------------------------------------------------------------------------------------------------------------*/
/*-------------------------- STM32F40xxx/STM32F41xxx/STM32F401xx/STM32F411xx -----------------------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
+
#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
@@ -304,7 +314,7 @@ typedef struct
#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx */
/*--------------------------------------------------------------------------------------------------------------*/
/**
@@ -315,16 +325,18 @@ typedef struct
/** @defgroup FLASHEx_Banks FLASH Banks
* @{
*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
#define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */
#define FLASH_BANK_2 ((uint32_t)2) /*!< Bank 2 */
#define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
#define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx */
/**
* @}
*/
@@ -332,14 +344,16 @@ typedef struct
/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
* @{
*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
#define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits here to clear */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER Bit */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx */
/**
* @}
*/
@@ -347,8 +361,9 @@ typedef struct
/** @defgroup FLASHEx_Sectors FLASH Sectors
* @{
*/
-/*------------------------------------------ STM32F42xxx/STM32F43xxx--------------------------------------*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+/*-------------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx ------------------------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */
#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */
#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */
@@ -373,11 +388,11 @@ typedef struct
#define FLASH_SECTOR_21 ((uint32_t)21) /*!< Sector Number 21 */
#define FLASH_SECTOR_22 ((uint32_t)22) /*!< Sector Number 22 */
#define FLASH_SECTOR_23 ((uint32_t)23) /*!< Sector Number 23 */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
/*-----------------------------------------------------------------------------------------------------*/
/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */
#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */
#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */
@@ -390,7 +405,7 @@ typedef struct
#define FLASH_SECTOR_9 ((uint32_t)9) /*!< Sector Number 9 */
#define FLASH_SECTOR_10 ((uint32_t)10) /*!< Sector Number 10 */
#define FLASH_SECTOR_11 ((uint32_t)11) /*!< Sector Number 11 */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
/*-----------------------------------------------------------------------------------------------------*/
/*--------------------------------------------- STM32F401xC -------------------------------------------*/
@@ -404,8 +419,18 @@ typedef struct
#endif /* STM32F401xC */
/*-----------------------------------------------------------------------------------------------------*/
-/*--------------------------------------- STM32F401xE/STM32F411xE -------------------------------------*/
-#if defined(STM32F401xE) || defined(STM32F411xE)
+/*--------------------------------------------- STM32F410xx -------------------------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */
+#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */
+#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */
+#define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */
+#define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */
#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */
#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */
@@ -414,7 +439,7 @@ typedef struct
#define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */
#define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */
#define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */
-#endif /* STM32F401xE || STM32F411xE */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
/*-----------------------------------------------------------------------------------------------------*/
/**
@@ -424,8 +449,9 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
* @{
*/
-/*----------------------------------------- STM32F42xxx/STM32F43xxx-------------------------------------*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+/*--------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx -------------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
@@ -451,11 +477,11 @@ typedef struct
#define OB_WRP_SECTOR_22 ((uint32_t)0x00000400 << 12) /*!< Write protection of Sector22 */
#define OB_WRP_SECTOR_23 ((uint32_t)0x00000800 << 12) /*!< Write protection of Sector23 */
#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF << 12) /*!< Write protection of all Sectors */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
/*-----------------------------------------------------------------------------------------------------*/
/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
@@ -469,7 +495,7 @@ typedef struct
#define OB_WRP_SECTOR_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
#define OB_WRP_SECTOR_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
/*-----------------------------------------------------------------------------------------------------*/
/*--------------------------------------------- STM32F401xC -------------------------------------------*/
@@ -483,9 +509,20 @@ typedef struct
#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
#endif /* STM32F401xC */
/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------------- STM32F410xx -------------------------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
+#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
+#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
+#define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
+#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
+#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*-----------------------------------------------------------------------------------------------------*/
-/*--------------------------------------- STM32F401xE/STM32F411xE -------------------------------------*/
-#if defined(STM32F401xE) || defined(STM32F411xE)
+/*---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
@@ -495,7 +532,7 @@ typedef struct
#define OB_WRP_SECTOR_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
#define OB_WRP_SECTOR_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
-#endif /* STM32F401xE || STM32F411xE */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
/*-----------------------------------------------------------------------------------------------------*/
/**
* @}
@@ -504,8 +541,9 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC ReadWrite Protection
* @{
*/
-/*----------------------------------------- STM32F42xxx/STM32F43xxx-------------------------------------*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+/*-------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx ---------------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */
#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */
#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */
@@ -531,7 +569,7 @@ typedef struct
#define OB_PCROP_SECTOR_22 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22 */
#define OB_PCROP_SECTOR_23 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23 */
#define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
/*-----------------------------------------------------------------------------------------------------*/
/*--------------------------------------------- STM32F401xC -------------------------------------------*/
@@ -546,8 +584,19 @@ typedef struct
#endif /* STM32F401xC */
/*-----------------------------------------------------------------------------------------------------*/
-/*--------------------------------------- STM32F401xE/STM32F411xE -------------------------------------*/
-#if defined(STM32F401xE) || defined(STM32F411xE)
+/*--------------------------------------------- STM32F410xx -------------------------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */
+#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */
+#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */
+#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */
+#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */
+#define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*------------------------------ STM32F401xE/STM32F411xE/STM32F446xx ----------------------*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */
#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */
#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */
@@ -557,7 +606,7 @@ typedef struct
#define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */
#define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */
#define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
-#endif /* STM32F401xE || STM32F411xE */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
/*-----------------------------------------------------------------------------------------------------*/
/**
@@ -567,10 +616,11 @@ typedef struct
/** @defgroup FLASHEx_Dual_Boot FLASH Dual Boot
* @{
*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
#define OB_DUAL_BOOT_ENABLE ((uint8_t)0x10) /*!< Dual Bank Boot Enable */
#define OB_DUAL_BOOT_DISABLE ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
@@ -579,10 +629,13 @@ typedef struct
* @{
*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
#define OB_PCROP_DESELECTED ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
#define OB_PCROP_SELECTED ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+ STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
@@ -608,16 +661,20 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+ STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
@@ -631,32 +688,37 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
/** @defgroup FLASHEx_Private_Constants FLASH Private Constants
* @{
*/
-/*--------------------------------------- STM32F42xxx/STM32F43xxx--------------------------------------*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+/*--------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx---------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define FLASH_SECTOR_TOTAL 24
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
#define FLASH_SECTOR_TOTAL 12
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
/*--------------------------------------------- STM32F401xC -------------------------------------------*/
#if defined(STM32F401xC)
#define FLASH_SECTOR_TOTAL 6
#endif /* STM32F401xC */
-/*--------------------------------------- STM32F401xE/STM32F411xE -------------------------------------*/
-#if defined(STM32F401xE) || defined(STM32F411xE)
+/*--------------------------------------------- STM32F410xx -------------------------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define FLASH_SECTOR_TOTAL 5
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+/*--------------------------------- STM32F401xE/STM32F411xE/STM32F446xx -------------------*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
#define FLASH_SECTOR_TOTAL 8
-#endif /* STM32F401xE || STM32F411xE */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
/**
* @brief OPTCR1 register byte 2 (Bits[23:16]) base address
*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A)
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
/**
* @}
@@ -684,9 +746,9 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
-#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
- ((LEVEL) == OB_RDP_LEVEL_1))/*||\
- ((LEVEL) == OB_RDP_LEVEL_2))*/
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
+ ((LEVEL) == OB_RDP_LEVEL_1) ||\
+ ((LEVEL) == OB_RDP_LEVEL_2))
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
@@ -698,21 +760,27 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
#define IS_PCROPSTATE(VALUE)(((VALUE) == OB_PCROP_STATE_DISABLE) || \
((VALUE) == OB_PCROP_STATE_ENABLE))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+ STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP) || \
((VALUE) == OPTIONBYTE_BOOTCONFIG))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP))
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
((LATENCY) == FLASH_LATENCY_1) || \
((LATENCY) == FLASH_LATENCY_2) || \
@@ -729,10 +797,11 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
((LATENCY) == FLASH_LATENCY_13) || \
((LATENCY) == FLASH_LATENCY_14) || \
((LATENCY) == FLASH_LATENCY_15))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
((LATENCY) == FLASH_LATENCY_1) || \
((LATENCY) == FLASH_LATENCY_2) || \
@@ -741,21 +810,22 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
((LATENCY) == FLASH_LATENCY_5) || \
((LATENCY) == FLASH_LATENCY_6) || \
((LATENCY) == FLASH_LATENCY_7))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
((BANK) == FLASH_BANK_2) || \
((BANK) == FLASH_BANK_BOTH))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
@@ -768,16 +838,16 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\
((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\
((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
#if defined(STM32F401xC)
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
@@ -785,19 +855,25 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5))
#endif /* STM32F401xC */
-#if defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))
-#endif /* STM32F401xE || STM32F411xE */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFF000000) == 0x00000000) && ((SECTOR) != 0x00000000))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
@@ -807,30 +883,42 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
#endif /* STM32F401xC */
-#if defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
-#endif /* STM32F401xE || STM32F411xE */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#if defined(STM32F401xC)
#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
#endif /* STM32F401xC */
-#if defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
-#endif /* STM32F401xE || STM32F411xE */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+ STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
diff --git a/f4/include/stm32f4xx_hal_flash_ramfunc.h b/f4/include/stm32f4xx_hal_flash_ramfunc.h
index af198c9..f6a46cc 100755
--- a/f4/include/stm32f4xx_hal_flash_ramfunc.h
+++ b/f4/include/stm32f4xx_hal_flash_ramfunc.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_flash_ramfunc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -42,8 +42,7 @@
#ifdef __cplusplus
extern "C" {
#endif
-
-#if defined(STM32F411xE)
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -52,18 +51,18 @@
* @{
*/
-/** @addtogroup FLASH_RAMFUNC
+/** @addtogroup FLASHRAMFUNC
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions
+/** @addtogroup FLASHRAMFUNC_Exported_Functions
* @{
*/
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
+/** @addtogroup FLASHRAMFUNC_Exported_Functions_Group1
* @{
*/
__RAM_FUNC HAL_FLASHEx_StopFlashInterfaceClk(void);
@@ -77,7 +76,6 @@ __RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode(void);
/**
* @}
*/
-#endif /* STM32F411xE */
/**
* @}
@@ -86,7 +84,8 @@ __RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode(void);
/**
* @}
*/
-
+
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx */
#ifdef __cplusplus
}
#endif
diff --git a/f4/include/stm32f4xx_hal_fmpi2c.h b/f4/include/stm32f4xx_hal_fmpi2c.h
new file mode 100644
index 0000000..a3ce213
--- /dev/null
+++ b/f4/include/stm32f4xx_hal_fmpi2c.h
@@ -0,0 +1,577 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_fmpi2c.h
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief Header file of FMPI2C HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_FMPI2C_H
+#define __STM32F4xx_HAL_FMPI2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FMPI2C
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FMPI2C_Exported_Types FMPI2C Exported Types
+ * @{
+ */
+
+/**
+ * @brief FMPI2C Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Timing; /*!< Specifies the FMPI2C_TIMINGR_register value.
+ This parameter calculated by referring to FMPI2C initialization
+ section in Reference manual */
+
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+ This parameter can be a value of @ref FMPI2C_addressing_mode */
+
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+ This parameter can be a value of @ref FMPI2C_dual_addressing_mode */
+
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+ This parameter can be a 7-bit address. */
+
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
+ This parameter can be a value of @ref FMPI2C_own_address2_masks */
+
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+ This parameter can be a value of @ref FMPI2C_general_call_addressing_mode */
+
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+ This parameter can be a value of @ref FMPI2C_nostretch_mode */
+
+}FMPI2C_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_FMPI2C_STATE_RESET = 0x00, /*!< FMPI2C not yet initialized or disabled */
+ HAL_FMPI2C_STATE_READY = 0x01, /*!< FMPI2C initialized and ready for use */
+ HAL_FMPI2C_STATE_BUSY = 0x02, /*!< FMPI2C internal process is ongoing */
+ HAL_FMPI2C_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */
+ HAL_FMPI2C_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */
+ HAL_FMPI2C_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */
+ HAL_FMPI2C_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */
+ HAL_FMPI2C_STATE_MEM_BUSY_TX = 0x52, /*!< Memory Data Transmission process is ongoing */
+ HAL_FMPI2C_STATE_MEM_BUSY_RX = 0x62, /*!< Memory Data Reception process is ongoing */
+ HAL_FMPI2C_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_FMPI2C_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+}HAL_FMPI2C_StateTypeDef;
+
+/**
+ * @brief HAL FMPI2C Error Code structure definition
+ */
+typedef enum
+{
+ HAL_FMPI2C_ERROR_NONE = 0x00, /*!< No error */
+ HAL_FMPI2C_ERROR_BERR = 0x01, /*!< BERR error */
+ HAL_FMPI2C_ERROR_ARLO = 0x02, /*!< ARLO error */
+ HAL_FMPI2C_ERROR_AF = 0x04, /*!< ACKF error */
+ HAL_FMPI2C_ERROR_OVR = 0x08, /*!< OVR error */
+ HAL_FMPI2C_ERROR_DMA = 0x10, /*!< DMA transfer error */
+ HAL_FMPI2C_ERROR_TIMEOUT = 0x20, /*!< Timeout error */
+ HAL_FMPI2C_ERROR_SIZE = 0x40 /*!< Size Management error */
+}HAL_FMPI2C_ErrorTypeDef;
+
+/**
+ * @brief FMPI2C handle Structure definition
+ */
+typedef struct
+{
+ FMPI2C_TypeDef *Instance; /*!< FMPI2C registers base address */
+
+ FMPI2C_InitTypeDef Init; /*!< FMPI2C communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to FMPI2C transfer buffer */
+
+ uint16_t XferSize; /*!< FMPI2C transfer size */
+
+ __IO uint16_t XferCount; /*!< FMPI2C transfer counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< FMPI2C Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< FMPI2C Rx DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< FMPI2C locking object */
+
+ __IO HAL_FMPI2C_StateTypeDef State; /*!< FMPI2C communication state */
+
+ __IO HAL_FMPI2C_ErrorTypeDef ErrorCode; /* FMPI2C Error code */
+
+}FMPI2C_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FMPI2C_Exported_Constants FMPI2C Exported Constants
+ * @{
+ */
+
+/** @defgroup FMPI2C_addressing_mode FMPI2C addressing mode
+ * @{
+ */
+#define FMPI2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
+#define FMPI2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_dual_addressing_mode FMPI2C dual addressing mode
+ * @{
+ */
+
+#define FMPI2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
+#define FMPI2C_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_own_address2_masks FMPI2C own address2 masks
+ * @{
+ */
+
+#define FMPI2C_OA2_NOMASK ((uint8_t)0x00)
+#define FMPI2C_OA2_MASK01 ((uint8_t)0x01)
+#define FMPI2C_OA2_MASK02 ((uint8_t)0x02)
+#define FMPI2C_OA2_MASK03 ((uint8_t)0x03)
+#define FMPI2C_OA2_MASK04 ((uint8_t)0x04)
+#define FMPI2C_OA2_MASK05 ((uint8_t)0x05)
+#define FMPI2C_OA2_MASK06 ((uint8_t)0x06)
+#define FMPI2C_OA2_MASK07 ((uint8_t)0x07)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_general_call_addressing_mode FMPI2C general call addressing mode
+ * @{
+ */
+#define FMPI2C_GENERALCALL_DISABLE ((uint32_t)0x00000000)
+#define FMPI2C_GENERALCALL_ENABLE FMPI2C_CR1_GCEN
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_nostretch_mode FMPI2C nostretch mode
+ * @{
+ */
+#define FMPI2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
+#define FMPI2C_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_Memory_Address_Size FMPI2C Memory Address Size
+ * @{
+ */
+#define FMPI2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
+#define FMPI2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_ReloadEndMode_definition FMPI2C ReloadEndMode definition
+ * @{
+ */
+
+#define FMPI2C_RELOAD_MODE FMPI2C_CR2_RELOAD
+#define FMPI2C_AUTOEND_MODE FMPI2C_CR2_AUTOEND
+#define FMPI2C_SOFTEND_MODE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_StartStopMode_definition FMPI2C StartStopMode definition
+ * @{
+ */
+
+#define FMPI2C_NO_STARTSTOP ((uint32_t)0x00000000)
+#define FMPI2C_GENERATE_STOP FMPI2C_CR2_STOP
+#define FMPI2C_GENERATE_START_READ (uint32_t)(FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN)
+#define FMPI2C_GENERATE_START_WRITE FMPI2C_CR2_START
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_Interrupt_configuration_definition FMPI2C Interrupt configuration definition
+ * @brief FMPI2C Interrupt definition
+ * Elements values convention: 0xXXXXXXXX
+ * - XXXXXXXX : Interrupt control mask
+ * @{
+ */
+#define FMPI2C_IT_ERRI FMPI2C_CR1_ERRIE
+#define FMPI2C_IT_TCI FMPI2C_CR1_TCIE
+#define FMPI2C_IT_STOPI FMPI2C_CR1_STOPIE
+#define FMPI2C_IT_NACKI FMPI2C_CR1_NACKIE
+#define FMPI2C_IT_ADDRI FMPI2C_CR1_ADDRIE
+#define FMPI2C_IT_RXI FMPI2C_CR1_RXIE
+#define FMPI2C_IT_TXI FMPI2C_CR1_TXIE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FMPI2C_Flag_definition FMPI2C Flag definition
+ * @{
+ */
+
+#define FMPI2C_FLAG_TXE FMPI2C_ISR_TXE
+#define FMPI2C_FLAG_TXIS FMPI2C_ISR_TXIS
+#define FMPI2C_FLAG_RXNE FMPI2C_ISR_RXNE
+#define FMPI2C_FLAG_ADDR FMPI2C_ISR_ADDR
+#define FMPI2C_FLAG_AF FMPI2C_ISR_NACKF
+#define FMPI2C_FLAG_STOPF FMPI2C_ISR_STOPF
+#define FMPI2C_FLAG_TC FMPI2C_ISR_TC
+#define FMPI2C_FLAG_TCR FMPI2C_ISR_TCR
+#define FMPI2C_FLAG_BERR FMPI2C_ISR_BERR
+#define FMPI2C_FLAG_ARLO FMPI2C_ISR_ARLO
+#define FMPI2C_FLAG_OVR FMPI2C_ISR_OVR
+#define FMPI2C_FLAG_PECERR FMPI2C_ISR_PECERR
+#define FMPI2C_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT
+#define FMPI2C_FLAG_ALERT FMPI2C_ISR_ALERT
+#define FMPI2C_FLAG_BUSY FMPI2C_ISR_BUSY
+#define FMPI2C_FLAG_DIR FMPI2C_ISR_DIR
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FMPI2C_Exported_Macros FMPI2C Exported Macros
+ * @{
+ */
+
+/** @brief Reset FMPI2C handle state
+ * @param __HANDLE__: specifies the FMPI2C Handle.
+ * This parameter can be FMPI2C where x: 1 or 2 to select the FMPI2C peripheral.
+ * @retval None
+ */
+#define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPI2C_STATE_RESET)
+
+/** @brief Enables or disables the specified FMPI2C interrupts.
+ * @param __HANDLE__: specifies the FMPI2C Handle.
+ * This parameter can be FMPI2C where x: 1 or 2 to select the FMPI2C peripheral.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg FMPI2C_IT_ERRI: Errors interrupt enable
+ * @arg FMPI2C_IT_TCI: Transfer complete interrupt enable
+ * @arg FMPI2C_IT_STOPI: STOP detection interrupt enable
+ * @arg FMPI2C_IT_NACKI: NACK received interrupt enable
+ * @arg FMPI2C_IT_ADDRI: Address match interrupt enable
+ * @arg FMPI2C_IT_RXI: RX interrupt enable
+ * @arg FMPI2C_IT_TXI: TX interrupt enable
+ *
+ * @retval None
+ */
+
+#define __HAL_FMPI2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+#define __HAL_FMPI2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief Checks if the specified FMPI2C interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the FMPI2C Handle.
+ * This parameter can be FMPI2C where x: 1 or 2 to select the FMPI2C peripheral.
+ * @param __INTERRUPT__: specifies the FMPI2C interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg FMPI2C_IT_ERRI: Errors interrupt enable
+ * @arg FMPI2C_IT_TCI: Transfer complete interrupt enable
+ * @arg FMPI2C_IT_STOPI: STOP detection interrupt enable
+ * @arg FMPI2C_IT_NACKI: NACK received interrupt enable
+ * @arg FMPI2C_IT_ADDRI: Address match interrupt enable
+ * @arg FMPI2C_IT_RXI: RX interrupt enable
+ * @arg FMPI2C_IT_TXI: TX interrupt enable
+ *
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified FMPI2C flag is set or not.
+ * @param __HANDLE__: specifies the FMPI2C Handle.
+ * This parameter can be FMPI2C where x: 1 or 2 to select the FMPI2C peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg FMPI2C_FLAG_TXE: Transmit data register empty
+ * @arg FMPI2C_FLAG_TXIS: Transmit interrupt status
+ * @arg FMPI2C_FLAG_RXNE: Receive data register not empty
+ * @arg FMPI2C_FLAG_ADDR: Address matched (slave mode)
+ * @arg FMPI2C_FLAG_AF: Acknowledge failure received flag
+ * @arg FMPI2C_FLAG_STOPF: STOP detection flag
+ * @arg FMPI2C_FLAG_TC: Transfer complete (master mode)
+ * @arg FMPI2C_FLAG_TCR: Transfer complete reload
+ * @arg FMPI2C_FLAG_BERR: Bus error
+ * @arg FMPI2C_FLAG_ARLO: Arbitration lost
+ * @arg FMPI2C_FLAG_OVR: Overrun/Underrun
+ * @arg FMPI2C_FLAG_PECERR: PEC error in reception
+ * @arg FMPI2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
+ * @arg FMPI2C_FLAG_ALERT: SMBus alert
+ * @arg FMPI2C_FLAG_BUSY: Bus busy
+ * @arg FMPI2C_FLAG_DIR: Transfer direction (slave mode)
+ *
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == ((__FLAG__) & FMPI2C_FLAG_MASK)))
+
+/** @brief Clears the FMPI2C pending flags which are cleared by writing 1 in a specific bit.
+ * @param __HANDLE__: specifies the FMPI2C Handle.
+ * This parameter can be FMPI2C where x: 1 or 2 to select the FMPI2C peripheral.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FMPI2C_FLAG_ADDR: Address matched (slave mode)
+ * @arg FMPI2C_FLAG_AF: Acknowledge failure received flag
+ * @arg FMPI2C_FLAG_STOPF: STOP detection flag
+ * @arg FMPI2C_FLAG_BERR: Bus error
+ * @arg FMPI2C_FLAG_ARLO: Arbitration lost
+ * @arg FMPI2C_FLAG_OVR: Overrun/Underrun
+ * @arg FMPI2C_FLAG_PECERR: PEC error in reception
+ * @arg FMPI2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
+ * @arg FMPI2C_FLAG_ALERT: SMBus alert
+ *
+ * @retval None
+ */
+#define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ((__FLAG__) & FMPI2C_FLAG_MASK))
+
+
+#define __HAL_FMPI2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= FMPI2C_CR1_PE)
+#define __HAL_FMPI2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~FMPI2C_CR1_PE)
+
+#define __HAL_FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
+
+#define __HAL_FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
+#define __HAL_FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+
+#define __HAL_FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
+
+#define IS_FMPI2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
+#define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
+
+/**
+ * @}
+ */
+
+/* Include FMPI2C HAL Extension module */
+#include "stm32f4xx_hal_fmpi2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FMPI2C_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FMPI2C_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization/de-initialization functions**********************************/
+HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hFMPI2C);
+HAL_StatusTypeDef HAL_FMPI2C_DeInit (FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_MspInit(FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hFMPI2C);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FMPI2C_Exported_Functions_Group2
+ * @{
+ */
+
+/* I/O operation functions ***************************************************/
+ /******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hFMPI2C, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hFMPI2C, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+ /******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hFMPI2C, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hFMPI2C, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+ /******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hFMPI2C, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hFMPI2C, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hFMPI2C, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+ /******* FMPI2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_MasterTxCpltCallback(FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_MasterRxCpltCallback(FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_SlaveTxCpltCallback(FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_SlaveRxCpltCallback(FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_MemTxCpltCallback(FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_MemRxCpltCallback(FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2C_ErrorCallback(FMPI2C_HandleTypeDef *hFMPI2C);
+/**
+ * @}
+ */
+
+/** @addtogroup FMPI2C_Exported_Functions_Group3
+ * @{
+ */
+
+/* Peripheral State functions ************************************************/
+HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hFMPI2C);
+uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hFMPI2C);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FMPI2C_Private_Constants FMPI2C Private Constants
+ * @{
+ */
+#define FMPI2C_FLAG_MASK ((uint32_t)0x0001FFFF)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FMPI2C_Private_Macros FMPI2C Private Macros
+ * @{
+ */
+
+#define IS_FMPI2C_ADDRESSING_MODE(MODE) (((MODE) == FMPI2C_ADDRESSINGMODE_7BIT) || \
+ ((MODE) == FMPI2C_ADDRESSINGMODE_10BIT))
+
+#define IS_FMPI2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPI2C_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == FMPI2C_DUALADDRESS_ENABLE))
+
+#define IS_FMPI2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPI2C_OA2_NOMASK) || \
+ ((MASK) == FMPI2C_OA2_MASK01) || \
+ ((MASK) == FMPI2C_OA2_MASK02) || \
+ ((MASK) == FMPI2C_OA2_MASK03) || \
+ ((MASK) == FMPI2C_OA2_MASK04) || \
+ ((MASK) == FMPI2C_OA2_MASK05) || \
+ ((MASK) == FMPI2C_OA2_MASK06) || \
+ ((MASK) == FMPI2C_OA2_MASK07))
+
+#define IS_FMPI2C_GENERAL_CALL(CALL) (((CALL) == FMPI2C_GENERALCALL_DISABLE) || \
+ ((CALL) == FMPI2C_GENERALCALL_ENABLE))
+
+#define IS_FMPI2C_NO_STRETCH(STRETCH) (((STRETCH) == FMPI2C_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == FMPI2C_NOSTRETCH_ENABLE))
+
+#define IS_FMPI2C_MEMADD_SIZE(SIZE) (((SIZE) == FMPI2C_MEMADD_SIZE_8BIT) || \
+ ((SIZE) == FMPI2C_MEMADD_SIZE_16BIT))
+
+#define IS_TRANSFER_MODE(MODE) (((MODE) == FMPI2C_RELOAD_MODE) || \
+ ((MODE) == FMPI2C_AUTOEND_MODE) || \
+ ((MODE) == FMPI2C_SOFTEND_MODE))
+
+#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPI2C_GENERATE_STOP) || \
+ ((REQUEST) == FMPI2C_GENERATE_START_READ) || \
+ ((REQUEST) == FMPI2C_GENERATE_START_WRITE) || \
+ ((REQUEST) == FMPI2C_NO_STARTSTOP))
+
+/**
+ * @}
+ */
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FMPI2C_Private_Functions FMPI2C Private Functions
+ * @brief FMPI2C private functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F410xx || STM32F446xx */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_FMPI2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/include/stm32f4xx_hal_fmpi2c_ex.h b/f4/include/stm32f4xx_hal_fmpi2c_ex.h
new file mode 100644
index 0000000..8a920b1
--- /dev/null
+++ b/f4/include/stm32f4xx_hal_fmpi2c_ex.h
@@ -0,0 +1,151 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_fmpi2c_ex.h
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief Header file of FMPI2C HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_FMPI2C_EX_H
+#define __STM32F4xx_HAL_FMPI2C_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FMPI2CEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FMPI2CEx_Exported_Constants FMPI2C Exported Constants
+ * @{
+ */
+
+/** @defgroup FMPI2CEx_Analog_Filter FMPI2C Analog Filter
+ * @{
+ */
+#define FMPI2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
+#define FMPI2C_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2CEx_FastModePlus FMPI2C Fast Mode Plus
+ * @{
+ */
+#define FMPI2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /*!< Enable Fast Mode Plus on FMPI2C1 SCL pins */
+#define FMPI2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /*!< Enable Fast Mode Plus on FMPI2C1 SDA pins */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FMPI2CEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FMPI2CEx_Exported_Functions_Group1
+ * @{
+ */
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_FMPI2CEx_AnalogFilter_Config(FMPI2C_HandleTypeDef *hFMPI2C, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_FMPI2CEx_DigitalFilter_Config(FMPI2C_HandleTypeDef *hFMPI2C, uint32_t DigitalFilter);
+HAL_StatusTypeDef HAL_FMPI2CEx_EnableWakeUp (FMPI2C_HandleTypeDef *hFMPI2C);
+HAL_StatusTypeDef HAL_FMPI2CEx_DisableWakeUp (FMPI2C_HandleTypeDef *hFMPI2C);
+void HAL_FMPI2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Constants I2C Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Macros I2C Private Macros
+ * @{
+ */
+#define IS_FMPI2C_ANALOG_FILTER(FILTER) (((FILTER) == FMPI2C_ANALOGFILTER_ENABLE) || \
+ ((FILTER) == FMPI2C_ANALOGFILTER_DISABLE))
+
+#define IS_FMPI2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
+
+#define IS_FMPI2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SCL)) == FMPI2C_FASTMODEPLUS_SCL) || \
+ (((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SDA)) == FMPI2C_FASTMODEPLUS_SDA))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F410xx || STM32F446xx */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_FMPI2C_EX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/include/stm32f4xx_hal_gpio.h b/f4/include/stm32f4xx_hal_gpio.h
index 51b55e0..3fe7c49 100755
--- a/f4/include/stm32f4xx_hal_gpio.h
+++ b/f4/include/stm32f4xx_hal_gpio.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_gpio.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -156,11 +156,11 @@ typedef enum
/** @defgroup GPIO_speed_define GPIO speed define
* @brief GPIO Output Maximum frequency
* @{
- */
-#define GPIO_SPEED_LOW ((uint32_t)0x00000000) /*!< Low speed */
-#define GPIO_SPEED_MEDIUM ((uint32_t)0x00000001) /*!< Medium speed */
-#define GPIO_SPEED_FAST ((uint32_t)0x00000002) /*!< Fast speed */
-#define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */
+ */
+#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000) /*!< IO works at 2 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001) /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002) /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003) /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */
/**
* @}
*/
@@ -293,8 +293,8 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
((MODE) == GPIO_MODE_EVT_FALLING) ||\
((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
((MODE) == GPIO_MODE_ANALOG))
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \
- ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH))
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
+ ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
((PULL) == GPIO_PULLDOWN))
/**
diff --git a/f4/include/stm32f4xx_hal_gpio_ex.h b/f4/include/stm32f4xx_hal_gpio_ex.h
index 15db6c1..e5865b0 100755
--- a/f4/include/stm32f4xx_hal_gpio_ex.h
+++ b/f4/include/stm32f4xx_hal_gpio_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_gpio_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,21 +50,22 @@
* @{
*/
-/** @addtogroup GPIO
+/** @defgroup GPIOEx GPIOEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/** @addtogroup GPIO_Exported_Constants
+/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
* @{
- */
-/*------------------------- STM32F429xx/STM32F439xx---------------------------*/
-#if defined (STM32F429xx) || defined (STM32F439xx)
+ */
+
+/*------------------------------------------ STM32F429xx/STM32F439xx ---------*/
+#if defined(STM32F429xx) || defined(STM32F439xx)
/**
* @brief AF 0 selection
*/
@@ -180,10 +181,10 @@
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#endif /* STM32F429xx || STM32F439xx */
-/*------------------------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------*/
-/*---------------------------------- STM32F427xx/STM32F437xx--------------------------------*/
-#if defined (STM32F427xx) || defined (STM32F437xx)
+/*---------------------------------- STM32F427xx/STM32F437xx------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx)
/**
* @brief AF 0 selection
*/
@@ -295,10 +296,10 @@
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#endif /* STM32F427xx || STM32F437xx */
-/*------------------------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------*/
-/*---------------------------------- STM32F407xx/STM32F417xx--------------------------------*/
-#if defined (STM32F407xx) || defined (STM32F417xx)
+/*---------------------------------- STM32F407xx/STM32F417xx------------------*/
+#if defined(STM32F407xx) || defined(STM32F417xx)
/**
* @brief AF 0 selection
*/
@@ -401,10 +402,10 @@
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#endif /* STM32F407xx || STM32F417xx */
-/*------------------------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------*/
-/*---------------------------------- STM32F405xx/STM32F415xx--------------------------------*/
-#if defined (STM32F405xx) || defined (STM32F415xx)
+/*---------------------------------- STM32F405xx/STM32F415xx------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx)
/**
* @brief AF 0 selection
*/
@@ -498,9 +499,9 @@
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#endif /* STM32F405xx || STM32F415xx */
-/*------------------------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------*/
-/*---------------------------------------- STM32F401xx--------------------------------------*/
+/*---------------------------------------- STM32F401xx------------------------*/
#if defined(STM32F401xC) || defined(STM32F401xE)
/**
* @brief AF 0 selection
@@ -544,7 +545,7 @@
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
-#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
/**
* @brief AF 6 selection
@@ -587,9 +588,8 @@
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#endif /* STM32F401xC || STM32F401xE */
-/*------------------------------------------------------------------------------------------*/
-
-/*---------------------------------------- STM32F411xx--------------------------------------*/
+/*----------------------------------------------------------------------------*/
+/*---------------------------------------- STM32F411xx------------------------*/
#if defined(STM32F411xE)
/**
* @brief AF 0 selection
@@ -639,11 +639,12 @@
/**
* @brief AF 6 selection
*/
-#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */
#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */
#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+
/**
* @brief AF 7 selection
*/
@@ -664,7 +665,6 @@
#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */
#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */
-
/**
* @brief AF 10 selection
*/
@@ -680,6 +680,326 @@
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#endif /* STM32F411xE */
+
+/*---------------------------------------- STM32F410xx------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
+#if defined(STM32F410Cx) || defined(STM32F410Rx)
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#endif /* STM32F410Cx || STM32F410Rx */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */
+#if defined(STM32F410Cx) || defined(STM32F410Rx)
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */
+#endif /* STM32F410Cx || STM32F410Rx */
+#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */
+#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+/*---------------------------------------- STM32F446xx -----------------------*/
+#if defined(STM32F446xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */
+#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping */
+#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */
+#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF7_SPDIFRX ((uint8_t)0x07) /* SPDIFRX Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+#define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /* SPDIFRX Alternate Function mapping */
+#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
+#define GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */
+#define GPIO_AF10_QSPI ((uint8_t)0xA) /* QSPI Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#endif /* STM32F446xx */
+/*----------------------------------------------------------------------------*/
+
+/*-------------------------------- STM32F469xx/STM32F479xx--------------------*/
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
+#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
+#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */
+#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */
+
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
+#define GPIO_AF10_QSPI ((uint8_t)0xA) /* QSPI Alternate Function mapping */
+
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
+#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#endif /* STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
/**
* @}
*/
@@ -689,15 +1009,15 @@
*/
/* Exported macro ------------------------------------------------------------*/
-/** @addtogroup GPIO_Exported_Macros
+/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
* @{
*/
/**
* @}
*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup GPIO_Exported_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
* @{
*/
/**
@@ -707,7 +1027,7 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @addtogroup GPIO_Private_Constants
+/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
* @{
*/
/**
@@ -715,54 +1035,72 @@
*/
/* Private macros ------------------------------------------------------------*/
-/** @addtogroup GPIO_Private_Macros
+/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
* @{
*/
-/** @defgroup GPIO_Get_Port_Index GPIO Get Port Index
+/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
* @{
*/
-#if defined (STM32F405xx) || defined (STM32F415xx) || defined (STM32F407xx) || defined (STM32F417xx)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
- ((__GPIOx__) == (GPIOB))? 1U :\
- ((__GPIOx__) == (GPIOC))? 2U :\
- ((__GPIOx__) == (GPIOD))? 3U :\
- ((__GPIOx__) == (GPIOE))? 4U :\
- ((__GPIOx__) == (GPIOF))? 5U :\
- ((__GPIOx__) == (GPIOG))? 6U :\
- ((__GPIOx__) == (GPIOH))? 7U :\
- ((__GPIOx__) == (GPIOI))? 8U : 9U)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U :\
+ ((__GPIOx__) == (GPIOF))? 5U :\
+ ((__GPIOx__) == (GPIOG))? 6U :\
+ ((__GPIOx__) == (GPIOH))? 7U :\
+ ((__GPIOx__) == (GPIOI))? 8U : 9U)
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-#if defined (STM32F427xx) || defined (STM32F437xx) || defined (STM32F429xx) || defined (STM32F439xx)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
- ((__GPIOx__) == (GPIOB))? 1U :\
- ((__GPIOx__) == (GPIOC))? 2U :\
- ((__GPIOx__) == (GPIOD))? 3U :\
- ((__GPIOx__) == (GPIOE))? 4U :\
- ((__GPIOx__) == (GPIOF))? 5U :\
- ((__GPIOx__) == (GPIOG))? 6U :\
- ((__GPIOx__) == (GPIOH))? 7U :\
- ((__GPIOx__) == (GPIOI))? 8U :\
- ((__GPIOx__) == (GPIOJ))? 9U : 10U)
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-
-#if defined (STM32F401xC) || defined (STM32F401xE) || defined (STM32F411xE)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
- ((__GPIOx__) == (GPIOB))? 1U :\
- ((__GPIOx__) == (GPIOC))? 2U :\
- ((__GPIOx__) == (GPIOD))? 3U :\
- ((__GPIOx__) == (GPIOE))? 4U : 5U)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U :\
+ ((__GPIOx__) == (GPIOF))? 5U :\
+ ((__GPIOx__) == (GPIOG))? 6U :\
+ ((__GPIOx__) == (GPIOH))? 7U :\
+ ((__GPIOx__) == (GPIOI))? 8U :\
+ ((__GPIOx__) == (GPIOJ))? 9U : 10U)
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOH))? 7U : 8U)
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U : 5U)
#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+#if defined(STM32F446xx)
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U :\
+ ((__GPIOx__) == (GPIOF))? 5U :\
+ ((__GPIOx__) == (GPIOG))? 6U : 8U)
+#endif /* STM32F446xx */
+
/**
* @}
*/
-/** @defgroup GPIO_IS_Alternate_function_selection GPIO Check Alternate Function
+/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
* @{
*/
-/*------------------------- STM32F429xx/STM32F439xx---------------------------*/
-#if defined (STM32F429xx) || defined (STM32F439xx)
+/*------------------------- STM32F429xx/STM32F439xx---------------------------*/
+#if defined(STM32F429xx) || defined(STM32F439xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
@@ -787,10 +1125,10 @@
((AF) == GPIO_AF14_LTDC))
#endif /* STM32F429xx || STM32F439xx */
-/*------------------------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------*/
-/*---------------------------------- STM32F427xx/STM32F437xx--------------------------------*/
-#if defined (STM32F427xx) || defined (STM32F437xx)
+/*---------------------------------- STM32F427xx/STM32F437xx------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
@@ -814,10 +1152,10 @@
((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1))
#endif /* STM32F427xx || STM32F437xx */
-/*------------------------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------*/
-/*---------------------------------- STM32F407xx/STM32F417xx--------------------------------*/
-#if defined (STM32F407xx) || defined (STM32F417xx)
+/*---------------------------------- STM32F407xx/STM32F417xx------------------*/
+#if defined(STM32F407xx) || defined(STM32F417xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
@@ -838,10 +1176,10 @@
((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT))
#endif /* STM32F407xx || STM32F417xx */
-/*------------------------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------*/
-/*---------------------------------- STM32F405xx/STM32F415xx--------------------------------*/
-#if defined (STM32F405xx) || defined (STM32F415xx)
+/*---------------------------------- STM32F405xx/STM32F415xx------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
@@ -862,9 +1200,9 @@
#endif /* STM32F405xx || STM32F415xx */
-/*------------------------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------*/
-/*---------------------------------------- STM32F401xx--------------------------------------*/
+/*---------------------------------------- STM32F401xx------------------------*/
#if defined(STM32F401xC) || defined(STM32F401xE)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
@@ -881,9 +1219,13 @@
((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT))
#endif /* STM32F401xC || STM32F401xE */
-/*------------------------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------*/
+/*---------------------------------------- STM32F410xx------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_GPIO_AF(AF) (((AF) < 10) || ((AF) == 15))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-/*---------------------------------------- STM32F411xx--------------------------------------*/
+/*---------------------------------------- STM32F411xx------------------------*/
#if defined(STM32F411xE)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
@@ -902,6 +1244,69 @@
((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT))
#endif /* STM32F411xE */
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------- STM32F446xx ----------------*/
+#if defined(STM32F446xx)
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
+ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \
+ ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \
+ ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF6_SPI2) || \
+ ((AF) == GPIO_AF6_SPI4) || ((AF) == GPIO_AF7_UART5) || \
+ ((AF) == GPIO_AF7_SPI2) || ((AF) == GPIO_AF7_SPI3) || \
+ ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \
+ ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF9_QSPI) || \
+ ((AF) == GPIO_AF10_SAI2) || ((AF) == GPIO_AF10_QSPI))
+
+#endif /* STM32F446xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------------------------------- STM32F469xx/STM32F479xx --------*/
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
+ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \
+ ((AF) == GPIO_AF14_LTDC) || ((AF) == GPIO_AF13_DSI) || \
+ ((AF) == GPIO_AF9_QSPI) || ((AF) == GPIO_AF10_QSPI))
+
+#endif /* STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
/**
* @}
*/
@@ -911,7 +1316,7 @@
*/
/* Private functions ---------------------------------------------------------*/
-/** @addtogroup GPIO_Private_Functions
+/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
* @{
*/
diff --git a/f4/include/stm32f4xx_hal_hash.h b/f4/include/stm32f4xx_hal_hash.h
index a0450e9..b219594 100755
--- a/f4/include/stm32f4xx_hal_hash.h
+++ b/f4/include/stm32f4xx_hal_hash.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_hash.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,7 @@
extern "C" {
#endif
-#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx)
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -210,8 +210,8 @@ typedef struct
/** @defgroup HASH_Exported_Constants_Group6 HASH Interrupts definition
* @{
*/
-#define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */
-#define HASH_IT_DCI HASH_IMR_DCIM /*!< Digest calculation complete */
+#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
+#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
/**
* @}
*/
@@ -241,7 +241,8 @@ typedef struct
* @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_HASH_GET_FLAG(__FLAG__) ((HASH->SR & (__FLAG__)) == (__FLAG__))
+#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
+ ((HASH->SR & (__FLAG__)) == (__FLAG__)))
/**
* @brief Enable the multiple DMA mode.
@@ -267,7 +268,7 @@ typedef struct
* @param SIZE: size in byte of last data written in Data register.
* @retval None
*/
-#define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBW);\
+#define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBLW);\
HASH->STR |= 8 * ((SIZE) % 4);\
}while(0)
@@ -416,6 +417,8 @@ void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
#define IS_HASH_HMAC_KEYTYPE(__KEYTYPE__) (((__KEYTYPE__) == HASH_HMAC_KEYTYPE_SHORTKEY) || \
((__KEYTYPE__) == HASH_HMAC_KEYTYPE_LONGKEY))
+#define IS_HASH_SHA1_BUFFER_SIZE(__SIZE__) ((((__SIZE__)%4) != 0)? 0U: 1U)
+
/**
* @}
*/
@@ -429,7 +432,7 @@ void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
* @}
*/
-#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx || STM32F479xx */
/**
* @}
*/
diff --git a/f4/include/stm32f4xx_hal_hash_ex.h b/f4/include/stm32f4xx_hal_hash_ex.h
index 0abcd87..6611863 100755
--- a/f4/include/stm32f4xx_hal_hash_ex.h
+++ b/f4/include/stm32f4xx_hal_hash_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_hash_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of HASH HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,7 @@
extern "C" {
#endif
-#if defined(STM32F437xx) || defined(STM32F439xx)
+#if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -182,7 +182,7 @@ void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash);
* @}
*/
-#endif /* STM32F437xx || STM32F439xx */
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
/**
* @}
*/
diff --git a/f4/include/stm32f4xx_hal_hcd.h b/f4/include/stm32f4xx_hal_hcd.h
index 934821d..b629723 100755
--- a/f4/include/stm32f4xx_hal_hcd.h
+++ b/f4/include/stm32f4xx_hal_hcd.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_hcd.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of HCD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -42,7 +42,10 @@
#ifdef __cplusplus
extern "C" {
#endif
-
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_usb.h"
@@ -50,8 +53,7 @@
* @{
*/
-/** @defgroup HCD HCD
- * @brief HCD HAL module driver
+/** @addtogroup HCD
* @{
*/
@@ -105,6 +107,7 @@ typedef struct
/** @defgroup HCD_Exported_Constants HCD Exported Constants
* @{
*/
+
/** @defgroup HCD_Speed HCD Speed
* @{
*/
@@ -150,11 +153,12 @@ typedef struct
*/
/* Exported functions --------------------------------------------------------*/
-/** @defgroup HCD_Exported_Functions HCD Exported Functions
+/** @addtogroup HCD_Exported_Functions HCD Exported Functions
* @{
*/
-/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+/* Initialization/de-initialization functions ********************************/
+/** @addtogroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
@@ -168,13 +172,15 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
uint16_t mps);
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
+
void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
-/** @defgroup HCD_Exported_Functions_Group2 IO operation functions
+/* I/O operation functions ***************************************************/
+/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
@@ -198,7 +204,8 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
* @}
*/
-/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
+/* Peripheral Control functions **********************************************/
+/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
@@ -208,7 +215,8 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
* @}
*/
-/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
+/* Peripheral State functions ************************************************/
+/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
* @{
*/
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
@@ -232,10 +240,12 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
/** @defgroup HCD_Instance_definition HCD Instance definition
* @{
*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) ||\
+ defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
((INSTANCE) == USB_OTG_HS))
-#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
#endif
/**
@@ -246,24 +256,6 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
* @}
*/
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup HCD_Private_Functions HCD Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
/**
* @}
*/
@@ -271,7 +263,8 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
-
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
#ifdef __cplusplus
}
#endif
diff --git a/f4/include/stm32f4xx_hal_i2c.h b/f4/include/stm32f4xx_hal_i2c.h
index 7ae7a59..3c05ad3 100755
--- a/f4/include/stm32f4xx_hal_i2c.h
+++ b/f4/include/stm32f4xx_hal_i2c.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_i2c.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
diff --git a/f4/include/stm32f4xx_hal_i2c_ex.h b/f4/include/stm32f4xx_hal_i2c_ex.h
index 442e3c0..e52dd91 100755
--- a/f4/include/stm32f4xx_hal_i2c_ex.h
+++ b/f4/include/stm32f4xx_hal_i2c_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_i2c_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of I2C HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,8 +43,9 @@
extern "C" {
#endif
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -124,7 +125,8 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
* @}
*/
-#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC || STM32F401xE */
+#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\
+ STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
#ifdef __cplusplus
}
diff --git a/f4/include/stm32f4xx_hal_i2s.h b/f4/include/stm32f4xx_hal_i2s.h
index 84d08f4..d5e15e7 100755
--- a/f4/include/stm32f4xx_hal_i2s.h
+++ b/f4/include/stm32f4xx_hal_i2s.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_i2s.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -162,15 +162,6 @@ typedef struct
* @}
*/
-/** @defgroup I2S_Clock_Source I2S Clock Source
- * @{
- */
-#define I2S_CLOCK_PLL ((uint32_t)0x00000000)
-#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)
-/**
- * @}
- */
-
/** @defgroup I2S_Mode I2S Mode
* @{
*/
@@ -436,9 +427,6 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
/** @defgroup I2S_Private_Macros I2S Private Macros
* @{
*/
-#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
- ((CLOCK) == I2S_CLOCK_PLL))
-
#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
((MODE) == I2S_MODE_SLAVE_RX) || \
((MODE) == I2S_MODE_MASTER_TX) || \
@@ -467,8 +455,7 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
((CPOL) == I2S_CPOL_HIGH))
-
-#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
+
/**
* @}
*/
@@ -483,6 +470,8 @@ void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
void I2S_DMAError(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
+HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
diff --git a/f4/include/stm32f4xx_hal_i2s_ex.h b/f4/include/stm32f4xx_hal_i2s_ex.h
index 5079d7e..1ec4654 100755
--- a/f4/include/stm32f4xx_hal_i2s_ex.h
+++ b/f4/include/stm32f4xx_hal_i2s_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_i2s_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -65,7 +65,37 @@
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2SEx_Exported_Constants I2S Exported Constants
* @{
- */
+ */
+
+/** @defgroup I2S_Clock_Source I2S Clock Source
+ * @{
+ */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \
+ defined(STM32F479xx)
+#define I2S_CLOCK_PLL ((uint32_t)0x00000000)
+#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F446xx)
+#define I2S_CLOCK_PLL ((uint32_t)0x00000000)
+#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)
+#define I2S_CLOCK_PLLR ((uint32_t)0x00000002)
+#define I2S_CLOCK_PLLSRC ((uint32_t)0x00000003)
+#endif /* STM32F446xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define I2S_CLOCK_PLLSRC ((uint32_t)0x00000000)
+#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)
+#define I2S_CLOCK_PLLR ((uint32_t)0x00000002)
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -116,6 +146,36 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_
/** @defgroup I2SEx_Private_Macros I2S Private Macros
* @{
*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \
+ defined(STM32F479xx)
+#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
+ ((CLOCK) == I2S_CLOCK_PLL))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F446xx)
+#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
+ ((CLOCK) == I2S_CLOCK_PLL) ||\
+ ((CLOCK) == I2S_CLOCK_PLLSRC) ||\
+ ((CLOCK) == I2S_CLOCK_PLLR))
+#endif /* STM32F446xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
+ ((CLOCK) == I2S_CLOCK_PLLSRC) ||\
+ ((CLOCK) == I2S_CLOCK_PLLR))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Cx) || defined(STM32F410Rx) || \
+ defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F410Cx || STM32F410Rx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+
/**
* @}
*/
@@ -125,6 +185,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_
* @{
*/
HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s);
+uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
diff --git a/f4/include/stm32f4xx_hal_irda.h b/f4/include/stm32f4xx_hal_irda.h
index da4a28e..2f4b719 100755
--- a/f4/include/stm32f4xx_hal_irda.h
+++ b/f4/include/stm32f4xx_hal_irda.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_irda.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,7 +55,7 @@
*/
/* Exported types ------------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Types USART Exported Types
+/** @defgroup IRDA_Exported_Types IRDA Exported Types
* @{
*/
/**
diff --git a/f4/include/stm32f4xx_hal_iwdg.h b/f4/include/stm32f4xx_hal_iwdg.h
index 207771e..498ce9f 100755
--- a/f4/include/stm32f4xx_hal_iwdg.h
+++ b/f4/include/stm32f4xx_hal_iwdg.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_iwdg.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
diff --git a/f4/include/stm32f4xx_hal_lptim.h b/f4/include/stm32f4xx_hal_lptim.h
new file mode 100644
index 0000000..2dfd34f
--- /dev/null
+++ b/f4/include/stm32f4xx_hal_lptim.h
@@ -0,0 +1,759 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_lptim.h
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief Header file of LPTIM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_LPTIM_H
+#define __STM32F4xx_HAL_LPTIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup LPTIM LPTIM
+ * @brief LPTIM HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
+ * @{
+ */
+
+/** @defgroup LPTIM_WAKEUPTIMER_EXTILINE LPTIM WAKEUP Timer EXTI Line
+ * @{
+ */
+#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR23) /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */
+/**
+ * @}
+ */
+
+/**
+ * @brief LPTIM Clock configuration definition
+ */
+typedef struct
+{
+ uint32_t Source; /*!< Selects the clock source.
+ This parameter can be a value of @ref LPTIM_Clock_Source */
+
+ uint32_t Prescaler; /*!< Specifies the counter clock Prescaler.
+ This parameter can be a value of @ref LPTIM_Clock_Prescaler */
+
+}LPTIM_ClockConfigTypeDef;
+
+/**
+ * @brief LPTIM Clock configuration definition
+ */
+typedef struct
+{
+ uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit
+ if the ULPTIM input is selected.
+ Note: This parameter is used only when Ultra low power clock source is used.
+ Note: If the polarity is configured on 'both edges', an auxiliary clock
+ (one of the Low power oscillator) must be active.
+ This parameter can be a value of @ref LPTIM_Clock_Polarity */
+
+ uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter.
+ Note: This parameter is used only when Ultra low power clock source is used.
+ This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
+
+}LPTIM_ULPClockConfigTypeDef;
+
+/**
+ * @brief LPTIM Trigger configuration definition
+ */
+typedef struct
+{
+ uint32_t Source; /*!< Selects the Trigger source.
+ This parameter can be a value of @ref LPTIM_Trigger_Source */
+
+ uint32_t ActiveEdge; /*!< Selects the Trigger active edge.
+ Note: This parameter is used only when an external trigger is used.
+ This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
+
+ uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter.
+ Note: This parameter is used only when an external trigger is used.
+ This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */
+}LPTIM_TriggerConfigTypeDef;
+
+/**
+ * @brief LPTIM Initialization Structure definition
+ */
+typedef struct
+{
+ LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
+
+ LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */
+
+ LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
+
+ uint32_t OutputPolarity; /*!< Specifies the Output polarity.
+ This parameter can be a value of @ref LPTIM_Output_Polarity */
+
+ uint32_t UpdateMode; /*!< Specifies whether the update of the autorelaod and the compare
+ values is done immediately or after the end of current period.
+ This parameter can be a value of @ref LPTIM_Updating_Mode */
+
+ uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
+ or each external event.
+ This parameter can be a value of @ref LPTIM_Counter_Source */
+
+}LPTIM_InitTypeDef;
+
+/**
+ * @brief HAL LPTIM State structure definition
+ */
+typedef enum __HAL_LPTIM_StateTypeDef
+{
+ HAL_LPTIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
+ HAL_LPTIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_LPTIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
+ HAL_LPTIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_LPTIM_STATE_ERROR = 0x04 /*!< Internal Process is ongoing */
+}HAL_LPTIM_StateTypeDef;
+
+/**
+ * @brief LPTIM handle Structure definition
+ */
+typedef struct
+{
+ LPTIM_TypeDef *Instance; /*!< Register base address */
+
+ LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
+
+ HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
+
+ HAL_LockTypeDef Lock; /*!< LPTIM locking object */
+
+ __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
+
+}LPTIM_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
+ * @{
+ */
+
+/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
+ * @{
+ */
+#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00)
+#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
+ * @{
+ */
+#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000)
+#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
+#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
+#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
+#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
+#define LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
+#define LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
+#define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
+ * @{
+ */
+
+#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000)
+#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
+ * @{
+ */
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
+#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
+#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
+#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
+ * @{
+ */
+
+#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000)
+#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
+#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
+ * @{
+ */
+#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFF)
+#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000)
+#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
+#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
+#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
+#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
+#define LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
+ * @{
+ */
+#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
+#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
+#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
+ * @{
+ */
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
+#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
+#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
+#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
+ * @{
+ */
+
+#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000)
+#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Counter_Source LPTIM Counter Source
+ * @{
+ */
+
+#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000)
+#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Flag_Definition LPTIM Flag Definition
+ * @{
+ */
+
+#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
+#define LPTIM_FLAG_UP LPTIM_ISR_UP
+#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
+#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
+#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
+#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
+#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
+ * @{
+ */
+
+#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE
+#define LPTIM_IT_UP LPTIM_IER_UPIE
+#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE
+#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
+#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
+#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE
+#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Option Register Definition
+ * @{
+ */
+#define LPTIM_OP_PAD_AF ((uint32_t)0x00000000)
+#define LPTIM_OP_PAD_PA4 LPTIM_OR_OR_0
+#define LPTIM_OP_PAD_PB9 LPTIM_OR_OR_1
+#define LPTIM_OP_TIM_DAC LPTIM_OR_OR
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
+ * @{
+ */
+
+/** @brief Reset LPTIM handle state
+ * @param __HANDLE__: LPTIM handle
+ * @retval None
+ */
+#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
+
+/**
+ * @brief Enable/Disable the LPTIM peripheral.
+ * @param __HANDLE__: LPTIM handle
+ * @retval None
+ */
+#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
+#define __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))
+
+/**
+ * @brief Starts the LPTIM peripheral in Continuous or in single mode.
+ * @param __HANDLE__: DMA handle
+ * @retval None
+ */
+#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
+#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
+
+
+/**
+ * @brief Writes the passed parameter in the Autoreload register.
+ * @param __HANDLE__: LPTIM handle
+ * @param __VALUE__ : Autoreload value
+ * @retval None
+ */
+#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
+
+/**
+ * @brief Writes the passed parameter in the Compare register.
+ * @param __HANDLE__: LPTIM handle
+ * @param __VALUE__ : Compare value
+ * @retval None
+ */
+#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
+
+/**
+ * @brief Checks whether the specified LPTIM flag is set or not.
+ * @param __HANDLE__: LPTIM handle
+ * @param __FLAG__ : LPTIM flag to check
+ * This parameter can be a value of:
+ * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
+ * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
+ * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
+ * @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
+ * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
+ * @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
+ * @arg LPTIM_FLAG_CMPM : Compare match Flag.
+ * @retval The state of the specified flag (SET or RESET).
+ */
+#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clears the specified LPTIM flag.
+ * @param __HANDLE__: LPTIM handle.
+ * @param __FLAG__ : LPTIM flag to clear.
+ * This parameter can be a value of:
+ * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
+ * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
+ * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
+ * @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
+ * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
+ * @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
+ * @arg LPTIM_FLAG_CMPM : Compare match Flag.
+ * @retval None.
+ */
+#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+ * @brief Enable the specified LPTIM interrupt.
+ * @param __HANDLE__ : LPTIM handle.
+ * @param __INTERRUPT__ : LPTIM interrupt to set.
+ * This parameter can be a value of:
+ * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
+ * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
+ * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
+ * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
+ * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+ * @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
+ * @arg LPTIM_IT_CMPM : Compare match Interrupt.
+ * @retval None.
+ */
+#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+ /**
+ * @brief Disable the specified LPTIM interrupt.
+ * @param __HANDLE__ : LPTIM handle.
+ * @param __INTERRUPT__ : LPTIM interrupt to set.
+ * This parameter can be a value of:
+ * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
+ * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
+ * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
+ * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
+ * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+ * @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
+ * @arg LPTIM_IT_CMPM : Compare match Interrupt.
+ * @retval None.
+ */
+#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
+
+ /**
+ * @brief Checks whether the specified LPTIM interrupt is set or not.
+ * @param __HANDLE__ : LPTIM handle.
+ * @param __INTERRUPT__ : LPTIM interrupt to check.
+ * This parameter can be a value of:
+ * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
+ * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
+ * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
+ * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
+ * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+ * @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
+ * @arg LPTIM_IT_CMPM : Compare match Interrupt.
+ * @retval Interrupt status.
+ */
+
+#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief LPTIM Option Register
+ * @param __HANDLE__: LPTIM handle
+ * @param __VALUE__: This parameter can be a value of :
+ * @arg LPTIM_OP_PAD_AF
+ * @arg LPTIM_OP_PAD_PA4
+ * @arg LPTIM_OP_PAD_PB9
+ * @arg LPTIM_OP_TIM_DAC
+ * @retval None
+ */
+#define __HAL_LPTIM_OPTR_CONFIG(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->OR = (__VALUE__))
+
+/**
+ * @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable event on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable event on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+ * @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Clear the LPTIM Wake-up Timer associated Exti line flag.
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
+HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
+
+/* MSP functions *************************************************************/
+void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
+
+/* Start/Stop operation functions *********************************************/
+/* ################################# PWM Mode ################################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################# One Pulse Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################## Set once Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################### Encoder Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################# Time out Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################## Counter Mode ###############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* Reading operation functions ************************************************/
+uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
+
+/* LPTIM IRQ functions *******************************************************/
+void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
+
+/* CallBack functions ********************************************************/
+void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
+
+/* Peripheral State functions ************************************************/
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Types LPTIM Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Variables LPTIM Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
+ * @{
+ */
+
+#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
+ ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
+
+#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
+#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
+
+#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
+ ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
+
+#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
+ ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \
+ ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \
+ ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
+
+#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \
+ ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
+ ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
+
+#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_5))
+
+#define IS_LPTIM_EXT_TRG_POLARITY(__POLAR__) (((__POLAR__) == LPTIM_ACTIVEEDGE_RISING ) || \
+ ((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING ) || \
+ ((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
+
+#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
+ ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \
+ ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \
+ ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
+
+#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
+ ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
+
+#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
+ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
+
+#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFF)
+
+#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFF)
+
+#define IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFF)
+
+#define IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFF)
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_LPTIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/include/stm32f4xx_hal_ltdc.h b/f4/include/stm32f4xx_hal_ltdc.h
index 01a3e23..165c9ba 100755
--- a/f4/include/stm32f4xx_hal_ltdc.h
+++ b/f4/include/stm32f4xx_hal_ltdc.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_ltdc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of LTDC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,7 @@
extern "C" {
#endif
-#if defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -467,6 +467,9 @@ typedef struct
* @}
*/
+/* Include LTDC HAL Extension module */
+#include "stm32f4xx_hal_ltdc_ex.h"
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup LTDC_Exported_Functions
* @{
@@ -480,7 +483,7 @@ HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc);
void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);
void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
-void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc);
/**
* @}
*/
@@ -504,6 +507,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
@@ -561,7 +565,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
/** @defgroup LTDC_Private_Macros LTDC Private Macros
* @{
*/
-#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__))))
+#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__)))))
#define IS_LTDC_LAYER(LAYER) ((LAYER) <= MAX_LAYER)
#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPOLARITY_AL) || \
((HSPOL) == LTDC_HSPOLARITY_AH))
@@ -620,7 +624,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
* @}
*/
-#endif /* STM32F429xx || STM32F439xx */
+#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#ifdef __cplusplus
}
diff --git a/f4/include/stm32f4xx_hal_ltdc_ex.h b/f4/include/stm32f4xx_hal_ltdc_ex.h
new file mode 100644
index 0000000..f91ad75
--- /dev/null
+++ b/f4/include/stm32f4xx_hal_ltdc_ex.h
@@ -0,0 +1,151 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_ltdc_ex.h
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief Header file of LTDC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_LTDC_EX_H
+#define __STM32F4xx_HAL_LTDC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+#include "stm32f4xx_hal_dsi.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup LTDCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup LTDCEx_Exported_Constants LTDCEx Exported Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LTDCEx_Exported_Macros LTDC Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg);
+HAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg);
+/**
+ * @}
+ */
+
+
+ /* Private types -------------------------------------------------------------*/
+/** @defgroup LTDCEx_Private_Types LTDCEx Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup LTDCEx_Private_Variables LTDCEx Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup LTDCEx_Private_Constants LTDCEx Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup LTDCEx_Private_Macros LTDCEx Private Macros
+ * @{
+ */
+
+ /**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LTDCEx_Private_Functions LTDCEx Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F469xx || STM32F479xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_LTDC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/include/stm32f4xx_hal_nand.h b/f4/include/stm32f4xx_hal_nand.h
index 1fbbba2..f13b0ab 100755
--- a/f4/include/stm32f4xx_hal_nand.h
+++ b/f4/include/stm32f4xx_hal_nand.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_nand.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -44,13 +44,15 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
#include "stm32f4xx_ll_fsmc.h"
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#include "stm32f4xx_ll_fmc.h"
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
+ STM32F479xx */
/** @addtogroup STM32F4xx_HAL_Driver
* @{
@@ -60,7 +62,10 @@
* @{
*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
/* Exported typedef ----------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup NAND_Exported_Types NAND Exported Types
@@ -143,7 +148,7 @@ typedef struct
*/
/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros ------------------------------------------------------------*/
/** @defgroup NAND_Exported_Macros NAND Exported Macros
* @{
*/
@@ -271,7 +276,7 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
/**
* @brief NAND memory address computation.
* @param __ADDRESS__: NAND memory address.
- * @param __HANDLE__ : NAND handle.
+ * @param __HANDLE__: NAND handle.
* @retval NAND Raw address value
*/
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
@@ -289,7 +294,9 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
diff --git a/f4/include/stm32f4xx_hal_nor.h b/f4/include/stm32f4xx_hal_nor.h
index 724d784..b587946 100755
--- a/f4/include/stm32f4xx_hal_nor.h
+++ b/f4/include/stm32f4xx_hal_nor.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_nor.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -44,13 +44,14 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
#include "stm32f4xx_ll_fsmc.h"
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#include "stm32f4xx_ll_fmc.h"
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/** @addtogroup STM32F4xx_HAL_Driver
* @{
@@ -60,7 +61,10 @@
* @{
*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup NOR_Exported_Types NOR Exported Types
* @{
@@ -145,7 +149,7 @@ typedef struct
*/
/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros ------------------------------------------------------------*/
/** @defgroup NOR_Exported_Macros NOR Exported Macros
* @{
*/
@@ -264,8 +268,8 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
* @param ADDRESS: NOR memory address
* @retval NOR shifted address value
*/
-#define NOR_ADDR_SHIFT(__NOR_ADDRESS__, NOR_MEMORY_WIDTH, ADDRESS) (((NOR_MEMORY_WIDTH) == NOR_MEMORY_8B)? ((uint32_t)((__NOR_ADDRESS__) + (2 * (ADDRESS)))):\
- ((uint32_t)((__NOR_ADDRESS__) + (ADDRESS))))
+#define NOR_ADDR_SHIFT(__NOR_ADDRESS__, NOR_MEMORY_WIDTH, ADDRESS) (uint32_t)(((NOR_MEMORY_WIDTH) == NOR_MEMORY_8B)? ((uint32_t)((__NOR_ADDRESS__) + (2 * (ADDRESS)))):\
+ ((uint32_t)((__NOR_ADDRESS__) + (ADDRESS))))
/**
* @brief NOR memory write data to specified address.
@@ -278,7 +282,9 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
diff --git a/f4/include/stm32f4xx_hal_pccard.h b/f4/include/stm32f4xx_hal_pccard.h
index 658edb7..156ab4c 100755
--- a/f4/include/stm32f4xx_hal_pccard.h
+++ b/f4/include/stm32f4xx_hal_pccard.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_pccard.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of PCCARD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -44,11 +44,11 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
#include "stm32f4xx_ll_fsmc.h"
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#include "stm32f4xx_ll_fmc.h"
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
@@ -56,7 +56,9 @@
* @{
*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
/** @addtogroup PCCARD
* @{
*/
@@ -186,6 +188,7 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
#define ATA_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */
#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */
#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
+#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202) /* Card Configuration and Status Register */
/* Flash-ATA commands */
#define ATA_READ_SECTOR_CMD ((uint8_t)0x20)
@@ -247,7 +250,8 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
/**
diff --git a/f4/include/stm32f4xx_hal_pcd.h b/f4/include/stm32f4xx_hal_pcd.h
index 61cc641..2bd9394 100755
--- a/f4/include/stm32f4xx_hal_pcd.h
+++ b/f4/include/stm32f4xx_hal_pcd.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_pcd.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -42,7 +42,10 @@
#ifdef __cplusplus
extern "C" {
#endif
-
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_usb.h"
@@ -71,6 +74,16 @@ typedef enum
HAL_PCD_STATE_TIMEOUT = 0x04
} PCD_StateTypeDef;
+#ifdef USB_OTG_GLPMCFG_LPMEN
+/* Device LPM suspend state */
+typedef enum
+{
+ LPM_L0 = 0x00, /* on */
+ LPM_L1 = 0x01, /* LPM L1 sleep */
+ LPM_L2 = 0x02, /* suspend */
+ LPM_L3 = 0x03, /* off */
+}PCD_LPM_StateTypeDef;
+#endif /* USB_OTG_GLPMCFG_LPMEN */
typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
@@ -81,15 +94,24 @@ typedef USB_OTG_EPTypeDef PCD_EPTypeDef ;
*/
typedef struct
{
- PCD_TypeDef *Instance; /*!< Register base address */
- PCD_InitTypeDef Init; /*!< PCD required parameters */
- PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
- HAL_LockTypeDef Lock; /*!< PCD peripheral status */
- __IO PCD_StateTypeDef State; /*!< PCD communication state */
- uint32_t Setup[12]; /*!< Setup packet buffer */
- void *pData; /*!< Pointer to upper stack Handler */
-
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+#ifdef USB_OTG_GLPMCFG_LPMEN
+ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
+ uint32_t BESL;
+ uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
+ This parameter can be set to ENABLE or DISABLE */
+#endif /* USB_OTG_GLPMCFG_LPMEN */
+#ifdef USB_OTG_GCCFG_BCDEN
+ uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
+ This parameter can be set to ENABLE or DISABLE */
+#endif /* USB_OTG_GCCFG_BCDEN */
+ void *pData; /*!< Pointer to upper stack Handler */
} PCD_HandleTypeDef;
/**
@@ -122,6 +144,19 @@ typedef struct
/**
* @}
*/
+
+/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
+ * @{
+ */
+#ifndef USBD_HS_TRDT_VALUE
+ #define USBD_HS_TRDT_VALUE 9
+#endif /* USBD_HS_TRDT_VALUE */
+#ifndef USBD_FS_TRDT_VALUE
+ #define USBD_FS_TRDT_VALUE 5
+#endif /* USBD_FS_TRDT_VALUE */
+/**
+ * @}
+ */
/**
* @}
@@ -136,7 +171,7 @@ typedef struct
#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
@@ -193,7 +228,10 @@ typedef struct
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PCD_Exported_Functions PCD Exported Functions
@@ -214,7 +252,7 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
/* I/O operation functions ***************************************************/
/* Non-Blocking mode: Interrupt */
-/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions
+/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* Non-Blocking mode: Interrupt */
@@ -269,15 +307,20 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
/**
* @}
- */
-
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
/** @defgroup PCD_Instance_definition PCD Instance definition
* @{
*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
((INSTANCE) == USB_OTG_HS))
-#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
#endif
/**
@@ -295,7 +338,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
/**
* @}
*/
-
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
#ifdef __cplusplus
}
#endif
diff --git a/f4/include/stm32f4xx_hal_pcd_ex.h b/f4/include/stm32f4xx_hal_pcd_ex.h
index 8e4e641..04b9a6c 100755
--- a/f4/include/stm32f4xx_hal_pcd_ex.h
+++ b/f4/include/stm32f4xx_hal_pcd_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_pcd_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -42,7 +42,10 @@
#ifdef __cplusplus
extern "C" {
#endif
-
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -54,10 +57,18 @@
* @{
*/
/* Exported types ------------------------------------------------------------*/
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+typedef enum
+{
+ PCD_LPM_L0_ACTIVE = 0x00, /* on */
+ PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
+}PCD_LPM_MsgTypeDef;
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
+/** @addtogroup PCDEx_Exported_Functions PCD Extended Exported Functions
* @{
*/
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
@@ -65,6 +76,12 @@
*/
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+
/**
* @}
*/
@@ -80,7 +97,8 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
/**
* @}
*/
-
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
#ifdef __cplusplus
}
#endif
diff --git a/f4/include/stm32f4xx_hal_pwr.h b/f4/include/stm32f4xx_hal_pwr.h
index 65b9252..26cfce2 100755
--- a/f4/include/stm32f4xx_hal_pwr.h
+++ b/f4/include/stm32f4xx_hal_pwr.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_pwr.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -84,7 +84,7 @@ typedef struct
/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
* @{
*/
-#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
+#define PWR_WAKEUP_PIN1 ((uint32_t)0x00000100)
/**
* @}
*/
@@ -147,16 +147,6 @@ typedef struct
* @}
*/
-/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
- * @{
- */
-#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS
-#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1
-#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0
-/**
- * @}
- */
-
/** @defgroup PWR_Flag PWR Flag
* @{
*/
@@ -178,18 +168,6 @@ typedef struct
* @{
*/
-/** @brief macros configure the main internal regulator output voltage.
- * @param __REGULATOR__: specifies the regulator output voltage to achieve
- * a tradeoff between performance and power consumption when the device does
- * not operate at the maximum frequency (refer to the datasheets for more details).
- * This parameter can be one of the following values:
- * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
- * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
- * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
- * @retval None
- */
-#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
-
/** @brief Check PWR flag is set or not.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
@@ -370,7 +348,7 @@ void HAL_PWR_DisableSEVOnPend(void);
/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
* @{
*/
-#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
/**
* @}
*/
@@ -394,15 +372,15 @@ void HAL_PWR_DisableSEVOnPend(void);
/* --- CR Register ---*/
/* Alias word address of DBP bit */
#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
-#define CR_DBP_BB (PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4))
+#define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4))
/* Alias word address of PVDE bit */
#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
-#define CR_PVDE_BB (PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4))
+#define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4))
/* Alias word address of PMODE bit */
#define PMODE_BIT_NUMBER POSITION_VAL(PWR_CR_PMODE)
-#define CR_PMODE_BB (PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PMODE_BIT_NUMBER * 4))
+#define CR_PMODE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PMODE_BIT_NUMBER * 4))
/**
* @}
*/
@@ -429,7 +407,6 @@ void HAL_PWR_DisableSEVOnPend(void);
/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
* @{
*/
-#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
@@ -442,10 +419,6 @@ void HAL_PWR_DisableSEVOnPend(void);
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
-#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
- ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
- ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
-
/**
* @}
*/
diff --git a/f4/include/stm32f4xx_hal_pwr_ex.h b/f4/include/stm32f4xx_hal_pwr_ex.h
index b47de7d..b5ea387 100755
--- a/f4/include/stm32f4xx_hal_pwr_ex.h
+++ b/f4/include/stm32f4xx_hal_pwr_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_pwr_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -59,8 +59,8 @@
/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
* @{
*/
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
* @{
@@ -80,7 +80,36 @@
/**
* @}
*/
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
+ * @{
+ */
+#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
+#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */
+#define PWR_REGULATOR_VOLTAGE_SCALE2 ((uint32_t)0x00000000) /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */
+#else
+#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to
+ 180 MHz by activating the over-drive mode. */
+#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to
+ 168 MHz by activating the over-drive mode. */
+#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0 /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */
+#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
+/**
+ * @}
+ */
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx)
+/** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins
+ * @{
+ */
+#define PWR_WAKEUP_PIN2 ((uint32_t)0x00000080)
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define PWR_WAKEUP_PIN3 ((uint32_t)0x00000040)
+#endif /* STM32F410xx */
+/**
+ * @}
+ */
+#endif /* STM32F410xx || STM32F446xx */
/**
* @}
@@ -90,7 +119,46 @@
/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
* @{
*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
+/** @brief macros configure the main internal regulator output voltage.
+ * @param __REGULATOR__: specifies the regulator output voltage to achieve
+ * a tradeoff between performance and power consumption when the device does
+ * not operate at the maximum frequency (refer to the datasheets for more details).
+ * This parameter can be one of the following values:
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
+ * @retval None
+ */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
+ __IO uint32_t tmpreg; \
+ MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
+ UNUSED(tmpreg); \
+ } while(0)
+#else
+/** @brief macros configure the main internal regulator output voltage.
+ * @param __REGULATOR__: specifies the regulator output voltage to achieve
+ * a tradeoff between performance and power consumption when the device does
+ * not operate at the maximum frequency (refer to the datasheets for more details).
+ * This parameter can be one of the following values:
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
+ * @retval None
+ */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
+ __IO uint32_t tmpreg; \
+ MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @brief Macros to enable or disable the Over drive mode.
* @note These macros can be used only for STM32F42xx/STM3243xx devices.
*/
@@ -135,7 +203,7 @@
*/
#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
@@ -152,19 +220,28 @@ void HAL_PWREx_EnableFlashPowerDown(void);
void HAL_PWREx_DisableFlashPowerDown(void);
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
+uint32_t HAL_PWREx_GetVoltageRange(void);
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F469xx) || defined(STM32F479xx)
+void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void);
+void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void);
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
+ defined(STM32F401xE) || defined(STM32F411xE)
void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
@@ -187,23 +264,23 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t
/* --- CR Register ---*/
/* Alias word address of FPDS bit */
#define FPDS_BIT_NUMBER POSITION_VAL(PWR_CR_FPDS)
-#define CR_FPDS_BB (PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FPDS_BIT_NUMBER * 4))
+#define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FPDS_BIT_NUMBER * 4))
/* Alias word address of ODEN bit */
#define ODEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODEN)
-#define CR_ODEN_BB (PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ODEN_BIT_NUMBER * 4))
+#define CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ODEN_BIT_NUMBER * 4))
/* Alias word address of ODSWEN bit */
#define ODSWEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODSWEN)
-#define CR_ODSWEN_BB (PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ODSWEN_BIT_NUMBER * 4))
+#define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ODSWEN_BIT_NUMBER * 4))
/* Alias word address of MRLVDS bit */
#define MRLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_MRLVDS)
-#define CR_MRLVDS_BB (PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (MRLVDS_BIT_NUMBER * 4))
+#define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (MRLVDS_BIT_NUMBER * 4))
/* Alias word address of LPLVDS bit */
#define LPLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_LPLVDS)
-#define CR_LPLVDS_BB (PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPLVDS_BIT_NUMBER * 4))
+#define CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPLVDS_BIT_NUMBER * 4))
/**
* @}
@@ -215,7 +292,13 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t
/* --- CSR Register ---*/
/* Alias word address of BRE bit */
#define BRE_BIT_NUMBER POSITION_VAL(PWR_CSR_BRE)
-#define CSR_BRE_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (BRE_BIT_NUMBER * 4))
+#define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (BRE_BIT_NUMBER * 4))
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/* Alias word address of WUPP bit */
+#define WUPP_BIT_NUMBER POSITION_VAL(PWR_CSR_WUPP)
+#define CSR_WUPP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (WUPP_BIT_NUMBER * 4))
+#endif /* STM32F469xx || STM32F479xx */
/**
* @}
*/
@@ -232,10 +315,29 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t
/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
* @{
*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
+#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
+#else
+#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
+#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
+
+#if defined(STM32F446xx)
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2))
+#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \
+ ((PIN) == PWR_WAKEUP_PIN3))
+#else
+#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
+#endif /* STM32F446xx */
/**
* @}
*/
diff --git a/f4/include/stm32f4xx_hal_qspi.h b/f4/include/stm32f4xx_hal_qspi.h
new file mode 100644
index 0000000..fbd58c4
--- /dev/null
+++ b/f4/include/stm32f4xx_hal_qspi.h
@@ -0,0 +1,788 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_qspi.h
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief Header file of QSPI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_QSPI_H
+#define __STM32F4xx_HAL_QSPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup QSPI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Types QSPI Exported Types
+ * @{
+ */
+
+/**
+ * @brief QSPI Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
+ This parameter can be a number between 0 and 255 */
+
+ uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
+ This parameter can be a value between 1 and 32 */
+
+ uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
+ take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
+ This parameter can be a value of @ref QSPI_SampleShifting */
+
+ uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
+ required to address the flash memory. The flash capacity can be up to 4GB
+ (addressed using 32 bits) in indirect mode, but the addressable space in
+ memory-mapped mode is limited to 256MB
+ This parameter can be a number between 0 and 31 */
+
+ uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
+ of clock cycles which the chip select must remain high between commands.
+ This parameter can be a value of @ref QSPI_ChipSelectHighTime */
+
+ uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
+ This parameter can be a value of @ref QSPI_ClockMode */
+
+ uint32_t FlashID; /* Specifies the Flash which will be used,
+ This parameter can be a value of @ref QSPI_Flash_Select */
+
+ uint32_t DualFlash; /* Specifies the Dual Flash Mode State
+ This parameter can be a value of @ref QSPI_DualFlash_Mode */
+}QSPI_InitTypeDef;
+
+/**
+ * @brief HAL QSPI State structures definition
+ */
+typedef enum
+{
+ HAL_QSPI_STATE_RESET = 0x00, /*!< Peripheral not initialized */
+ HAL_QSPI_STATE_READY = 0x01, /*!< Peripheral initialized and ready for use */
+ HAL_QSPI_STATE_BUSY = 0x02, /*!< Peripheral in indirect mode and busy */
+ HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /*!< Peripheral in indirect mode with transmission ongoing */
+ HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /*!< Peripheral in indirect mode with reception ongoing */
+ HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, /*!< Peripheral in auto polling mode ongoing */
+ HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, /*!< Peripheral in memory mapped mode ongoing */
+ HAL_QSPI_STATE_ERROR = 0x04 /*!< Peripheral in error */
+}HAL_QSPI_StateTypeDef;
+
+/**
+ * @brief QSPI Handle Structure definition
+ */
+typedef struct
+{
+ QUADSPI_TypeDef *Instance; /* QSPI registers base address */
+ QSPI_InitTypeDef Init; /* QSPI communication parameters */
+ uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
+ __IO uint16_t TxXferSize; /* QSPI Tx Transfer size */
+ __IO uint16_t TxXferCount; /* QSPI Tx Transfer Counter */
+ uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
+ __IO uint16_t RxXferSize; /* QSPI Rx Transfer size */
+ __IO uint16_t RxXferCount; /* QSPI Rx Transfer Counter */
+ DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
+ __IO HAL_LockTypeDef Lock; /* Locking object */
+ __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
+ __IO uint32_t ErrorCode; /* QSPI Error code */
+ uint32_t Timeout; /* Timeout for the QSPI memory access */
+}QSPI_HandleTypeDef;
+
+/**
+ * @brief QSPI Command structure definition
+ */
+typedef struct
+{
+ uint32_t Instruction; /* Specifies the Instruction to be sent
+ This parameter can be a value (8-bit) between 0x00 and 0xFF */
+ uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
+ This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
+ uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
+ This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
+ uint32_t AddressSize; /* Specifies the Address Size
+ This parameter can be a value of @ref QSPI_AddressSize */
+ uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
+ This parameter can be a value of @ref QSPI_AlternateBytesSize */
+ uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
+ This parameter can be a number between 0 and 31 */
+ uint32_t InstructionMode; /* Specifies the Instruction Mode
+ This parameter can be a value of @ref QSPI_InstructionMode */
+ uint32_t AddressMode; /* Specifies the Address Mode
+ This parameter can be a value of @ref QSPI_AddressMode */
+ uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
+ This parameter can be a value of @ref QSPI_AlternateBytesMode */
+ uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
+ This parameter can be a value of @ref QSPI_DataMode */
+ uint32_t NbData; /* Specifies the number of data to transfer.
+ This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
+ until end of memory)*/
+ uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
+ This parameter can be a value of @ref QSPI_DdrMode */
+ uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
+ system clock in DDR mode.
+ This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
+ uint32_t SIOOMode; /* Specifies the send instruction only once mode
+ This parameter can be a value of @ref QSPI_SIOOMode */
+}QSPI_CommandTypeDef;
+
+/**
+ * @brief QSPI Auto Polling mode configuration structure definition
+ */
+typedef struct
+{
+ uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
+ This parameter can be any value between 0 and 0xFFFFFFFF */
+ uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
+ This parameter can be any value between 0 and 0xFFFFFFFF */
+ uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
+ This parameter can be any value between 0 and 0xFFFF */
+ uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
+ This parameter can be any value between 1 and 4 */
+ uint32_t MatchMode; /* Specifies the method used for determining a match.
+ This parameter can be a value of @ref QSPI_MatchMode */
+ uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
+ This parameter can be a value of @ref QSPI_AutomaticStop */
+}QSPI_AutoPollingTypeDef;
+
+/**
+ * @brief QSPI Memory Mapped mode configuration structure definition
+ */
+typedef struct
+{
+ uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
+ This parameter can be any value between 0 and 0xFFFF */
+ uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
+ This parameter can be a value of @ref QSPI_TimeOutActivation */
+}QSPI_MemoryMappedTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
+ * @{
+ */
+/** @defgroup QSPI_ErrorCode QSPI Error Code
+ * @{
+ */
+#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */
+#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */
+#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
+ * @{
+ */
+#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000) /*!<No clock cycle shift to sample data*/
+#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
+ * @{
+ */
+#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000) /*!<nCS stay high for at least 1 clock cycle between commands*/
+#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_ClockMode QSPI Clock Mode
+ * @{
+ */
+#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /*!<Clk stays low while nCS is released*/
+#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Flash_Select QSPI Flash Select
+ * @{
+ */
+#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000)
+#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
+/**
+ * @}
+ */
+
+ /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
+ * @{
+ */
+#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
+#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_AddressSize QSPI Address Size
+ * @{
+ */
+#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /*!<8-bit address*/
+#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
+#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
+#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
+ * @{
+ */
+#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /*!<8-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
+* @{
+*/
+#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /*!<No instruction*/
+#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
+#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
+#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_AddressMode QSPI Address Mode
+* @{
+*/
+#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /*!<No address*/
+#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
+#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
+#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
+* @{
+*/
+#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /*!<No alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
+#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
+#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_DataMode QSPI Data Mode
+ * @{
+ */
+#define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/
+#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
+#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
+#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_DdrMode QSPI Ddr Mode
+ * @{
+ */
+#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /*!<Double data rate mode disabled*/
+#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
+ * @{
+ */
+#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/
+#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_SIOOMode QSPI SIOO Mode
+ * @{
+ */
+#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/
+#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_MatchMode QSPI Match Mode
+ * @{
+ */
+#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /*!<AND match mode between unmasked bits*/
+#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
+ * @{
+ */
+#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /*!<AutoPolling stops only with abort or QSPI disabling*/
+#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
+ * @{
+ */
+#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /*!<Timeout counter disabled, nCS remains active*/
+#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Flags QSPI Flags
+ * @{
+ */
+#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
+#define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
+#define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
+#define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
+#define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
+#define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Interrupts QSPI Interrupts
+ * @{
+ */
+#define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
+#define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
+#define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
+#define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
+#define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
+ * @{
+ */
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
+ * @{
+ */
+
+/** @brief Reset QSPI handle state
+ * @param __HANDLE__: QSPI handle.
+ * @retval None
+ */
+#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
+
+/** @brief Enable QSPI
+ * @param __HANDLE__: specifies the QSPI Handle.
+ * @retval None
+ */
+#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
+
+/** @brief Disable QSPI
+ * @param __HANDLE__: specifies the QSPI Handle.
+ * @retval None
+ */
+#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
+
+/** @brief Enables the specified QSPI interrupt.
+ * @param __HANDLE__: specifies the QSPI Handle.
+ * @param __INTERRUPT__: specifies the QSPI interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg QSPI_IT_TO: QSPI Time out interrupt
+ * @arg QSPI_IT_SM: QSPI Status match interrupt
+ * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+ * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+ * @arg QSPI_IT_TE: QSPI Transfer error interrupt
+ * @retval None
+ */
+#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+
+/** @brief Disables the specified QSPI interrupt.
+ * @param __HANDLE__: specifies the QSPI Handle.
+ * @param __INTERRUPT__: specifies the QSPI interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg QSPI_IT_TO: QSPI Timeout interrupt
+ * @arg QSPI_IT_SM: QSPI Status match interrupt
+ * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+ * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+ * @arg QSPI_IT_TE: QSPI Transfer error interrupt
+ * @retval None
+ */
+#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+/** @brief Checks whether the specified QSPI interrupt source is enabled.
+ * @param __HANDLE__: specifies the QSPI Handle.
+ * @param __INTERRUPT__: specifies the QSPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg QSPI_IT_TO: QSPI Time out interrupt
+ * @arg QSPI_IT_SM: QSPI Status match interrupt
+ * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+ * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+ * @arg QSPI_IT_TE: QSPI Transfer error interrupt
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Get the selected QSPI's flag status.
+ * @param __HANDLE__: specifies the QSPI Handle.
+ * @param __FLAG__: specifies the QSPI flag to check.
+ * This parameter can be one of the following values:
+ * @arg QSPI_FLAG_BUSY: QSPI Busy flag
+ * @arg QSPI_FLAG_TO: QSPI Time out flag
+ * @arg QSPI_FLAG_SM: QSPI Status match flag
+ * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
+ * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
+ * @arg QSPI_FLAG_TE: QSPI Transfer error flag
+ * @retval None
+ */
+#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
+
+/** @brief Clears the specified QSPI's flag status.
+ * @param __HANDLE__: specifies the QSPI Handle.
+ * @param __FLAG__: specifies the QSPI clear register flag that needs to be set
+ * This parameter can be one of the following values:
+ * @arg QSPI_FLAG_TO: QSPI Time out flag
+ * @arg QSPI_FLAG_SM: QSPI Status match flag
+ * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
+ * @arg QSPI_FLAG_TE: QSPI Transfer error flag
+ * @retval None
+ */
+#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup QSPI_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup QSPI_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
+/**
+ * @}
+ */
+
+/** @addtogroup QSPI_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+/* QSPI IRQ handler method */
+void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
+
+/* QSPI indirect mode */
+HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
+HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
+HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+
+/* QSPI status flag polling mode */
+HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
+HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
+
+/* QSPI memory-mapped mode */
+HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
+/**
+ * @}
+ */
+
+/** @addtogroup QSPI_Exported_Functions_Group3
+ * @{
+ */
+/* Callback functions in non-blocking modes ***********************************/
+void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
+
+/* QSPI indirect mode */
+void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
+
+/* QSPI status flag polling mode */
+void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
+
+/* QSPI memory-mapped mode */
+void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
+/**
+ * @}
+ */
+
+/** @addtogroup QSPI_Exported_Functions_Group4
+ * @{
+ */
+/* Peripheral Control and State functions ************************************/
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi);
+uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup QSPI_Private_Constants QSPI Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup QSPI_Private_Macros QSPI Private Macros
+ * @{
+ */
+/** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler
+ * @{
+ */
+#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold
+ * @{
+ */
+#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32))
+/**
+ * @}
+ */
+
+#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
+ ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
+
+/** @defgroup QSPI_FlashSize QSPI Flash Size
+ * @{
+ */
+#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
+/**
+ * @}
+ */
+
+#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
+
+#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
+ ((CLKMODE) == QSPI_CLOCK_MODE_3))
+
+#define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \
+ ((FLA) == QSPI_FLASH_ID_2))
+
+#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
+ ((MODE) == QSPI_DUALFLASH_DISABLE))
+
+
+/** @defgroup QSPI_Instruction QSPI Instruction
+ * @{
+ */
+#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
+/**
+ * @}
+ */
+
+#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
+ ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
+ ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
+ ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
+
+#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
+ ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
+ ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
+ ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
+
+
+/** @defgroup QSPI_DummyCycles QSPI Dummy Cycles
+ * @{
+ */
+#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
+/**
+ * @}
+ */
+
+#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
+ ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
+ ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
+ ((MODE) == QSPI_INSTRUCTION_4_LINES))
+
+#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
+ ((MODE) == QSPI_ADDRESS_1_LINE) || \
+ ((MODE) == QSPI_ADDRESS_2_LINES) || \
+ ((MODE) == QSPI_ADDRESS_4_LINES))
+
+#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
+ ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
+ ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
+ ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
+
+#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
+ ((MODE) == QSPI_DATA_1_LINE) || \
+ ((MODE) == QSPI_DATA_2_LINES) || \
+ ((MODE) == QSPI_DATA_4_LINES))
+
+#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
+ ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
+
+#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
+ ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
+
+#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
+ ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
+
+/** @defgroup QSPI_Interval QSPI Interval
+ * @{
+ */
+#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size
+ * @{
+ */
+#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
+/**
+ * @}
+ */
+#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
+ ((MODE) == QSPI_MATCH_MODE_OR))
+
+#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
+ ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
+
+#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
+ ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
+
+/** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period
+ * @{
+ */
+#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)
+/**
+ * @}
+ */
+
+#define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \
+ ((FLAG) == QSPI_FLAG_TO) || \
+ ((FLAG) == QSPI_FLAG_SM) || \
+ ((FLAG) == QSPI_FLAG_FT) || \
+ ((FLAG) == QSPI_FLAG_TC) || \
+ ((FLAG) == QSPI_FLAG_TE))
+
+#define IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFF) == 0x00000000) && ((IT) != 0x00000000))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup QSPI_Private_Functions QSPI Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_QSPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/include/stm32f4xx_hal_rcc.h b/f4/include/stm32f4xx_hal_rcc.h
index 92b89fb..83e0936 100755
--- a/f4/include/stm32f4xx_hal_rcc.h
+++ b/f4/include/stm32f4xx_hal_rcc.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_rcc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -46,6 +46,10 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+/* Include RCC HAL Extended module */
+/* (include on top of file since RCC structures are defined in extended file) */
+#include "stm32f4xx_hal_rcc_ex.h"
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
@@ -59,31 +63,6 @@
* @{
*/
-/**
- * @brief RCC PLL configuration structure definition
- */
-typedef struct
-{
- uint32_t PLLState; /*!< The new state of the PLL.
- This parameter can be a value of @ref RCC_PLL_Config */
-
- uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
- This parameter must be a value of @ref RCC_PLL_Clock_Source */
-
- uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
- This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
-
- uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
- This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
-
- uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
- This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
-
- uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
- This parameter must be a number between Min_Data = 4 and Max_Data = 15 */
-
-}RCC_PLLInitTypeDef;
-
/**
* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
*/
@@ -239,9 +218,21 @@ typedef struct
#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
+#define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
/**
* @}
- */
+ */
+
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1)) /*!< PLLR used as system clock */
+/**
+ * @}
+ */
/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
* @{
@@ -310,15 +301,6 @@ typedef struct
* @}
*/
-/** @defgroup RCC_I2S_Clock_Source I2S Clock Source
- * @{
- */
-#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
-#define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001)
-/**
- * @}
- */
-
/** @defgroup RCC_MCO_Index MCO Index
* @{
*/
@@ -339,17 +321,6 @@ typedef struct
* @}
*/
-/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
- * @{
- */
-#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
-#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
-#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
-#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
-/**
- * @}
- */
-
/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
* @{
*/
@@ -423,52 +394,56 @@ typedef struct
* using it.
* @{
*/
-#define __HAL_RCC_GPIOA_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOAEN))
-#define __HAL_RCC_GPIOB_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOBEN))
-#define __HAL_RCC_GPIOC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOCEN))
-#define __HAL_RCC_GPIOD_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIODEN))
-#define __HAL_RCC_GPIOE_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOEEN))
-#define __HAL_RCC_GPIOH_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOHEN))
-#define __HAL_RCC_CRC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_CRCEN))
-#define __HAL_RCC_BKPSRAM_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_BKPSRAMEN))
-#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_CCMDATARAMEN))
-#define __HAL_RCC_DMA1_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA1EN))
-#define __HAL_RCC_DMA2_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2EN))
+#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
-#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
-#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
-#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
-#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
-#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
- * @brief Enable or disable the AHB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
- __HAL_RCC_SYSCFG_CLK_ENABLE();\
- }while(0)
-
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
- __HAL_RCC_SYSCFG_CLK_DISABLE();\
- }while(0)
-
-#define __HAL_RCC_RNG_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_RNGEN))
-#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
-
/**
* @}
*/
@@ -480,30 +455,62 @@ typedef struct
* using it.
* @{
*/
-#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_TIM5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN))
-#define __HAL_RCC_WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
-#define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
-#define __HAL_RCC_PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
-
-#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_PWR_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
/**
* @}
@@ -516,28 +523,70 @@ typedef struct
* using it.
* @{
*/
-#define __HAL_RCC_TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
-#define __HAL_RCC_USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
-#define __HAL_RCC_USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN))
-#define __HAL_RCC_ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
-#define __HAL_RCC_SDIO_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDIOEN))
-#define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
-#define __HAL_RCC_SPI4_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI4EN))
-#define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
-#define __HAL_RCC_TIM9_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM9EN))
-#define __HAL_RCC_TIM10_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM10EN))
-#define __HAL_RCC_TIM11_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM11EN))
+#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
-#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
-#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
-#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
/**
* @}
@@ -551,10 +600,7 @@ typedef struct
#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
-#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
-#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
@@ -562,65 +608,33 @@ typedef struct
#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
-#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
-#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
-#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
/**
* @}
*/
-/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Force Release Reset
- * @brief Force or release AHB2 peripheral reset.
- * @{
- */
-#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
-
-#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
-
-#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
-#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
-/**
- * @}
- */
-
/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
* @brief Force or release APB1 peripheral reset.
* @{
*/
#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
-#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
-#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
/**
* @}
@@ -635,12 +649,9 @@ typedef struct
#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
-#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
-#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
@@ -648,27 +659,14 @@ typedef struct
#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
-#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
-#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
/**
* @}
*/
-/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Force Release Reset
- * @brief Force or release AHB3 peripheral reset.
- * @{
- */
-#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
-#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
-/**
- * @}
- */
-
/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
@@ -680,50 +678,20 @@ typedef struct
#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
/**
* @}
*/
-/** @defgroup RCC_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
- * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
-
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
-
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
-/**
- * @}
- */
-
/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
@@ -732,30 +700,20 @@ typedef struct
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @{
*/
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
/**
* @}
@@ -773,24 +731,18 @@ typedef struct
#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
/**
* @}
@@ -854,6 +806,8 @@ typedef struct
/**
* @brief Macro to configure the External High Speed oscillator (HSE).
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
+ * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
* software should wait on HSERDY flag to be set indicating that HSE clock
* is stable and can be used to clock the PLL and/or system clock.
@@ -882,6 +836,8 @@ typedef struct
/**
* @brief Macro to configure the External Low Speed oscillator (LSE).
+ * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
+ * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
* @note As the LSE is in the Backup domain and write access is denied to
* this domain after reset, you have to enable write access using
* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
@@ -965,89 +921,51 @@ typedef struct
#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
-/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
+/** @brief Macro to configure the PLL clock source.
* @note This function must be used only when the main PLL is disabled.
- * @param __RCC_PLLSource__: specifies the PLL entry clock source.
+ * @param __PLLSOURCE__: specifies the PLL entry clock source.
* This parameter can be one of the following values:
* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
- * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
+ *
+ */
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
+
+/** @brief Macro to configure the PLL multiplication factor.
+ * @note This function must be used only when the main PLL is disabled.
* @param __PLLM__: specifies the division factor for PLL VCO input clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
* @note You have to set the PLLM parameter correctly to ensure that the VCO input
* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
* of 2 MHz to limit PLL jitter.
- * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
- * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
- * @note You have to set the PLLN parameter correctly to ensure that the VCO
- * output frequency is between 192 and 432 MHz.
- * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
- * This parameter must be a number in the range {2, 4, 6, or 8}.
- * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
- * the System clock frequency.
- * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
- * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
- * @note If the USB OTG FS is used in your application, you have to set the
- * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
- * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
- * correctly.
- */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
- (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
- ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \
- ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
- * @{
+ *
*/
-
-/** @brief Macro to configure the I2S clock source (I2SCLK).
- * @note This function must be called before enabling the I2S APB clock.
- * @param __SOURCE__: specifies the I2S clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
- * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
- * used as I2S clock source.
- */
-#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
-
-/** @brief Macros to enable or disable the PLLI2S.
- * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
-#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
-
-/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
- * @note This macro must be used only when the PLLI2S is disabled.
- * @note PLLI2S clock source is common with the main PLL (configured in
- * HAL_RCC_ClockConfig() API).
- * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
- * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
- * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
- * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
- * @param __PLLI2SR__: specifies the division factor for I2S clock
- * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
- * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
- * on the I2S clock frequency.
- */
-#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) | ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
+#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
/**
* @}
- */
-
+ */
+
/** @defgroup RCC_Get_Clock_source Get Clock source
* @{
*/
+/**
+ * @brief Macro to configure the system clock source.
+ * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
+ * This parameter can be one of the following values:
+ * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
+ * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source.
+ */
+#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
/** @brief Macro to get the clock source used as system clock.
* @retval The clock source used as system clock. The returned value can be one
* of the following:
- * - RCC_CFGR_SWS_HSI: HSI used as system clock.
- * - RCC_CFGR_SWS_HSE: HSE used as system clock.
- * - RCC_CFGR_SWS_PLL: PLL used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock.
*/
#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
@@ -1062,6 +980,54 @@ typedef struct
* @}
*/
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the MCO1 clock.
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+ * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+ * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+ * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
+ * @param __MCODIV__ specifies the MCO clock prescaler.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCODIV_1: no division applied to MCOx clock
+ * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+ * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+ * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+ * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+ */
+
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
+
+/** @brief Macro to configure the MCO2 clock.
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+ * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
+ * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
+ * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+ * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
+ * @param __MCODIV__ specifies the MCO clock prescaler.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCODIV_1: no division applied to MCOx clock
+ * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+ * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+ * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+ * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+ * @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
+ * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
+ */
+
+#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (__MCOCLKSOURCE__ | (__MCODIV__ << 3)));
+/**
+ * @}
+ */
+
/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
* @brief macros to manage the specified RCC Flags and interrupts.
* @{
@@ -1155,9 +1121,6 @@ typedef struct
* @}
*/
-/* Include RCC HAL Extension module */
-#include "stm32f4xx_hal_rcc_ex.h"
-
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RCC_Exported_Functions
* @{
@@ -1225,15 +1188,6 @@ void HAL_RCC_CSSCallback(void);
/* Alias word address of PLLON bit */
#define RCC_PLLON_BIT_NUMBER 0x18
#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLON_BIT_NUMBER * 4))
-/* Alias word address of PLLI2SON bit */
-#define RCC_PLLI2SON_BIT_NUMBER 0x1A
-#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4))
-
-/* --- CFGR Register ---*/
-/* Alias word address of I2SSRC bit */
-#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
-#define RCC_I2SSRC_BIT_NUMBER 0x17
-#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_I2SSRC_BIT_NUMBER * 4))
/* --- BDCR Register ---*/
/* Alias word address of RTCEN bit */
@@ -1264,6 +1218,11 @@ void HAL_RCC_CSSCallback(void);
#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
#define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)
+
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+
/**
* @}
*/
@@ -1299,7 +1258,9 @@ void HAL_RCC_CSSCallback(void);
#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
+ ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
+
#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
@@ -1308,10 +1269,6 @@ void HAL_RCC_CSSCallback(void);
#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
-#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
-
-#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
-
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
@@ -1329,9 +1286,6 @@ void HAL_RCC_CSSCallback(void);
#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
-#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
- ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
-
#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
((DIV) == RCC_MCODIV_5))
diff --git a/f4/include/stm32f4xx_hal_rcc_ex.h b/f4/include/stm32f4xx_hal_rcc_ex.h
index 7165609..013970d 100755
--- a/f4/include/stm32f4xx_hal_rcc_ex.h
+++ b/f4/include/stm32f4xx_hal_rcc_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_rcc_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -58,8 +58,164 @@
/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
* @{
*/
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+
+/**
+ * @brief RCC PLL configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PLLState; /*!< The new state of the PLL.
+ This parameter can be a value of @ref RCC_PLL_Config */
+
+ uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */
+
+ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
+
+ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
+ This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
+
+ uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
+ This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
+
+ uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
+ This parameter must be a number between Min_Data = 4 and Max_Data = 15 */
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
+ uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
+ This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx and STM32F479xx
+ devices.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
+#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
+}RCC_PLLInitTypeDef;
+
+#if defined(STM32F446xx)
+/**
+ * @brief PLLI2S Clock structure definition
+ */
+typedef struct
+{
+ uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
+
+ uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+ This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
+
+ uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
+ This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
+
+ uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+
+ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S */
+}RCC_PLLI2SInitTypeDef;
+
+/**
+ * @brief PLLSAI Clock structure definition
+ */
+typedef struct
+{
+ uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
+
+ uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+ This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
+
+ uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
+ This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
+
+ uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI */
+}RCC_PLLSAIInitTypeDef;
+/**
+ * @brief RCC extended clocks structure definition
+ */
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+ RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
+
+ uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+
+ uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI */
+
+ uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
+
+ uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
+
+ uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
+
+ uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
+
+ uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
+
+ uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
+
+ uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
+
+ uint32_t Clk48ClockSelection; /*!< Specifies CK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
+ This parameter can be a value of @ref RCCEx_CK48_Clock_Source */
+
+ uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F446xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/**
+ * @brief RCC extended clocks structure definition
+ */
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
+
+ uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
+ uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
/**
* @brief PLLI2S Clock structure definition
*/
@@ -86,6 +242,11 @@ typedef struct
uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
This parameter must be a number between Min_Data = 192 and Max_Data = 432.
This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
+#if defined(STM32F469xx) || defined(STM32F479xx)
+ uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks.
+ This parameter is only available in STM32F469xx/STM32F479xx devices.
+ This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
+#endif /* STM32F469xx || STM32F479xx */
uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 15.
@@ -126,18 +287,24 @@ typedef struct
uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+#if defined(STM32F469xx) || defined(STM32F479xx)
+ uint32_t Clk48ClockSelection; /*!< Specifies CK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
+ This parameter can be a value of @ref RCCEx_CK48_Clock_Source */
+ uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
+#endif /* STM32F469xx || STM32F479xx */
}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
/**
* @brief PLLI2S Clock structure definition
*/
typedef struct
{
-#if defined(STM32F411xE)
+#if defined(STM32F411xE)
uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
#endif /* STM32F411xE */
@@ -165,7 +332,7 @@ typedef struct
This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
- This parameter can be a value of @ref RCC_RTC_Clock_Source */
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
@@ -181,36 +348,126 @@ typedef struct
/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
* @{
*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+/*------------------- Peripheral Clock source for STM32F410xx ----------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000008)
+#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000010)
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------- Peripheral Clock source for STM32F446xx ----------------*/
+#if defined(STM32F446xx)
+#define RCC_PERIPHCLK_I2S_APB1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_I2S_APB2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00000008)
+#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000040)
+#define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000080)
+#define RCC_PERIPHCLK_CK48 ((uint32_t)0x00000100)
+#define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000200)
+#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x00000400)
+#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000800)
+#endif /* STM32F446xx */
+/*-----------------------------------------------------------------------------*/
+
+/*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
+#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040)
+#define RCC_PERIPHCLK_CK48 ((uint32_t)0x00000080)
+#define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000100)
+#endif /* STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040)
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/*----------------------------------------------------------------------------*/
+/*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000004)
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+/*----------------------------------------------------------------------------*/
/**
* @}
*/
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
-/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
+ * @{
+ */
+#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
+#define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+
+/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
* @{
*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
#define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
#define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
#define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
-
+
+/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
+ * @{
+ */
+#if defined(STM32F446xx)
+#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000002)
+#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000004)
+#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000006)
+#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000008)
+#endif /* STM32F446xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
+ * @{
+ */
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000002)
+#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000004)
+#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000006)
+#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000008)
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
* @{
*/
@@ -230,6 +487,162 @@ typedef struct
/**
* @}
*/
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup RCCEx_CK48_Clock_Source RCC CK48 Clock Source
+ * @{
+ */
+#define RCC_CK48CLKSOURCE_PLLQ ((uint32_t)0x00000000)
+#define RCC_CK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
+ * @{
+ */
+#define RCC_SDIOCLKSOURCE_CK48 ((uint32_t)0x00000000)
+#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
+ * @{
+ */
+#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000)
+#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL)
+/**
+ * @}
+ */
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F446xx)
+/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
+ * @{
+ */
+#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
+#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
+#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
+#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
+ * @{
+ */
+#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
+#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
+#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
+#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
+ * @{
+ */
+#define RCC_I2SAPB1CLKSOURCE_PLLI2S ((uint32_t)0x00000000)
+#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
+#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
+#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
+ * @{
+ */
+#define RCC_I2SAPB2CLKSOURCE_PLLI2S ((uint32_t)0x00000000)
+#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
+#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
+#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
+ * @{
+ */
+#define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000)
+#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
+#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
+ * @{
+ */
+#define RCC_CECCLKSOURCE_HSI ((uint32_t)0x00000000)
+#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CK48_Clock_Source RCC CK48 Clock Source
+ * @{
+ */
+#define RCC_CK48CLKSOURCE_PLLQ ((uint32_t)0x00000000)
+#define RCC_CK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
+ * @{
+ */
+#define RCC_SDIOCLKSOURCE_CK48 ((uint32_t)0x00000000)
+#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
+ * @{
+ */
+#define RCC_SPDIFRXCLKSOURCE_PLLR ((uint32_t)0x00000000)
+#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
+/**
+ * @}
+ */
+
+#endif /* STM32F446xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+
+/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
+ * @{
+ */
+#define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000)
+#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
+#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
+ * @{
+ */
+#define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000)
+#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
+#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
+ * @{
+ */
+#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
+#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
+#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
+#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
+/**
+ * @}
+ */
/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
* @{
@@ -239,9 +652,24 @@ typedef struct
/**
* @}
*/
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
+ * @{
+ */
+#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
+#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+ STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
-#if defined(STM32F411xE)
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
* @{
*/
@@ -250,7 +678,38 @@ typedef struct
/**
* @}
*/
-#endif /* STM32F411xE */
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
+ * @{
+ */
+#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
+#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
+#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
+#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
+ * @{
+ */
+#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
+#define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0
+#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
+#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
+/**
+ * @}
+ */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
/**
* @}
@@ -260,26 +719,135 @@ typedef struct
/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
* @{
*/
-/*----------------------------------- STM32F42xxx/STM32F43xxx----------------------------------*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
-/** @brief Enables or disables the AHB1 peripheral clock.
+/*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
-#define __HAL_RCC_GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
-#define __HAL_RCC_GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
-#define __HAL_RCC_GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
-#define __HAL_RCC_GPIOJ_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOJEN))
-#define __HAL_RCC_GPIOK_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOKEN))
-#define __HAL_RCC_DMA2D_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2DEN))
-#define __HAL_RCC_ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
-#define __HAL_RCC_ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
-#define __HAL_RCC_ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
-#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
-
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
@@ -292,6 +860,9 @@ typedef struct
#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
/**
* @brief Enable ETHERNET clock.
@@ -309,58 +880,252 @@ typedef struct
__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
__HAL_RCC_ETHMAC_CLK_DISABLE(); \
} while(0)
-
-/** @brief Enable or disable the AHB2 peripheral clock.
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
-
-#define __HAL_RCC_DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
+ #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
-#if defined(STM32F437xx)|| defined(STM32F439xx)
-#define __HAL_RCC_CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
-#define __HAL_RCC_HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
+#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
+#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_HASH_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
-#endif /* STM32F437xx || STM32F439xx */
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\
+ }while(0)
+
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
+ __HAL_RCC_SYSCFG_CLK_DISABLE();\
+ }while(0)
+
+#define __HAL_RCC_RNG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+/**
+ * @}
+ */
-/** @brief Enables or disables the AHB3 peripheral clock.
+/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB3 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
-#define __HAL_RCC_FMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN))
+#define __HAL_RCC_FMC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
-/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
-#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
-#define __HAL_RCC_TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
-#define __HAL_RCC_TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
-#define __HAL_RCC_WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
-#define __HAL_RCC_USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
-#define __HAL_RCC_UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
-#define __HAL_RCC_UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
-#define __HAL_RCC_CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
-#define __HAL_RCC_CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
-#define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
-#define __HAL_RCC_UART7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART7EN))
-#define __HAL_RCC_UART8_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART8EN))
-
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
@@ -369,71 +1134,190 @@ typedef struct
#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
+/**
+ * @}
+ */
-/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
-#define __HAL_RCC_TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
-#define __HAL_RCC_ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
-#define __HAL_RCC_ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
-#define __HAL_RCC_SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
-#define __HAL_RCC_SPI6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI6EN))
-#define __HAL_RCC_SAI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SAI1EN))
-
-#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
-#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
-#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
-#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
-#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
-
-#if defined(STM32F429xx)|| defined(STM32F439xx)
-#define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN))
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
+#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
+
+#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
-#endif /* STM32F429xx || STM32F439xx */
+#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_DSI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-/** @brief Force or release AHB1 peripheral reset.
- */
+#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
+ * @brief Force or release AHB1 peripheral reset.
+ */
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
-#define __HAL_RCC_OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
-#define __HAL_RCC_OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
-
-/** @brief Force or release AHB2 peripheral reset.
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
+ * @brief Force or release AHB2 peripheral reset.
+ * @{
*/
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+
+#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
-#if defined(STM32F437xx)|| defined(STM32F439xx)
+#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
-#endif /* STM32F437xx || STM32F439xx */
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
+/**
+ * @}
+ */
-/** @brief Force or release AHB3 peripheral reset
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
+ * @brief Force or release AHB3 peripheral reset.
+ * @{
*/
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
-
-/** @brief Force or release APB1 peripheral reset.
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
+#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
*/
#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
@@ -448,7 +1332,17 @@ typedef struct
#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
-
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
@@ -462,30 +1356,51 @@ typedef struct
#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
+/**
+ * @}
+ */
-/** @brief Force or release APB2 peripheral reset.
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
*/
#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
-
+#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+
+#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
-#if defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
-#endif /* STM32F429xx|| STM32F439xx */
+#endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST))
+#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
-/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
- */
+ */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
@@ -494,13 +1409,19 @@ typedef struct
#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
-#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
@@ -509,30 +1430,49 @@ typedef struct
#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
-#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
-
-/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
*/
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+
#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
-#if defined(STM32F437xx)|| defined(STM32F439xx)
+#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
-#endif /* STM32F437xx || STM32F439xx */
-
-/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
@@ -541,7 +1481,16 @@ typedef struct
#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
-/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
@@ -560,7 +1509,17 @@ typedef struct
#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
-
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
@@ -574,8 +1533,12 @@ typedef struct
#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
-
-/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
@@ -587,7 +1550,13 @@ typedef struct
#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
@@ -595,46 +1564,147 @@ typedef struct
#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
-#if defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
-#endif /* STM32F429xx || STM32F439xx */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
-/*---------------------------------------------------------------------------------------------*/
+#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN))
+#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
-/*----------------------------------- STM32F40xxx/STM32F41xxx----------------------------------*/
+/*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
-/** @brief Enables or disables the AHB1 peripheral clock.
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
-#define __HAL_RCC_GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
-#define __HAL_RCC_GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
-#define __HAL_RCC_GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
-
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
-
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
#if defined(STM32F407xx)|| defined(STM32F417xx)
/**
* @brief Enable ETHERNET clock.
*/
-#define __HAL_RCC_ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
-#define __HAL_RCC_ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
-#define __HAL_RCC_ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
-#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
-#define __HAL_RCC_ETH_CLK_ENABLE() do { \
- __HAL_RCC_ETHMAC_CLK_ENABLE(); \
- __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
- __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
- } while(0)
+#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ETH_CLK_ENABLE() do { \
+ __HAL_RCC_ETHMAC_CLK_ENABLE(); \
+ __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
+ __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
+ } while(0)
/**
* @brief Disable ETHERNET clock.
@@ -649,93 +1719,311 @@ typedef struct
__HAL_RCC_ETHMAC_CLK_DISABLE(); \
} while(0)
#endif /* STM32F407xx || STM32F417xx */
-
-/** @brief Enable or disable the AHB2 peripheral clock.
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\
+ }while(0)
+
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
+ __HAL_RCC_SYSCFG_CLK_DISABLE();\
+ }while(0)
+
+#define __HAL_RCC_RNG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+
#if defined(STM32F407xx)|| defined(STM32F417xx)
-#define __HAL_RCC_DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
+#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
#endif /* STM32F407xx || STM32F417xx */
#if defined(STM32F415xx) || defined(STM32F417xx)
-#define __HAL_RCC_CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
-#define __HAL_RCC_HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
-
+#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_HASH_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
#endif /* STM32F415xx || STM32F417xx */
+/**
+ * @}
+ */
-/** @brief Enables or disables the AHB3 peripheral clock.
+/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB3 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
-#define __HAL_RCC_FSMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FSMCEN))
+#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
+/**
+ * @}
+ */
-/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
-#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
-#define __HAL_RCC_TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
-#define __HAL_RCC_TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
-#define __HAL_RCC_WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
-#define __HAL_RCC_USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
-#define __HAL_RCC_UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
-#define __HAL_RCC_UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
-#define __HAL_RCC_CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
-#define __HAL_RCC_CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
-#define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
-
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+/**
+ * @}
+ */
-/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
-#define __HAL_RCC_TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
-#define __HAL_RCC_ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
-#define __HAL_RCC_ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
-
-#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
-#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+/**
+ * @}
+ */
-/** @brief Force or release AHB1 peripheral reset.
- */
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
+ * @brief Force or release AHB1 peripheral reset.
+ */
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
-#define __HAL_RCC_OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
-#define __HAL_RCC_OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+ * @}
+ */
-/** @brief Force or release AHB2 peripheral reset.
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
+ * @brief Force or release AHB2 peripheral reset.
*/
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
+
#if defined(STM32F407xx)|| defined(STM32F417xx)
#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
@@ -747,15 +2035,32 @@ typedef struct
#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
-
#endif /* STM32F415xx || STM32F417xx */
+
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
-/** @brief Force or release AHB3 peripheral reset
+#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+/**
+ * @}
*/
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
+ * @brief Force or release AHB3 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
+
#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
+/**
+ * @}
+ */
-/** @brief Force or release APB1 peripheral reset.
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
*/
#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
@@ -768,7 +2073,17 @@ typedef struct
#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
@@ -780,18 +2095,35 @@ typedef struct
#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+/**
+ * @}
+ */
-/** @brief Force or release APB2 peripheral reset.
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
*/
#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+
+#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
-
-/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
- */
+ */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
@@ -800,9 +2132,15 @@ typedef struct
#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
-#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
-
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
@@ -811,15 +2149,30 @@ typedef struct
#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
-#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
+/**
+ * @}
+ */
-/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
*/
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+
#if defined(STM32F407xx)|| defined(STM32F417xx)
#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
@@ -832,8 +2185,12 @@ typedef struct
#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
#endif /* STM32F415xx || STM32F417xx */
-
-/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
@@ -841,8 +2198,12 @@ typedef struct
*/
#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
-
-/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
@@ -859,7 +2220,17 @@ typedef struct
#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
-
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
@@ -871,8 +2242,12 @@ typedef struct
#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
-
-/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
@@ -881,62 +2256,1657 @@ typedef struct
#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+/**
+ * @}
+ */
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-/*---------------------------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------*/
-/*------------------------------------------ STM32F411xx --------------------------------------*/
-#if defined(STM32F411xE)
-/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
- */
-#define __HAL_RCC_SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
-#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
-
-/** @brief Force or release APB2 peripheral reset.
+/*------------------------- STM32F401xE/STM32F401xC --------------------------*/
+#if defined(STM32F401xC) || defined(STM32F401xE)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
*/
-#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
-#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
-
-/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
- */
-#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
-#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#endif /* STM32F411xE */
-/*---------------------------------------------------------------------------------------------*/
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+/**
+ * @}
+ */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
-
-/** @brief Macro to configure the Timers clocks prescalers
- * @note This feature is only available with STM32F429x/439x Devices.
- * @param __PRESC__ : specifies the Timers clocks prescalers selection
- * This parameter can be one of the following values:
- * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
- * equal to HPRE if PPREx is corresponding to division by 1 or 2,
- * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
- * division by 4 or more.
- * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
- * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
- * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
- * to division by 8 or more.
- */
-#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\
+ }while(0)
+
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
+ __HAL_RCC_SYSCFG_CLK_DISABLE();\
+ }while(0)
+/**
+ * @}
+ */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F411xE */
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+/**
+ * @}
+ */
-#if defined(STM32F411xE)
-
-/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
+ * @brief Force or release AHB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
+ * @brief Force or release AHB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+
+#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+
+#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
+#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
+ * @brief Force or release AHB3 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+/**
+ * @}
+ */
+#endif /* STM32F401xC || STM32F401xE*/
+/*----------------------------------------------------------------------------*/
+
+/*-------------------------------- STM32F410xx -------------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_RNG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB1) peripheral clock.
+ */
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
+#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ */
+#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
+ * @brief Force or release AHB1 peripheral reset.
+ */
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST))
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
+ * @brief Force or release AHB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB2_FORCE_RESET()
+#define __HAL_RCC_AHB2_RELEASE_RESET()
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
+ * @brief Force or release AHB3 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB3_FORCE_RESET()
+#define __HAL_RCC_AHB3_RELEASE_RESET()
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ */
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ */
+#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+ */
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+ */
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
+/**
+ * @}
+ */
+
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*----------------------------------------------------------------------------*/
+
+/*-------------------------------- STM32F411xx -------------------------------*/
+#if defined(STM32F411xE)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\
+ }while(0)
+
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
+ __HAL_RCC_SYSCFG_CLK_DISABLE();\
+ }while(0)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+/**
+ * @}
+ */
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ */
+#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
+ * @brief Force or release AHB1 peripheral reset.
+ */
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
+ * @brief Force or release AHB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+
+#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
+ * @brief Force or release AHB3 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ */
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ */
+#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+
+#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+ */
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+ */
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+/**
+ * @}
+ */
+#endif /* STM32F411xE */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F446xx -----------------------------*/
+#if defined(STM32F446xx)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\
+ }while(0)
+
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
+ __HAL_RCC_SYSCFG_CLK_DISABLE();\
+ }while(0)
+
+#define __HAL_RCC_RNG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB3 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __HAL_RCC_FMC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
+#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CEC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
+#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
+#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
+ * @brief Force or release AHB1 peripheral reset.
+ */
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
+ * @brief Force or release AHB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+
+#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
+ * @brief Force or release AHB3 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
+
+#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
+#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
+
+#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
+#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ */
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ */
+#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
+#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
+#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+
+#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
+#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
+/**
+ * @}
+ */
+
+#endif /* STM32F446xx */
+/*----------------------------------------------------------------------------*/
+/*------------------------------- PLL Configuration --------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
+ * @note This function must be used only when the main PLL is disabled.
+ * @param __RCC_PLLSource__: specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+ * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
+ * @param __PLLM__: specifies the division factor for PLL VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLL jitter.
+ * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO
+ * output frequency is between 192 and 432 MHz.
+ *
+ * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ *
+ * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ * @note If the USB OTG FS is used in your application, you have to set the
+ * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+ * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
+ * correctly.
+ *
+ * @param __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx devices.
+ *
+ */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
+ (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \
+ ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
+ ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
+ ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) | \
+ ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
+#else
+/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
+ * @note This function must be used only when the main PLL is disabled.
+ * @param __RCC_PLLSource__: specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+ * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
+ * @param __PLLM__: specifies the division factor for PLL VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLL jitter.
+ * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO
+ * output frequency is between 192 and 432 MHz.
+ *
+ * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ *
+ * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ * @note If the USB OTG FS is used in your application, you have to set the
+ * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+ * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
+ * correctly.
+ *
+ */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
+ (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \
+ ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
+ ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
+ ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
+ #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------PLLI2S Configuration ---------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
+
+/** @brief Macros to enable or disable the PLLI2S.
+ * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
+#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+#if defined(STM32F446xx)
+/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
+ * @note This macro must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * HAL_RCC_ClockConfig() API).
+ * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 1 MHz to limit PLLI2S jitter.
+ *
+ * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+ *
+ * @param __PLLI2SP__: specifies division factor for SPDIFRX Clock.
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ * @note the PLLI2SP parameter is only available with STM32F446xx Devices
+ *
+ * @param __PLLI2SR__: specifies the division factor for I2S clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ *
+ * @param __PLLI2SQ__: specifies the division factor for SAI clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
+ (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
+ ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
+ ((((__PLLI2SP__) >> 1) -1) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\
+ ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\
+ ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
+#else
+/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
+ * @note This macro must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * HAL_RCC_ClockConfig() API).
+ * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+ *
+ * @param __PLLI2SR__: specifies the division factor for I2S clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ *
+ */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
+ (RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
+ ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
+#endif /* STM32F446xx */
+
+#if defined(STM32F411xE)
+/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
* @note This macro must be used only when the PLLI2S is disabled.
* @note This macro must be used only when the PLLI2S is disabled.
* @note PLLI2S clock source is common with the main PLL (configured in
* HAL_RCC_ClockConfig() API).
* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices
* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
* of 2 MHz to limit PLLI2S jitter.
@@ -949,85 +3919,178 @@ typedef struct
* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
* on the I2S clock frequency.
*/
-#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
- ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)) | (__PLLI2SM__))
+#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
+ ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
+ ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
#endif /* STM32F411xE */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
+ * @note This macro must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * HAL_RCC_ClockConfig() API)
+ * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+ * @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ * @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx
+ * Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
+ * @param __PLLI2SR__: specifies the division factor for I2S clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ */
+#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) |\
+ ((__PLLI2SQ__) << 24) |\
+ ((__PLLI2SR__) << 28))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------------------ PLLSAI Configuration ------------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @brief Macros to Enable or Disable the PLLISAI.
- * @note The PLLSAI is only available with STM32F429x/439x Devices.
+ * @note The PLLSAI is only available with STM32F429x/439x Devices.
* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
*/
#define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE)
#define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE)
+#if defined(STM32F446xx)
/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
- * @note The PLLSAI is only available with STM32F429x/439x Devices.
- * @note This function must be used only when the PLLSAI is disabled.
- * @note PLLSAI clock source is common with the main PLL (configured in
- * RCC_PLLConfig function )
+ *
+ * @param __PLLSAIM__: specifies the division factor for PLLSAI VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 1 MHz to limit PLLI2S jitter.
+ * @note The PLLSAIM parameter is only used with STM32F446xx Devices
+ *
* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
- * @param __PLLSAIQ__: specifies the division factor for SAI1 clock
+ *
+ * @param __PLLSAIP__: specifies division factor for OTG FS, SDIO and RNG clocks.
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ * @note the PLLSAIP parameter is only available with STM32F446xx Devices
+ *
+ * @param __PLLSAIQ__: specifies the division factor for SAI clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ *
* @param __PLLSAIR__: specifies the division factor for LTDC clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
- */
-#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
+ * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
+ */
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
+ (RCC->PLLSAICFGR = ((__PLLSAIM__) | \
+ ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) | \
+ ((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) | \
+ ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))))
+#endif /* STM32F446xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
+ *
+ * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+ *
+ * @param __PLLSAIP__: specifies division factor for SDIO and CLK48 clocks.
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ *
+ * @param __PLLSAIQ__: specifies the division factor for SAI clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ *
+ * @param __PLLSAIR__: specifies the division factor for LTDC clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ */
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
+ (RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\
+ ((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\
+ ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) |\
+ ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
+#endif /* STM32F469xx || STM32F479xx */
-/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
- * @note This macro must be used only when the PLLI2S is disabled.
- * @note PLLI2S clock source is common with the main PLL (configured in
- * HAL_RCC_ClockConfig() API)
- * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
+ *
+ * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
- * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
- * @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
- * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
- * @note the PLLI2SQ parameter is only available with STM32F429x/439x Devices
- * and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
- * @param __PLLI2SR__: specifies the division factor for I2S clock
+ *
+ * @param __PLLSAIQ__: specifies the division factor for SAI clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ *
+ * @param __PLLSAIR__: specifies the division factor for LTDC clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
- * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
- * on the I2S clock frequency.
+ * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
*/
-#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
-
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
+ (RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) | \
+ ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) | \
+ ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
- * @note The SAI peripheral is only available with STM32F429x/439x Devices.
- * @note This function must be called before enabling the PLLI2S.
- * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
+ * @note This function must be called before enabling the PLLI2S.
+ * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock.
* This parameter must be a number between 1 and 32.
* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
*/
#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
- * @note The SAI peripheral is only available with STM32F429x/439x Devices.
* @note This function must be called before enabling the PLLSAI.
* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
*/
#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
*
- * @note The LTDC peripheral is only available with STM32F429x/439x Devices.
+ * @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
* @note This function must be called before enabling the PLLSAI.
* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
- */
+ */
#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
-
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------------- Peripheral Clock selection -----------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
+/** @brief Macro to configure the I2S clock source (I2SCLK).
+ * @note This function must be called before enabling the I2S APB clock.
+ * @param __SOURCE__: specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
+ * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source.
+ */
+#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
/** @brief Macro to configure SAI1BlockA clock source selection.
- * @note The SAI peripheral is only available with STM32F429x/439x Devices.
+ * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
* @note This function must be called before enabling PLLSAI, PLLI2S and
* the SAI clock.
* @param __SOURCE__: specifies the SAI Block A clock source.
@@ -1042,7 +4105,7 @@ typedef struct
#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
/** @brief Macro to configure SAI1BlockB clock source selection.
- * @note The SAI peripheral is only available with STM32F429x/439x Devices.
+ * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
* @note This function must be called before enabling PLLSAI, PLLI2S and
* the SAI clock.
* @param __SOURCE__: specifies the SAI Block B clock source.
@@ -1055,7 +4118,302 @@ typedef struct
* used as SAI1 Block B clock.
*/
#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F446xx)
+/** @brief Macro to configure SAI1 clock source selection.
+ * @note This configuration is only available with STM32F446xx Devices.
+ * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param __SOURCE__: specifies the SAI1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
+ * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
+ * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
+ * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
+ */
+#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
+
+/** @brief Macro to Get SAI1 clock source selection.
+ * @note This configuration is only available with STM32F446xx Devices.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
+ * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
+ * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
+ * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
+ */
+#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
+
+/** @brief Macro to configure SAI2 clock source selection.
+ * @note This configuration is only available with STM32F446xx Devices.
+ * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param __SOURCE__: specifies the SAI2 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
+ * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
+ * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
+ * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
+ */
+#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
+
+/** @brief Macro to Get SAI2 clock source selection.
+ * @note This configuration is only available with STM32F446xx Devices.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
+ * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
+ * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
+ * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
+ */
+#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
+
+/** @brief Macro to configure I2S APB1 clock source selection.
+ * @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
+ * @param __SOURCE__: specifies the I2S APB1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
+ * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
+
+/** @brief Macro to Get I2S APB1 clock source selection.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
+ * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
+
+/** @brief Macro to configure I2S APB2 clock source selection.
+ * @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
+ * @param __SOURCE__: specifies the SAI Block A clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
+ * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
+
+/** @brief Macro to Get I2S APB2 clock source selection.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
+ * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
+
+/** @brief Macro to configure the CEC clock.
+ * @param __SOURCE__: specifies the CEC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
+ * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+ */
+#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the CEC clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
+ * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+ */
+#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
+
+/** @brief Macro to configure the FMPI2C1 clock.
+ * @param __SOURCE__: specifies the FMPI2C1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+ */
+#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the FMPI2C1 clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+ */
+#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
+
+/** @brief Macro to configure the CLK48 clock.
+ * @param __SOURCE__: specifies the CK48 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
+ * @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
+ */
+#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the CLK48 clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
+ * @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
+ */
+#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
+
+/** @brief Macro to configure the SDIO clock.
+ * @param __SOURCE__: specifies the SDIO clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
+ * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
+ */
+#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the SDIO clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
+ * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
+ */
+#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
+
+/** @brief Macro to configure the SPDIFRX clock.
+ * @param __SOURCE__: specifies the SPDIFRX clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
+ * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
+ */
+#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the SPDIFRX clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
+ * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
+ */
+#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
+#endif /* STM32F446xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+
+/** @brief Macro to configure the CLK48 clock.
+ * @param __SOURCE__: specifies the CK48 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
+ * @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
+ */
+#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the CLK48 clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
+ * @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
+ */
+#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
+
+/** @brief Macro to configure the SDIO clock.
+ * @param __SOURCE__: specifies the SDIO clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
+ * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
+ */
+#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the SDIO clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
+ * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
+ */
+#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))
+
+/** @brief Macro to configure the DSI clock.
+ * @param __SOURCE__: specifies the DSI clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
+ * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
+ */
+#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the DSI clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
+ * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
+ */
+#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))
+
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** @brief Macro to configure I2S clock source selection.
+ * @param __SOURCE__: specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
+ * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+ * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
+ */
+#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
+
+/** @brief Macro to Get I2S clock source selection.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
+ * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+ * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
+ */
+#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
+
+/** @brief Macro to configure the FMPI2C1 clock.
+ * @param __SOURCE__: specifies the FMPI2C1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+ */
+#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the FMPI2C1 clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+ */
+#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
+
+/** @brief Macro to configure the LPTIM1 clock.
+ * @param __SOURCE__: specifies the LPTIM1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_LPTIM1CLKSOURCE_PCLK: APB selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+ */
+#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the LPTIM1 clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_LPTIM1CLKSOURCE_PCLK: APB selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+ */
+#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
+/** @brief Macro to configure the Timers clocks prescalers
+ * @note This feature is only available with STM32F429x/439x Devices.
+ * @param __PRESC__ : specifies the Timers clocks prescalers selection
+ * This parameter can be one of the following values:
+ * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
+ * equal to HPRE if PPREx is corresponding to division by 1 or 2,
+ * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
+ * division by 4 or more.
+ * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
+ * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
+ * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
+ * to division by 8 or more.
+ */
+#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\
+ STM32F446xx || STM32F469xx || STM32F479xx */
+
+/*----------------------------------------------------------------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @brief Enable PLLSAI_RDY interrupt.
*/
#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
@@ -1078,7 +4436,28 @@ typedef struct
*/
#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** @defgroup RCCEx_MCO1_Enable MCO1 Enable
+ * @brief Macros to enable or disable the RCC MCO1 feature.
+ */
+#define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE)
+#define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_MCO2_Enable MCO2 Enable
+ * @brief Macros to enable or disable the RCC MCO2 feature.
+ */
+#define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE)
+#define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE)
+/**
+ * @}
+ */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
/**
* @}
*/
@@ -1094,9 +4473,14 @@ typedef struct
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
-#if defined(STM32F411xE)
+#if defined(STM32F446xx)
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
+#endif /* STM32F446xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
-#endif /* STM32F411xE */
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
@@ -1110,25 +4494,69 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
* @{
*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+
/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
* @brief RCC registers bit address in the alias region
* @{
*/
-/* --- CR Register ---*/
+/* --- CR Register ---*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* Alias word address of PLLSAION bit */
#define RCC_PLLSAION_BIT_NUMBER 0x1C
#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLSAION_BIT_NUMBER * 4))
+#define PLLSAI_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
+/* Alias word address of PLLI2SON bit */
+#define RCC_PLLI2SON_BIT_NUMBER 0x1A
+#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+
/* --- DCKCFGR Register ---*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
/* Alias word address of TIMPRE bit */
#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
#define RCC_TIMPRE_BIT_NUMBER 0x18
#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+/* --- CFGR Register ---*/
+#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
+/* Alias word address of I2SSRC bit */
+#define RCC_I2SSRC_BIT_NUMBER 0x17
+#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_I2SSRC_BIT_NUMBER * 4))
+
+#define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/* Alias word address of MCO1EN bit */
+#define RCC_MCO1EN_BIT_NUMBER 0x8
+#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4))
+
+/* Alias word address of MCO2EN bit */
+#define RCC_MCO2EN_BIT_NUMBER 0x9
+#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
/**
* @}
*/
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
/**
* @}
@@ -1141,35 +4569,167 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
* @{
*/
+
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000007F))
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000007))
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
-#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
-#define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
-#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000001F))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F446xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000FFF))
+#endif /* STM32F446xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000001FF))
+#endif /* STM32F469xx || STM32F479xx */
+
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+
+#define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
+
+#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+
+#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+
#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+
#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
-#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
+
+#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
((VALUE) == RCC_PLLSAIDIVR_4) ||\
((VALUE) == RCC_PLLSAIDIVR_8) ||\
((VALUE) == RCC_PLLSAIDIVR_16))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F411xE) || defined(STM32F446xx)
+#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
+
+#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
+ ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
+#endif /* STM32F411xE || STM32F446xx */
-#if defined(STM32F411xE)
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
-#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
((MODE) == RCC_LSE_HIGHDRIVE_MODE))
-#endif /* STM32F411xE */
+#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) ||\
+ ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
+ ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
+
+#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) ||\
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
+
+#define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) ||\
+ ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F446xx)
+#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+
+#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\
+ ((VALUE) == RCC_PLLI2SP_DIV4) ||\
+ ((VALUE) == RCC_PLLI2SP_DIV6) ||\
+ ((VALUE) == RCC_PLLI2SP_DIV8))
+
+#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
+
+#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
+ ((VALUE) == RCC_PLLSAIP_DIV4) ||\
+ ((VALUE) == RCC_PLLSAIP_DIV6) ||\
+ ((VALUE) == RCC_PLLSAIP_DIV8))
+
+#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\
+ ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\
+ ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
+
+#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
+
+#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
+ ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\
+ ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
+
+ #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
+ ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\
+ ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
+
+#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) ||\
+ ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
+ ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
+
+#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) ||\
+ ((SOURCE) == RCC_CECCLKSOURCE_LSE))
+
+#define IS_RCC_CK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CK48CLKSOURCE_PLLQ) ||\
+ ((SOURCE) == RCC_CK48CLKSOURCE_PLLSAIP))
+
+#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CK48) ||\
+ ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
+
+#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
+#endif /* STM32F446xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+
+#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
+ ((VALUE) == RCC_PLLSAIP_DIV4) ||\
+ ((VALUE) == RCC_PLLSAIP_DIV6) ||\
+ ((VALUE) == RCC_PLLSAIP_DIV8))
+
+#define IS_RCC_CK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CK48CLKSOURCE_PLLQ) ||\
+ ((SOURCE) == RCC_CK48CLKSOURCE_PLLSAIP))
+
+#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CK48) ||\
+ ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
+
+#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
+
+#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
+ ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
+
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
+ ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \
+ ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
/**
* @}
*/
diff --git a/f4/include/stm32f4xx_hal_rng.h b/f4/include/stm32f4xx_hal_rng.h
index c1c5e1c..bd7a45b 100755
--- a/f4/include/stm32f4xx_hal_rng.h
+++ b/f4/include/stm32f4xx_hal_rng.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_rng.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of RNG HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -44,7 +44,9 @@
#endif
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -352,7 +354,8 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F410xx || STM32F469xx || STM32F479xx */
#ifdef __cplusplus
}
diff --git a/f4/include/stm32f4xx_hal_rtc.h b/f4/include/stm32f4xx_hal_rtc.h
index 9fc47ed..cb7c4bc 100755
--- a/f4/include/stm32f4xx_hal_rtc.h
+++ b/f4/include/stm32f4xx_hal_rtc.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_rtc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -110,13 +110,20 @@ typedef struct
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
- uint32_t SubSeconds; /*!< Specifies the RTC Time SubSeconds.
- This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
- This parameter can be a value of @ref RTC_AM_PM_Definitions */
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */
+ uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
+ This parameter corresponds to a time unit range between [0-1] Second
+ with [1 Sec / SecondFraction +1] granularity */
+
+ uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
+ corresponding to Synchronous pre-scaler factor value (PREDIV_S)
+ This parameter corresponds to a time unit range between [0-1] Second
+ with [1 Sec / SecondFraction +1] granularity.
+ This field will be used only by HAL_RTC_GetTime function */
+
uint32_t DayLightSaving; /*!< Specifies DayLight Save Operation.
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
@@ -503,7 +510,7 @@ typedef struct
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
/**
* @brief Get the selected RTC Alarm's flag status.
@@ -527,7 +534,7 @@ typedef struct
* @arg RTC_FLAG_ALRBF
* @retval None
*/
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
@@ -710,7 +717,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
#define RTC_TIMEOUT_VALUE 1000
-#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
/**
* @}
*/
diff --git a/f4/include/stm32f4xx_hal_rtc_ex.h b/f4/include/stm32f4xx_hal_rtc_ex.h
index 0a1bef9..b9c8d64 100755
--- a/f4/include/stm32f4xx_hal_rtc_ex.h
+++ b/f4/include/stm32f4xx_hal_rtc_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_rtc_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of RTC HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -145,8 +145,8 @@ typedef struct
/** @defgroup RTCEx_Tamper_Pins_Selection RTC tamper Pins Selection
* @{
*/
-#define RTC_TAMPERPIN_PC13 ((uint32_t)0x00000000)
-#define RTC_TAMPERPIN_PI8 ((uint32_t)0x00010000)
+#define RTC_TAMPERPIN_DEFAULT ((uint32_t)0x00000000)
+#define RTC_TAMPERPIN_POS1 ((uint32_t)0x00010000)
/**
* @}
*/
@@ -154,8 +154,8 @@ typedef struct
/** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection
* @{
*/
-#define RTC_TIMESTAMPPIN_PC13 ((uint32_t)0x00000000)
-#define RTC_TIMESTAMPPIN_PI8 ((uint32_t)0x00020000)
+#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)
+#define RTC_TIMESTAMPPIN_POS1 ((uint32_t)0x00020000)
/**
* @}
*/
@@ -395,7 +395,7 @@ typedef struct
* @arg RTC_FLAG_WUTF
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
* @brief Enable interrupt on the RTC Wake-up Timer associated Exti line.
@@ -558,7 +558,7 @@ typedef struct
* @arg RTC_FLAG_TSF
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
* @}
@@ -638,7 +638,7 @@ typedef struct
* @arg RTC_FLAG_TAMP2F
* @retval None
*/
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
* @}
*/
@@ -713,7 +713,7 @@ typedef struct
* @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
* @retval Line Status.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
* @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
@@ -811,11 +811,11 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe
HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
-void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
@@ -829,10 +829,10 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_
/* RTC Wake-up functions ******************************************************/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
-uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
/**
* @}
@@ -842,8 +842,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin
* @{
*/
/* Extension Control functions ************************************************/
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value);
HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc);
@@ -863,7 +863,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
* @{
*/
/* Extension RTC features functions *******************************************/
-void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
/**
* @}
@@ -879,8 +879,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
* @{
*/
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wake-up event */
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR21) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR22) /*!< External interrupt line 22 Connected to the RTC Wake-up event */
/**
* @}
*/
@@ -915,11 +915,14 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
((BKP) == RTC_BKP_DR19))
#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
-#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFF6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
-#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TAMPERPIN_PC13) || \
- ((PIN) == RTC_TAMPERPIN_PI8))
-#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_PC13) || \
- ((PIN) == RTC_TIMESTAMPPIN_PI8))
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)!(RTC_TAFCR_TAMP1E | RTC_TAFCR_TAMP2E))) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+
+#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TAMPERPIN_DEFAULT) || \
+ ((PIN) == RTC_TAMPERPIN_POS1))
+
+#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT) || \
+ ((PIN) == RTC_TIMESTAMPPIN_POS1))
+
#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
diff --git a/f4/include/stm32f4xx_hal_sai.h b/f4/include/stm32f4xx_hal_sai.h
index 3a77190..36ac635 100755
--- a/f4/include/stm32f4xx_hal_sai.h
+++ b/f4/include/stm32f4xx_hal_sai.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_sai.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of SAI HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -49,7 +49,8 @@
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @addtogroup SAI
* @{
@@ -71,58 +72,79 @@ typedef enum
HAL_SAI_STATE_BUSY_TX = 0x12, /*!< Data transmission process is ongoing */
HAL_SAI_STATE_BUSY_RX = 0x22, /*!< Data reception process is ongoing */
HAL_SAI_STATE_TIMEOUT = 0x03, /*!< SAI timeout state */
- HAL_SAI_STATE_ERROR = 0x04 /*!< SAI error state */
-
+ HAL_SAI_STATE_ERROR = 0x04 /*!< SAI error state */
}HAL_SAI_StateTypeDef;
-
+
+/**
+ * @brief SAI Callback prototype
+ */
+typedef void (*SAIcallback)(void);
+
/**
* @brief SAI Init Structure definition
*/
typedef struct
{
- uint32_t Protocol; /*!< Specifies the SAI Block protocol.
- This parameter can be a value of @ref SAI_Block_Protocol */
-
- uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode.
- This parameter can be a value of @ref SAI_Block_Mode */
+ uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode.
+ This parameter can be a value of @ref SAI_Block_Mode */
+
+ uint32_t Synchro; /*!< Specifies SAI Block synchronization
+ This parameter can be a value of @ref SAI_Block_Synchronization */
+
+ uint32_t SynchroExt; /*!< Specifies SAI Block synchronization, this setup is common
+ for BLOCKA and BLOCKB
+ This parameter can be a value of @ref SAI_Block_SyncExt */
+
+ uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven.
+ This parameter can be a value of @ref SAI_Block_Output_Drive
+ @note this value has to be set before enabling the audio block
+ but after the audio block configuration. */
+
+ uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.
+ This parameter can be a value of @ref SAI_Block_NoDivider
+ @note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length
+ should be aligned to a number equal to a power of 2, from 8 to 256.
+ If bit NODIV in the SAI_xCR1 register is set, the frame length can
+ take any of the values without constraint since the input clock of
+ the audio block should be equal to the bit clock.
+ There is no MCLK_x clock which can be output. */
+
+ uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold.
+ This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
+
+ uint32_t ClockSource; /*!< Specifies the SAI Block x Clock source.
+ This parameter is not used for STM32F446xx devices. */
+
+ uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
+ This parameter can be a value of @ref SAI_Audio_Frequency */
+
+ uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for
+ AudioFrequency the user choice
+ This parameter must be a number between Min_Data = 0 and Max_Data = 15 */
+
+ uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected.
+ This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
+
+ uint32_t CompandingMode; /*!< Specifies the companding mode type.
+ This parameter can be a value of @ref SAI_Block_Companding_Mode */
+
+ uint32_t TriState; /*!< Specifies the companding mode type.
+ This parameter can be a value of @ref SAI_TRIState_Management */
+
+ /* This part of the structure is automatically filled if your are using the high level intialisation
+ function HAL_SAI_InitProtocol */
+ uint32_t Protocol; /*!< Specifies the SAI Block protocol.
+ This parameter can be a value of @ref SAI_Block_Protocol */
+
uint32_t DataSize; /*!< Specifies the SAI Block data size.
- This parameter can be a value of @ref SAI_Block_Data_Size */
+ This parameter can be a value of @ref SAI_Block_Data_Size */
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
+ This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
- This parameter can be a value of @ref SAI_Block_Clock_Strobing */
-
- uint32_t Synchro; /*!< Specifies SAI Block synchronization
- This parameter can be a value of @ref SAI_Block_Synchronization */
-
- uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven.
- This parameter can be a value of @ref SAI_Block_Output_Drive
- @note this value has to be set before enabling the audio block
- but after the audio block configuration. */
-
- uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.
- This parameter can be a value of @ref SAI_Block_NoDivider
- @note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length
- should be aligned to a number equal to a power of 2, from 8 to 256.
- If bit NODIV in the SAI_xCR1 register is set, the frame length can
- take any of the values without constraint since the input clock of
- the audio block should be equal to the bit clock.
- There is no MCLK_x clock which can be output. */
-
- uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold.
- This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
-
- uint32_t ClockSource; /*!< Specifies the SAI Block x Clock source.
- This parameter can be a value of @ref SAI_Clock_Source
- @note: If ClockSource is equal to SAI_CLKSource_Ext, the PLLI2S
- and PLLSAI divisions factors will be ignored. */
-
- uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
- This parameter can be a value of @ref SAI_Audio_Frequency */
-
+ This parameter can be a value of @ref SAI_Block_Clock_Strobing */
}SAI_InitTypeDef;
/**
@@ -176,7 +198,7 @@ typedef struct
/**
* @brief SAI handle Structure definition
*/
-typedef struct
+typedef struct __SAI_HandleTypeDef
{
SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */
@@ -186,22 +208,20 @@ typedef struct
SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */
- uint16_t *pTxBuffPtr; /*!< Pointer to SAI Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< SAI Tx transfer size */
+ uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */
- uint16_t TxXferCount; /*!< SAI Tx transfer counter */
+ uint16_t XferSize; /*!< SAI transfer size */
- uint16_t *pRxBuffPtr; /*!< Pointer to SAI Rx transfer buffer */
-
- uint16_t RxXferSize; /*!< SAI Rx transfer size */
-
- uint16_t RxXferCount; /*!< SAI Rx transfer counter */
+ uint16_t XferCount; /*!< SAI transfer counter */
DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */
+ SAIcallback mutecallback;/*!< SAI mute callback */
+
+ void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */
+
HAL_LockTypeDef Lock; /*!< SAI locking object */
__IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */
@@ -221,22 +241,60 @@ typedef struct
/** @defgroup SAI_Error_Code SAI Error Code
* @{
- */
-#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001) /*!< Overrun Error */
-#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002) /*!< Underrun error */
-#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+ */
+#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001) /*!< Overrun Error */
+#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002) /*!< Underrun error */
+#define HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004) /*!< Anticipated Frame synchronisation detection */
+#define HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008) /*!< Late Frame synchronisation detection */
+#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010) /*!< codec not ready */
+#define HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020) /*!< Wrong clock configuration */
+#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040) /*!< Timeout error */
/**
* @}
*/
-/** @defgroup SAI_Clock_Source SAI Clock Source
+/** @defgroup SAI_Block_SyncExt SAI External synchronisation
* @{
*/
-#define SAI_CLKSOURCE_PLLSAI ((uint32_t)RCC_SAIACLKSOURCE_PLLSAI)
-#define SAI_CLKSOURCE_PLLI2S ((uint32_t)RCC_SAIACLKSOURCE_PLLI2S)
-#define SAI_CLKSOURCE_EXT ((uint32_t)RCC_SAIACLKSOURCE_EXT)
+#define SAI_SYNCEXT_DISABLE ((uint32_t)0x00000000)
+#define SAI_SYNCEXT_IN_ENABLE ((uint32_t)0x00000001)
+#define SAI_SYNCEXT_OUTBLOCKA_ENABLE ((uint32_t)0x00000002)
+#define SAI_SYNCEXT_OUTBLOCKB_ENABLE ((uint32_t)0x00000004)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Protocol SAI Supported protocol
+ * @{
+ */
+#define SAI_I2S_STANDARD ((uint32_t)0x00000000)
+#define SAI_I2S_MSBJUSTIFIED ((uint32_t)0x00000001)
+#define SAI_I2S_LSBJUSTIFIED ((uint32_t)0x00000002)
+#define SAI_PCM_LONG ((uint32_t)0x00000004)
+#define SAI_PCM_SHORT ((uint32_t)0x00000008)
+/**
+ * @}
+ */
+/** @defgroup SAI_Protocol_DataSize SAI protocol data size
+ * @{
+ */
+#define SAI_PROTOCOL_DATASIZE_16BIT ((uint32_t)0x00000000)
+#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED ((uint32_t)0x00000001)
+#define SAI_PROTOCOL_DATASIZE_24BIT ((uint32_t)0x00000002)
+#define SAI_PROTOCOL_DATASIZE_32BIT ((uint32_t)0x00000004)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Clock_Source SAI Clock Source
+ * @{
+ */
+#define SAI_CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
+#define SAI_CLKSOURCE_PLLI2S ((uint32_t)0x00100000)
+#define SAI_CLKSOURCE_EXT ((uint32_t)0x00200000)
+#define SAI_CLKSOURCE_NA ((uint32_t)0x00400000) /*!< No applicable for STM32F446xx */
/**
* @}
*/
@@ -252,7 +310,8 @@ typedef struct
#define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050)
#define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000)
#define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025)
-#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000)
+#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000)
+#define SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0)
/**
* @}
@@ -262,9 +321,9 @@ typedef struct
* @{
*/
#define SAI_MODEMASTER_TX ((uint32_t)0x00000000)
-#define SAI_MODEMASTER_RX ((uint32_t)0x00000001)
-#define SAI_MODESLAVE_TX ((uint32_t)0x00000002)
-#define SAI_MODESLAVE_RX ((uint32_t)0x00000003)
+#define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0)
+#define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1)
+#define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))
/**
* @}
@@ -274,6 +333,7 @@ typedef struct
* @{
*/
#define SAI_FREE_PROTOCOL ((uint32_t)0x00000000)
+#define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0)
#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)
/**
@@ -283,12 +343,12 @@ typedef struct
/** @defgroup SAI_Block_Data_Size SAI Block Data Size
* @{
*/
-#define SAI_DATASIZE_8 ((uint32_t)0x00000040)
-#define SAI_DATASIZE_10 ((uint32_t)0x00000060)
-#define SAI_DATASIZE_16 ((uint32_t)0x00000080)
-#define SAI_DATASIZE_20 ((uint32_t)0x000000A0)
-#define SAI_DATASIZE_24 ((uint32_t)0x000000C0)
-#define SAI_DATASIZE_32 ((uint32_t)0x000000E0)
+#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1)
+#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
+#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2)
+#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
+#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
+#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
/**
* @}
@@ -319,6 +379,7 @@ typedef struct
*/
#define SAI_ASYNCHRONOUS ((uint32_t)0x00000000)
#define SAI_SYNCHRONOUS ((uint32_t)SAI_xCR1_SYNCEN_0)
+#define SAI_SYNCHRONOUS_EXT ((uint32_t)SAI_xCR1_SYNCEN_1)
/**
* @}
@@ -415,8 +476,8 @@ typedef struct
/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
* @{
*/
-#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)
#define SAI_STEREOMODE ((uint32_t)0x00000000)
+#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)
/**
* @}
@@ -436,10 +497,10 @@ typedef struct
* @{
*/
#define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000)
-#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)0x00000001)
-#define SAI_FIFOTHRESHOLD_HF ((uint32_t)0x00000002)
-#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)0x00000003)
-#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)0x00000004)
+#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)SAI_xCR2_FTH_0)
+#define SAI_FIFOTHRESHOLD_HF ((uint32_t)SAI_xCR2_FTH_1)
+#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
+#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)SAI_xCR2_FTH_2)
/**
* @}
@@ -449,10 +510,10 @@ typedef struct
* @{
*/
#define SAI_NOCOMPANDING ((uint32_t)0x00000000)
-#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)0x00008000)
-#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)0x0000C000)
-#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)0x0000A000)
-#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)0x0000E000)
+#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)SAI_xCR2_COMP_1)
+#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
+#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
+#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
/**
* @}
@@ -540,7 +601,7 @@ typedef struct
* @arg SAI_IT_FREQ: FIFO request interrupt enable
* @arg SAI_IT_CNRDY: Codec not ready interrupt enable
* @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
- * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
+ * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enabl
* @retval None
*/
@@ -596,7 +657,10 @@ typedef struct
/**
* @}
*/
-
+
+/* Include RCC SAI Extension module */
+#include "stm32f4xx_hal_sai_ex.h"
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SAI_Exported_Functions
@@ -607,6 +671,7 @@ typedef struct
/** @addtogroup SAI_Exported_Functions_Group1
* @{
*/
+HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);
void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
@@ -621,20 +686,29 @@ void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
* @{
*/
/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
+/* Abort function */
+HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
+
+/* Mute management */
+HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
+HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
+HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
+
/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
@@ -691,6 +765,22 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
/** @addtogroup SAI_Private_Macros
* @{
*/
+#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
+ ((STATE) == SAI_SYNCEXT_IN_ENABLE) ||\
+ ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
+ ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
+
+#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\
+ ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
+ ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
+ ((PROTOCOL) == SAI_PCM_LONG) ||\
+ ((PROTOCOL) == SAI_PCM_SHORT))
+
+#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE) (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT) ||\
+ ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
+ ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) ||\
+ ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
+
#define IS_SAI_CLK_SOURCE(SOURCE) (((SOURCE) == SAI_CLKSOURCE_PLLSAI) ||\
((SOURCE) == SAI_CLKSOURCE_PLLI2S) ||\
((SOURCE) == SAI_CLKSOURCE_EXT))
@@ -699,7 +789,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
- ((AUDIO) == SAI_AUDIO_FREQUENCY_8K))
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \
((MODE) == SAI_MODEMASTER_RX) || \
@@ -707,7 +797,8 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
((MODE) == SAI_MODESLAVE_RX))
#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \
- ((PROTOCOL) == SAI_AC97_PROTOCOL))
+ ((PROTOCOL) == SAI_AC97_PROTOCOL) || \
+ ((PROTOCOL) == SAI_SPDIF_PROTOCOL))
#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \
((DATASIZE) == SAI_DATASIZE_10) || \
@@ -723,7 +814,8 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
- ((SYNCHRO) == SAI_SYNCHRONOUS))
+ ((SYNCHRO) == SAI_SYNCHRONOUS) || \
+ ((SYNCHRO) == SAI_SYNCHRONOUS_EXT))
#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
@@ -736,7 +828,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
((STATUS) == SAI_FIFOSTATUS_1QUARTERFULL) || \
((STATUS) == SAI_FIFOSTATUS_3QUARTERFULL) || \
((STATUS) == SAI_FIFOSTATUS_FULL) || \
- ((STATUS) == SAI_FIFOSTATUS_EMPTY))
+ ((STATUS) == SAI_FIFOSTATUS_EMPTY))
#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
@@ -758,10 +850,10 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
((STATE) == SAI_OUTPUT_RELEASED))
-#define IS_SAI_BLOCK_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
- ((MODE) == SAI_STEREOMODE))
+#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
+ ((MODE) == SAI_STEREOMODE))
-#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) != 0)
+#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((((ACTIVE) >> 16 ) > 0) && (((ACTIVE) >> 16 ) <= (SAI_SLOTACTIVE_ALL >> 16)))
#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
@@ -799,7 +891,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
* @}
*/
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
diff --git a/f4/include/stm32f4xx_hal_sai_ex.h b/f4/include/stm32f4xx_hal_sai_ex.h
new file mode 100644
index 0000000..cffcf57
--- /dev/null
+++ b/f4/include/stm32f4xx_hal_sai_ex.h
@@ -0,0 +1,102 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sai_ex.h
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief Header file of SAI Extension HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SAI_EX_H
+#define __STM32F4xx_HAL_SAI_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SAIEx
+ * @{
+ */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SAIEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SAIEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* Extended features functions ************************************************/
+void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai);
+uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SAI_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/include/stm32f4xx_hal_sd.h b/f4/include/stm32f4xx_hal_sd.h
index 85795cf..b5d6fb9 100755
--- a/f4/include/stm32f4xx_hal_sd.h
+++ b/f4/include/stm32f4xx_hal_sd.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_sd.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of SD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -42,7 +42,10 @@
#ifdef __cplusplus
extern "C" {
#endif
-
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_sdmmc.h"
@@ -779,7 +782,8 @@ HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
/**
* @}
*/
-
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
#ifdef __cplusplus
}
#endif
diff --git a/f4/include/stm32f4xx_hal_sdram.h b/f4/include/stm32f4xx_hal_sdram.h
index 00ccbef..1453011 100755
--- a/f4/include/stm32f4xx_hal_sdram.h
+++ b/f4/include/stm32f4xx_hal_sdram.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_sdram.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of SDRAM HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,8 @@
extern "C" {
#endif
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_fmc.h"
@@ -181,7 +182,7 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
* @}
*/
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
diff --git a/f4/include/stm32f4xx_hal_smartcard.h b/f4/include/stm32f4xx_hal_smartcard.h
index c9b0867..8275f95 100755
--- a/f4/include/stm32f4xx_hal_smartcard.h
+++ b/f4/include/stm32f4xx_hal_smartcard.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_smartcard.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -180,7 +180,6 @@ typedef struct
/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
* @{
*/
-#define SMARTCARD_WORDLENGTH_8B ((uint32_t)0x00000000)
#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
/**
* @}
@@ -189,9 +188,7 @@ typedef struct
/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
* @{
*/
-#define SMARTCARD_STOPBITS_1 ((uint32_t)0x00000000)
#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
-#define SMARTCARD_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
/**
* @}
@@ -200,7 +197,6 @@ typedef struct
/** @defgroup SMARTCARD_Parity SMARTCARD Parity
* @{
*/
-#define SMARTCARD_PARITY_NONE ((uint32_t)0x00000000)
#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
@@ -582,14 +578,10 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
* @{
*/
-#define IS_SMARTCARD_WORD_LENGTH(LENGTH) (((LENGTH) == SMARTCARD_WORDLENGTH_8B) || \
- ((LENGTH) == SMARTCARD_WORDLENGTH_9B))
-#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_1) || \
- ((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
- ((STOPBITS) == SMARTCARD_STOPBITS_1_5) || \
- ((STOPBITS) == SMARTCARD_STOPBITS_2))
-#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_NONE) || \
- ((PARITY) == SMARTCARD_PARITY_EVEN) || \
+#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
+#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
+ ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
+#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
((PARITY) == SMARTCARD_PARITY_ODD))
#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
diff --git a/f4/include/stm32f4xx_hal_spdifrx.h b/f4/include/stm32f4xx_hal_spdifrx.h
new file mode 100644
index 0000000..24bebf4
--- /dev/null
+++ b/f4/include/stm32f4xx_hal_spdifrx.h
@@ -0,0 +1,559 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_spdifrx.h
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief Header file of SPDIFRX HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SPDIFRX_H
+#define __STM32F4xx_HAL_SPDIFRX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F446xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPDIFRX
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types
+ * @{
+ */
+
+/**
+ * @brief SPDIFRX Init structure definition
+ */
+typedef struct
+{
+ uint32_t InputSelection; /*!< Specifies the SPDIF input selection.
+ This parameter can be a value of @ref SPDIFRX_Input_Selection */
+
+ uint32_t Retries; /*!< Specifies the Maximum allowed re-tries during synchronization phase.
+ This parameter can be a value of @ref SPDIFRX_Max_Retries */
+
+ uint32_t WaitForActivity; /*!< Specifies the wait for activity on SPDIF selected input.
+ This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */
+
+ uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status from channel A or B.
+ This parameter can be a value of @ref SPDIFRX_Channel_Selection */
+
+ uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
+ This parameter can be a value of @ref SPDIFRX_Data_Format */
+
+ uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
+ This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
+
+ uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_PT_Mask */
+
+ uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
+
+ uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_V_Mask */
+
+ uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_PE_Mask */
+
+}SPDIFRX_InitTypeDef;
+
+/**
+ * @brief SPDIFRX SetDataFormat structure definition
+ */
+typedef struct
+{
+ uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
+ This parameter can be a value of @ref SPDIFRX_Data_Format */
+
+ uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
+ This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
+
+ uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_PT_Mask */
+
+ uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
+
+ uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_V_Mask */
+
+ uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_PE_Mask */
+
+}SPDIFRX_SetDataFormatTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_SPDIFRX_STATE_RESET = 0x00, /*!< SPDIFRX not yet initialized or disabled */
+ HAL_SPDIFRX_STATE_READY = 0x01, /*!< SPDIFRX initialized and ready for use */
+ HAL_SPDIFRX_STATE_BUSY = 0x02, /*!< SPDIFRX internal process is ongoing */
+ HAL_SPDIFRX_STATE_BUSY_RX = 0x03, /*!< SPDIFRX internal Data Flow RX process is ongoing */
+ HAL_SPDIFRX_STATE_BUSY_CX = 0x04, /*!< SPDIFRX internal Control Flow RX process is ongoing */
+ HAL_SPDIFRX_STATE_ERROR = 0x07 /*!< SPDIFRX error state */
+}HAL_SPDIFRX_StateTypeDef;
+
+/**
+ * @brief SPDIFRX handle Structure definition
+ */
+typedef struct
+{
+ SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */
+
+ SPDIFRX_InitTypeDef Init; /* SPDIFRX communication parameters */
+
+ uint32_t *pRxBuffPtr; /* Pointer to SPDIFRX Rx transfer buffer */
+
+ uint32_t *pCsBuffPtr; /* Pointer to SPDIFRX Cx transfer buffer */
+
+ __IO uint16_t RxXferSize; /* SPDIFRX Rx transfer size */
+
+ __IO uint16_t RxXferCount; /* SPDIFRX Rx transfer counter
+ (This field is initialized at the
+ same value as transfer size at the
+ beginning of the transfer and
+ decremented when a sample is received.
+ NbSamplesReceived = RxBufferSize-RxBufferCount) */
+
+ __IO uint16_t CsXferSize; /* SPDIFRX Rx transfer size */
+
+ __IO uint16_t CsXferCount; /* SPDIFRX Rx transfer counter
+ (This field is initialized at the
+ same value as transfer size at the
+ beginning of the transfer and
+ decremented when a sample is received.
+ NbSamplesReceived = RxBufferSize-RxBufferCount) */
+
+ DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */
+
+ __IO HAL_LockTypeDef Lock; /* SPDIFRX locking object */
+
+ __IO HAL_SPDIFRX_StateTypeDef State; /* SPDIFRX communication state */
+
+ __IO uint32_t ErrorCode; /* SPDIFRX Error code */
+
+}SPDIFRX_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
+ * @{
+ */
+/** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code
+ * @{
+ */
+#define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */
+#define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002) /*!< OVR error */
+#define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004) /*!< Parity error */
+#define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008) /*!< DMA transfer error */
+#define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010) /*!< Unknown Error error */
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection
+ * @{
+ */
+#define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000)
+#define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000)
+#define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000)
+#define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries
+ * @{
+ */
+#define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000)
+#define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000)
+#define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000)
+#define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity
+ * @{
+ */
+#define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000)
+#define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask
+* @{
+*/
+#define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000)
+#define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask
+* @{
+*/
+#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000) /* The channel status and user bits are copied into the SPDIF_DR */
+#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask
+* @{
+*/
+#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000)
+#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_PE_Mask SPDIFRX Parity Error Mask
+* @{
+*/
+#define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000)
+#define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Channel_Selection SPDIFRX Channel Selection
+ * @{
+ */
+#define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000)
+#define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format
+ * @{
+ */
+#define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000)
+#define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010)
+#define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode
+ * @{
+ */
+#define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000)
+#define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_State SPDIFRX State
+ * @{
+ */
+
+#define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFC)
+#define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001)
+#define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition
+ * @{
+ */
+#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
+#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
+#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
+#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
+#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
+#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
+#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition
+ * @{
+ */
+#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
+#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
+#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
+#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
+#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
+#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
+#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
+#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
+#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros
+ * @{
+ */
+
+/** @brief Reset SPDIFRX handle state
+ * @param __HANDLE__: SPDIFRX handle.
+ * @retval None
+ */
+#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)
+
+/** @brief Disable the specified SPDIFRX peripheral (IDLE State).
+ * @param __HANDLE__: specifies the SPDIFRX Handle.
+ * @retval None
+ */
+#define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)
+
+/** @brief Enable the specified SPDIFRX peripheral (SYNC State).
+ * @param __HANDLE__: specifies the SPDIFRX Handle.
+ * @retval None
+ */
+#define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)
+
+
+/** @brief Enable the specified SPDIFRX peripheral (RCV State).
+ * @param __HANDLE__: specifies the SPDIFRX Handle.
+ * @retval None
+ */
+#define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
+
+
+/** @brief Enable or disable the specified SPDIFRX interrupts.
+ * @param __HANDLE__: specifies the SPDIFRX Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg SPDIFRX_IT_RXNE
+ * @arg SPDIFRX_IT_CSRNE
+ * @arg SPDIFRX_IT_PERRIE
+ * @arg SPDIFRX_IT_OVRIE
+ * @arg SPDIFRX_IT_SBLKIE
+ * @arg SPDIFRX_IT_SYNCDIE
+ * @arg SPDIFRX_IT_IFEIE
+ * @retval None
+ */
+#define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
+#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
+
+/** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the SPDIFRX Handle.
+ * @param __INTERRUPT__: specifies the SPDIFRX interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPDIFRX_IT_RXNE
+ * @arg SPDIFRX_IT_CSRNE
+ * @arg SPDIFRX_IT_PERRIE
+ * @arg SPDIFRX_IT_OVRIE
+ * @arg SPDIFRX_IT_SBLKIE
+ * @arg SPDIFRX_IT_SYNCDIE
+ * @arg SPDIFRX_IT_IFEIE
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified SPDIFRX flag is set or not.
+ * @param __HANDLE__: specifies the SPDIFRX Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPDIFRX_FLAG_RXNE
+ * @arg SPDIFRX_FLAG_CSRNE
+ * @arg SPDIFRX_FLAG_PERR
+ * @arg SPDIFRX_FLAG_OVR
+ * @arg SPDIFRX_FLAG_SBD
+ * @arg SPDIFRX_FLAG_SYNCD
+ * @arg SPDIFRX_FLAG_FERR
+ * @arg SPDIFRX_FLAG_SERR
+ * @arg SPDIFRX_FLAG_TERR
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt
+ * This parameter can be one of the following values:
+ * @arg SPDIFRX_FLAG_PERR
+ * @arg SPDIFRX_FLAG_OVR
+ * @arg SPDIFRX_SR_SBD
+ * @arg SPDIFRX_SR_SYNCD
+ * @retval None
+ */
+#define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPDIFRX_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SPDIFRX_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif);
+HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);
+HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat);
+/**
+ * @}
+ */
+
+/** @addtogroup SPDIFRX_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
+
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
+void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif);
+
+/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
+void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
+/**
+ * @}
+ */
+
+/** @addtogroup SPDIFRX_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control and State functions ************************************/
+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif);
+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros
+ * @{
+ */
+#define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \
+ ((INPUT) == SPDIFRX_INPUT_IN2) || \
+ ((INPUT) == SPDIFRX_INPUT_IN3) || \
+ ((INPUT) == SPDIFRX_INPUT_IN0))
+#define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \
+ ((RET) == SPDIFRX_MAXRETRIES_3) || \
+ ((RET) == SPDIFRX_MAXRETRIES_15) || \
+ ((RET) == SPDIFRX_MAXRETRIES_63))
+#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
+ ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
+#define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
+ ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
+#define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
+ ((VAL) == SPDIFRX_VALIDITYMASK_ON))
+#define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
+ ((VAL) == SPDIFRX_PARITYERRORMASK_ON))
+#define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \
+ ((CHANNEL) == SPDIFRX_CHANNEL_B))
+#define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
+ ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \
+ ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
+#define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
+ ((MODE) == SPDIFRX_STEREOMODE_ENABLE))
+
+#define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
+ ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_SPDIFRX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/include/stm32f4xx_hal_spi.h b/f4/include/stm32f4xx_hal_spi.h
index 5612692..b70dd2e 100755
--- a/f4/include/stm32f4xx_hal_spi.h
+++ b/f4/include/stm32f4xx_hal_spi.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_spi.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -173,7 +173,7 @@ typedef struct __SPI_HandleTypeDef
#define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004) /*!< OVR error */
#define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008) /*!< FRE error */
#define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
-#define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000010) /*!< Flag: RXNE,TXE, BSY */
+#define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020) /*!< Flag: RXNE,TXE, BSY */
/**
* @}
*/
diff --git a/f4/include/stm32f4xx_hal_sram.h b/f4/include/stm32f4xx_hal_sram.h
index 0580c2f..fcd3772 100755
--- a/f4/include/stm32f4xx_hal_sram.h
+++ b/f4/include/stm32f4xx_hal_sram.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_sram.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of SRAM HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -44,20 +44,24 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
#include "stm32f4xx_ll_fsmc.h"
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#include "stm32f4xx_ll_fmc.h"
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
/** @addtogroup SRAM
* @{
*/
@@ -187,7 +191,8 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
diff --git a/f4/include/stm32f4xx_hal_tim.h b/f4/include/stm32f4xx_hal_tim.h
index 82d805a..6763258 100755
--- a/f4/include/stm32f4xx_hal_tim.h
+++ b/f4/include/stm32f4xx_hal_tim.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_tim.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
diff --git a/f4/include/stm32f4xx_hal_tim_ex.h b/f4/include/stm32f4xx_hal_tim_ex.h
index 532812a..3b2aca5 100755
--- a/f4/include/stm32f4xx_hal_tim_ex.h
+++ b/f4/include/stm32f4xx_hal_tim_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_tim_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of TIM HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -93,19 +93,19 @@ typedef struct {
*/
typedef struct
{
- uint32_t OffStateRunMode; /*!< TIM off state in run mode.
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode.
This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
- uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode.
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode.
This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
- uint32_t LockLevel; /*!< TIM Lock level.
+ uint32_t LockLevel; /*!< TIM Lock level.
This parameter can be a value of @ref TIM_Lock_level */
- uint32_t DeadTime; /*!< TIM dead Time.
+ uint32_t DeadTime; /*!< TIM dead Time.
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
- uint32_t BreakState; /*!< TIM Break State.
+ uint32_t BreakState; /*!< TIM Break State.
This parameter can be a value of @ref TIM_Break_Input_enable_disable */
- uint32_t BreakPolarity; /*!< TIM Break input polarity.
+ uint32_t BreakPolarity; /*!< TIM Break input polarity.
This parameter can be a value of @ref TIM_Break_Polarity */
- uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state.
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state.
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
}TIM_BreakDeadTimeConfigTypeDef;
/**
@@ -130,14 +130,29 @@ typedef struct
#define TIM_TIM5_RTC (0x000000C0)
#define TIM_TIM11_GPIO (0x00000000)
#define TIM_TIM11_HSE (0x00000002)
+
+#if defined (STM32F446xx)
+#define TIM_TIM11_SPDIFRX (0x00000001)
+#endif /* STM32F446xx */
/**
* @}
- */
-
+ */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** @defgroup TIMEx_SystemBreakInput TIM System Break Input
+ * @{
+ */
+#define TIM_SYSTEMBREAKINPUT_HARDFAULT ((uint32_t)0x00000001) /* Core Lockup lock output(Hardfault) is connected to Break Input of TIM1 and TIM8 */
+#define TIM_SYSTEMBREAKINPUT_PVD ((uint32_t)0x00000004) /* PVD Interrupt is connected to Break Input of TIM1 and TIM8 */
+#define TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD ((uint32_t)0x00000005) /* Core Lockup lock output(Hardfault) and PVD Interrupt are connected to Break Input of TIM1 and TIM8 */
+/**
+ * @}
+ */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
/**
* @}
*/
-
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup TIMEx_Exported_Functions
@@ -264,7 +279,8 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
/** @defgroup TIMEx_Private_Macros TIM Private Macros
* @{
*/
-#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
+#if defined (STM32F446xx)
+#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
@@ -273,7 +289,27 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
((TIM_REMAP) == TIM_TIM5_LSE)||\
((TIM_REMAP) == TIM_TIM5_RTC)||\
((TIM_REMAP) == TIM_TIM11_GPIO)||\
+ ((TIM_REMAP) == TIM_TIM11_SPDIFRX)||\
((TIM_REMAP) == TIM_TIM11_HSE))
+#else
+#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
+ ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
+ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
+ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
+ ((TIM_REMAP) == TIM_TIM5_GPIO)||\
+ ((TIM_REMAP) == TIM_TIM5_LSI)||\
+ ((TIM_REMAP) == TIM_TIM5_LSE)||\
+ ((TIM_REMAP) == TIM_TIM5_RTC)||\
+ ((TIM_REMAP) == TIM_TIM11_GPIO)||\
+ ((TIM_REMAP) == TIM_TIM11_HSE))
+#endif /* STM32F446xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_TIM_SYSTEMBREAKINPUT(BREAKINPUT) (((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_HARDFAULT)||\
+ ((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_PVD)||\
+ ((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD))
+
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF)
/**
diff --git a/f4/include/stm32f4xx_hal_uart.h b/f4/include/stm32f4xx_hal_uart.h
index f73dc40..7f54aca 100755
--- a/f4/include/stm32f4xx_hal_uart.h
+++ b/f4/include/stm32f4xx_hal_uart.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_uart.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of UART HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
diff --git a/f4/include/stm32f4xx_hal_usart.h b/f4/include/stm32f4xx_hal_usart.h
index 4f2ae2f..17a2ca9 100755
--- a/f4/include/stm32f4xx_hal_usart.h
+++ b/f4/include/stm32f4xx_hal_usart.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_usart.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -554,7 +554,7 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFF3) == 0x00) && ((MODE) != (uint32_t)0x00))
#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
-#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
+#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(2*(_BAUD_)))
#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100)
#define USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
#define USART_BRR(_PCLK_, _BAUD_) ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
diff --git a/f4/include/stm32f4xx_hal_wwdg.h b/f4/include/stm32f4xx_hal_wwdg.h
index efe4026..c910267 100755
--- a/f4/include/stm32f4xx_hal_wwdg.h
+++ b/f4/include/stm32f4xx_hal_wwdg.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_wwdg.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
diff --git a/f4/include/stm32f4xx_ll_fmc.h b/f4/include/stm32f4xx_ll_fmc.h
index d43ed08..33bbdd6 100755
--- a/f4/include/stm32f4xx_ll_fmc.h
+++ b/f4/include/stm32f4xx_ll_fmc.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_ll_fmc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of FMC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -53,7 +53,8 @@
/** @addtogroup FMC_LL
* @{
*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* Private types -------------------------------------------------------------*/
/** @defgroup FMC_LL_Private_Types FMC Private Types
* @{
@@ -88,7 +89,8 @@ typedef struct
uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
memory, valid only when accessing Flash memories in burst mode.
- This parameter can be a value of @ref FMC_Wrap_Mode */
+ This parameter can be a value of @ref FMC_Wrap_Mode
+ This mode is not available for the STM32F446/467/479xx devices */
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
@@ -117,6 +119,16 @@ typedef struct
through FMC_BCR2..4 registers.
This parameter can be a value of @ref FMC_Continous_Clock */
+ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
+ This parameter is only enabled through the FMC_BCR1 register, and don't care
+ through FMC_BCR2..4 registers.
+ This parameter can be a value of @ref FMC_Write_FIFO
+ This mode is available only for the STM32F446/469/479xx devices */
+
+ uint32_t PageSize; /*!< Specifies the memory page size.
+ This parameter can be a value of @ref FMC_Page_Size
+ This mode is available only for the STM32F446xx devices */
+
}FMC_NORSRAM_InitTypeDef;
/**
@@ -409,6 +421,8 @@ typedef struct
/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
* @{
*/
+/** @note This mode is not available for the STM32F446/469/479xx devices
+ */
#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
/**
@@ -456,6 +470,28 @@ typedef struct
*/
#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Page_Size FMC Page Size
+ * @note These values are available only for the STM32F446/469/479xx devices.
+ * @{
+ */
+#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
+#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
+#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
+#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_FIFO FMC Write FIFO
+ * @note These values are available only for the STM32F446/469/479xx devices.
+ * @{
+ */
+#define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS)
/**
* @}
*/
@@ -469,15 +505,15 @@ typedef struct
* @}
*/
-/** @defgroup FMC_Continous_Clock FMC Continous Clock
+/** @defgroup FMC_Continous_Clock FMC Continuous Clock
* @{
*/
#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
/**
* @}
- */
-
+ */
+
/** @defgroup FMC_Access_Mode FMC Access Mode
* @{
*/
@@ -725,17 +761,26 @@ typedef struct
/** @defgroup FMC_LL_Alias_definition FMC Alias definition
* @{
*/
-#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
-#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
-#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
-#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
-#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
-
-#define FMC_NORSRAM_DEVICE FMC_Bank1
-#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
-#define FMC_NAND_DEVICE FMC_Bank2_3
-#define FMC_PCCARD_DEVICE FMC_Bank4
-#define FMC_SDRAM_DEVICE FMC_Bank5_6
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ #define FMC_NAND_TypeDef FMC_Bank3_TypeDef
+#else
+ #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
+ #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+ #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
+ #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
+ #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
+
+
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ #define FMC_NAND_DEVICE FMC_Bank3
+#else
+ #define FMC_NAND_DEVICE FMC_Bank2_3
+ #define FMC_PCCARD_DEVICE FMC_Bank4
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+ #define FMC_NORSRAM_DEVICE FMC_Bank1
+ #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
+ #define FMC_SDRAM_DEVICE FMC_Bank5_6
/**
* @}
*/
@@ -776,6 +821,23 @@ typedef struct
* @brief macros to handle NAND device enable/disable
* @{
*/
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Enable the NAND device access.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @retval None
+ */
+#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
+
+/**
+ * @brief Disable the NAND device access.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @retval None
+ */
+#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
+#else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
/**
* @brief Enable the NAND device access.
* @param __INSTANCE__: FMC_NAND Instance
@@ -793,10 +855,12 @@ typedef struct
*/
#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
+
+#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
/**
* @}
*/
-
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
* @brief macros to handle SRAM read/write operations
* @{
@@ -817,11 +881,66 @@ typedef struct
/**
* @}
*/
-
+#endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
+
/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
* @brief macros to handle FMC flags and interrupts
* @{
*/
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Enable the NAND device interrupt.
+ * @param __INSTANCE__: FMC_NAND instance
+ * @param __BANK__: FMC_NAND Bank
+ * @param __INTERRUPT__: FMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the NAND device interrupt.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @param __INTERRUPT__: FMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Get flag status of the NAND device.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @param __FLAG__: FMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
+/**
+ * @brief Clear flag status of the NAND device.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @param __FLAG__: FMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
+#else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
/**
* @brief Enable the NAND device interrupt.
* @param __INSTANCE__: FMC_NAND instance
@@ -877,7 +996,10 @@ typedef struct
* @retval None
*/
#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
- ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
+ ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
+#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/**
* @brief Enable the PCCARD device interrupt.
* @param __INSTANCE__: FMC_PCCARD instance
@@ -927,7 +1049,8 @@ typedef struct
* @retval None
*/
#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
-
+#endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
+
/**
* @brief Enable the SDRAM device interrupt.
* @param __INSTANCE__: FMC_SDRAM instance
@@ -1042,8 +1165,10 @@ typedef struct
#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
- ((__MODE__) == FMC_WRAP_MODE_ENABLE))
+ ((__MODE__) == FMC_WRAP_MODE_ENABLE))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
@@ -1060,8 +1185,6 @@ typedef struct
#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
-#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
-
#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
((__BURST__) == FMC_WRITE_BURST_ENABLE))
@@ -1076,6 +1199,8 @@ typedef struct
#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
+#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
+
#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
@@ -1150,6 +1275,16 @@ typedef struct
#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
+
+#if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) || \
+ ((SIZE) == FMC_PAGE_SIZE_128) || \
+ ((SIZE) == FMC_PAGE_SIZE_256) || \
+ ((SIZE) == FMC_PAGE_SIZE_1024))
+
+#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) || \
+ ((FIFO) == FMC_WRITE_FIFO_ENABLE))
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
@@ -1217,7 +1352,7 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u
/**
* @}
*/
-
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/** @defgroup FMC_LL_PCCARD PCCARD
* @{
*/
@@ -1235,6 +1370,7 @@ HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
/**
* @}
*/
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
/** @defgroup FMC_LL_SDRAM SDRAM
* @{
@@ -1269,7 +1405,7 @@ uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t B
* @}
*/
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
diff --git a/f4/include/stm32f4xx_ll_fsmc.h b/f4/include/stm32f4xx_ll_fsmc.h
index 8b532c5..e541092 100755
--- a/f4/include/stm32f4xx_ll_fsmc.h
+++ b/f4/include/stm32f4xx_ll_fsmc.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_ll_fsmc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of FSMC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,7 +54,7 @@
* @{
*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
/* Private types -------------------------------------------------------------*/
/** @defgroup FSMC_LL_Private_Types FSMC Private Types
* @{
@@ -159,6 +159,7 @@ typedef struct
}FSMC_NORSRAM_TimingTypeDef;
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
/**
* @brief FSMC NAND Configuration Structure definition
*/
@@ -241,6 +242,7 @@ typedef struct
/**
* @}
*/
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
/* Private constants ---------------------------------------------------------*/
/** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
@@ -403,6 +405,7 @@ typedef struct
* @}
*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
/** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
* @{
*/
@@ -466,7 +469,8 @@ typedef struct
/**
* @}
*/
-
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
* @{
*/
@@ -494,13 +498,17 @@ typedef struct
*/
#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
#define FSMC_NORSRAM_DEVICE FSMC_Bank1
#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
#define FSMC_NAND_DEVICE FSMC_Bank2_3
#define FSMC_PCCARD_DEVICE FSMC_Bank4
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
@@ -517,6 +525,7 @@ typedef struct
#define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
#define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
#define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
#define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
#define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
@@ -546,18 +555,23 @@ typedef struct
#define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
#define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
#define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
#define FMC_NAND_TypeDef FSMC_NAND_TypeDef
#define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
#define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
-#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
+#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
#define FMC_NAND_DEVICE FSMC_NAND_DEVICE
#define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
#define FMC_NAND_BANK2 FSMC_NAND_BANK2
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
#define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
#define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
@@ -612,6 +626,7 @@ typedef struct
* @brief macros to handle NAND device enable/disable
* @{
*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
/**
* @brief Enable the NAND device access.
* @param __INSTANCE__: FSMC_NAND Instance
@@ -766,6 +781,7 @@ typedef struct
/**
* @}
*/
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
* @{
@@ -911,6 +927,7 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Dev
* @}
*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
/** @defgroup FSMC_LL_NAND NAND
* @{
*/
@@ -955,11 +972,12 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
/**
* @}
*/
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
/**
* @}
diff --git a/f4/include/stm32f4xx_ll_sdmmc.h b/f4/include/stm32f4xx_ll_sdmmc.h
index b2f1514..37b39e6 100755
--- a/f4/include/stm32f4xx_ll_sdmmc.h
+++ b/f4/include/stm32f4xx_ll_sdmmc.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_ll_sdmmc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of SDMMC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -42,7 +42,10 @@
#ifdef __cplusplus
extern "C" {
#endif
-
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -791,7 +794,10 @@ typedef struct
* @retval None
*/
#define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
-
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
/**
* @brief Enable the command completion signal.
* @retval None
@@ -827,7 +833,8 @@ typedef struct
* @retval None
*/
#define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
-
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
/**
* @}
*/
@@ -897,7 +904,8 @@ HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
/**
* @}
*/
-
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
#ifdef __cplusplus
}
#endif
diff --git a/f4/include/stm32f4xx_ll_usb.h b/f4/include/stm32f4xx_ll_usb.h
index dd2a516..4c3152c 100755
--- a/f4/include/stm32f4xx_ll_usb.h
+++ b/f4/include/stm32f4xx_ll_usb.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_ll_usb.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Header file of USB Core HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -42,7 +42,10 @@
#ifdef __cplusplus
extern "C" {
#endif
-
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -122,7 +125,11 @@ typedef struct
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
- uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
+ uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
+
+ uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
+
+ uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
@@ -450,7 +457,8 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
/**
* @}
*/
-
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
#ifdef __cplusplus
}
#endif
diff --git a/f4/src/devices/system_stm32f4xx.c b/f4/src/devices/system_stm32f4xx.c
index 318a217..ead4414 100755
--- a/f4/src/devices/system_stm32f4xx.c
+++ b/f4/src/devices/system_stm32f4xx.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
- * @version V2.2.0
- * @date 15-December-2014
+ * @version V2.4.1
+ * @date 09-October-2015
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@@ -24,7 +24,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -67,7 +67,7 @@
#include "stm32f4xx.h"
#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
@@ -91,15 +91,18 @@
*/
/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
- on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
+ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx)
/* #define DATA_IN_ExtSRAM */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* #define DATA_IN_ExtSDRAM */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
+ STM32F479xx */
#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
#error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
@@ -136,7 +139,7 @@
variable is updated automatically.
*/
uint32_t SystemCoreClock = 16000000;
- __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
@@ -297,15 +300,51 @@ void SystemCoreClockUpdate(void)
*/
void SystemInit_ExtMemCtl(void)
{
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ __IO uint32_t tmp = 0x00;
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#if defined (DATA_IN_ExtSDRAM)
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register uint32_t index;
+#if defined(STM32F446xx)
+ /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
+ clock */
+ RCC->AHB1ENR |= 0x0000007D;
+#else
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
clock */
RCC->AHB1ENR |= 0x000001F8;
+#endif /* STM32F446xx */
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
+#if defined(STM32F446xx)
+ /* Connect PAx pins to FMC Alternate function */
+ GPIOA->AFR[0] |= 0xC0000000;
+ GPIOA->AFR[1] |= 0x00000000;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOA->MODER |= 0x00008000;
+ /* Configure PDx pins speed to 50 MHz */
+ GPIOA->OSPEEDR |= 0x00008000;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOA->OTYPER |= 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOA->PUPDR |= 0x00000000;
+
+ /* Connect PCx pins to FMC Alternate function */
+ GPIOC->AFR[0] |= 0x00CC0000;
+ GPIOC->AFR[1] |= 0x00000000;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOC->MODER |= 0x00000A00;
+ /* Configure PDx pins speed to 50 MHz */
+ GPIOC->OSPEEDR |= 0x00000A00;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOC->OTYPER |= 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOC->PUPDR |= 0x00000000;
+#endif /* STM32F446xx */
+
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x000000CC;
GPIOD->AFR[1] = 0xCC000CCC;
@@ -353,7 +392,9 @@ void SystemInit_ExtMemCtl(void)
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
-
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx)
/* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
@@ -377,13 +418,20 @@ void SystemInit_ExtMemCtl(void)
GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00000000;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-/*-- FMC Configuration ------------------------------------------------------*/
+/*-- FMC Configuration -------------------------------------------------------*/
/* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001;
-
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
/* Configure and enable SDRAM bank1 */
+#if defined(STM32F446xx)
+ FMC_Bank5_6->SDCR[0] = 0x00001954;
+#else
FMC_Bank5_6->SDCR[0] = 0x000019E4;
+#endif /* STM32F446xx */
FMC_Bank5_6->SDTR[0] = 0x01115351;
/* SDRAM initialization sequence */
@@ -407,7 +455,11 @@ void SystemInit_ExtMemCtl(void)
}
/* Auto refresh command */
+#if defined(STM32F446xx)
+ FMC_Bank5_6->SDCMR = 0x000000F3;
+#else
FMC_Bank5_6->SDCMR = 0x00000073;
+#endif /* STM32F446xx */
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
@@ -415,7 +467,11 @@ void SystemInit_ExtMemCtl(void)
}
/* MRD register program */
+#if defined(STM32F446xx)
+ FMC_Bank5_6->SDCMR = 0x00044014;
+#else
FMC_Bank5_6->SDCMR = 0x00046014;
+#endif /* STM32F446xx */
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
@@ -424,19 +480,28 @@ void SystemInit_ExtMemCtl(void)
/* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR;
+#if defined(STM32F446xx)
+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
+#else
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+#endif /* STM32F446xx */
/* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#endif /* DATA_IN_ExtSDRAM */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
+ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx)
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#if defined(DATA_IN_ExtSRAM)
/*-- GPIOs Configuration -----------------------------------------------------*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR |= 0x00000078;
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x00CCC0CC;
@@ -486,18 +551,29 @@ void SystemInit_ExtMemCtl(void)
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
-/*-- FMC/FSMC Configuration --------------------------------------------------*/
+/*-- FMC/FSMC Configuration --------------------------------------------------*/
/* Enable the FMC/FSMC interface clock */
RCC->AHB3ENR |= 0x00000001;
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-
+#if defined(STM32F469xx) || defined(STM32F479xx)
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1->BTCR[2] = 0x00001091;
+ FMC_Bank1->BTCR[3] = 0x00110212;
+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F469xx || STM32F479xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001011;
FSMC_Bank1->BTCR[3] = 0x00000201;
@@ -505,7 +581,9 @@ void SystemInit_ExtMemCtl(void)
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+ (void)(tmp);
}
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/**
@@ -515,8 +593,8 @@ void SystemInit_ExtMemCtl(void)
/**
* @}
*/
-
+
/**
* @}
- */
+ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/src/stm32f4xx_hal.c b/f4/src/stm32f4xx_hal.c
index bc21a33..210bfc6 100755
--- a/f4/src/stm32f4xx_hal.c
+++ b/f4/src/stm32f4xx_hal.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@@ -23,7 +23,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -68,11 +68,11 @@
* @{
*/
/**
- * @brief STM32F4xx HAL Driver version number V1.2.0
+ * @brief STM32F4xx HAL Driver version number V1.4.1
*/
#define __STM32F4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32F4xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
-#define __STM32F4xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F4xx_HAL_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
+#define __STM32F4xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24)\
|(__STM32F4xx_HAL_VERSION_SUB1 << 16)\
@@ -87,13 +87,13 @@
/* Alias word address of UFB_MODE bit */
#define MEMRMP_OFFSET SYSCFG_OFFSET
#define UFB_MODE_BIT_NUMBER POSITION_VAL(SYSCFG_MEMRMP_UFB_MODE)
-#define UFB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BIT_NUMBER * 4))
+#define UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BIT_NUMBER * 4))
/* --- CMPCR Register ---*/
/* Alias word address of CMP_PD bit */
#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20)
#define CMP_PD_BIT_NUMBER POSITION_VAL(SYSCFG_CMPCR_CMP_PD)
-#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BIT_NUMBER * 4))
+#define CMPCR_CMP_PD_BB (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BIT_NUMBER * 4))
/**
* @}
*/
@@ -479,7 +479,8 @@ void HAL_DisableCompensationCell(void)
*(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE;
}
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Enables the Internal FLASH Bank Swapping.
*
@@ -510,7 +511,7 @@ void HAL_DisableMemorySwappingBank(void)
*(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE;
}
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
/**
* @}
diff --git a/f4/src/stm32f4xx_hal_adc.c b/f4/src/stm32f4xx_hal_adc.c
index 7407d46..263e50f 100755
--- a/f4/src/stm32f4xx_hal_adc.c
+++ b/f4/src/stm32f4xx_hal_adc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* + Initialization and de-initialization functions
@@ -36,8 +36,8 @@
##### How to use this driver #####
==============================================================================
- [..]
- (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
+ [..]
+ (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
(##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
(##) ADC pins configuration
(+++) Enable the clock for the ADC GPIOs using the following function:
@@ -47,7 +47,7 @@
(+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
(+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
- (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
+ (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
(+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
(+++) Configure and enable two DMA streams stream for managing data
transfer from peripheral to memory (output stream)
@@ -57,14 +57,35 @@
interrupt on the two DMA Streams. The output stream should have higher
priority than the input stream.
- (#) Configure the ADC Prescaler, conversion resolution and data alignment
- using the HAL_ADC_Init() function.
-
- (#) Configure the ADC regular channels group features, use HAL_ADC_Init()
- and HAL_ADC_ConfigChannel() functions.
-
- (#) Three operation modes are available within this driver :
-
+ *** Configuration of ADC, groups regular/injected, channels parameters ***
+ ==============================================================================
+ [..]
+ (#) Configure the ADC parameters (resolution, data alignment, ...)
+ and regular group parameters (conversion trigger, sequencer, ...)
+ using function HAL_ADC_Init().
+
+ (#) Configure the channels for regular group parameters (channel number,
+ channel rank into sequencer, ..., into regular group)
+ using function HAL_ADC_ConfigChannel().
+
+ (#) Optionally, configure the injected group parameters (conversion trigger,
+ sequencer, ..., of injected group)
+ and the channels for injected group parameters (channel number,
+ channel rank into sequencer, ..., into injected group)
+ using function HAL_ADCEx_InjectedConfigChannel().
+
+ (#) Optionally, configure the analog watchdog parameters (channels
+ monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
+
+ (#) Optionally, for devices with several ADC instances: configure the
+ multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
+
+ *** Execution of ADC conversions ***
+ ==============================================================================
+ [..]
+ (#) ADC driver can be used among three modes: polling, interruption,
+ transfer by DMA.
+
*** Polling mode IO operation ***
=================================
[..]
@@ -80,10 +101,10 @@
(+) Start the ADC peripheral using HAL_ADC_Start_IT()
(+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
(+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
- add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
+ add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
(+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_ADC_ErrorCallback
- (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
+ add his own code by customization of function pointer HAL_ADC_ErrorCallback
+ (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
*** DMA mode IO operation ***
==============================
@@ -91,9 +112,9 @@
(+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
of data to be transferred at each end of conversion
(+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
- add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
+ add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
(+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_ADC_ErrorCallback
+ add his own code by customization of function pointer HAL_ADC_ErrorCallback
(+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
*** ADC HAL driver macros list ***
@@ -111,13 +132,39 @@
(+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register
[..]
- (@) You can refer to the ADC HAL driver header file for more useful macros
-
+ (@) You can refer to the ADC HAL driver header file for more useful macros
+
+ *** Deinitialization of ADC ***
+ ==============================================================================
+ [..]
+ (#) Disable the ADC interface
+ (++) ADC clock can be hard reset and disabled at RCC top level.
+ (++) Hard reset of ADC peripherals
+ using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
+ (++) ADC clock disable using the equivalent macro/functions as configuration step.
+ (+++) Example:
+ Into HAL_ADC_MspDeInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
+ (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
+ (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+ (#) ADC pins configuration
+ (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Deinitialize the DMA using function HAL_DMA_DeInit().
+ (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -159,7 +206,7 @@
#ifdef HAL_ADC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @addtogroup ADC_Private_Functions
@@ -222,16 +269,22 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
- assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+
+ if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ {
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ }
if(hadc->State == HAL_ADC_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hadc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
}
@@ -346,7 +399,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
{
- uint16_t i = 0;
+ __IO uint32_t counter = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -368,24 +421,29 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
}
/* Check if ADC peripheral is disabled in order to enable it and wait during
- Tstab time the ADC's stabilization */
+ Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay inserted to wait during Tstab time the ADC's stabilization */
- for(; i <= 540; i++)
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
{
- __NOP();
+ counter--;
}
}
-
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
{
/* if no external trigger present enable software conversion of regular channels */
- if(hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
@@ -394,16 +452,13 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
else
{
/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
- if((hadc->Instance == ADC1) && (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
+ if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
}
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
/* Return function status */
return HAL_OK;
}
@@ -432,6 +487,14 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
/**
* @brief Poll for regular conversion complete
+ * @note ADC conversion flags EOS (end of sequence) and EOC (end of
+ * conversion) are cleared by this function.
+ * @note This function cannot be used in a particular setup: ADC configured
+ * in DMA mode and polling for end of each conversion (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+ * In this case, DMA resets the flag EOC and polling cannot be
+ * performed on each conversion. Nevertheless, polling can still
+ * be performed on the complete sequence.
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param Timeout: Timeout value in millisecond.
@@ -441,6 +504,24 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
{
uint32_t tickstart = 0;
+ /* Verification that ADC configuration is compliant with polling for */
+ /* each conversion: */
+ /* Particular case is ADC configured in DMA mode and ADC sequencer with */
+ /* several ranks and polling for end of each conversion. */
+ /* For code simplicity sake, this particular case is generalized to */
+ /* ADC configured in DMA mode and polling for end of each conversion. */
+ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
+ HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
/* Get tick */
tickstart = HAL_GetTick();
@@ -544,7 +625,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
*/
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
{
- uint16_t i = 0;
+ __IO uint32_t counter = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -575,10 +656,12 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay inserted to wait during Tstab time the ADC's stabilization */
- for(; i <= 540; i++)
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
{
- __NOP();
+ counter--;
}
}
@@ -588,11 +671,14 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
/* Enable the ADC end of conversion interrupt for regular group */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
{
/* if no external trigger present enable software conversion of regular channels */
- if (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
@@ -601,16 +687,13 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
else
{
/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
- if ((hadc->Instance == (ADC_TypeDef*)0x40012000) && (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
+ if((hadc->Instance == (ADC_TypeDef*)0x40012000) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
}
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
+
/* Return function status */
return HAL_OK;
}
@@ -674,7 +757,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
hadc->State = HAL_ADC_STATE_EOC_REG;
}
- if((hadc->Init.ContinuousConvMode == DISABLE) && (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
+ if((hadc->Init.ContinuousConvMode == DISABLE) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
{
if(hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
{
@@ -789,7 +872,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
- uint16_t i = 0;
+ __IO uint32_t counter = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -818,7 +901,10 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_REG;
-
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
@@ -826,23 +912,22 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay inserted to wait during Tstab time the ADC's stabilization */
- for(; i <= 540; i++)
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
{
- __NOP();
+ counter--;
}
}
/* if no external trigger present enable software conversion of regular channels */
- if (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= ADC_CR2_SWSTART;
}
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
/* Return function status */
return HAL_OK;
}
@@ -969,6 +1054,8 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
+ __IO uint32_t counter = 0;
+
/* Check the parameters */
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
@@ -1035,6 +1122,17 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
{
/* Enable the TSVREFE channel*/
ADC->CCR |= ADC_CCR_TSVREFE;
+
+ if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
+ {
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
+ {
+ counter--;
+ }
+ }
}
/* Process unlocked */
@@ -1155,6 +1253,10 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
* @}
*/
+/** @addtogroup ADC_Private_Functions
+ * @{
+ */
+
/**
* @brief Initializes the ADCx peripheral according to the specified parameters
* in the ADC_InitStruct without initializing the ADC MSP.
@@ -1164,7 +1266,6 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
*/
static void ADC_Init(ADC_HandleTypeDef* hadc)
{
-
/* Set ADC parameters */
/* Set the ADC clock prescaler */
ADC->CCR &= ~(ADC_CCR_ADCPRE);
@@ -1182,19 +1283,33 @@ static void ADC_Init(ADC_HandleTypeDef* hadc)
hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
hadc->Instance->CR2 |= hadc->Init.DataAlign;
- /* Select external trigger to start conversion */
- hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
- hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
-
- /* Select external trigger polarity */
- hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
- hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ {
+ /* Select external trigger to start conversion */
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
+ hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
+
+ /* Select external trigger polarity */
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
+ hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
+ }
+ else
+ {
+ /* Reset the external trigger */
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
+ }
/* Enable or disable ADC continuous conversion mode */
hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);
- if (hadc->Init.DiscontinuousConvMode != DISABLE)
+ if(hadc->Init.DiscontinuousConvMode != DISABLE)
{
assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
@@ -1277,6 +1392,9 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma)
HAL_ADC_ErrorCallback(hadc);
}
+/**
+ * @}
+ */
/**
* @}
diff --git a/f4/src/stm32f4xx_hal_adc_ex.c b/f4/src/stm32f4xx_hal_adc_ex.c
index e8129b7..632eb95 100755
--- a/f4/src/stm32f4xx_hal_adc_ex.c
+++ b/f4/src/stm32f4xx_hal_adc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief This file provides firmware functions to manage the following
* functionalities of the ADC extension peripheral:
* + Extended features functions
@@ -86,7 +86,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -176,7 +176,8 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
{
- uint32_t i = 0, tmp1 = 0, tmp2 = 0;
+ __IO uint32_t counter = 0;
+ uint32_t tmp1 = 0, tmp2 = 0;
/* Process locked */
__HAL_LOCK(hadc);
@@ -200,10 +201,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay inserted to wait during Tstab time the ADC's stabilization */
- for(; i <= 540; i++)
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
{
- __NOP();
+ counter--;
}
}
@@ -245,7 +248,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
{
- uint32_t i = 0, tmp1 = 0, tmp2 =0;
+ __IO uint32_t counter = 0;
+ uint32_t tmp1 = 0, tmp2 =0;
/* Process locked */
__HAL_LOCK(hadc);
@@ -272,10 +276,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay inserted to wait during Tstab time the ADC's stabilization */
- for(; i <= 540; i++)
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
{
- __NOP();
+ counter--;
}
}
@@ -472,7 +478,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
- uint16_t counter = 0;
+ __IO uint32_t counter = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -518,15 +524,17 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay inserted to wait during Tstab time the ADC's stabilization */
- for(; counter <= 540; counter++)
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(counter != 0)
{
- __NOP();
+ counter--;
}
}
/* if no external trigger present enable software conversion of regular channels */
- if (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
@@ -618,7 +626,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));
- assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
@@ -628,6 +635,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
#endif /* USE_FULL_ASSERT */
+ if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)
+ {
+ assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
+ }
+
/* Process locked */
__HAL_LOCK(hadc);
@@ -661,13 +673,27 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* Set the SQx bits for the selected rank */
hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
- /* Select external trigger to start conversion */
- hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
- hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv;
-
- /* Select external trigger polarity */
- hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
- hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+ {
+ /* Select external trigger to start conversion */
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
+ hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv;
+
+ /* Select external trigger polarity */
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
+ hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
+ }
+ else
+ {
+ /* Reset the external trigger */
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
+ }
if (sConfigInjected->AutoInjectedConv != DISABLE)
{
diff --git a/f4/src/stm32f4xx_hal_can.c b/f4/src/stm32f4xx_hal_can.c
index 5270fc4..f4f4913 100755
--- a/f4/src/stm32f4xx_hal_can.c
+++ b/f4/src/stm32f4xx_hal_can.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_can.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
* + Initialization and de-initialization functions
@@ -17,7 +17,7 @@
==============================================================================
[..]
(#) Enable the CAN controller interface clock using
- __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN1_CLK_ENABLE() for CAN2
+ __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
-@- In case you are using CAN2 only, you have to enable the CAN1 clock.
(#) CAN pins configuration
@@ -72,7 +72,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -113,7 +113,9 @@
#ifdef HAL_CAN_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -191,6 +193,8 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
if(hcan->State == HAL_CAN_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hcan->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_CAN_MspInit(hcan);
}
@@ -1420,7 +1424,8 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM3F412xE */
#endif /* HAL_CAN_MODULE_ENABLED */
/**
diff --git a/f4/src/stm32f4xx_hal_cec.c b/f4/src/stm32f4xx_hal_cec.c
new file mode 100644
index 0000000..00bb1c4
--- /dev/null
+++ b/f4/src/stm32f4xx_hal_cec.c
@@ -0,0 +1,1107 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_cec.c
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief CEC HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the High Definition Multimedia Interface
+ * Consumer Electronics Control Peripheral (CEC).
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ *
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The CEC HAL driver can be used as follow:
+
+ (#) Declare a CEC_HandleTypeDef handle structure.
+ (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
+ (##) Enable the CEC interface clock.
+ (##) CEC pins configuration:
+ (+) Enable the clock for the CEC GPIOs.
+ (+) Configure these CEC pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
+ and HAL_CEC_Receive_IT() APIs):
+ (+) Configure the CEC interrupt priority.
+ (+) Enable the NVIC CEC IRQ handle.
+ (@) The specific CEC interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
+ and receive process.
+
+ (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
+ in case of Bit Rising Error, Error-Bit generation conditions, device logical
+ address and Listen mode in the hcec Init structure.
+
+ (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
+
+ (@) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_CEC_MspInit() API.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CEC CEC
+ * @brief HAL CEC module driver
+ * @{
+ */
+#ifdef HAL_CEC_MODULE_ENABLED
+
+#if defined(STM32F446xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup CEC_Private_Constants CEC Private Constants
+ * @{
+ */
+#define CEC_CFGR_FIELDS (CEC_CFGR_SFT | CEC_CFGR_RXTOL | CEC_CFGR_BRESTP \
+ | CEC_CFGR_BREGEN | CEC_CFGR_LBPEGEN | CEC_CFGR_SFTOPT \
+ | CEC_CFGR_BRDNOGEN | CEC_CFGR_OAR | CEC_CFGR_LSTN)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CEC_Private_Functions CEC Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec);
+static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup CEC_Exported_Functions CEC Exported Functions
+ * @{
+ */
+
+/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the CEC
+ (+) The following parameters need to be configured:
+ (++) SignalFreeTime
+ (++) Tolerance
+ (++) BRERxStop (RX stopped or not upon Bit Rising Error)
+ (++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error)
+ (++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error)
+ (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
+ (++) SignalFreeTimeOption (SFT Timer start definition)
+ (++) OwnAddress (CEC device address)
+ (++) ListenMode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CEC mode according to the specified
+ * parameters in the CEC_InitTypeDef and creates the associated handle .
+ * @param hcec: CEC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
+{
+ uint32_t tmpreg = 0x0;
+
+ /* Check the CEC handle allocation */
+ if(hcec == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
+ assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
+ assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
+ assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
+ assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
+ assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
+ assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
+ assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
+ assert_param(IS_CEC_OAR_ADDRESS(hcec->Init.OwnAddress));
+ assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
+ assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress));
+
+
+ if(hcec->State == HAL_CEC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcec->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_CEC_MspInit(hcec);
+ }
+
+ hcec->State = HAL_CEC_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_CEC_DISABLE(hcec);
+
+ tmpreg = hcec->Init.SignalFreeTime;
+ tmpreg |= hcec->Init.Tolerance;
+ tmpreg |= hcec->Init.BRERxStop;
+ tmpreg |= hcec->Init.BREErrorBitGen;
+ tmpreg |= hcec->Init.LBPEErrorBitGen;
+ tmpreg |= hcec->Init.BroadcastMsgNoErrorBitGen;
+ tmpreg |= hcec->Init.SignalFreeTimeOption;
+ tmpreg |= (hcec->Init.OwnAddress << CEC_CFGR_OAR_LSB_POS);
+ tmpreg |= hcec->Init.ListenMode;
+
+ /* Write to CEC Control Register */
+ MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, tmpreg);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ hcec->State = HAL_CEC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the CEC peripheral
+ * @param hcec: CEC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
+{
+ /* Check the CEC handle allocation */
+ if(hcec == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
+
+ hcec->State = HAL_CEC_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_CEC_MspDeInit(hcec);
+ /* Disable the Peripheral */
+ __HAL_CEC_DISABLE(hcec);
+
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ hcec->State = HAL_CEC_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief CEC MSP Init
+ * @param hcec: CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief CEC MSP DeInit
+ * @param hcec: CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_MspDeInit can be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
+ * @brief CEC Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of functions allowing to manage the CEC data transfers.
+
+ (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
+ logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
+
+ (#) There are two mode of transfer:
+ (+) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (+) No-Blocking mode: The communication is performed using Interrupts.
+ These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated CEC IRQ when using Interrupt mode.
+ The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
+ will be executed respectivelly at the end of the transmit or Receive process
+ The HAL_CEC_ErrorCallback()user callback will be executed when a communication
+ error is detected
+
+ (#) Blocking mode API's are :
+ (+) HAL_CEC_Transmit()
+ (+) HAL_CEC_Receive()
+
+ (#) Non-Blocking mode API's with Interrupt are :
+ (+) HAL_CEC_Transmit_IT()
+ (+) HAL_CEC_Receive_IT()
+ (+) HAL_CEC_IRQHandler()
+
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (+) HAL_CEC_TxCpltCallback()
+ (+) HAL_CEC_RxCpltCallback()
+ (+) HAL_CEC_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send data in blocking mode
+ * @param hcec: CEC handle
+ * @param DestinationAddress: destination logical address
+ * @param pData: pointer to input byte data buffer
+ * @param Size: amount of data to be sent in bytes (without counting the header).
+ * 0 means only the header is sent (ping operation).
+ * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout)
+{
+ uint8_t temp = 0;
+ uint32_t tempisr = 0;
+ uint32_t tickstart = 0;
+
+ if((hcec->State == HAL_CEC_STATE_READY) && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
+ {
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ if((pData == NULL ) && (Size > 0))
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_CEC_ADDRESS(DestinationAddress));
+ assert_param(IS_CEC_MSGSIZE(Size));
+
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+
+ hcec->TxXferCount = Size;
+
+ /* case no data to be sent, sender is only pinging the system */
+ if (Size == 0)
+ {
+ /* Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+
+ /* send header block */
+ temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;
+ hcec->Instance->TXDR = temp;
+ /* Set TX Start of Message (TXSOM) bit */
+ __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
+
+ while (hcec->TxXferCount > 0)
+ {
+ hcec->TxXferCount--;
+
+ tickstart = HAL_GetTick();
+ while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_TXBR))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hcec->State = HAL_CEC_STATE_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* check whether error occured while waiting for TXBR to be set:
+ * has Tx underrun occurred ?
+ * has Tx error occurred ?
+ * has Tx Missing Acknowledge error occurred ?
+ * has Arbitration Loss error occurred ? */
+ tempisr = hcec->Instance->ISR;
+ if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0)
+ {
+ /* copy ISR for error handling purposes */
+ hcec->ErrorCode = tempisr;
+ /* clear all error flags by default */
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+ }
+ /* TXBR to clear BEFORE writing TXDR register */
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
+ if (hcec->TxXferCount == 0)
+ {
+ /* if last byte transmission, set TX End of Message (TXEOM) bit */
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+ hcec->Instance->TXDR = *pData++;
+
+ /* error check after TX byte write up */
+ tempisr = hcec->Instance->ISR;
+ if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0)
+ {
+ /* copy ISR for error handling purposes */
+ hcec->ErrorCode = tempisr;
+ /* clear all error flags by default */
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+ } /* end while (while (hcec->TxXferCount > 0)) */
+
+ /* if no error up to this point, check that transmission is
+ * complete, that is wait until TXEOM is reset */
+ tickstart = HAL_GetTick();
+
+ while (HAL_IS_BIT_SET(hcec->Instance->CR, CEC_CR_TXEOM))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart) > Timeout)
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Final error check once all bytes have been transmitted */
+ tempisr = hcec->Instance->ISR;
+ if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)) != 0)
+ {
+ /* copy ISR for error handling purposes */
+ hcec->ErrorCode = tempisr;
+ /* clear all error flags by default */
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE));
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive data in blocking mode. Must be invoked when RXBR has been set.
+ * @param hcec: CEC handle
+ * @param pData: pointer to received data buffer.
+ * @param Timeout: Timeout duration.
+ * Note that the received data size is not known beforehand, the latter is known
+ * when the reception is complete and is stored in hcec->RxXferSize.
+ * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
+ * If only a header is received, hcec->RxXferSize = 0
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout)
+{
+ uint32_t temp;
+ uint32_t tickstart = 0;
+
+ if (hcec->State == HAL_CEC_STATE_READY)
+ {
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ if (pData == NULL )
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ hcec->RxXferSize = 0;
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+
+ /* Rx loop until CEC_ISR_RXEND is set */
+ while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND))
+ {
+ tickstart = HAL_GetTick();
+ /* Wait for next byte to be received */
+ while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hcec->State = HAL_CEC_STATE_TIMEOUT;
+ __HAL_UNLOCK(hcec);
+ return HAL_TIMEOUT;
+ }
+ }
+ /* any error so far ?
+ * has Rx Missing Acknowledge occurred ?
+ * has Rx Long Bit Period error occurred ?
+ * has Rx Short Bit Period error occurred ?
+ * has Rx Bit Rising error occurred ?
+ * has Rx Overrun error occurred ? */
+ temp = (uint32_t) (hcec->Instance->ISR);
+ if ((temp & (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)) != 0)
+ {
+ /* copy ISR for error handling purposes */
+ hcec->ErrorCode = temp;
+ /* clear all error flags by default */
+ __HAL_CEC_CLEAR_FLAG(hcec,(CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR));
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+ } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXBR)) */
+
+ /* read received data */
+ *pData++ = hcec->Instance->RXDR;
+ temp = (uint32_t) (hcec->Instance->ISR);
+ /* end of message ? */
+ if ((temp & CEC_ISR_RXEND) != 0)
+ {
+ assert_param(IS_CEC_MSGSIZE(hcec->RxXferSize));
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND);
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+ return HAL_OK;
+ }
+
+ /* clear Rx-Byte Received flag */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR);
+ /* increment payload byte counter */
+ hcec->RxXferSize++;
+ } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND)) */
+
+ /* if the instructions below are executed, it means RXEND was set when RXBR was
+ * set for the first time:
+ * the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND))"
+ * loop has not been executed and this means a single byte has been sent */
+ *pData++ = hcec->Instance->RXDR;
+ /* only one header is received: RxXferSize is set to 0 (no operand, no opcode) */
+ hcec->RxXferSize = 0;
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
+
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send data in interrupt mode
+ * @param hcec: CEC handle
+ * @param DestinationAddress: destination logical address
+ * @param pData: pointer to input byte data buffer
+ * @param Size: amount of data to be sent in bytes (without counting the header).
+ * 0 means only the header is sent (ping operation).
+ * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
+{
+ uint8_t temp = 0;
+ /* if the IP isn't already busy and if there is no previous transmission
+ already pending due to arbitration lost */
+ if (((hcec->State == HAL_CEC_STATE_READY) || (hcec->State == HAL_CEC_STATE_STANDBY_RX))
+ && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
+ {
+ if((pData == NULL) && (Size > 0))
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_CEC_ADDRESS(DestinationAddress));
+ assert_param(IS_CEC_MSGSIZE(Size));
+
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+ hcec->pTxBuffPtr = pData;
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+
+ /* Disable Peripheral to write CEC_IER register */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Enable the following two CEC Transmission interrupts as
+ * well as the following CEC Transmission Errors interrupts:
+ * Tx Byte Request IT
+ * End of Transmission IT
+ * Tx Missing Acknowledge IT
+ * Tx-Error IT
+ * Tx-Buffer Underrun IT
+ * Tx arbitration lost */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ /* initialize the number of bytes to send,
+ * 0 means only one header is sent (ping operation) */
+ hcec->TxXferCount = Size;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ /* in case of no payload (Size = 0), sender is only pinging the system;
+ * Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
+ if (Size == 0)
+ {
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+
+ /* send header block */
+ temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress;
+ hcec->Instance->TXDR = temp;
+ /* Set TX Start of Message (TXSOM) bit */
+ __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
+
+ return HAL_OK;
+ }
+ /* if the IP is already busy or if there is a previous transmission
+ already pending due to arbitration loss */
+ else if ((hcec->State == HAL_CEC_STATE_BUSY_TX) || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
+ {
+ __HAL_LOCK(hcec);
+ /* set state to BUSY TX, in case it wasn't set already (case
+ * of transmission new attempt after arbitration loss) */
+ if (hcec->State != HAL_CEC_STATE_BUSY_TX)
+ {
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+ }
+
+ /* if all data have been sent */
+ if(hcec->TxXferCount == 0)
+ {
+ /* Disable Peripheral to write CEC_IER register */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Disable the CEC Transmission Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
+ /* Disable the CEC Transmission Error Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR|CEC_FLAG_TXEND);
+
+ hcec->State = HAL_CEC_STATE_READY;
+ /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
+ start again the Transmission under the Tx call back API */
+ __HAL_UNLOCK(hcec);
+
+ HAL_CEC_TxCpltCallback(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if (hcec->TxXferCount == 1)
+ {
+ /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+ /* clear Tx-Byte request flag */
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ hcec->TxXferCount--;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive data in interrupt mode.
+ * @param hcec: CEC handle
+ * @param pData: pointer to received data buffer.
+ * Note that the received data size is not known beforehand, the latter is known
+ * when the reception is complete and is stored in hcec->RxXferSize.
+ * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
+ * If only a header is received, hcec->RxXferSize = 0
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData)
+{
+ if(hcec->State == HAL_CEC_STATE_READY)
+ {
+ if(pData == NULL)
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+ hcec->RxXferSize = 0;
+ hcec->pRxBuffPtr = pData;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ /* the IP is moving to a ready to receive state */
+ hcec->State = HAL_CEC_STATE_STANDBY_RX;
+
+ /* Disable Peripheral to write CEC_IER register */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Enable the following CEC Reception Error Interrupts:
+ * Rx overrun
+ * Rx bit rising error
+ * Rx short bit period error
+ * Rx long bit period error
+ * Rx missing acknowledge */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IER_RX_ALL_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ /* Enable the following two CEC Reception interrupts:
+ * Rx Byte Received IT
+ * End of Reception IT */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND);
+
+ __HAL_CEC_ENABLE(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Get size of the received frame.
+ * @param hcec: CEC handle
+ * @retval Frame size
+ */
+uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec)
+{
+ return hcec->RxXferSize;
+}
+
+/**
+ * @brief This function handles CEC interrupt requests.
+ * @param hcec: CEC handle
+ * @retval None
+ */
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
+{
+ /* save interrupts register for further error or interrupts handling purposes */
+ hcec->ErrorCode = hcec->Instance->ISR;
+ /* CEC TX missing acknowledge error interrupt occurred -------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXACKE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXACKE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC transmit error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXERR) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXERR);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC TX underrun error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXUDR) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXUDR);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC TX arbitration error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_ARBLST) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX overrun error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXOVR) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXOVR);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX bit rising error interrupt occured -------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_BRE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_BRE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX short bit period error interrupt occured -------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_SBPE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_SBPE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX long bit period error interrupt occured --------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_LBPE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_LBPE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX missing acknowledge error interrupt occured ----------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXACKE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXACKE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ if ((hcec->ErrorCode & CEC_ISR_ALL_ERROR) != 0)
+ {
+ HAL_CEC_ErrorCallback(hcec);
+ }
+
+ /* CEC RX byte received interrupt -----------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXBR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXBR) != RESET))
+ {
+ /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
+ CEC_Receive_IT(hcec);
+ }
+
+ /* CEC RX end received interrupt ------------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXEND) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXEND) != RESET))
+ {
+ /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
+ CEC_Receive_IT(hcec);
+ }
+
+ /* CEC TX byte request interrupt -------------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXBR) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXBR) != RESET))
+ {
+ /* TXBR IT is cleared during HAL_CEC_Transmit_IT processing */
+ CEC_Transmit_IT(hcec);
+ }
+
+ /* CEC TX end interrupt ----------------------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXEND) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXEND) != RESET))
+ {
+ /* TXEND IT is cleared during HAL_CEC_Transmit_IT processing */
+ CEC_Transmit_IT(hcec);
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback
+ * @param hcec: CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback
+ * @param hcec: CEC handle
+ * @retval None
+ */
+__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief CEC error callbacks
+ * @param hcec: CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_ErrorCallback can be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
+ * @brief CEC control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control function #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the CEC.
+ (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
+@endverbatim
+ * @{
+ */
+/**
+ * @brief return the CEC state
+ * @param hcec: CEC handle
+ * @retval HAL state
+ */
+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
+{
+ return hcec->State;
+}
+
+/**
+* @brief Return the CEC error code
+* @param hcec : pointer to a CEC_HandleTypeDef structure that contains
+ * the configuration information for the specified CEC.
+* @retval CEC Error Code
+*/
+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
+{
+ return hcec->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Send data in interrupt mode
+ * @param hcec: CEC handle.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_CEC_Transmit_IT()
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
+{
+ /* if the IP is already busy or if there is a previous transmission
+ already pending due to arbitration loss */
+ if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
+ || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
+ {
+ __HAL_LOCK(hcec);
+ /* set state to BUSY TX, in case it wasn't set already (case
+ * of transmission new attempt after arbitration loss) */
+ if (hcec->State != HAL_CEC_STATE_BUSY_TX)
+ {
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+ }
+
+ /* if all data have been sent */
+ if(hcec->TxXferCount == 0)
+ {
+ /* Disable Peripheral to write CEC_IER register */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Disable the CEC Transmission Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
+ /* Disable the CEC Transmission Error Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND);
+
+ hcec->State = HAL_CEC_STATE_READY;
+ /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
+ start again the Transmission under the Tx call back API */
+ __HAL_UNLOCK(hcec);
+
+ HAL_CEC_TxCpltCallback(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if (hcec->TxXferCount == 1)
+ {
+ /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+ /* clear Tx-Byte request flag */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ hcec->TxXferCount--;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Receive data in interrupt mode.
+ * @param hcec: CEC handle.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_CEC_Receive_IT()
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec)
+{
+ uint32_t tempisr;
+
+ /* Three different conditions are tested to carry out the RX IT processing:
+ * - the IP is in reception stand-by (the IP state is HAL_CEC_STATE_STANDBY_RX) and
+ * the reception of the first byte is starting
+ * - a message reception is already on-going (the IP state is HAL_CEC_STATE_BUSY_RX)
+ * and a new byte is being received
+ * - a transmission has just been started (the IP state is HAL_CEC_STATE_BUSY_TX)
+ * but has been interrupted by a new message reception or discarded due to
+ * arbitration loss: the reception of the first or higher priority message
+ * (the arbitration winner) is starting */
+ if ((hcec->State == HAL_CEC_STATE_STANDBY_RX)
+ || (hcec->State == HAL_CEC_STATE_BUSY_RX)
+ || (hcec->State == HAL_CEC_STATE_BUSY_TX))
+ {
+ /* reception is starting */
+ hcec->State = HAL_CEC_STATE_BUSY_RX;
+ tempisr = (uint32_t) (hcec->Instance->ISR);
+ if ((tempisr & CEC_FLAG_RXBR) != 0)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+ /* read received byte */
+ *hcec->pRxBuffPtr++ = hcec->Instance->RXDR;
+ /* if last byte has been received */
+ if ((tempisr & CEC_FLAG_RXEND) != 0)
+ {
+ /* clear IT */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR|CEC_FLAG_RXEND);
+ /* RX interrupts are not disabled at this point.
+ * Indeed, to disable the IT, the IP must be disabled first
+ * which resets the TXSOM flag. In case of arbitration loss,
+ * this leads to a transmission abort.
+ * Therefore, RX interruptions disabling if so required,
+ * is done in HAL_CEC_RxCpltCallback */
+
+ /* IP state is moved to READY.
+ * If the IP must remain in standby mode to listen
+ * any new message, it is up to HAL_CEC_RxCpltCallback
+ * to move it again to HAL_CEC_STATE_STANDBY_RX */
+ hcec->State = HAL_CEC_STATE_READY;
+
+ /* Call the Process Unlocked before calling the Rx call back API */
+ __HAL_UNLOCK(hcec);
+ HAL_CEC_RxCpltCallback(hcec);
+
+ return HAL_OK;
+ }
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
+
+ hcec->RxXferSize++;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @}
+ */
+
+#endif /* STM32F446xx */
+
+#endif /* HAL_CEC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/src/stm32f4xx_hal_cortex.c b/f4/src/stm32f4xx_hal_cortex.c
index d6ed20c..776ade7 100755
--- a/f4/src/stm32f4xx_hal_cortex.c
+++ b/f4/src/stm32f4xx_hal_cortex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cortex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
@@ -70,7 +70,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -261,13 +261,60 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
==============================================================================
[..]
This subsection provides a set of functions allowing to control the CORTEX
- (NVIC, SYSTICK) functionalities.
+ (NVIC, SYSTICK, MPU) functionalities.
@endverbatim
* @{
*/
+#if (__MPU_PRESENT == 1)
+/**
+ * @brief Initializes and configures the Region and the memory to be protected.
+ * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
+ * the initialization and configuration information.
+ * @retval None
+ */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+ assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+ /* Set the Region number */
+ MPU->RNR = MPU_Init->Number;
+
+ if ((MPU_Init->Enable) != RESET)
+ {
+ /* Check the parameters */
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+ MPU->RBAR = MPU_Init->BaseAddress;
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
+ }
+ else
+ {
+ MPU->RBAR = 0x00;
+ MPU->RASR = 0x00;
+ }
+}
+#endif /* __MPU_PRESENT */
+
/**
* @brief Gets the priority grouping field from the NVIC Interrupt Controller.
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
diff --git a/f4/src/stm32f4xx_hal_crc.c b/f4/src/stm32f4xx_hal_crc.c
index b6832d7..9b4c270 100755
--- a/f4/src/stm32f4xx_hal_crc.c
+++ b/f4/src/stm32f4xx_hal_crc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_crc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@@ -32,7 +32,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -122,6 +122,8 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
if(hcrc->State == HAL_CRC_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hcrc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_CRC_MspInit(hcrc);
}
diff --git a/f4/src/stm32f4xx_hal_cryp.c b/f4/src/stm32f4xx_hal_cryp.c
index 46ec114..e6d4199 100755
--- a/f4/src/stm32f4xx_hal_cryp.c
+++ b/f4/src/stm32f4xx_hal_cryp.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cryp.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief CRYP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
@@ -70,7 +70,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -111,7 +111,7 @@
#ifdef HAL_CRYP_MODULE_ENABLED
-#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx)
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -164,7 +164,7 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
/* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
in the DMACR register */
- CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
/* Call input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
@@ -181,10 +181,10 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
/* Disable the DMA transfer for output FIFO request by resetting the DOEN bit
in the DMACR register */
- CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Change the CRYP state to ready */
hcryp->State = HAL_CRYP_STATE_READY;
@@ -221,43 +221,43 @@ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySiz
{
case CRYP_KEYSIZE_256B:
/* Key Initialisation */
- CRYP->K0LR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K0RR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
break;
case CRYP_KEYSIZE_192B:
- CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
break;
case CRYP_KEYSIZE_128B:
- CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
break;
default:
break;
@@ -279,24 +279,24 @@ static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, u
switch(IVSize)
{
case CRYP_KEYSIZE_128B:
- CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
+ hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
- CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
+ hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
- CRYP->IV1LR = __REV(*(uint32_t*)(ivaddr));
+ hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
- CRYP->IV1RR = __REV(*(uint32_t*)(ivaddr));
+ hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));
break;
/* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */
case CRYP_KEYSIZE_192B:
- CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
+ hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
- CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
+ hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
break;
case CRYP_KEYSIZE_256B:
- CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
+ hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
- CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
+ hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
break;
default:
break;
@@ -324,19 +324,19 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In
for(i=0; (i < Ilength); i+=16)
{
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -354,13 +354,13 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In
}
}
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
}
/* Return function status */
@@ -388,15 +388,15 @@ static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8
for(i=0; (i < Ilength); i+=8)
{
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -414,9 +414,9 @@ static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8
}
}
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
}
/* Return function status */
@@ -445,19 +445,19 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin
hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&CRYP->DR, Size/4);
+ HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4);
/* Enable In DMA request */
- CRYP->DMACR = (CRYP_DMACR_DIEN);
+ hcryp->Instance->DMACR = (CRYP_DMACR_DIEN);
/* Enable the DMA Out DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&CRYP->DOUT, outputaddr, Size/4);
+ HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4);
/* Enable Out DMA request */
- CRYP->DMACR |= CRYP_DMACR_DOEN;
+ hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;
}
@@ -474,14 +474,14 @@ static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
if(hcryp->Phase == HAL_CRYP_PHASE_READY)
{
/* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_DES_ECB | Direction);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_ECB | Direction);
/* Set the key */
- CRYP->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
- CRYP->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -501,17 +501,17 @@ static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
if(hcryp->Phase == HAL_CRYP_PHASE_READY)
{
/* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_DES_CBC | Direction);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_CBC | Direction);
/* Set the key */
- CRYP->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
- CRYP->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -531,13 +531,13 @@ static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
if(hcryp->Phase == HAL_CRYP_PHASE_READY)
{
/* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_TDES_ECB | Direction);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_ECB | Direction);
/* Set the key */
CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -557,7 +557,7 @@ static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
if(hcryp->Phase == HAL_CRYP_PHASE_READY)
{
/* Set the CRYP peripheral in AES CBC mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_TDES_CBC | Direction);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_CBC | Direction);
/* Set the key */
CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
@@ -566,7 +566,7 @@ static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -621,6 +621,8 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
if(hcryp->State == HAL_CRYP_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hcryp->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_CRYP_MspInit(hcryp);
}
@@ -670,7 +672,7 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
hcryp->CrypOutCount = 0;
/* Disable the CRYP Peripheral Clock */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_CRYP_MspDeInit(hcryp);
@@ -760,20 +762,20 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
/* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -814,16 +816,16 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -871,16 +873,16 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -932,15 +934,15 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -959,18 +961,18 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
}
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Reset the ALGOMODE bits*/
CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
/* Set the CRYP peripheral in AES ECB decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1020,15 +1022,15 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -1050,16 +1052,16 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
/* Set the CRYP peripheral in AES CBC decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1107,16 +1109,16 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1172,60 +1174,60 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Locked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -1273,62 +1275,62 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CBC mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Locked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -1376,62 +1378,62 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -1482,14 +1484,14 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
@@ -1508,60 +1510,60 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
/* Set the CRYP peripheral in AES ECB decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -1612,15 +1614,15 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
@@ -1639,66 +1641,66 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
/* Set the CRYP peripheral in AES CBC decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -1747,63 +1749,63 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -1849,10 +1851,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1904,13 +1906,13 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1962,13 +1964,13 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -2022,15 +2024,15 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
@@ -2049,10 +2051,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
/* Set the CRYP peripheral in AES ECB decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -2106,15 +2108,15 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
@@ -2133,13 +2135,13 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
/* Set the CRYP peripheral in AES CBC decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -2192,13 +2194,13 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
/* Set the Initialization Vector */
CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -2265,7 +2267,7 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
CRYP_SetDESECBMode(hcryp, 0);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -2305,7 +2307,7 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -2345,7 +2347,7 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
CRYP_SetDESCBCMode(hcryp, 0);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -2385,7 +2387,7 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -2434,47 +2436,47 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetDESECBMode(hcryp, 0);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
/* Disable IT */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -2519,48 +2521,48 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetDESCBCMode(hcryp, 0);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
/* Disable IT */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -2605,47 +2607,47 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
/* Disable IT */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -2690,47 +2692,47 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
/* Disable IT */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -2962,7 +2964,7 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
CRYP_SetTDESECBMode(hcryp, 0);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -3003,7 +3005,7 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Cypher Data and Get Plain Data */
if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
@@ -3044,7 +3046,7 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
CRYP_SetTDESCBCMode(hcryp, 0);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -3085,7 +3087,7 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write Cypher Data and Get Plain Data */
if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
@@ -3134,47 +3136,47 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetTDESECBMode(hcryp, 0);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
/* Disable IT */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -3219,46 +3221,46 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetTDESCBCMode(hcryp, 0);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -3303,46 +3305,46 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -3387,46 +3389,46 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable CRYP */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 8;
hcryp->CrypInCount -= 8;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 8;
hcryp->CrypOutCount -= 8;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
@@ -3797,7 +3799,7 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
* @}
*/
-#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx || STM32F479xx */
#endif /* HAL_CRYP_MODULE_ENABLED */
/**
diff --git a/f4/src/stm32f4xx_hal_cryp_ex.c b/f4/src/stm32f4xx_hal_cryp_ex.c
index 3a13337..2de031b 100755
--- a/f4/src/stm32f4xx_hal_cryp_ex.c
+++ b/f4/src/stm32f4xx_hal_cryp_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cryp_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Extended CRYP HAL module driver
* This file provides firmware functions to manage the following
* functionalities of CRYP extension peripheral:
@@ -69,7 +69,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -110,7 +110,7 @@
#ifdef HAL_CRYP_MODULE_ENABLED
-#if defined(STM32F437xx) || defined(STM32F439xx)
+#if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -156,7 +156,7 @@ static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma)
/* Disable the DMA transfer for input Fifo request by resetting the DIEN bit
in the DMACR register */
- CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
/* Call input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
@@ -173,10 +173,10 @@ static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma)
/* Disable the DMA transfer for output Fifo request by resetting the DOEN bit
in the DMACR register */
- CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
/* Enable the CRYP peripheral */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
@@ -213,43 +213,43 @@ static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32
{
case CRYP_KEYSIZE_256B:
/* Key Initialisation */
- CRYP->K0LR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K0RR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
break;
case CRYP_KEYSIZE_192B:
- CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
break;
case CRYP_KEYSIZE_128B:
- CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
- CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
break;
default:
break;
@@ -267,13 +267,13 @@ static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *Init
{
uint32_t ivaddr = (uint32_t)InitVector;
- CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
+ hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
- CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
+ hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
- CRYP->IV1LR = __REV(*(uint32_t*)(ivaddr));
+ hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
- CRYP->IV1RR = __REV(*(uint32_t*)(ivaddr));
+ hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));
}
/**
@@ -296,19 +296,19 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, ui
for(i=0; (i < Ilength); i+=16)
{
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -326,13 +326,13 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, ui
}
}
/* Read the Output block from the OUT FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
}
/* Return function status */
@@ -358,16 +358,16 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp,
if(hcryp->Init.HeaderSize != 0)
{
/* Select header phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
for(loopcounter = 0; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=16)
{
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -385,13 +385,13 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp,
}
}
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
}
@@ -400,7 +400,7 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp,
/* Get tick */
tickstart = HAL_GetTick();
- while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -444,19 +444,19 @@ static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t input
hcryp->hdmaout->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&CRYP->DR, Size/4);
+ HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4);
/* Enable In DMA request */
- CRYP->DMACR = CRYP_DMACR_DIEN;
+ hcryp->Instance->DMACR = CRYP_DMACR_DIEN;
/* Enable the DMA Out DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&CRYP->DOUT, outputaddr, Size/4);
+ HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4);
/* Enable Out DMA request */
- CRYP->DMACR |= CRYP_DMACR_DOEN;
+ hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;
}
/**
@@ -602,26 +602,26 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
/* Set the Initialization Vector */
CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
/* Select init phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
b0addr = (uint32_t)blockb0;
/* Write the blockb0 block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -647,17 +647,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
if(headersize != 0)
{
/* Select header phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
{
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
{
{
/* Check for the Timeout */
@@ -677,20 +677,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
}
}
/* Write the header block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
}
/* Get tick */
tickstart = HAL_GetTick();
- while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -717,13 +717,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
hcryp->Init.pScratch[15] &= 0xfe;
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -773,16 +773,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES GCM mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
/* Set the Initialization Vector */
CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -812,16 +812,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
}
/* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -871,16 +871,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES GCM decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
/* Set the Initialization Vector */
CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -909,13 +909,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
return HAL_TIMEOUT;
}
/* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -966,48 +966,48 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t S
hcryp->Phase = HAL_CRYP_PHASE_FINAL;
/* Disable CRYP to start the final phase */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Select final phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_FINAL);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write the number of bits in header (64 bits) followed by the number of bits
in the payload */
if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
- CRYP->DR = __RBIT(headerlength >> 32);
- CRYP->DR = __RBIT(headerlength);
- CRYP->DR = __RBIT(inputlength >> 32);
- CRYP->DR = __RBIT(inputlength);
+ hcryp->Instance->DR = __RBIT(headerlength >> 32);
+ hcryp->Instance->DR = __RBIT(headerlength);
+ hcryp->Instance->DR = __RBIT(inputlength >> 32);
+ hcryp->Instance->DR = __RBIT(inputlength);
}
else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
- CRYP->DR = __REV(headerlength >> 32);
- CRYP->DR = __REV(headerlength);
- CRYP->DR = __REV(inputlength >> 32);
- CRYP->DR = __REV(inputlength);
+ hcryp->Instance->DR = __REV(headerlength >> 32);
+ hcryp->Instance->DR = __REV(headerlength);
+ hcryp->Instance->DR = __REV(inputlength >> 32);
+ hcryp->Instance->DR = __REV(inputlength);
}
else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
- CRYP->DR = __ROR((uint32_t)(headerlength >> 32), 16);
- CRYP->DR = __ROR((uint32_t)headerlength, 16);
- CRYP->DR = __ROR((uint32_t)(inputlength >> 32), 16);
- CRYP->DR = __ROR((uint32_t)inputlength, 16);
+ hcryp->Instance->DR = __ROR((uint32_t)(headerlength >> 32), 16);
+ hcryp->Instance->DR = __ROR((uint32_t)headerlength, 16);
+ hcryp->Instance->DR = __ROR((uint32_t)(inputlength >> 32), 16);
+ hcryp->Instance->DR = __ROR((uint32_t)inputlength, 16);
}
else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
{
- CRYP->DR = (uint32_t)(headerlength >> 32);
- CRYP->DR = (uint32_t)(headerlength);
- CRYP->DR = (uint32_t)(inputlength >> 32);
- CRYP->DR = (uint32_t)(inputlength);
+ hcryp->Instance->DR = (uint32_t)(headerlength >> 32);
+ hcryp->Instance->DR = (uint32_t)(headerlength);
+ hcryp->Instance->DR = (uint32_t)(inputlength >> 32);
+ hcryp->Instance->DR = (uint32_t)(inputlength);
}
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -1026,13 +1026,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t S
}
/* Read the Auth TAG in the IN FIFO */
- *(uint32_t*)(tagaddr) = CRYP->DOUT;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
tagaddr+=4;
- *(uint32_t*)(tagaddr) = CRYP->DOUT;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
tagaddr+=4;
- *(uint32_t*)(tagaddr) = CRYP->DOUT;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
tagaddr+=4;
- *(uint32_t*)(tagaddr) = CRYP->DOUT;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
}
/* Change the CRYP peripheral state */
@@ -1075,27 +1075,27 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *A
hcryp->Phase = HAL_CRYP_PHASE_FINAL;
/* Disable CRYP to start the final phase */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Select final phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_FINAL);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Write the counter block in the IN FIFO */
- CRYP->DR = *(uint32_t*)ctraddr;
+ hcryp->Instance->DR = *(uint32_t*)ctraddr;
ctraddr+=4;
- CRYP->DR = *(uint32_t*)ctraddr;
+ hcryp->Instance->DR = *(uint32_t*)ctraddr;
ctraddr+=4;
- CRYP->DR = *(uint32_t*)ctraddr;
+ hcryp->Instance->DR = *(uint32_t*)ctraddr;
ctraddr+=4;
- CRYP->DR = *(uint32_t*)ctraddr;
+ hcryp->Instance->DR = *(uint32_t*)ctraddr;
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -1114,10 +1114,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *A
}
/* Read the Auth TAG in the IN FIFO */
- temptag[0] = CRYP->DOUT;
- temptag[1] = CRYP->DOUT;
- temptag[2] = CRYP->DOUT;
- temptag[3] = CRYP->DOUT;
+ temptag[0] = hcryp->Instance->DOUT;
+ temptag[1] = hcryp->Instance->DOUT;
+ temptag[2] = hcryp->Instance->DOUT;
+ temptag[3] = hcryp->Instance->DOUT;
}
/* Copy temporary authentication TAG in user TAG buffer */
@@ -1250,26 +1250,26 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
/* Set the Initialization Vector */
CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
/* Select init phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
b0addr = (uint32_t)blockb0;
/* Write the blockb0 block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -1295,17 +1295,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
if(headersize != 0)
{
/* Select header phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
/* Enable Crypto processor */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
{
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -1323,20 +1323,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
}
}
/* Write the header block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
}
/* Get tick */
tickstart = HAL_GetTick();
- while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -1362,13 +1362,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
/* Reset bit 0 */
hcryp->Init.pScratch[15] &= 0xfe;
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1426,16 +1426,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES GCM mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
/* Set the Initialization Vector */
CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP to start the init phase */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -1463,13 +1463,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
return HAL_TIMEOUT;
}
/* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1478,9 +1478,9 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
if(Size != 0)
{
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
}
else
{
@@ -1492,42 +1492,42 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
/* Return function status */
return HAL_OK;
}
- else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP peripheral state */
@@ -1662,26 +1662,26 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
/* Set the Initialization Vector */
CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
/* Select init phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
b0addr = (uint32_t)blockb0;
/* Write the blockb0 block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -1704,17 +1704,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
if(headersize != 0)
{
/* Select header phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
/* Enable Crypto processor */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
{
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -1729,20 +1729,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
}
}
/* Write the header block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
}
/* Get tick */
tickstart = HAL_GetTick();
- while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -1766,10 +1766,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
hcryp->Init.pScratch[15] &= 0xfe;
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1778,9 +1778,9 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
if(Size != 0)
{
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
}
else
{
@@ -1791,42 +1791,42 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
/* Return function status */
return HAL_OK;
}
- else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call Input transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP peripheral state */
@@ -1876,16 +1876,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES GCM decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
/* Set the Initialization Vector */
CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP to start the init phase */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -1911,10 +1911,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
return HAL_TIMEOUT;
}
/* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1923,9 +1923,9 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
if(Size != 0)
{
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
}
else
{
@@ -1938,42 +1938,42 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
/* Return function status */
return HAL_OK;
}
- else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP peripheral state */
@@ -2108,26 +2108,26 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
/* Set the Initialization Vector */
CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
/* Select init phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
b0addr = (uint32_t)blockb0;
/* Write the blockb0 block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -2150,17 +2150,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
if(headersize != 0)
{
/* Select header phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
/* Enable Crypto processor */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
{
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -2175,20 +2175,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
}
}
/* Write the header block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
}
/* Get tick */
tickstart = HAL_GetTick();
- while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -2211,60 +2211,60 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
/* Reset bit 0 */
hcryp->Init.pScratch[15] &= 0xfe;
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
}
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Return function status */
return HAL_OK;
}
- else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
{
inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
/* Write the Input block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
inputaddr+=4;
- CRYP->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
if(hcryp->CrypInCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the Input data transfer complete callback */
HAL_CRYP_InCpltCallback(hcryp);
}
}
- else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
{
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP->DOUT;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
if(hcryp->CrypOutCount == 0)
{
- __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP peripheral state */
@@ -2311,16 +2311,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES GCM mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
/* Set the Initialization Vector */
CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Enable CRYP to start the init phase */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -2340,7 +2340,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
}
}
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the header phase */
if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
@@ -2348,13 +2348,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
return HAL_TIMEOUT;
}
/* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -2501,26 +2501,26 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
/* Set the Initialization Vector */
CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
/* Select init phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
b0addr = (uint32_t)blockb0;
/* Write the blockb0 block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -2543,17 +2543,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
if(headersize != 0)
{
/* Select header phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
/* Enable Crypto processor */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
{
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -2568,20 +2568,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
}
}
/* Write the header block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
}
/* Get tick */
tickstart = HAL_GetTick();
- while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -2605,10 +2605,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
hcryp->Init.pScratch[15] &= 0xfe;
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -2662,13 +2662,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES GCM decryption mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
/* Set the Initialization Vector */
CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
/* Enable CRYP to start the init phase */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -2694,10 +2694,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
return HAL_TIMEOUT;
}
/* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE();
+ __HAL_CRYP_DISABLE(hcryp);
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -2845,26 +2845,26 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
/* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
/* Set the Initialization Vector */
CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
/* Select init phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
b0addr = (uint32_t)blockb0;
/* Write the blockb0 block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
b0addr+=4;
- CRYP->DR = *(uint32_t*)(b0addr);
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
/* Get tick */
tickstart = HAL_GetTick();
@@ -2889,17 +2889,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
if(headersize != 0)
{
/* Select header phase */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
/* Enable Crypto processor */
- __HAL_CRYP_ENABLE();
+ __HAL_CRYP_ENABLE(hcryp);
for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
{
/* Get tick */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -2914,20 +2914,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
}
}
/* Write the header block in the IN FIFO */
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
- CRYP->DR = *(uint32_t*)(headeraddr);
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
headeraddr+=4;
}
/* Get tick */
tickstart = HAL_GetTick();
- while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -2950,10 +2950,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
/* Reset bit 0 */
hcryp->Init.pScratch[15] &= 0xfe;
/* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH();
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
/* Set the phase */
hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -3029,7 +3029,7 @@ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp)
/**
* @}
*/
-#endif /* STM32F437xx || STM32F439xx */
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
#endif /* HAL_CRYP_MODULE_ENABLED */
/**
diff --git a/f4/src/stm32f4xx_hal_dac.c b/f4/src/stm32f4xx_hal_dac.c
index bc84afe..3ff79e6 100755
--- a/f4/src/stm32f4xx_hal_dac.c
+++ b/f4/src/stm32f4xx_hal_dac.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dac.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
@@ -20,7 +20,7 @@
[..]
*** DAC Channels ***
====================
- [..]
+ [..]
The device integrates two 12-bit Digital Analog Converters that can
be used independently or simultaneously (dual mode):
(#) DAC channel1 with DAC_OUT1 (PA4) as output
@@ -141,7 +141,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -183,7 +183,10 @@
#ifdef HAL_DAC_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -238,6 +241,8 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
if(hdac->State == HAL_DAC_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hdac->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_DAC_MspInit(hdac);
}
@@ -415,7 +420,7 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, Channel);
-
+
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -932,7 +937,9 @@ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
#endif /* HAL_DAC_MODULE_ENABLED */
/**
diff --git a/f4/src/stm32f4xx_hal_dac_ex.c b/f4/src/stm32f4xx_hal_dac_ex.c
index 67f1403..c10d0f4 100755
--- a/f4/src/stm32f4xx_hal_dac_ex.c
+++ b/f4/src/stm32f4xx_hal_dac_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dac_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DAC extension peripheral:
@@ -25,7 +25,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -67,8 +67,10 @@
#ifdef HAL_DAC_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -153,7 +155,7 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the selected wave generation for the selected DAC channel */
- MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_WAVE_TRIANGLE | Amplitude) << Channel);
+ MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -201,7 +203,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the selected wave generation for the selected DAC channel */
- MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_WAVE_NOISE | Amplitude) << Channel);
+ MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -363,7 +365,9 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
#endif /* HAL_DAC_MODULE_ENABLED */
diff --git a/f4/src/stm32f4xx_hal_dcmi.c b/f4/src/stm32f4xx_hal_dcmi.c
index 6317020..1708320 100755
--- a/f4/src/stm32f4xx_hal_dcmi.c
+++ b/f4/src/stm32f4xx_hal_dcmi.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dcmi.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief DCMI HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the Digital Camera Interface (DCMI) peripheral:
@@ -63,7 +63,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -103,7 +103,9 @@
#ifdef HAL_DCMI_MODULE_ENABLED
-#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* 1s */
@@ -141,7 +143,7 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma);
* the configuration information for DCMI.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
+__weak HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
{
/* Check the DCMI peripheral state */
if(hdcmi == NULL)
@@ -161,13 +163,15 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
if(hdcmi->State == HAL_DCMI_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hdcmi->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_DCMI_MspInit(hdcmi);
}
/* Change the DCMI state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
- /* Configures the HS, VS, DE and PC polarity */
+ /* Configures the HS, VS, DE and PC polarity */
hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |
DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |
DCMI_CR_ESS);
@@ -604,10 +608,10 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
* @brief Configure the DCMI CROP coordinate.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
- * @param YSize: DCMI Line number
- * @param XSize: DCMI Pixel per line
* @param X0: DCMI window X offset
* @param Y0: DCMI window Y offset
+ * @param XSize: DCMI Pixel per line
+ * @param YSize: DCMI Line number
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
@@ -813,7 +817,9 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
+ STM32F479xx */
#endif /* HAL_DCMI_MODULE_ENABLED */
/**
* @}
diff --git a/f4/src/stm32f4xx_hal_dcmi_ex.c b/f4/src/stm32f4xx_hal_dcmi_ex.c
new file mode 100644
index 0000000..3a1d74d
--- /dev/null
+++ b/f4/src/stm32f4xx_hal_dcmi_ex.c
@@ -0,0 +1,214 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dcmi_ex.c
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief DCMI Extension HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of DCMI extension peripheral:
+ * + Extension features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### DCMI peripheral extension features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the DCMI interface for STM32F446xx
+ devices contains the following additional features :
+
+ (+) Support of Black and White cameras
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to manage the Black and White feature
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+/** @defgroup DCMIEx DCMIEx
+ * @brief DCMI Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) ||\
+ defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DCMIEx_Exported_Functions DCMI Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup DCMIEx_Exported_Functions_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the DCMI
+ (+) De-initialize the DCMI
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the DCMI according to the specified
+ * parameters in the DCMI_InitTypeDef and create the associated handle.
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Check the DCMI peripheral state */
+ if(hdcmi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check function parameters */
+ assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
+ assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
+ assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
+ assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
+ assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
+ assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
+ assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
+ assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));
+ assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));
+ assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));
+ assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+ if(hdcmi->State == HAL_DCMI_STATE_RESET)
+ {
+ /* Init the low level hardware */
+ HAL_DCMI_MspInit(hdcmi);
+ }
+
+ /* Change the DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+ /* Configures the HS, VS, DE and PC polarity */
+ hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\
+ DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |\
+ DCMI_CR_ESS
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\
+ DCMI_CR_LSM | DCMI_CR_OELS
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+ );
+ hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\
+ hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity |\
+ hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\
+ hdcmi->Init.JPEGMode
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ | hdcmi->Init.ByteSelectMode |\
+ hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\
+ hdcmi->Init.LineSelectStart
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+ );
+ if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
+ {
+ DCMI->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |
+ ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << 8)|
+ ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << 16) |
+ ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << 24));
+
+ }
+
+ /* Enable the Line interrupt */
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE);
+
+ /* Enable the VSYNC interrupt */
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_VSYNC);
+
+ /* Enable the Frame capture complete interrupt */
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
+
+ /* Enable the Synchronization error interrupt */
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_ERR);
+
+ /* Enable the Overflow interrupt */
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_OVF);
+
+ /* Enable DCMI by setting DCMIEN bit */
+ __HAL_DCMI_ENABLE(hdcmi);
+
+ /* Update error code */
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
+
+ /* Initialize the DCMI state*/
+ hdcmi->State = HAL_DCMI_STATE_READY;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx ||\
+ STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* HAL_DCMI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/src/stm32f4xx_hal_dma.c b/f4/src/stm32f4xx_hal_dma.c
index 66657b1..bb9a03a 100755
--- a/f4/src/stm32f4xx_hal_dma.c
+++ b/f4/src/stm32f4xx_hal_dma.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -86,7 +86,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -128,6 +128,14 @@
#ifdef HAL_DMA_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register */
+ __IO uint32_t Reserved0;
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
+} DMA_Base_Registers;
+
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup DMA_Private_Constants
@@ -143,6 +151,8 @@
* @{
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
+
/**
* @}
*/
@@ -178,9 +188,9 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
-{
+{
uint32_t tmp = 0;
-
+
/* Check the DMA peripheral state */
if(hdma == NULL)
{
@@ -254,6 +264,10 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
/* Write to DMA Stream FCR */
hdma->Instance->FCR = tmp;
+ /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+ DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+ DMA_CalcBaseAndBitshift(hdma);
+
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@@ -271,6 +285,8 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
*/
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
{
+ DMA_Base_Registers *regs;
+
/* Check the DMA peripheral state */
if(hdma == NULL)
{
@@ -297,19 +313,18 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
/* Reset DMA Streamx memory 0 address register */
hdma->Instance->M0AR = 0;
-
+
/* Reset DMA Streamx memory 1 address register */
hdma->Instance->M1AR = 0;
-
+
/* Reset DMA Streamx FIFO control register */
hdma->Instance->FCR = (uint32_t)0x00000021;
-
- /* Clear all flags */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+ /* Get DMA steam Base Address */
+ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+ /* Clear all interrupt flags at correct offset within the register */
+ regs->IFCR = 0x3F << hdma->StreamIndex;
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@@ -403,20 +418,9 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
/* Configure the source, destination address and the data length */
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
- /* Enable the transfer complete interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
-
- /* Enable the Half transfer complete interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
-
- /* Enable the transfer Error interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
-
- /* Enable the FIFO Error interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE);
-
- /* Enable the direct mode Error interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME);
+ /* Enable all interrupts */
+ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME;
+ hdma->Instance->FCR |= DMA_IT_FE;
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
@@ -484,28 +488,33 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
{
uint32_t temp, tmp, tmp1, tmp2;
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0;
+
+ /* calculate DMA base and stream number */
+ DMA_Base_Registers *regs;
+
+ regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
/* Get the level transfer complete flag */
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
{
/* Transfer Complete flag */
- temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
+ temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
}
else
{
/* Half Transfer Complete flag */
- temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
+ temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
}
/* Get tick */
tickstart = HAL_GetTick();
- while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
+ while((regs->ISR & temp) == RESET)
{
- tmp = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
- tmp1 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
- tmp2 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ tmp = regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex);
+ tmp1 = regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex);
+ tmp2 = regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex);
if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET))
{
if(tmp != RESET)
@@ -514,15 +523,15 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
hdma->ErrorCode |= HAL_DMA_ERROR_TE;
/* Clear the transfer error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
}
if(tmp1 != RESET)
{
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_FE;
-
+
/* Clear the FIFO error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
}
if(tmp2 != RESET)
{
@@ -530,16 +539,16 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
hdma->ErrorCode |= HAL_DMA_ERROR_DME;
/* Clear the Direct Mode error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
}
/* Change the DMA state */
hdma->State= HAL_DMA_STATE_ERROR;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
- }
+ }
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
@@ -553,7 +562,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
/* Process Unlocked */
__HAL_UNLOCK(hdma);
-
+
return HAL_TIMEOUT;
}
}
@@ -561,14 +570,12 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
{
+ /* Clear the half transfer and transfer complete flags */
+ regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
+
/* Multi_Buffering mode enabled */
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
{
- /* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
- /* Clear the transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-
/* Current memory buffer used is Memory 0 */
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
{
@@ -584,11 +591,6 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
}
else
{
- /* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
- /* Clear the transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-
/* The selected Streamx EN bit is cleared (DMA is disabled and all transfers
are complete) */
hdma->State = HAL_DMA_STATE_READY_MEM0;
@@ -597,13 +599,13 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
__HAL_UNLOCK(hdma);
}
else
- {
+ {
+ /* Clear the half transfer complete flag */
+ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+
/* Multi_Buffering mode enabled */
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
{
- /* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
/* Current memory buffer used is Memory 0 */
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
{
@@ -619,9 +621,6 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
}
else
{
- /* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
}
@@ -637,8 +636,13 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
+ /* calculate DMA base and stream number */
+ DMA_Base_Registers *regs;
+
+ regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+
/* Transfer Error Interrupt management ***************************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
+ if ((regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
{
@@ -646,7 +650,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
/* Clear the transfer error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_TE;
@@ -655,7 +659,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
hdma->State = HAL_DMA_STATE_ERROR;
/* Process Unlocked */
- __HAL_UNLOCK(hdma);
+ __HAL_UNLOCK(hdma);
if(hdma->XferErrorCallback != NULL)
{
@@ -665,7 +669,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
}
}
/* FIFO Error Interrupt management ******************************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)) != RESET)
+ if ((regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
{
@@ -673,7 +677,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE);
/* Clear the FIFO error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_FE;
@@ -692,7 +696,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
}
}
/* Direct Mode Error Interrupt management ***********************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)) != RESET)
+ if ((regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
{
@@ -700,7 +704,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME);
/* Clear the direct mode error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_DME;
@@ -719,15 +723,15 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
}
}
/* Half Transfer Complete Interrupt management ******************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
+ if ((regs->ISR & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
- {
+ {
/* Multi_Buffering mode enabled */
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
{
/* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
/* Current memory buffer used is Memory 0 */
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
@@ -751,7 +755,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
}
/* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
@@ -765,14 +769,14 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
}
}
/* Transfer Complete Interrupt management ***********************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
+ if ((regs->ISR & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
{
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
{
/* Clear the transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
/* Current memory buffer used is Memory 1 */
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
@@ -784,7 +788,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
}
}
/* Current memory buffer used is Memory 0 */
- else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
+ else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
{
if(hdma->XferCpltCallback != NULL)
{
@@ -802,7 +806,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
}
/* Clear the transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
@@ -811,7 +815,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
hdma->State = HAL_DMA_STATE_READY_MEM0;
/* Process Unlocked */
- __HAL_UNLOCK(hdma);
+ __HAL_UNLOCK(hdma);
if(hdma->XferCpltCallback != NULL)
{
@@ -912,6 +916,34 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
hdma->Instance->M0AR = DstAddress;
}
}
+
+/**
+ * @brief Returns the DMA Stream base address depending on stream number
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval Stream base address
+ */
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
+{
+ uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFF) - 16) / 24;
+
+ /* lookup table for necessary bitshift of flags within status registers */
+ static const uint8_t flagBitshiftOffset[8] = {0, 6, 16, 22, 0, 6, 16, 22};
+ hdma->StreamIndex = flagBitshiftOffset[stream_number];
+
+ if (stream_number > 3)
+ {
+ /* return pointer to HISR and HIFCR */
+ hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FF)) + 4);
+ }
+ else
+ {
+ /* return pointer to LISR and LIFCR */
+ hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FF));
+ }
+
+ return hdma->StreamBaseAddress;
+}
/**
* @}
*/
diff --git a/f4/src/stm32f4xx_hal_dma2d.c b/f4/src/stm32f4xx_hal_dma2d.c
index 21e47a2..46e5b70 100755
--- a/f4/src/stm32f4xx_hal_dma2d.c
+++ b/f4/src/stm32f4xx_hal_dma2d.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma2d.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief DMA2D HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the DMA2D peripheral:
@@ -87,7 +87,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -127,7 +127,7 @@
#ifdef HAL_DMA2D_MODULE_ENABLED
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* Private types -------------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -198,6 +198,8 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
if(hdma2d->State == HAL_DMA2D_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hdma2d->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_DMA2D_MspInit(hdma2d);
}
@@ -893,7 +895,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La
if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
{
/* Prepare the value to be wrote to the BGCOLR register */
- tmp |= ((pLayerCfg->InputAlpha) & 0x00FFFFFF);
+ tmp = ((pLayerCfg->InputAlpha) & 0x00FFFFFF);
/* Write to DMA2D BGCOLR register */
hdma2d->Instance->BGCOLR = tmp;
@@ -939,7 +941,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La
if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
{
/* Prepare the value to be wrote to the FGCOLR register */
- tmp |= ((pLayerCfg->InputAlpha) & 0x00FFFFFF);
+ tmp = ((pLayerCfg->InputAlpha) & 0x00FFFFFF);
/* Write to DMA2D FGCOLR register */
hdma2d->Instance->FGCOLR = tmp;
@@ -1251,7 +1253,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_
/**
* @}
*/
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#endif /* HAL_DMA2D_MODULE_ENABLED */
/**
* @}
diff --git a/f4/src/stm32f4xx_hal_dma_ex.c b/f4/src/stm32f4xx_hal_dma_ex.c
index 521fe36..17ecbb0 100755
--- a/f4/src/stm32f4xx_hal_dma_ex.c
+++ b/f4/src/stm32f4xx_hal_dma_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the DMA Extension peripheral:
@@ -27,7 +27,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
diff --git a/f4/src/stm32f4xx_hal_dsi.c b/f4/src/stm32f4xx_hal_dsi.c
new file mode 100644
index 0000000..f956ae3
--- /dev/null
+++ b/f4/src/stm32f4xx_hal_dsi.c
@@ -0,0 +1,2244 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dsi.c
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief DSI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the DSI peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+/** @addtogroup DSI
+ * @{
+ */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @addtogroup DSI_Private_Constants
+ * @{
+ */
+#define DSI_TIMEOUT_VALUE ((uint32_t)1000) /* 1s */
+
+#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
+ DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
+ DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \
+ DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15)
+#define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4)
+#define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX
+#define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX
+#define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME)
+#define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE
+#define DSI_ERROR_PSE_MASK DSI_ISR1_PSE
+#define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE
+#define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE
+#define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE)
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1);
+
+/* Private functions ---------------------------------------------------------*/
+/**
+ * @brief Generic DSI packet header configuration
+ * @param DSIx: Pointer to DSI register base
+ * @param ChannelID: Virtual channel ID of the header packet
+ * @param DataType: Packet data type of the header packet
+ * This parameter can be any value of :
+ * @ref DSI_SHORT_WRITE_PKT_Data_Type
+ * or @ref DSI_LONG_WRITE_PKT_Data_Type
+ * or @ref DSI_SHORT_READ_PKT_Data_Type
+ * or DSI_MAX_RETURN_PKT_SIZE
+ * @param Data0: Word count LSB
+ * @param Data1: Word count MSB
+ * @retval None
+ */
+static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
+ uint32_t ChannelID,
+ uint32_t DataType,
+ uint32_t Data0,
+ uint32_t Data1)
+{
+ /* Update the DSI packet header with new information */
+ DSIx->GHCR = (DataType | (ChannelID<<6) | (Data0<<8) | (Data1<<16));
+}
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DSI_Exported_Functions
+ * @{
+ */
+
+/** @defgroup DSI_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the DSI
+ (+) De-initialize the DSI
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the DSI according to the specified
+ * parameters in the DSI_InitTypeDef and create the associated handle.
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains
+ * the PLL Clock structure definition for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
+{
+ uint32_t tickstart = 0;
+ uint32_t unitIntervalx4 = 0;
+ uint32_t tempIDF = 0;
+
+ /* Check the DSI handle allocation */
+ if(hdsi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check function parameters */
+ assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
+ assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
+ assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
+ assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
+ assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
+
+ if(hdsi->State == HAL_DSI_STATE_RESET)
+ {
+ /* Initialize the low level hardware */
+ HAL_DSI_MspInit(hdsi);
+ }
+
+ /* Change DSI peripheral state */
+ hdsi->State = HAL_DSI_STATE_BUSY;
+
+ /**************** Turn on the regulator and enable the DSI PLL ****************/
+
+ /* Enable the regulator */
+ __HAL_DSI_REG_ENABLE(hdsi);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until the regulator is ready */
+ while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the PLL division factors */
+ hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
+ hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2) | ((PLLInit->PLLIDF)<<11) | ((PLLInit->PLLODF)<<16));
+
+ /* Enable the DSI PLL */
+ __HAL_DSI_PLL_ENABLE(hdsi);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for the lock of the PLL */
+ while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /*************************** Set the PHY parameters ***************************/
+
+ /* D-PHY clock and digital enable*/
+ hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
+
+ /* Clock lane configuration */
+ hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
+ hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
+
+ /* Configure the number of active data lanes */
+ hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
+ hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
+
+ /************************ Set the DSI clock parameters ************************/
+
+ /* Set the TX escape clock division factor */
+ hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
+ hdsi->Instance->CCR = hdsi->Init.TXEscapeCkdiv;
+
+ /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
+ /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
+ /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */
+ tempIDF = (PLLInit->PLLIDF > 0) ? PLLInit->PLLIDF : 1;
+ unitIntervalx4 = (4000000 * tempIDF * (1 << PLLInit->PLLODF)) / ((HSE_VALUE/1000) * PLLInit->PLLNDIV);
+
+ /* Set the bit period in high-speed mode */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_UIX4;
+ hdsi->Instance->WPCR[0] |= unitIntervalx4;
+
+ /****************************** Error management *****************************/
+
+ /* Disable all error interrupts and reset the Error Mask */
+ hdsi->Instance->IER[0] = 0;
+ hdsi->Instance->IER[1] = 0;
+ hdsi->ErrorMsk = 0;
+
+ /* Initialise the error code */
+ hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
+
+ /* Initialize the DSI state*/
+ hdsi->State = HAL_DSI_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-initializes the DSI peripheral registers to their default reset
+ * values.
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
+{
+ /* Check the DSI handle allocation */
+ if(hdsi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Change DSI peripheral state */
+ hdsi->State = HAL_DSI_STATE_BUSY;
+
+ /* Disable the DSI wrapper */
+ __HAL_DSI_WRAPPER_DISABLE(hdsi);
+
+ /* Disable the DSI host */
+ __HAL_DSI_DISABLE(hdsi);
+
+ /* D-PHY clock and digital disable */
+ hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);
+
+ /* Turn off the DSI PLL */
+ __HAL_DSI_PLL_DISABLE(hdsi);
+
+ /* Disable the regulator */
+ __HAL_DSI_REG_DISABLE(hdsi);
+
+ /* DeInit the low level hardware */
+ HAL_DSI_MspDeInit(hdsi);
+
+ /* Initialise the error code */
+ hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
+
+ /* Initialize the DSI state*/
+ hdsi->State = HAL_DSI_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Return the DSI error code
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval DSI Error Code
+ */
+uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
+{
+ /* Get the error code */
+ return hdsi->ErrorCode;
+}
+
+/**
+ * @brief Enable the error monitor flags
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param ActiveErrors: indicates which error interrupts will be enabled.
+ * This parameter can be any combination of @ref DSI_Error_Data_Type.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ hdsi->Instance->IER[0] = 0;
+ hdsi->Instance->IER[1] = 0;
+
+ /* Store active errors to the handle */
+ hdsi->ErrorMsk = ActiveErrors;
+
+ if(ActiveErrors & HAL_DSI_ERROR_ACK)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[0] |= DSI_ERROR_ACK_MASK;
+ }
+
+ if(ActiveErrors & HAL_DSI_ERROR_PHY)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[0] |= DSI_ERROR_PHY_MASK;
+ }
+
+ if(ActiveErrors & HAL_DSI_ERROR_TX)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[1] |= DSI_ERROR_TX_MASK;
+ }
+
+ if(ActiveErrors & HAL_DSI_ERROR_RX)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[1] |= DSI_ERROR_RX_MASK;
+ }
+
+ if(ActiveErrors & HAL_DSI_ERROR_ECC)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[1] |= DSI_ERROR_ECC_MASK;
+ }
+
+ if(ActiveErrors & HAL_DSI_ERROR_CRC)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[1] |= DSI_ERROR_CRC_MASK;
+ }
+
+ if(ActiveErrors & HAL_DSI_ERROR_PSE)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[1] |= DSI_ERROR_PSE_MASK;
+ }
+
+ if(ActiveErrors & HAL_DSI_ERROR_EOT)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[1] |= DSI_ERROR_EOT_MASK;
+ }
+
+ if(ActiveErrors & HAL_DSI_ERROR_OVF)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[1] |= DSI_ERROR_OVF_MASK;
+ }
+
+ if(ActiveErrors & HAL_DSI_ERROR_GEN)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[1] |= DSI_ERROR_GEN_MASK;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the DSI MSP.
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval None
+ */
+__weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DSI_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief De-initializes the DSI MSP.
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval None
+ */
+__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DSI_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides function allowing to:
+ (+) Handle DSI interrupt request
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Handles DSI interrupt request.
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
+{
+ uint32_t ErrorStatus0, ErrorStatus1;
+
+ /* Tearing Effect Interrupt management ***************************************/
+ if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET)
+ {
+ if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET)
+ {
+ /* Clear the Tearing Effect Interrupt Flag */
+ __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
+
+ /* Tearing Effect Callback */
+ HAL_DSI_TearingEffectCallback(hdsi);
+ }
+ }
+
+ /* End of Refresh Interrupt management ***************************************/
+ if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET)
+ {
+ if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET)
+ {
+ /* Clear the End of Refresh Interrupt Flag */
+ __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
+
+ /* End of Refresh Callback */
+ HAL_DSI_EndOfRefreshCallback(hdsi);
+ }
+ }
+
+ /* Error Interrupts management ***********************************************/
+ if(hdsi->ErrorMsk != 0)
+ {
+ ErrorStatus0 = hdsi->Instance->ISR[0];
+ ErrorStatus0 &= hdsi->Instance->IER[0];
+ ErrorStatus1 = hdsi->Instance->ISR[1];
+ ErrorStatus1 &= hdsi->Instance->IER[1];
+
+ if(ErrorStatus0 & DSI_ERROR_ACK_MASK)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
+ }
+
+ if(ErrorStatus0 & DSI_ERROR_PHY_MASK)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
+ }
+
+ if(ErrorStatus1 & DSI_ERROR_TX_MASK)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
+ }
+
+ if(ErrorStatus1 & DSI_ERROR_RX_MASK)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
+ }
+
+ if(ErrorStatus1 & DSI_ERROR_ECC_MASK)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
+ }
+
+ if(ErrorStatus1 & DSI_ERROR_CRC_MASK)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
+ }
+
+ if(ErrorStatus1 & DSI_ERROR_PSE_MASK)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
+ }
+
+ if(ErrorStatus1 & DSI_ERROR_EOT_MASK)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
+ }
+
+ if(ErrorStatus1 & DSI_ERROR_OVF_MASK)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
+ }
+
+ if(ErrorStatus1 & DSI_ERROR_GEN_MASK)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
+ }
+
+ /* Check only selected errors */
+ if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
+ {
+ /* DSI error interrupt user callback */
+ HAL_DSI_ErrorCallback(hdsi);
+ }
+ }
+}
+
+/**
+ * @brief Tearing Effect DSI callback.
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval None
+ */
+__weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DSI_TearingEffectCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief End of Refresh DSI callback.
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval None
+ */
+__weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DSI_EndOfRefreshCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Operation Error DSI callback.
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval None
+ */
+__weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DSI_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+)
+ (+)
+ (+)
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the Generic interface read-back Virtual Channel ID.
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param VirtualChannelID: Virtual channel ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Update the GVCID register */
+ hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;
+ hdsi->Instance->GVCIDR |= VirtualChannelID;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Select video mode and configure the corresponding parameters
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains
+ * the DSI video mode configuration parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check the parameters */
+ assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
+ assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
+ assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));
+ assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));
+ assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));
+ assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));
+ assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));
+ assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));
+ assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));
+ assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));
+ assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));
+ assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
+ assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
+ /* Check the LooselyPacked variant only in 18-bit mode */
+ if(VidCfg->ColorCoding == DSI_RGB666)
+ {
+ assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
+ }
+
+ /* Select video mode by resetting CMDM and DSIM bits */
+ hdsi->Instance->MCR &= ~DSI_MCR_CMDM;
+ hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
+
+ /* Configure the video mode transmission type */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;
+ hdsi->Instance->VMCR |= VidCfg->Mode;
+
+ /* Configure the video packet size */
+ hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;
+ hdsi->Instance->VPCR |= VidCfg->PacketSize;
+
+ /* Set the chunks number to be transmitted through the DSI link */
+ hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;
+ hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;
+
+ /* Set the size of the null packet */
+ hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;
+ hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;
+
+ /* Select the virtual channel for the LTDC interface traffic */
+ hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
+ hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;
+
+ /* Configure the polarity of control signals */
+ hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
+ hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);
+
+ /* Select the color coding for the host */
+ hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
+ hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;
+
+ /* Select the color coding for the wrapper */
+ hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
+ hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1);
+
+ /* Enable/disable the loosely packed variant to 18-bit configuration */
+ if(VidCfg->ColorCoding == DSI_RGB666)
+ {
+ hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
+ hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;
+ }
+
+ /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
+ hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;
+ hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;
+
+ /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
+ hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;
+ hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;
+
+ /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
+ hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;
+ hdsi->Instance->VLCR |= VidCfg->HorizontalLine;
+
+ /* Set the Vertical Synchronization Active (VSA) */
+ hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;
+ hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;
+
+ /* Set the Vertical Back Porch (VBP)*/
+ hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;
+ hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;
+
+ /* Set the Vertical Front Porch (VFP)*/
+ hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;
+ hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;
+
+ /* Set the Vertical Active period*/
+ hdsi->Instance->VVACR &= ~DSI_VVACR_VA;
+ hdsi->Instance->VVACR |= VidCfg->VerticalActive;
+
+ /* Configure the command transmission mode */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;
+ hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;
+
+ /* Low power largest packet size */
+ hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
+ hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16);
+
+ /* Low power VACT largest packet size */
+ hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
+ hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;
+
+ /* Enable LP transition in HFP period */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;
+ hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;
+
+ /* Enable LP transition in HBP period */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;
+ hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;
+
+ /* Enable LP transition in VACT period */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;
+ hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;
+
+ /* Enable LP transition in VFP period */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;
+ hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;
+
+ /* Enable LP transition in VBP period */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;
+ hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;
+
+ /* Enable LP transition in vertical sync period */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;
+ hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;
+
+ /* Enable the request for an acknowledge response at the end of a frame */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;
+ hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Select adapted command mode and configure the corresponding parameters
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains
+ * the DSI command mode configuration parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check the parameters */
+ assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
+ assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
+ assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));
+ assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));
+ assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));
+ assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));
+ assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
+ assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
+ assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
+
+ /* Select command mode by setting CMDM and DSIM bits */
+ hdsi->Instance->MCR |= DSI_MCR_CMDM;
+ hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
+ hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;
+
+ /* Select the virtual channel for the LTDC interface traffic */
+ hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
+ hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;
+
+ /* Configure the polarity of control signals */
+ hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
+ hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);
+
+ /* Select the color coding for the host */
+ hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
+ hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;
+
+ /* Select the color coding for the wrapper */
+ hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
+ hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1);
+
+ /* Configure the maximum allowed size for write memory command */
+ hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
+ hdsi->Instance->LCCR |= CmdCfg->CommandSize;
+
+ /* Configure the tearing effect source and polarity and select the refresh mode */
+ hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
+ hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol);
+
+ /* Configure the tearing effect acknowledge request */
+ hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
+ hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;
+
+ /* Enable the Tearing Effect interrupt */
+ __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);
+
+ /* Enable the End of Refresh interrupt */
+ __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure command transmission mode: High-speed or Low-power
+ * and enable/disable acknowledge request after packet transmission
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains
+ * the DSI command transmission mode configuration parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
+ assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
+ assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
+ assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));
+ assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));
+ assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));
+ assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));
+ assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));
+ assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));
+ assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));
+ assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
+ assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
+ assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
+
+ /* Select High-speed or Low-power for command transmission */
+ hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\
+ DSI_CMCR_GSW1TX |\
+ DSI_CMCR_GSW2TX |\
+ DSI_CMCR_GSR0TX |\
+ DSI_CMCR_GSR1TX |\
+ DSI_CMCR_GSR2TX |\
+ DSI_CMCR_GLWTX |\
+ DSI_CMCR_DSW0TX |\
+ DSI_CMCR_DSW1TX |\
+ DSI_CMCR_DSR0TX |\
+ DSI_CMCR_DLWTX |\
+ DSI_CMCR_MRDPS);
+ hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\
+ LPCmd->LPGenShortWriteOneP |\
+ LPCmd->LPGenShortWriteTwoP |\
+ LPCmd->LPGenShortReadNoP |\
+ LPCmd->LPGenShortReadOneP |\
+ LPCmd->LPGenShortReadTwoP |\
+ LPCmd->LPGenLongWrite |\
+ LPCmd->LPDcsShortWriteNoP |\
+ LPCmd->LPDcsShortWriteOneP |\
+ LPCmd->LPDcsShortReadNoP |\
+ LPCmd->LPDcsLongWrite |\
+ LPCmd->LPMaxReadPacket);
+
+ /* Configure the acknowledge request after each packet transmission */
+ hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;
+ hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the flow control parameters
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param FlowControl: flow control feature(s) to be enabled.
+ * This parameter can be any combination of @ref DSI_FlowControl.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check the parameters */
+ assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
+
+ /* Set the DSI Host Protocol Configuration Register */
+ hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;
+ hdsi->Instance->PCR |= FlowControl;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the DSI PHY timer parameters
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains
+ * the DSI PHY timing parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)
+{
+ uint32_t maxTime;
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime;
+
+ /* Clock lane timer configuration */
+
+ /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two
+ High-Speed transmission.
+ To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
+ to Low-Power and from Low-Power to High-Speed.
+ This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
+ But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
+
+ Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
+ */
+ hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
+ hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16));
+
+ /* Data lane timer configuration */
+ hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
+ hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16) | ((PhyTimers->DataLaneHS2LPTime)<<24));
+
+ /* Configure the wait period to request HS transmission after a stop state */
+ hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
+ hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the DSI HOST timeout parameters
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains
+ * the DSI host timeout parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Set the timeout clock division factor */
+ hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
+ hdsi->Instance->CCR = ((HostTimeouts->TimeoutCkdiv)<<8);
+
+ /* High-speed transmission timeout */
+ hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_HSTX_TOCNT;
+ hdsi->Instance->TCCR[0] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16);
+
+ /* Low-power reception timeout */
+ hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_LPRX_TOCNT;
+ hdsi->Instance->TCCR[0] |= HostTimeouts->LowPowerReceptionTimeout;
+
+ /* High-speed read timeout */
+ hdsi->Instance->TCCR[1] &= ~DSI_TCCR1_HSRD_TOCNT;
+ hdsi->Instance->TCCR[1] |= HostTimeouts->HighSpeedReadTimeout;
+
+ /* Low-power read timeout */
+ hdsi->Instance->TCCR[2] &= ~DSI_TCCR2_LPRD_TOCNT;
+ hdsi->Instance->TCCR[2] |= HostTimeouts->LowPowerReadTimeout;
+
+ /* High-speed write timeout */
+ hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_HSWR_TOCNT;
+ hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWriteTimeout;
+
+ /* High-speed write presp mode */
+ hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_PM;
+ hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWritePrespMode;
+
+ /* Low-speed write timeout */
+ hdsi->Instance->TCCR[4] &= ~DSI_TCCR4_LPWR_TOCNT;
+ hdsi->Instance->TCCR[4] |= HostTimeouts->LowPowerWriteTimeout;
+
+ /* BTA timeout */
+ hdsi->Instance->TCCR[5] &= ~DSI_TCCR5_BTA_TOCNT;
+ hdsi->Instance->TCCR[5] |= HostTimeouts->BTATimeout;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the DSI module
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Enable the DSI host */
+ __HAL_DSI_ENABLE(hdsi);
+
+ /* Enable the DSI wrapper */
+ __HAL_DSI_WRAPPER_ENABLE(hdsi);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DSI module
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Disable the DSI host */
+ __HAL_DSI_DISABLE(hdsi);
+
+ /* Disable the DSI wrapper */
+ __HAL_DSI_WRAPPER_DISABLE(hdsi);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Refresh the display in command mode
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Update the display */
+ hdsi->Instance->WCR |= DSI_WCR_LTDCEN;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Controls the display color mode in Video mode
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param ColorMode: Color mode (full or 8-colors).
+ * This parameter can be any value of @ref DSI_Color_Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check the parameters */
+ assert_param(IS_DSI_COLOR_MODE(ColorMode));
+
+ /* Update the display color mode */
+ hdsi->Instance->WCR &= ~DSI_WCR_COLM;
+ hdsi->Instance->WCR |= ColorMode;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Control the display shutdown in Video mode
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param Shutdown: Shut-down (Display-ON or Display-OFF).
+ * This parameter can be any value of @ref DSI_ShutDown
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check the parameters */
+ assert_param(IS_DSI_SHUT_DOWN(Shutdown));
+
+ /* Update the display Shutdown */
+ hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;
+ hdsi->Instance->WCR |= Shutdown;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DCS or Generic short write command
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param ChannelID: Virtual channel ID.
+ * @param Mode: DSI short packet data type.
+ * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
+ * @param Param1: DSC command or first generic parameter.
+ * This parameter can be any value of @ref DSI_DCS_Command or a
+ * generic command code.
+ * @param Param2: DSC parameter or second generic parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
+ uint32_t ChannelID,
+ uint32_t Mode,
+ uint32_t Param1,
+ uint32_t Param2)
+{
+ uint32_t tickstart = 0;
+
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check the parameters */
+ assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for Command FIFO Empty */
+ while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the packet to send a short DCS command with 0 or 1 parameter */
+ DSI_ConfigPacketHeader(hdsi->Instance,
+ ChannelID,
+ Mode,
+ Param1,
+ Param2);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DCS or Generic long write command
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param ChannelID: Virtual channel ID.
+ * @param Mode: DSI long packet data type.
+ * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.
+ * @param NbParams: Number of parameters.
+ * @param Param1: DSC command or first generic parameter.
+ * This parameter can be any value of @ref DSI_DCS_Command or a
+ * generic command code
+ * @param ParametersTable: Pointer to parameter values table.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
+ uint32_t ChannelID,
+ uint32_t Mode,
+ uint32_t NbParams,
+ uint32_t Param1,
+ uint8_t* ParametersTable)
+{
+ uint32_t uicounter = 0;
+ uint32_t tickstart = 0;
+
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check the parameters */
+ assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for Command FIFO Empty */
+ while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the DCS code hexadecimal on payload byte 1, and the other parameters on the write FIFO command*/
+ while(uicounter < NbParams)
+ {
+ if(uicounter == 0x00)
+ {
+ hdsi->Instance->GPDR=(Param1 | \
+ ((*(ParametersTable+uicounter))<<8) | \
+ ((*(ParametersTable+uicounter+1))<<16) | \
+ ((*(ParametersTable+uicounter+2))<<24));
+ uicounter += 3;
+ }
+ else
+ {
+ hdsi->Instance->GPDR=((*(ParametersTable+uicounter)) | \
+ ((*(ParametersTable+uicounter+1))<<8) | \
+ ((*(ParametersTable+uicounter+2))<<16) | \
+ ((*(ParametersTable+uicounter+3))<<24));
+ uicounter+=4;
+ }
+ }
+
+ /* Configure the packet to send a long DCS command */
+ DSI_ConfigPacketHeader(hdsi->Instance,
+ ChannelID,
+ Mode,
+ ((NbParams+1)&0x00FF),
+ (((NbParams+1)&0xFF00)>>8));
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read command (DCS or generic)
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param ChannelNbr: Virtual channel ID
+ * @param Array: pointer to a buffer to store the payload of a read back operation.
+ * @param Size: Data size to be read (in byte).
+ * @param Mode: DSI read packet data type.
+ * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.
+ * @param DCSCmd: DCS get/read command.
+ * @param ParametersTable: Pointer to parameter values table.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
+ uint32_t ChannelNbr,
+ uint8_t* Array,
+ uint32_t Size,
+ uint32_t Mode,
+ uint32_t DCSCmd,
+ uint8_t* ParametersTable)
+{
+ uint32_t tickstart = 0;
+
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check the parameters */
+ assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
+
+ if(Size > 2)
+ {
+ /* set max return packet size */
+ HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((Size)&0xFF), (((Size)>>8)&0xFF));
+ }
+
+ /* Configure the packet to read command */
+ if (Mode == DSI_DCS_SHORT_PKT_READ)
+ {
+ DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0);
+ }
+ else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
+ {
+ DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0, 0);
+ }
+ else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
+ {
+ DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], 0);
+ }
+ else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)
+ {
+ DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], ParametersTable[1]);
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check that the payload read FIFO is not empty */
+ while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Get the first byte */
+ *((uint32_t *)Array) = (hdsi->Instance->GPDR);
+ if (Size > 4)
+ {
+ Size -= 4;
+ Array += 4;
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Get the remaining bytes if any */
+ while(((int)(Size)) > 0)
+ {
+ if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0)
+ {
+ *((uint32_t *)Array) = (hdsi->Instance->GPDR);
+ Size -= 4;
+ Array += 4;
+ }
+
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
+ * (only data lanes are in ULPM)
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
+{
+ uint32_t tickstart = 0;
+
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* ULPS Request on Data Lanes */
+ hdsi->Instance->PUCR |= DSI_PUCR_URDL;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until the D-PHY active lanes enter into ULPM */
+ if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+ {
+ while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
+ {
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
+ * (only data lanes are in ULPM)
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
+{
+ uint32_t tickstart = 0;
+
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Exit ULPS on Data Lanes */
+ hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until all active lanes exit ULPM */
+ if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+ {
+ while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
+ {
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* De-assert the ULPM requests and the ULPM exit bits */
+ hdsi->Instance->PUCR = 0;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
+ * (both data and clock lanes are in ULPM)
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
+{
+ uint32_t tickstart = 0;
+
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Clock lane configuration: no more HS request */
+ hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
+
+ /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
+ __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR);
+
+ /* ULPS Request on Clock and Data Lanes */
+ hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until all active lanes exit ULPM */
+ if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+ {
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
+ {
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Turn off the DSI PLL */
+ __HAL_DSI_PLL_DISABLE(hdsi);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
+ * (both data and clock lanes are in ULPM)
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
+{
+ uint32_t tickstart = 0;
+
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Turn on the DSI PLL */
+ __HAL_DSI_PLL_ENABLE(hdsi);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for the lock of the PLL */
+ while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Exit ULPS on Clock and Data Lanes */
+ hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until all active lanes exit ULPM */
+ if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+ {
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
+ {
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC))
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* De-assert the ULPM requests and the ULPM exit bits */
+ hdsi->Instance->PUCR = 0;
+
+ /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
+ __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
+
+ /* Restore clock lane configuration to HS */
+ hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start test pattern generation
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param Mode: Pattern generator mode
+ * This parameter can be one of the following values:
+ * 0 : Color bars (horizontal or vertical)
+ * 1 : BER pattern (vertical only)
+ * @param Orientation: Pattern generator orientation
+ * This parameter can be one of the following values:
+ * 0 : Vertical color bars
+ * 1 : Horizontal color bars
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Configure pattern generator mode and orientation */
+ hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
+ hdsi->Instance->VMCR |= ((Mode<<20) | (Orientation<<24));
+
+ /* Enable pattern generator by setting PGE bit */
+ hdsi->Instance->VMCR |= DSI_VMCR_PGE;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop test pattern generation
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Disable pattern generator by clearing PGE bit */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set Slew-Rate And Delay Tuning
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param CommDelay: Communication delay to be adjusted.
+ * This parameter can be any value of @ref DSI_Communication_Delay
+ * @param Lane: select between clock or data lanes.
+ * This parameter can be any value of @ref DSI_Lane_Group
+ * @param Value: Custom value of the slew-rate or delay
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check function parameters */
+ assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
+ assert_param(IS_DSI_LANE_GROUP(Lane));
+
+ switch(CommDelay)
+ {
+ case DSI_SLEW_RATE_HSTX:
+ if(Lane == DSI_CLOCK_LANE)
+ {
+ /* High-Speed Transmission Slew Rate Control on Clock Lane */
+ hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCCL;
+ hdsi->Instance->WPCR[1] |= Value<<16;
+ }
+ else if(Lane == DSI_DATA_LANES)
+ {
+ /* High-Speed Transmission Slew Rate Control on Data Lanes */
+ hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCDL;
+ hdsi->Instance->WPCR[1] |= Value<<18;
+ }
+ break;
+ case DSI_SLEW_RATE_LPTX:
+ if(Lane == DSI_CLOCK_LANE)
+ {
+ /* Low-Power transmission Slew Rate Compensation on Clock Lane */
+ hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCCL;
+ hdsi->Instance->WPCR[1] |= Value<<6;
+ }
+ else if(Lane == DSI_DATA_LANES)
+ {
+ /* Low-Power transmission Slew Rate Compensation on Data Lanes */
+ hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCDL;
+ hdsi->Instance->WPCR[1] |= Value<<8;
+ }
+ break;
+ case DSI_HS_DELAY:
+ if(Lane == DSI_CLOCK_LANE)
+ {
+ /* High-Speed Transmission Delay on Clock Lane */
+ hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDCL;
+ hdsi->Instance->WPCR[1] |= Value;
+ }
+ else if(Lane == DSI_DATA_LANES)
+ {
+ /* High-Speed Transmission Delay on Data Lanes */
+ hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDDL;
+ hdsi->Instance->WPCR[1] |= Value<<2;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Low-Power Reception Filter Tuning
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Low-Power RX low-pass Filtering Tuning */
+ hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPRXFT;
+ hdsi->Instance->WPCR[1] |= Frequency<<25;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Activate an additional current path on all lanes to meet the SDDTx parameter
+ * defined in the MIPI D-PHY specification
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param State: ENABLE or DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check function parameters */
+ assert_param(IS_FUNCTIONAL_STATE(State));
+
+ /* Activate/Disactivate additional current path on all lanes */
+ hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_SDDC;
+ hdsi->Instance->WPCR[1] |= State<<12;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Custom lane pins configuration
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param CustomLane: Function to be applyed on selected lane.
+ * This parameter can be any value of @ref DSI_CustomLane
+ * @param Lane: select between clock or data lane 0 or data lane 1.
+ * This parameter can be any value of @ref DSI_Lane_Select
+ * @param State: ENABLE or DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check function parameters */
+ assert_param(IS_DSI_CUSTOM_LANE(CustomLane));
+ assert_param(IS_DSI_LANE(Lane));
+ assert_param(IS_FUNCTIONAL_STATE(State));
+
+ switch(CustomLane)
+ {
+ case DSI_SWAP_LANE_PINS:
+ if(Lane == DSI_CLOCK_LANE)
+ {
+ /* Swap pins on clock lane */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWCL;
+ hdsi->Instance->WPCR[0] |= (State<<6);
+ }
+ else if(Lane == DSI_DATA_LANE0)
+ {
+ /* Swap pins on data lane 0 */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL0;
+ hdsi->Instance->WPCR[0] |= (State<<7);
+ }
+ else if(Lane == DSI_DATA_LANE1)
+ {
+ /* Swap pins on data lane 1 */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL1;
+ hdsi->Instance->WPCR[0] |= (State<<8);
+ }
+ break;
+ case DSI_INVERT_HS_SIGNAL:
+ if(Lane == DSI_CLOCK_LANE)
+ {
+ /* Invert HS signal on clock lane */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSICL;
+ hdsi->Instance->WPCR[0] |= (State<<9);
+ }
+ else if(Lane == DSI_DATA_LANE0)
+ {
+ /* Invert HS signal on data lane 0 */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL0;
+ hdsi->Instance->WPCR[0] |= (State<<10);
+ }
+ else if(Lane == DSI_DATA_LANE1)
+ {
+ /* Invert HS signal on data lane 1 */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL1;
+ hdsi->Instance->WPCR[0] |= (State<<11);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set custom timing for the PHY
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param Timing: PHY timing to be adjusted.
+ * This parameter can be any value of @ref DSI_PHY_Timing
+ * @param State: ENABLE or DISABLE
+ * @param Value: Custom value of the timing
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check function parameters */
+ assert_param(IS_DSI_PHY_TIMING(Timing));
+ assert_param(IS_FUNCTIONAL_STATE(State));
+
+ switch(Timing)
+ {
+ case DSI_TCLK_POST:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPOSTEN;
+ hdsi->Instance->WPCR[0] |= (State<<27);
+
+ if(State)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[4] &= ~DSI_WPCR4_TCLKPOST;
+ hdsi->Instance->WPCR[4] |= Value;
+ }
+
+ break;
+ case DSI_TLPX_CLK:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXCEN;
+ hdsi->Instance->WPCR[0] |= (State<<26);
+
+ if(State)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXC;
+ hdsi->Instance->WPCR[3] |= Value;
+ }
+
+ break;
+ case DSI_THS_EXIT:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSEXITEN;
+ hdsi->Instance->WPCR[0] |= (State<<25);
+
+ if(State)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSEXIT;
+ hdsi->Instance->WPCR[3] |= Value;
+ }
+
+ break;
+ case DSI_TLPX_DATA:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXDEN;
+ hdsi->Instance->WPCR[0] |= (State<<24);
+
+ if(State)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXD;
+ hdsi->Instance->WPCR[3] |= Value;
+ }
+
+ break;
+ case DSI_THS_ZERO:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSZEROEN;
+ hdsi->Instance->WPCR[0] |= (State<<23);
+
+ if(State)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSZERO;
+ hdsi->Instance->WPCR[3] |= Value;
+ }
+
+ break;
+ case DSI_THS_TRAIL:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSTRAILEN;
+ hdsi->Instance->WPCR[0] |= (State<<22);
+
+ if(State)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSTRAIL;
+ hdsi->Instance->WPCR[2] |= Value;
+ }
+
+ break;
+ case DSI_THS_PREPARE:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSPREPEN;
+ hdsi->Instance->WPCR[0] |= (State<<21);
+
+ if(State)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSPREP;
+ hdsi->Instance->WPCR[2] |= Value;
+ }
+
+ break;
+ case DSI_TCLK_ZERO:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKZEROEN;
+ hdsi->Instance->WPCR[0] |= (State<<20);
+
+ if(State)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKZERO;
+ hdsi->Instance->WPCR[2] |= Value;
+ }
+
+ break;
+ case DSI_TCLK_PREPARE:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPREPEN;
+ hdsi->Instance->WPCR[0] |= (State<<19);
+
+ if(State)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKPREP;
+ hdsi->Instance->WPCR[2] |= Value;
+ }
+
+ break;
+ default:
+ break;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Force the Clock/Data Lane in TX Stop Mode
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param Lane: select between clock or data lanes.
+ * This parameter can be any value of @ref DSI_Lane_Group
+ * @param State: ENABLE or DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check function parameters */
+ assert_param(IS_DSI_LANE_GROUP(Lane));
+ assert_param(IS_FUNCTIONAL_STATE(State));
+
+ if(Lane == DSI_CLOCK_LANE)
+ {
+ /* Force/Unforce the Clock Lane in TX Stop Mode */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMCL;
+ hdsi->Instance->WPCR[0] |= (State<<12);
+ }
+ else if(Lane == DSI_DATA_LANES)
+ {
+ /* Force/Unforce the Data Lanes in TX Stop Mode */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMDL;
+ hdsi->Instance->WPCR[0] |= (State<<13);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Forces LP Receiver in Low-Power Mode
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param State: ENABLE or DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check function parameters */
+ assert_param(IS_FUNCTIONAL_STATE(State));
+
+ /* Force/Unforce LP Receiver in Low-Power Mode */
+ hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_FLPRXLPM;
+ hdsi->Instance->WPCR[1] |= State<<22;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Force Data Lanes in RX Mode after a BTA
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param State: ENABLE or DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check function parameters */
+ assert_param(IS_FUNCTIONAL_STATE(State));
+
+ /* Force Data Lanes in RX Mode */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TDDL;
+ hdsi->Instance->WPCR[0] |= State<<16;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable a pull-down on the lanes to prevent from floating states when unused
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param State: ENABLE or DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check function parameters */
+ assert_param(IS_FUNCTIONAL_STATE(State));
+
+ /* Enable/Disable pull-down on lanes */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_PDEN;
+ hdsi->Instance->WPCR[0] |= State<<18;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Switch off the contention detection on data lanes
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param State: ENABLE or DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check function parameters */
+ assert_param(IS_FUNCTIONAL_STATE(State));
+
+ /* Contention Detection on Data Lanes OFF */
+ hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_CDOFFDL;
+ hdsi->Instance->WPCR[0] |= State<<14;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Group4 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DSI state.
+ (+) Get error code.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the DSI state
+ * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL state
+ */
+HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
+{
+ return hdsi->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F469xx || STM32F479xx */
+#endif /* HAL_DSI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/src/stm32f4xx_hal_eth.c b/f4/src/stm32f4xx_hal_eth.c
index 5cd3486..d2b5084 100755
--- a/f4/src/stm32f4xx_hal_eth.c
+++ b/f4/src/stm32f4xx_hal_eth.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_eth.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief ETH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Ethernet (ETH) peripheral:
@@ -71,7 +71,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -112,7 +112,8 @@
#ifdef HAL_ETH_MODULE_ENABLED
-#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -176,7 +177,7 @@ static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
*/
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
{
- uint32_t tmpreg = 0, phyreg = 0;
+ uint32_t tmpreg1 = 0, phyreg = 0;
uint32_t hclk = 60000000;
uint32_t tickstart = 0;
uint32_t err = ETH_SUCCESS;
@@ -195,6 +196,8 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
if(heth->State == HAL_ETH_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ heth->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC. */
HAL_ETH_MspInit(heth);
}
@@ -218,9 +221,9 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
/*-------------------------------- MAC Initialization ----------------------*/
/* Get the ETHERNET MACMIIAR value */
- tmpreg = (heth->Instance)->MACMIIAR;
+ tmpreg1 = (heth->Instance)->MACMIIAR;
/* Clear CSR Clock Range CR[2:0] bits */
- tmpreg &= ETH_MACMIIAR_CR_MASK;
+ tmpreg1 &= ETH_MACMIIAR_CR_MASK;
/* Get hclk frequency value */
hclk = HAL_RCC_GetHCLKFreq();
@@ -229,31 +232,31 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
if((hclk >= 20000000)&&(hclk < 35000000))
{
/* CSR Clock Range between 20-35 MHz */
- tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16;
}
else if((hclk >= 35000000)&&(hclk < 60000000))
{
/* CSR Clock Range between 35-60 MHz */
- tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26;
}
else if((hclk >= 60000000)&&(hclk < 100000000))
{
/* CSR Clock Range between 60-100 MHz */
- tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42;
}
else if((hclk >= 100000000)&&(hclk < 150000000))
{
/* CSR Clock Range between 100-150 MHz */
- tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62;
}
else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */
{
/* CSR Clock Range between 150-168 MHz */
- tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102;
}
/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
- (heth->Instance)->MACMIIAR = (uint32_t)tmpreg;
+ (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
/*-------------------- PHY initialization and configuration ----------------*/
/* Put the PHY in reset mode */
@@ -1029,7 +1032,7 @@ __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
*/
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0;
uint32_t tickstart = 0;
/* Check parameters */
@@ -1044,25 +1047,25 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR
heth->State = HAL_ETH_STATE_BUSY_RD;
/* Get the ETHERNET MACMIIAR value */
- tmpreg = heth->Instance->MACMIIAR;
+ tmpreg1 = heth->Instance->MACMIIAR;
/* Keep only the CSR Clock Range CR[2:0] bits value */
- tmpreg &= ~ETH_MACMIIAR_CR_MASK;
+ tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
/* Prepare the MII address register value */
- tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
- tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
- tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
- tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
+ tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+ tmpreg1 |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
+ tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
+ tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
/* Write the result value into the MII Address register */
- heth->Instance->MACMIIAR = tmpreg;
+ heth->Instance->MACMIIAR = tmpreg1;
/* Get tick */
tickstart = HAL_GetTick();
/* Check for the Busy flag */
- while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
+ while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
@@ -1075,7 +1078,7 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR
return HAL_TIMEOUT;
}
- tmpreg = heth->Instance->MACMIIAR;
+ tmpreg1 = heth->Instance->MACMIIAR;
}
/* Get MACMIIDR value */
@@ -1101,7 +1104,7 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR
*/
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0;
uint32_t tickstart = 0;
/* Check parameters */
@@ -1116,28 +1119,28 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY
heth->State = HAL_ETH_STATE_BUSY_WR;
/* Get the ETHERNET MACMIIAR value */
- tmpreg = heth->Instance->MACMIIAR;
+ tmpreg1 = heth->Instance->MACMIIAR;
/* Keep only the CSR Clock Range CR[2:0] bits value */
- tmpreg &= ~ETH_MACMIIAR_CR_MASK;
+ tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
/* Prepare the MII register address value */
- tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
- tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
- tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
- tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
+ tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+ tmpreg1 |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
+ tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */
+ tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
/* Give the value to the MII data register */
heth->Instance->MACMIIDR = (uint16_t)RegValue;
/* Write the result value into the MII Address register */
- heth->Instance->MACMIIAR = tmpreg;
+ heth->Instance->MACMIIAR = tmpreg1;
/* Get tick */
tickstart = HAL_GetTick();
/* Check for the Busy flag */
- while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
+ while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
@@ -1150,7 +1153,7 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY
return HAL_TIMEOUT;
}
- tmpreg = heth->Instance->MACMIIAR;
+ tmpreg1 = heth->Instance->MACMIIAR;
}
/* Set ETH HAL State to READY */
@@ -1272,7 +1275,7 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
*/
HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0;
/* Process Locked */
__HAL_LOCK(heth);
@@ -1316,11 +1319,11 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
/* Clear WD, PCE, PS, TE and RE bits */
- tmpreg &= ETH_MACCR_CLEAR_MASK;
+ tmpreg1 &= ETH_MACCR_CLEAR_MASK;
- tmpreg |= (uint32_t)(macconf->Watchdog |
+ tmpreg1 |= (uint32_t)(macconf->Watchdog |
macconf->Jabber |
macconf->InterFrameGap |
macconf->CarrierSense |
@@ -1335,13 +1338,13 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
macconf->DeferralCheck);
/* Write to ETHERNET MACCR */
- (heth->Instance)->MACCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
/*----------------------- ETHERNET MACFFR Configuration --------------------*/
/* Write to ETHERNET MACFFR */
@@ -1356,9 +1359,9 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACFFR;
+ tmpreg1 = (heth->Instance)->MACFFR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFFR = tmpreg;
+ (heth->Instance)->MACFFR = tmpreg1;
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
/* Write to ETHERNET MACHTHR */
@@ -1369,11 +1372,11 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
/*----------------------- ETHERNET MACFCR Configuration --------------------*/
/* Get the ETHERNET MACFCR value */
- tmpreg = (heth->Instance)->MACFCR;
+ tmpreg1 = (heth->Instance)->MACFCR;
/* Clear xx bits */
- tmpreg &= ETH_MACFCR_CLEAR_MASK;
+ tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
- tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
+ tmpreg1 |= (uint32_t)((macconf->PauseTime << 16) |
macconf->ZeroQuantaPause |
macconf->PauseLowThreshold |
macconf->UnicastPauseFrameDetect |
@@ -1381,13 +1384,13 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
macconf->TransmitFlowControl);
/* Write to ETHERNET MACFCR */
- (heth->Instance)->MACFCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACFCR;
+ tmpreg1 = (heth->Instance)->MACFCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFCR = tmpreg;
+ (heth->Instance)->MACFCR = tmpreg1;
/*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
(heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
@@ -1395,29 +1398,29 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACVLANTR;
+ tmpreg1 = (heth->Instance)->MACVLANTR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACVLANTR = tmpreg;
+ (heth->Instance)->MACVLANTR = tmpreg1;
}
else /* macconf == NULL : here we just configure Speed and Duplex mode */
{
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
/* Clear FES and DM bits */
- tmpreg &= ~((uint32_t)0x00004800);
+ tmpreg1 &= ~((uint32_t)0x00004800);
- tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
+ tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
/* Write to ETHERNET MACCR */
- (heth->Instance)->MACCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
}
/* Set the ETH state to Ready */
@@ -1439,7 +1442,7 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
*/
HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0;
/* Process Locked */
__HAL_LOCK(heth);
@@ -1467,11 +1470,11 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef
/*----------------------- ETHERNET DMAOMR Configuration --------------------*/
/* Get the ETHERNET DMAOMR value */
- tmpreg = (heth->Instance)->DMAOMR;
+ tmpreg1 = (heth->Instance)->DMAOMR;
/* Clear xx bits */
- tmpreg &= ETH_DMAOMR_CLEAR_MASK;
+ tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
- tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
+ tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
dmaconf->ReceiveStoreForward |
dmaconf->FlushReceivedFrame |
dmaconf->TransmitStoreForward |
@@ -1482,13 +1485,13 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef
dmaconf->SecondFrameOperate);
/* Write to ETHERNET DMAOMR */
- (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
+ (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMAOMR;
+ tmpreg1 = (heth->Instance)->DMAOMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMAOMR = tmpreg;
+ (heth->Instance)->DMAOMR = tmpreg1;
/*----------------------- ETHERNET DMABMR Configuration --------------------*/
(heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
@@ -1502,9 +1505,9 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMABMR;
+ tmpreg1 = (heth->Instance)->DMABMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMABMR = tmpreg;
+ (heth->Instance)->DMABMR = tmpreg1;
/* Set the ETH state to Ready */
heth->State= HAL_ETH_STATE_READY;
@@ -1573,7 +1576,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
{
ETH_MACInitTypeDef macinit;
ETH_DMAInitTypeDef dmainit;
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0;
if (err != ETH_SUCCESS) /* Auto-negotiation failed */
{
@@ -1624,9 +1627,9 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
/* Clear WD, PCE, PS, TE and RE bits */
- tmpreg &= ETH_MACCR_CLEAR_MASK;
+ tmpreg1 &= ETH_MACCR_CLEAR_MASK;
/* Set the WD bit according to ETH Watchdog value */
/* Set the JD: bit according to ETH Jabber value */
/* Set the IFG bit according to ETH InterFrameGap value */
@@ -1640,7 +1643,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
/* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
/* Set the BL bit according to ETH BackOffLimit value */
/* Set the DC bit according to ETH DeferralCheck value */
- tmpreg |= (uint32_t)(macinit.Watchdog |
+ tmpreg1 |= (uint32_t)(macinit.Watchdog |
macinit.Jabber |
macinit.InterFrameGap |
macinit.CarrierSense |
@@ -1655,13 +1658,13 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
macinit.DeferralCheck);
/* Write to ETHERNET MACCR */
- (heth->Instance)->MACCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
/*----------------------- ETHERNET MACFFR Configuration --------------------*/
/* Set the RA bit according to ETH ReceiveAll value */
@@ -1684,9 +1687,9 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACFFR;
+ tmpreg1 = (heth->Instance)->MACFFR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFFR = tmpreg;
+ (heth->Instance)->MACFFR = tmpreg1;
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
/* Write to ETHERNET MACHTHR */
@@ -1697,9 +1700,9 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
/*----------------------- ETHERNET MACFCR Configuration -------------------*/
/* Get the ETHERNET MACFCR value */
- tmpreg = (heth->Instance)->MACFCR;
+ tmpreg1 = (heth->Instance)->MACFCR;
/* Clear xx bits */
- tmpreg &= ETH_MACFCR_CLEAR_MASK;
+ tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
/* Set the PT bit according to ETH PauseTime value */
/* Set the DZPQ bit according to ETH ZeroQuantaPause value */
@@ -1707,7 +1710,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
/* Set the UP bit according to ETH UnicastPauseFrameDetect value */
/* Set the RFE bit according to ETH ReceiveFlowControl value */
/* Set the TFE bit according to ETH TransmitFlowControl value */
- tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
+ tmpreg1 |= (uint32_t)((macinit.PauseTime << 16) |
macinit.ZeroQuantaPause |
macinit.PauseLowThreshold |
macinit.UnicastPauseFrameDetect |
@@ -1715,13 +1718,13 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
macinit.TransmitFlowControl);
/* Write to ETHERNET MACFCR */
- (heth->Instance)->MACFCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACFCR;
+ tmpreg1 = (heth->Instance)->MACFCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFCR = tmpreg;
+ (heth->Instance)->MACFCR = tmpreg1;
/*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
/* Set the ETV bit according to ETH VLANTagComparison value */
@@ -1731,9 +1734,9 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACVLANTR;
+ tmpreg1 = (heth->Instance)->MACVLANTR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACVLANTR = tmpreg;
+ (heth->Instance)->MACVLANTR = tmpreg1;
/* Ethernet DMA default initialization ************************************/
dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
@@ -1754,9 +1757,9 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
/* Get the ETHERNET DMAOMR value */
- tmpreg = (heth->Instance)->DMAOMR;
+ tmpreg1 = (heth->Instance)->DMAOMR;
/* Clear xx bits */
- tmpreg &= ETH_DMAOMR_CLEAR_MASK;
+ tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
/* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
/* Set the RSF bit according to ETH ReceiveStoreForward value */
@@ -1767,7 +1770,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
/* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
/* Set the RTC bit according to ETH ReceiveThresholdControl value */
/* Set the OSF bit according to ETH SecondFrameOperate value */
- tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
+ tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
dmainit.ReceiveStoreForward |
dmainit.FlushReceivedFrame |
dmainit.TransmitStoreForward |
@@ -1778,13 +1781,13 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
dmainit.SecondFrameOperate);
/* Write to ETHERNET DMAOMR */
- (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
+ (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMAOMR;
+ tmpreg1 = (heth->Instance)->DMAOMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMAOMR = tmpreg;
+ (heth->Instance)->DMAOMR = tmpreg1;
/*----------------------- ETHERNET DMABMR Configuration ------------------*/
/* Set the AAL bit according to ETH AddressAlignedBeats value */
@@ -1805,9 +1808,9 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMABMR;
+ tmpreg1 = (heth->Instance)->DMABMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMABMR = tmpreg;
+ (heth->Instance)->DMABMR = tmpreg1;
if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
{
@@ -1834,20 +1837,20 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
*/
static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
{
- uint32_t tmpreg;
+ uint32_t tmpreg1;
/* Check the parameters */
assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
/* Calculate the selected MAC address high register */
- tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
+ tmpreg1 = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
/* Load the selected MAC address high register */
- (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
+ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
/* Calculate the selected MAC address low register */
- tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
+ tmpreg1 = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
/* Load the selected MAC address low register */
- (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
+ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
}
/**
@@ -1858,16 +1861,16 @@ static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint
*/
static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0;
/* Enable the MAC transmission */
(heth->Instance)->MACCR |= ETH_MACCR_TE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
}
/**
@@ -1878,16 +1881,16 @@ static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
*/
static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0;
/* Disable the MAC transmission */
(heth->Instance)->MACCR &= ~ETH_MACCR_TE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
}
/**
@@ -1898,16 +1901,16 @@ static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
*/
static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0;
/* Enable the MAC reception */
(heth->Instance)->MACCR |= ETH_MACCR_RE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
}
/**
@@ -1918,16 +1921,16 @@ static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
*/
static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0;
/* Disable the MAC reception */
(heth->Instance)->MACCR &= ~ETH_MACCR_RE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
}
/**
@@ -1986,23 +1989,24 @@ static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
*/
static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0;
/* Set the Flush Transmit FIFO bit */
(heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMAOMR;
+ tmpreg1 = (heth->Instance)->DMAOMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMAOMR = tmpreg;
+ (heth->Instance)->DMAOMR = tmpreg1;
}
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
+ STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#endif /* HAL_ETH_MODULE_ENABLED */
/**
* @}
diff --git a/f4/src/stm32f4xx_hal_flash.c b/f4/src/stm32f4xx_hal_flash.c
index 6ec4690..0236e8f 100755
--- a/f4/src/stm32f4xx_hal_flash.c
+++ b/f4/src/stm32f4xx_hal_flash.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_flash.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@@ -65,7 +65,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -111,7 +111,6 @@
/** @addtogroup FLASH_Private_Constants
* @{
*/
-#define SECTOR_MASK ((uint32_t)0xFFFFFF07)
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
/**
* @}
@@ -137,6 +136,7 @@ static void FLASH_Program_Word(uint32_t Address, uint32_t Data);
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
static void FLASH_Program_Byte(uint32_t Address, uint8_t Data);
static void FLASH_SetErrorCode(void);
+extern void FLASH_FlushCaches(void);
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/**
@@ -178,10 +178,10 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
/* Process Locked */
__HAL_LOCK(&pFlash);
-
+
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
-
+
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
@@ -190,7 +190,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
{
/*Program byte (8-bit) at a specified address.*/
- FLASH_Program_Byte(Address, (uint8_t) Data);
+ FLASH_Program_Byte(Address, (uint8_t) Data);
}
else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
{
@@ -207,17 +207,17 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
/*Program double word (64-bit) at a specified address.*/
FLASH_Program_DoubleWord(Address, Data);
}
-
+
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
+ FLASH->CR &= (~FLASH_CR_PG);
}
-
+
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
-
+
return status;
}
@@ -245,10 +245,6 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
/* Enable Error source interrupt */
__HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
-
- /* Clear pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
- FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR);
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
pFlash.Address = Address;
@@ -283,58 +279,84 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
*/
void HAL_FLASH_IRQHandler(void)
{
- uint32_t temp;
+ uint32_t addresstmp = 0;
+
+ /* Check FLASH operation error flags */
+ if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
+ FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
+ {
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
+ {
+ /*return the faulty sector*/
+ addresstmp = pFlash.Sector;
+ pFlash.Sector = 0xFFFFFFFF;
+ }
+ else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
+ {
+ /*return the faulty bank*/
+ addresstmp = pFlash.Bank;
+ }
+ else
+ {
+ /*return the faulty address*/
+ addresstmp = pFlash.Address;
+ }
+
+ /*Save the Error code*/
+ FLASH_SetErrorCode();
+
+ /* FLASH error interrupt user callback */
+ HAL_FLASH_OperationErrorCallback(addresstmp);
+
+ /*Stop the procedure ongoing*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
- /* If the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
-
- /* If the erase operation is completed, disable the SER Bit */
- FLASH->CR &= (~FLASH_CR_SER);
- FLASH->CR &= SECTOR_MASK;
-
- /* if the erase operation is completed, disable the MER Bit */
- FLASH->CR &= (~FLASH_MER_BIT);
-
/* Check FLASH End of Operation flag */
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
{
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+
if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
{
/*Nb of sector to erased can be decreased*/
pFlash.NbSectorsToErase--;
-
+
/* Check if there are still sectors to erase*/
if(pFlash.NbSectorsToErase != 0)
{
- temp = pFlash.Sector;
+ addresstmp = pFlash.Sector;
/*Indicate user which sector has been erased*/
- HAL_FLASH_EndOfOperationCallback(temp);
-
- /* Clear pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
- FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR);
-
+ HAL_FLASH_EndOfOperationCallback(addresstmp);
+
/*Increment sector number*/
- temp = ++pFlash.Sector;
- FLASH_Erase_Sector(temp, pFlash.VoltageForErase);
+ pFlash.Sector++;
+ addresstmp = pFlash.Sector;
+ FLASH_Erase_Sector(addresstmp, pFlash.VoltageForErase);
}
else
{
/*No more sectors to Erase, user callback can be called.*/
/*Reset Sector and stop Erase sectors procedure*/
- pFlash.Sector = temp = 0xFFFFFFFF;
+ pFlash.Sector = addresstmp = 0xFFFFFFFF;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+ /* Flush the caches to be sure of the data consistency */
+ FLASH_FlushCaches() ;
+
/* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(temp);
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ HAL_FLASH_EndOfOperationCallback(addresstmp);
}
}
else
{
if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
{
- /*MassErase ended. Return the selected bank*/
+ /* MassErase ended. Return the selected bank */
+ /* Flush the caches to be sure of the data consistency */
+ FLASH_FlushCaches() ;
+
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
}
@@ -345,58 +367,23 @@ void HAL_FLASH_IRQHandler(void)
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
}
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
- }
-
- }
-
- /* Check FLASH operation error flags */
- if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
- FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
- {
- if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
- {
- /*return the faulty sector*/
- temp = pFlash.Sector;
- pFlash.Sector = 0xFFFFFFFF;
- }
- else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
- {
- /*return the faulty bank*/
- temp = pFlash.Bank;
- }
- else
- {
- /*return the faulty address*/
- temp = pFlash.Address;
}
-
- /*Save the Error code*/
- FLASH_SetErrorCode();
-
- /* FLASH error interrupt user callback */
- HAL_FLASH_OperationErrorCallback(temp);
- /* Clear FLASH error pending bits */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR |\
- FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR);
-
- /*Stop the procedure ongoing*/
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
{
+ /* Operation is completed, disable the PG, SER, SNB and MER Bits */
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_SER | FLASH_CR_SNB | FLASH_MER_BIT));
+
/* Disable End of FLASH Operation interrupt */
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
-
+
/* Disable Error source interrupt */
__HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
-
+
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
}
-
}
/**
@@ -591,6 +578,13 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
}
}
}
+
+ /* Check FLASH End of Operation flag */
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ }
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
@@ -600,7 +594,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
return HAL_ERROR;
}
- /* If there is an error flag set */
+ /* If there is no error flag set */
return HAL_OK;
}
@@ -623,7 +617,7 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
FLASH->CR |= FLASH_CR_PG;
@@ -649,7 +643,7 @@ static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
FLASH->CR |= FLASH_PSIZE_WORD;
FLASH->CR |= FLASH_CR_PG;
@@ -674,7 +668,7 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
FLASH->CR |= FLASH_PSIZE_HALF_WORD;
FLASH->CR |= FLASH_CR_PG;
@@ -699,7 +693,7 @@ static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
FLASH->CR |= FLASH_PSIZE_BYTE;
FLASH->CR |= FLASH_CR_PG;
@@ -715,31 +709,49 @@ static void FLASH_SetErrorCode(void)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
+
+ /* Clear FLASH write protection error pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR);
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
+
+ /* Clear FLASH Programming alignment error pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR);
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;
+
+ /* Clear FLASH Programming parallelism error pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGPERR);
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS;
+
+ /* Clear FLASH Programming sequence error pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR);
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
+
+ /* Clear FLASH Proprietary readout protection error pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR);
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
+
+ /* Clear FLASH Operation error pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR);
}
}
diff --git a/f4/src/stm32f4xx_hal_flash_ex.c b/f4/src/stm32f4xx_hal_flash_ex.c
index ac59579..f06116d 100755
--- a/f4/src/stm32f4xx_hal_flash_ex.c
+++ b/f4/src/stm32f4xx_hal_flash_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_flash_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Extended FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the FLASH extension peripheral:
@@ -25,7 +25,8 @@
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to configure and program the FLASH memory
- of all STM32F427xx/437xx andSTM32F429xx/439xx devices. It includes
+ of all STM32F427xx/437xx, STM32F429xx/439xx, STM32F469xx/479xx and STM32F446xx
+ devices. It includes
(#) FLASH Memory Erase functions:
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
HAL_FLASH_Lock() functions
@@ -50,7 +51,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -96,7 +97,6 @@
/** @addtogroup FLASHEx_Private_Constants
* @{
*/
-#define SECTOR_MASK ((uint32_t)0xFFFFFF07)
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
/**
* @}
@@ -118,6 +118,7 @@ extern FLASH_ProcessTypeDef pFlash;
*/
/* Option bytes control */
static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
+void FLASH_FlushCaches(void);
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks);
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level);
@@ -125,19 +126,20 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_
static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);
static uint8_t FLASH_OB_GetUser(void);
static uint16_t FLASH_OB_GetWRP(void);
-static FlagStatus FLASH_OB_GetRDP(void);
+static uint8_t FLASH_OB_GetRDP(void);
static uint8_t FLASH_OB_GetBOR(void);
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
+ defined(STM32F446xx)
static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector);
static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector);
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
-static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/**
@@ -158,7 +160,7 @@ extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the Extension FLASH
- programming operations Operations.
+ programming operations.
@endverbatim
* @{
@@ -217,9 +219,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- /* If the erase operation is completed, disable the SER Bit */
- FLASH->CR &= (~FLASH_CR_SER);
- FLASH->CR &= SECTOR_MASK;
+ /* If the erase operation is completed, disable the SER and SNB Bits */
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));
if(status != HAL_OK)
{
@@ -229,6 +230,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
}
}
}
+ /* Flush the caches to be sure of the data consistency */
+ FLASH_FlushCaches();
}
/* Process Unlocked */
@@ -349,6 +352,35 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
return status;
}
+/**
+ * @brief Flush the instruction and data caches
+ * @retval None
+ */
+void FLASH_FlushCaches(void)
+{
+ /* Flush instruction cache */
+ if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN))
+ {
+ /* Disable instruction cache */
+ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+ /* Reset instruction cache */
+ __HAL_FLASH_INSTRUCTION_CACHE_RESET();
+ /* Enable instruction cache */
+ __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+ }
+
+ /* Flush data cache */
+ if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN))
+ {
+ /* Disable data cache */
+ __HAL_FLASH_DATA_CACHE_DISABLE();
+ /* Reset data cache */
+ __HAL_FLASH_DATA_CACHE_RESET();
+ /* Enable data cache */
+ __HAL_FLASH_DATA_CACHE_ENABLE();
+ }
+}
+
/**
* @brief Get the Option byte configuration
* @param pOBInit: pointer to an FLASH_OBInitStruct structure that
@@ -361,20 +393,22 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR;
/*Get WRP*/
- pOBInit->WRPSector = FLASH_OB_GetWRP();
+ pOBInit->WRPSector = (uint32_t)FLASH_OB_GetWRP();
/*Get RDP Level*/
- pOBInit->RDPLevel = FLASH_OB_GetRDP();
+ pOBInit->RDPLevel = (uint32_t)FLASH_OB_GetRDP();
/*Get USER*/
- pOBInit->USERConfig = FLASH_OB_GetUser();
+ pOBInit->USERConfig = (uint8_t)FLASH_OB_GetUser();
/*Get BOR Level*/
- pOBInit->BORLevel = FLASH_OB_GetBOR();
+ pOBInit->BORLevel = (uint32_t)FLASH_OB_GetBOR();
}
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
/**
* @brief Program option bytes
* @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
@@ -397,30 +431,32 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO
if((pAdvOBInit->PCROPState) == OB_PCROP_STATE_ENABLE)
{
/*Enable of Write protection on the selected Sector*/
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+ defined(STM32F411xE) || defined(STM32F446xx)
status = FLASH_OB_EnablePCROP(pAdvOBInit->Sectors);
-#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
status = FLASH_OB_EnablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
}
else
{
/*Disable of Write protection on the selected Sector*/
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+ defined(STM32F411xE) || defined(STM32F446xx)
status = FLASH_OB_DisablePCROP(pAdvOBInit->Sectors);
-#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
status = FLASH_OB_DisablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
}
}
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/*Program BOOT config option byte*/
if(((pAdvOBInit->OptionType) & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG)
{
status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig);
}
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
return status;
}
@@ -434,10 +470,11 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO
*/
void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
{
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+ defined(STM32F411xE) || defined(STM32F446xx)
/*Get Sector*/
pAdvOBInit->Sectors = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
-#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
/*Get Sector for Bank1*/
pAdvOBInit->SectorsBank1 = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
@@ -446,7 +483,7 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
/*Get Boot config OB*/
pAdvOBInit->BootConfig = *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS;
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
}
/**
@@ -456,7 +493,8 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
* Global Read Out Protection modification (from level1 to level0)
* @note Once SPRMOD bit is active unprotection of a protected sector is not possible
* @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
- * @note This function can be used only for STM32F427xx/STM32F429xx/STM32F437xx/STM32F439xx/STM32F401xx devices.
+ * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/
+ * STM32F469xx/STM32F479xx devices.
*
* @retval HAL Status
*/
@@ -480,7 +518,8 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
* Global Read Out Protection modification (from level1 to level0)
* @note Once SPRMOD bit is active unprotection of a protected sector is not possible
* @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
- * @note This function can be used only for STM32F427xx/STM32F429xx/STM32F437xx/STM32F439xx/STM32F401xx devices.
+ * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/
+ * STM32F469xx/STM32F479xx devices.
*
* @retval HAL Status
*/
@@ -496,12 +535,13 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
return HAL_OK;
}
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx ||\
+ STM32F411xE || STM32F469xx || STM32F479xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Returns the FLASH Write Protection Option Bytes value for Bank 2
- * @note This function can be used only for STM32F427X and STM32F429X devices.
+ * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx devices.
* @retval The FLASH Write Protection Option Bytes value
*/
uint16_t HAL_FLASHEx_OB_GetBank2WRP(void)
@@ -509,13 +549,13 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void)
/* Return the FLASH write protection Register value */
return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
}
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Full erase of FLASH memory sectors
* @param VoltageRange: The device voltage range which defines the erase parallelism.
@@ -546,7 +586,7 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
assert_param(IS_FLASH_BANK(Banks));
/* if the previous operation is completed, proceed to erase all sectors */
- FLASH->CR &= CR_PSIZE_MASK;
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
FLASH->CR |= tmp_psize;
if(Banks == FLASH_BANK_BOTH)
{
@@ -614,9 +654,9 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
Sector += 4;
}
/* If the previous operation is completed, proceed to erase the sector */
- FLASH->CR &= CR_PSIZE_MASK;
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
FLASH->CR |= tmp_psize;
- FLASH->CR &= SECTOR_MASK;
+ CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
FLASH->CR |= FLASH_CR_STRT;
}
@@ -631,7 +671,7 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
*
* @param WRPSector: specifies the sector(s) to be write protected.
* This parameter can be one of the following values:
- * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
+ * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
* @arg OB_WRP_SECTOR_All
* @note BANK2 starts from OB_WRP_SECTOR_12
*
@@ -702,7 +742,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
*
* @param WRPSector: specifies the sector(s) to be write protected.
* This parameter can be one of the following values:
- * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
+ * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
* @arg OB_WRP_Sector_All
* @note BANK2 starts from OB_WRP_SECTOR_12
*
@@ -924,10 +964,11 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t Se
}
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
/**
* @brief Mass erase of FLASH memory
* @param VoltageRange: The device voltage range which defines the erase parallelism.
@@ -954,12 +995,12 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
/* Check the parameters */
assert_param(IS_VOLTAGERANGE(VoltageRange));
assert_param(IS_FLASH_BANK(Banks));
-
+
/* If the previous operation is completed, proceed to erase all sectors */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= tmp_psize;
- FLASH->CR |= FLASH_CR_MER;
- FLASH->CR |= FLASH_CR_STRT;
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+ FLASH->CR |= tmp_psize;
+ FLASH->CR |= FLASH_CR_MER;
+ FLASH->CR |= FLASH_CR_STRT;
}
/**
@@ -1005,9 +1046,9 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
}
/* If the previous operation is completed, proceed to erase the sector */
- FLASH->CR &= CR_PSIZE_MASK;
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
FLASH->CR |= tmp_psize;
- FLASH->CR &= SECTOR_MASK;
+ CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
FLASH->CR |= FLASH_CR_STRT;
}
@@ -1083,9 +1124,10 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
return status;
}
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx */
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+ defined(STM32F411xE) || defined(STM32F446xx)
/**
* @brief Enable the read/write protection (PCROP) of the desired sectors.
* @note This function can be used only for STM32F401xx devices.
@@ -1141,7 +1183,7 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector)
return status;
}
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
/**
* @brief Set the read protection level.
@@ -1212,7 +1254,6 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t
}
return status;
-
}
/**
@@ -1261,19 +1302,29 @@ static uint16_t FLASH_OB_GetWRP(void)
/**
* @brief Returns the FLASH Read Protection level.
- * @retval FlagStatus FLASH Readout Protection Status:
- * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
- * - RESET, when OB_RDP_Level_0 is set
+ * @retval FLASH ReadOut Protection Status:
+ * This parameter can be one of the following values:
+ * @arg OB_RDP_LEVEL_0: No protection
+ * @arg OB_RDP_LEVEL_1: Read protection of the memory
+ * @arg OB_RDP_LEVEL_2: Full chip protection
*/
-static FlagStatus FLASH_OB_GetRDP(void)
+static uint8_t FLASH_OB_GetRDP(void)
{
- FlagStatus readstatus = RESET;
+ uint8_t readstatus = OB_RDP_LEVEL_0;
- if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_LEVEL_0))
+ if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2))
{
- readstatus = SET;
+ readstatus = OB_RDP_LEVEL_2;
}
-
+ else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_1))
+ {
+ readstatus = OB_RDP_LEVEL_1;
+ }
+ else
+ {
+ readstatus = OB_RDP_LEVEL_0;
+ }
+
return readstatus;
}
diff --git a/f4/src/stm32f4xx_hal_flash_ramfunc.c b/f4/src/stm32f4xx_hal_flash_ramfunc.c
index 26e7076..b860f71 100755
--- a/f4/src/stm32f4xx_hal_flash_ramfunc.c
+++ b/f4/src/stm32f4xx_hal_flash_ramfunc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_flash_ramfunc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief FLASH RAMFUNC module driver.
* This file provides a FLASH firmware functions which should be
* executed from internal SRAM
@@ -36,7 +36,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -70,14 +70,12 @@
* @{
*/
-/** @defgroup FLASH_RAMFUNC FLASH RAMFUNC
+/** @defgroup FLASHRAMFUNC FLASH RAMFUNC
* @brief FLASH functions executed from RAM
* @{
*/
-
#ifdef HAL_FLASH_MODULE_ENABLED
-
-#if defined(STM32F411xE)
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -85,11 +83,11 @@
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions
+/** @defgroup FLASHRAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions
* @{
*/
-/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM
+/** @defgroup FLASHRAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM
* @brief Peripheral Extended features functions
*
@verbatim
@@ -159,7 +157,7 @@ __RAM_FUNC HAL_FLASHEx_EnableFlashSleepMode(void)
/**
* @brief Disable the flash sleep while System Run
* @note This mode is only available for STM32F411xx devices.
- * @note This mode could n't be set while executing with the flash itself.
+ * @note This mode couldn't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
* @retval None
*/
@@ -181,7 +179,7 @@ __RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode(void)
* @}
*/
-#endif /* STM32F411xE */
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx */
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
diff --git a/f4/src/stm32f4xx_hal_fmpi2c.c b/f4/src/stm32f4xx_hal_fmpi2c.c
new file mode 100644
index 0000000..545679b
--- /dev/null
+++ b/f4/src/stm32f4xx_hal_fmpi2c.c
@@ -0,0 +1,4098 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_fmpi2c.c
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief FMPI2C HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Inter Integrated Circuit (FMPI2C) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The FMPI2C HAL driver can be used as follows:
+
+ (#) Declare a FMPI2C_HandleTypeDef handle structure, for example:
+ FMPI2C_HandleTypeDef hfmpi2c;
+
+ (#)Initialize the FMPI2C low level resources by implement the HAL_FMPI2C_MspInit ()API:
+ (##) Enable the FMPI2Cx interface clock
+ (##) FMPI2C pins configuration
+ (+++) Enable the clock for the FMPI2C GPIOs
+ (+++) Configure FMPI2C pins as alternate function open-drain
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the FMPI2Cx interrupt priority
+ (+++) Enable the NVIC FMPI2C IRQ Channel
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
+ (+++) Enable the DMAx interface clock using
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx Stream
+ (+++) Associate the initilalized DMA handle to the hfmpi2c DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
+
+ (#) Configure the Communication Clock Timing, Own Address1, Master Adressing Mode, Dual Addressing mode,
+ Own Address2, Own Address2 Mask, General call and Nostretch mode in the hfmpi2c Init structure.
+
+ (#) Initialize the FMPI2C registers by calling the HAL_FMPI2C_Init() API:
+ (+++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_FMPI2C_MspInit(&hfmpi2c) API.
+
+ (#) To check if target device is ready for communication, use the function HAL_FMPI2C_IsDeviceReady()
+
+ (#) For FMPI2C IO and IO MEM operations, three mode of operations are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Transmit in master mode an amount of data in blocking mode using HAL_FMPI2C_Master_Transmit()
+ (+) Receive in master mode an amount of data in blocking mode using HAL_FMPI2C_Master_Receive()
+ (+) Transmit in slave mode an amount of data in blocking mode using HAL_FMPI2C_Slave_Transmit()
+ (+) Receive in slave mode an amount of data in blocking mode using HAL_FMPI2C_Slave_Receive()
+
+ *** Polling mode IO MEM operation ***
+ =====================================
+ [..]
+ (+) Write an amount of data in blocking mode to a specific memory address using HAL_FMPI2C_Mem_Write()
+ (+) Read an amount of data in blocking mode from a specific memory address using HAL_FMPI2C_Mem_Read()
+
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Transmit in master mode an amount of data in non blocking mode using HAL_FMPI2C_Master_Transmit_IT()
+ (+) At transmission end of transfer HAL_FMPI2C_MasterTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback
+ (+) Receive in master mode an amount of data in non blocking mode using HAL_FMPI2C_Master_Receive_IT()
+ (+) At reception end of transfer HAL_FMPI2C_MasterRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback
+ (+) Transmit in slave mode an amount of data in non blocking mode using HAL_FMPI2C_Slave_Transmit_IT()
+ (+) At transmission end of transfer HAL_FMPI2C_SlaveTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback
+ (+) Receive in slave mode an amount of data in non blocking mode using HAL_FMPI2C_Slave_Receive_IT()
+ (+) At reception end of transfer HAL_FMPI2C_SlaveRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback
+ (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback
+
+ *** Interrupt mode IO MEM operation ***
+ =======================================
+ [..]
+ (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
+ HAL_FMPI2C_Mem_Write_IT()
+ (+) At MEM end of write transfer HAL_FMPI2C_MemTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback
+ (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
+ HAL_FMPI2C_Mem_Read_IT()
+ (+) At MEM end of read transfer HAL_FMPI2C_MemRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback
+ (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
+ HAL_FMPI2C_Master_Transmit_DMA()
+ (+) At transmission end of transfer HAL_FMPI2C_MasterTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback
+ (+) Receive in master mode an amount of data in non blocking mode (DMA) using
+ HAL_FMPI2C_Master_Receive_DMA()
+ (+) At reception end of transfer HAL_FMPI2C_MasterRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback
+ (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
+ HAL_FMPI2C_Slave_Transmit_DMA()
+ (+) At transmission end of transfer HAL_FMPI2C_SlaveTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback
+ (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
+ HAL_FMPI2C_Slave_Receive_DMA()
+ (+) At reception end of transfer HAL_FMPI2C_SlaveRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback
+ (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback
+
+ *** DMA mode IO MEM operation ***
+ =================================
+ [..]
+ (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
+ HAL_FMPI2C_Mem_Write_DMA()
+ (+) At MEM end of write transfer HAL_FMPI2C_MemTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback
+ (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
+ HAL_FMPI2C_Mem_Read_DMA()
+ (+) At MEM end of read transfer HAL_FMPI2C_MemRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback
+ (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback
+
+
+ *** FMPI2C HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in FMPI2C HAL driver.
+
+ (+) __HAL_FMPI2C_ENABLE: Enable the FMPI2C peripheral
+ (+) __HAL_FMPI2C_DISABLE: Disable the FMPI2C peripheral
+ (+) __HAL_FMPI2C_GET_FLAG : Checks whether the specified FMPI2C flag is set or not
+ (+) __HAL_FMPI2C_CLEAR_FLAG : Clears the specified FMPI2C pending flag
+ (+) __HAL_FMPI2C_ENABLE_IT: Enables the specified FMPI2C interrupt
+ (+) __HAL_FMPI2C_DISABLE_IT: Disables the specified FMPI2C interrupt
+
+ [..]
+ (@) You can refer to the FMPI2C HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FMPI2C FMPI2C
+ * @brief FMPI2C HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FMPI2C_Private_Constants
+ * @{
+ */
+#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! FMPI2C TIMING clear register Mask */
+#define FMPI2C_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */
+#define FMPI2C_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */
+#define FMPI2C_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */
+#define FMPI2C_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */
+#define FMPI2C_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */
+#define FMPI2C_TIMEOUT_TC ((uint32_t)25) /* 25 ms */
+#define FMPI2C_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */
+#define FMPI2C_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */
+#define FMPI2C_TIMEOUT_FLAG ((uint32_t)25) /* 25 ms */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FMPI2C_Private_Functions
+ * @brief FMPI2C private functions
+ * @{
+ */
+static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+static void FMPI2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma);
+static void FMPI2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma);
+static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma);
+
+static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
+static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
+static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout);
+static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout);
+static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout);
+static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout);
+
+static HAL_StatusTypeDef FMPI2C_MasterTransmit_ISR(FMPI2C_HandleTypeDef *hfmpi2c);
+static HAL_StatusTypeDef FMPI2C_MasterReceive_ISR(FMPI2C_HandleTypeDef *hfmpi2c);
+
+static HAL_StatusTypeDef FMPI2C_SlaveTransmit_ISR(FMPI2C_HandleTypeDef *hfmpi2c);
+static HAL_StatusTypeDef FMPI2C_SlaveReceive_ISR(FMPI2C_HandleTypeDef *hfmpi2c);
+
+static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FMPI2C_Exported_Functions FMPI2C Exported Functions
+ * @{
+ */
+
+/** @defgroup FMPI2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialiaze the FMPI2Cx peripheral:
+
+ (+) User must Implement HAL_FMPI2C_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_FMPI2C_Init() to configure the selected device with
+ the selected configuration:
+ (++) Clock Timing
+ (++) Own Address 1
+ (++) Addressing mode (Master, Slave)
+ (++) Dual Addressing mode
+ (++) Own Address 2
+ (++) Own Address 2 Mask
+ (++) General call mode
+ (++) Nostretch mode
+
+ (+) Call the function HAL_FMPI2C_DeInit() to restore the default configuration
+ of the selected FMPI2Cx periperal.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the FMPI2C according to the specified parameters
+ * in the FMPI2C_InitTypeDef and create the associated handle.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Check the FMPI2C handle allocation */
+ if(hfmpi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
+ assert_param(IS_FMPI2C_OWN_ADDRESS1(hfmpi2c->Init.OwnAddress1));
+ assert_param(IS_FMPI2C_ADDRESSING_MODE(hfmpi2c->Init.AddressingMode));
+ assert_param(IS_FMPI2C_DUAL_ADDRESS(hfmpi2c->Init.DualAddressMode));
+ assert_param(IS_FMPI2C_OWN_ADDRESS2(hfmpi2c->Init.OwnAddress2));
+ assert_param(IS_FMPI2C_OWN_ADDRESS2_MASK(hfmpi2c->Init.OwnAddress2Masks));
+ assert_param(IS_FMPI2C_GENERAL_CALL(hfmpi2c->Init.GeneralCallMode));
+ assert_param(IS_FMPI2C_NO_STRETCH(hfmpi2c->Init.NoStretchMode));
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hfmpi2c->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_FMPI2C_MspInit(hfmpi2c);
+ }
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
+
+ /* Disable the selected FMPI2C peripheral */
+ __HAL_FMPI2C_DISABLE(hfmpi2c);
+
+ /*---------------------------- FMPI2Cx TIMINGR Configuration ------------------*/
+ /* Configure FMPI2Cx: Frequency range */
+ hfmpi2c->Instance->TIMINGR = hfmpi2c->Init.Timing & TIMING_CLEAR_MASK;
+
+ /*---------------------------- FMPI2Cx OAR1 Configuration ---------------------*/
+ /* Configure FMPI2Cx: Own Address1 and ack own address1 mode */
+ hfmpi2c->Instance->OAR1 &= ~FMPI2C_OAR1_OA1EN;
+ if(hfmpi2c->Init.OwnAddress1 != 0)
+ {
+ if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_7BIT)
+ {
+ hfmpi2c->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | hfmpi2c->Init.OwnAddress1);
+ }
+ else /* FMPI2C_ADDRESSINGMODE_10BIT */
+ {
+ hfmpi2c->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | FMPI2C_OAR1_OA1MODE | hfmpi2c->Init.OwnAddress1);
+ }
+ }
+
+ /*---------------------------- FMPI2Cx CR2 Configuration ----------------------*/
+ /* Configure FMPI2Cx: Addressing Master mode */
+ if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
+ {
+ hfmpi2c->Instance->CR2 = (FMPI2C_CR2_ADD10);
+ }
+ /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+ hfmpi2c->Instance->CR2 |= (FMPI2C_CR2_AUTOEND | FMPI2C_CR2_NACK);
+
+ /*---------------------------- FMPI2Cx OAR2 Configuration ---------------------*/
+ /* Configure FMPI2Cx: Dual mode and Own Address2 */
+ hfmpi2c->Instance->OAR2 = (hfmpi2c->Init.DualAddressMode | hfmpi2c->Init.OwnAddress2 | (hfmpi2c->Init.OwnAddress2Masks << 8));
+
+ /*---------------------------- FMPI2Cx CR1 Configuration ----------------------*/
+ /* Configure FMPI2Cx: Generalcall and NoStretch mode */
+ hfmpi2c->Instance->CR1 = (hfmpi2c->Init.GeneralCallMode | hfmpi2c->Init.NoStretchMode);
+
+ /* Enable the selected FMPI2C peripheral */
+ __HAL_FMPI2C_ENABLE(hfmpi2c);
+
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the FMPI2C peripheral.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Check the FMPI2C handle allocation */
+ if(hfmpi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
+
+ /* Disable the FMPI2C Peripheral Clock */
+ __HAL_FMPI2C_DISABLE(hfmpi2c);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_FMPI2C_MspDeInit(hfmpi2c);
+
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+ hfmpi2c->State = HAL_FMPI2C_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief FMPI2C MSP Init.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+ __weak void HAL_FMPI2C_MspInit(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FMPI2C_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FMPI2C MSP DeInit
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+ __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FMPI2C_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_Exported_Functions_Group2 I/O operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the FMPI2C data
+ transfers.
+
+ (#) There is two mode of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated FMPI2C IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_FMPI2C_Master_Transmit()
+ (++) HAL_FMPI2C_Master_Receive()
+ (++) HAL_FMPI2C_Slave_Transmit()
+ (++) HAL_FMPI2C_Slave_Receive()
+ (++) HAL_FMPI2C_Mem_Write()
+ (++) HAL_FMPI2C_Mem_Read()
+ (++) HAL_FMPI2C_IsDeviceReady()
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_FMPI2C_Master_Transmit_IT()
+ (++) HAL_FMPI2C_Master_Receive_IT()
+ (++) HAL_FMPI2C_Slave_Transmit_IT()
+ (++) HAL_FMPI2C_Slave_Receive_IT()
+ (++) HAL_FMPI2C_Mem_Write_IT()
+ (++) HAL_FMPI2C_Mem_Read_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_FMPI2C_Master_Transmit_DMA()
+ (++) HAL_FMPI2C_Master_Receive_DMA()
+ (++) HAL_FMPI2C_Slave_Transmit_DMA()
+ (++) HAL_FMPI2C_Slave_Receive_DMA()
+ (++) HAL_FMPI2C_Mem_Write_DMA()
+ (++) HAL_FMPI2C_Mem_Read_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (++) HAL_FMPI2C_MemTxCpltCallback()
+ (++) HAL_FMPI2C_MemRxCpltCallback()
+ (++) HAL_FMPI2C_MasterTxCpltCallback()
+ (++) HAL_FMPI2C_MasterRxCpltCallback()
+ (++) HAL_FMPI2C_SlaveTxCpltCallback()
+ (++) HAL_FMPI2C_SlaveRxCpltCallback()
+ (++) HAL_FMPI2C_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmits in master mode an amount of data in blocking mode.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t sizetmp = 0;
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MASTER_BUSY_TX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ /* Size > 255, need to set RELOAD bit */
+ if(Size > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
+ sizetmp = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
+ sizetmp = Size;
+ }
+
+ do
+ {
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Write data to TXDR */
+ hfmpi2c->Instance->TXDR = (*pData++);
+ sizetmp--;
+ Size--;
+
+ if((sizetmp == 0)&&(Size!=0))
+ {
+ /* Wait until TXE flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(Size > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ sizetmp = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ sizetmp = Size;
+ }
+ }
+
+ }while(Size > 0);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives in master mode an amount of data in blocking mode.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t sizetmp = 0;
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MASTER_BUSY_RX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ /* Size > 255, need to set RELOAD bit */
+ if(Size > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
+ sizetmp = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+ sizetmp = Size;
+ }
+
+ do
+ {
+ /* Wait until RXNE flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Write data to RXDR */
+ (*pData++) =hfmpi2c->Instance->RXDR;
+ sizetmp--;
+ Size--;
+
+ if((sizetmp == 0)&&(Size!=0))
+ {
+ /* Wait until TCR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(Size > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ sizetmp = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ sizetmp = Size;
+ }
+ }
+
+ }while(Size > 0);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmits in slave mode an amount of data in blocking mode.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_SLAVE_BUSY_RX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+
+ /* If 10bit addressing mode is selected */
+ if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
+ {
+ /* Wait until ADDR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+ }
+
+ /* Wait until DIR flag is set Transmitter mode */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, RESET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ do
+ {
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Read data from TXDR */
+ hfmpi2c->Instance->TXDR = (*pData++);
+ Size--;
+ }while(Size > 0);
+
+ /* Wait until STOP flag is set */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Normal use case for Transmitter mode */
+ /* A NACK is generated to confirm the end of transfer */
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in blocking mode
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_SLAVE_BUSY_RX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+
+ /* Wait until DIR flag is reset Receiver mode */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, SET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ while(Size > 0)
+ {
+ /* Wait until RXNE flag is set */
+ if(FMPI2C_WaitOnRXNEFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Read data from RXDR */
+ (*pData++) = hfmpi2c->Instance->RXDR;
+ Size--;
+ }
+
+ /* Wait until STOP flag is set */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MASTER_BUSY_TX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_TXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in no-blocking mode with Interrupt
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MASTER_BUSY_RX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_SLAVE_BUSY_TX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferSize = Size;
+ hfmpi2c->XferCount = Size;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_TXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_SLAVE_BUSY_RX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferSize = Size;
+ hfmpi2c->XferCount = Size;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in master mode an amount of data in no-blocking mode with DMA
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MASTER_BUSY_TX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = Size;
+ }
+
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMasterTransmitCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
+ }
+
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_TXIS) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in no-blocking mode with DMA
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MASTER_BUSY_RX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = Size;
+ }
+
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMAMasterReceiveCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, FMPI2C_TIMEOUT_RXNE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in no-blocking mode with DMA
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_SLAVE_BUSY_TX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferSize = Size;
+
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMASlaveTransmitCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, FMPI2C_TIMEOUT_ADDR) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+
+ /* If 10bits addressing mode is selected */
+ if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
+ {
+ /* Wait until ADDR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, FMPI2C_TIMEOUT_ADDR) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+ }
+
+ /* Wait until DIR flag is set Transmitter mode */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, RESET, FMPI2C_TIMEOUT_BUSY) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in no-blocking mode with DMA
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_SLAVE_BUSY_RX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferSize = Size;
+ hfmpi2c->XferCount = Size;
+
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMASlaveReceiveCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, Size);
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, FMPI2C_TIMEOUT_ADDR) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+
+ /* Wait until DIR flag is set Receiver mode */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, SET, FMPI2C_TIMEOUT_DIR) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in blocking mode to a specific memory address
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t Sizetmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MEM_BUSY_TX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Send Slave Address and Memory Address */
+ if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if size > 255 */
+ /* Size > 255, need to set RELOAD bit */
+ if(Size > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ Sizetmp = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ Sizetmp = Size;
+ }
+
+ do
+ {
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Write data to DR */
+ hfmpi2c->Instance->TXDR = (*pData++);
+ Sizetmp--;
+ Size--;
+
+ if((Sizetmp == 0)&&(Size!=0))
+ {
+ /* Wait until TCR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+
+ if(Size > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ Sizetmp = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ Sizetmp = Size;
+ }
+ }
+
+ }while(Size > 0);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in blocking mode from a specific memory address
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t Sizetmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MEM_BUSY_RX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Send Slave Address and Memory Address */
+ if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ /* Size > 255, need to set RELOAD bit */
+ if(Size > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
+ Sizetmp = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+ Sizetmp = Size;
+ }
+
+ do
+ {
+ /* Wait until RXNE flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Read data from RXDR */
+ (*pData++) = hfmpi2c->Instance->RXDR;
+
+ /* Decrement the Size counter */
+ Sizetmp--;
+ Size--;
+
+ if((Sizetmp == 0)&&(Size!=0))
+ {
+ /* Wait until TCR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(Size > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ Sizetmp = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ Sizetmp = Size;
+ }
+ }
+
+ }while(Size > 0);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MEM_BUSY_TX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = Size;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if size > 255 */
+ /* Size > 255, need to set RELOAD bit */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_TXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MEM_BUSY_RX;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = Size;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ /* Size > 255, need to set RELOAD bit */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ __HAL_FMPI2C_ENABLE_IT(hfmpi2c, FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_RXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in no-blocking mode with DMA to a specific memory address
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MEM_BUSY_TX;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = Size;
+ }
+
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMemTransmitCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+
+ /* Send Slave Address and Memory Address */
+ if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ }
+
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_TXIS) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be read
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_MEM_BUSY_RX;
+
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = Size;
+ }
+
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMAMemReceiveCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
+
+ /* Send Slave Address and Memory Address */
+ if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, FMPI2C_TIMEOUT_RXNE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Checks if target device is ready for communication.
+ * @note This function is used with Memory devices
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param Trials: Number of trials
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ __IO uint32_t FMPI2C_Trials = 0;
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ do
+ {
+ /* Generate Start */
+ hfmpi2c->Instance->CR2 = __HAL_FMPI2C_GENERATE_START(hfmpi2c->Init.AddressingMode,DevAddress);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set or a NACK flag is set*/
+ tickstart = HAL_GetTick();
+ while((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) && (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == RESET) && (hfmpi2c->State != HAL_FMPI2C_STATE_TIMEOUT))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Device is ready */
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check if the NACKF flag has not been set */
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == RESET)
+ {
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Device is ready */
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Clear STOP Flag, auto generated with autoend*/
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+ }
+
+ /* Check if the maximum allowed number of trials has been reached */
+ if (FMPI2C_Trials++ == Trials)
+ {
+ /* Generate Stop */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
+
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+ }
+ }while(FMPI2C_Trials < Trials);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief This function handles FMPI2C event interrupt request.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* FMPI2C in mode Transmitter ---------------------------------------------------*/
+ if (((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TCR) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TC) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR) == SET)) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, (FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI | FMPI2C_IT_ADDRI)) == SET))
+ {
+ /* Slave mode selected */
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_TX)
+ {
+ FMPI2C_SlaveTransmit_ISR(hfmpi2c);
+ }
+ }
+
+ if (((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TCR) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TC) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET)) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, (FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI)) == SET))
+ {
+ /* Master mode selected */
+ if ((hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_MEM_BUSY_TX))
+ {
+ FMPI2C_MasterTransmit_ISR(hfmpi2c);
+ }
+ }
+
+ /* FMPI2C in mode Receiver ----------------------------------------------------*/
+ if (((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TCR) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TC) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR) == SET)) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, (FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_RXI | FMPI2C_IT_ADDRI)) == SET))
+ {
+ /* Slave mode selected */
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_RX)
+ {
+ FMPI2C_SlaveReceive_ISR(hfmpi2c);
+ }
+ }
+ if (((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TCR) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TC) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET) || (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET)) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, (FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_RXI)) == SET))
+ {
+ /* Master mode selected */
+ if ((hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_RX) || (hfmpi2c->State == HAL_FMPI2C_STATE_MEM_BUSY_RX))
+ {
+ FMPI2C_MasterReceive_ISR(hfmpi2c);
+ }
+ }
+}
+
+/**
+ * @brief This function handles FMPI2C error interrupt request.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* FMPI2C Bus error interrupt occurred ------------------------------------*/
+ if((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BERR) == SET) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, FMPI2C_IT_ERRI) == SET))
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_BERR);
+ }
+
+ /* FMPI2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+ if((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_OVR) == SET) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, FMPI2C_IT_ERRI) == SET))
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_OVR);
+ }
+
+ /* FMPI2C Arbitration Loss error interrupt occurred -------------------------------------*/
+ if((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ARLO) == SET) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, FMPI2C_IT_ERRI) == SET))
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ARLO);
+ }
+
+ /* Call the Error Callback in case of Error detected */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+}
+
+/**
+ * @brief Master Tx Transfer completed callbacks.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+ __weak void HAL_FMPI2C_MasterTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Master Rx Transfer completed callbacks.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+__weak void HAL_FMPI2C_MasterRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/** @brief Slave Tx Transfer completed callbacks.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+ __weak void HAL_FMPI2C_SlaveTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Rx Transfer completed callbacks.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+__weak void HAL_FMPI2C_SlaveRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Tx Transfer completed callbacks.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+ __weak void HAL_FMPI2C_MemTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Rx Transfer completed callbacks.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+__weak void HAL_FMPI2C_MemRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FMPI2C error callbacks.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+ __weak void HAL_FMPI2C_ErrorCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FMPI2C_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the FMPI2C state.
+ * @param hfmpi2c : FMPI2C handle
+ * @retval HAL state
+ */
+HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ return hfmpi2c->State;
+}
+
+/**
+* @brief Return the FMPI2C error code
+* @param hfmpi2c : pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+* @retval FMPI2C Error Code
+*/
+uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ return hfmpi2c->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Handle Interrupt Flags Master Transmit Mode
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_MasterTransmit_ISR(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ uint16_t DevAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == SET)
+ {
+ /* Write data to TXDR */
+ hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
+ hfmpi2c->XferSize--;
+ hfmpi2c->XferCount--;
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TCR) == SET)
+ {
+ if((hfmpi2c->XferSize == 0)&&(hfmpi2c->XferCount!=0))
+ {
+ DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
+
+ if(hfmpi2c->XferCount > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferCount, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ }
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Wrong size Status regarding TCR flag event */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_SIZE;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TC) == SET)
+ {
+ if(hfmpi2c->XferCount == 0)
+ {
+ /* Generate Stop */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Wrong size Status regarding TCR flag event */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_SIZE;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET)
+ {
+ /* Disable ERR, TC, STOP, NACK, TXI interrupt */
+ __HAL_FMPI2C_DISABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_TXI );
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_MEM_BUSY_TX)
+ {
+ HAL_FMPI2C_MemTxCpltCallback(hfmpi2c);
+ }
+ else
+ {
+ HAL_FMPI2C_MasterTxCpltCallback(hfmpi2c);
+ }
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET)
+ {
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle Interrupt Flags Master Receive Mode
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_MasterReceive_ISR(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ uint16_t DevAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from RXDR */
+ (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+ hfmpi2c->XferSize--;
+ hfmpi2c->XferCount--;
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TCR) == SET)
+ {
+ if((hfmpi2c->XferSize == 0)&&(hfmpi2c->XferCount!=0))
+ {
+ DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
+
+ if(hfmpi2c->XferCount > 255)
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,255, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferCount, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ }
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Wrong size Status regarding TCR flag event */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_SIZE;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TC) == SET)
+ {
+ if(hfmpi2c->XferCount == 0)
+ {
+ /* Generate Stop */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Wrong size Status regarding TCR flag event */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_SIZE;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET)
+ {
+ /* Disable ERR, TC, STOP, NACK, TXI interrupt */
+ __HAL_FMPI2C_DISABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_RXI );
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ if(hfmpi2c->State == HAL_FMPI2C_STATE_MEM_BUSY_RX)
+ {
+ HAL_FMPI2C_MemRxCpltCallback(hfmpi2c);
+ }
+ else
+ {
+ HAL_FMPI2C_MasterRxCpltCallback(hfmpi2c);
+ }
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET)
+ {
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Handle Interrupt Flags Slave Transmit Mode
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_SlaveTransmit_ISR(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Process locked */
+ __HAL_LOCK(hfmpi2c);
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) != RESET)
+ {
+ /* Check that FMPI2C transfer finished */
+ /* if yes, normal usecase, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0*/
+ /* So clear Flag NACKF only */
+ if(hfmpi2c->XferCount == 0)
+ {
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ }
+ else
+ {
+ /* if no, error usecase, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Call the Error callback to prevent upper layer */
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR) == SET)
+ {
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
+ }
+ /* Check first if STOPF is set */
+ /* to prevent a Write Data in TX buffer */
+ /* which is stuck in TXDR until next */
+ /* communication with Master */
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET)
+ {
+ /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */
+ __HAL_FMPI2C_DISABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI );
+
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == SET)
+ {
+ /* Write data to TXDR only if XferCount not reach "0" */
+ /* A TXIS flag can be set, during STOP treatment */
+ if(hfmpi2c->XferCount > 0)
+ {
+ /* Write data to TXDR */
+ hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
+ hfmpi2c->XferCount--;
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle Interrupt Flags Slave Receive Mode
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_SlaveReceive_ISR(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) != RESET)
+ {
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR) == SET)
+ {
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from RXDR */
+ (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+ hfmpi2c->XferSize--;
+ hfmpi2c->XferCount--;
+ }
+ else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET)
+ {
+ /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */
+ __HAL_FMPI2C_DISABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_RXI );
+
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ HAL_FMPI2C_SlaveRxCpltCallback(hfmpi2c);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for write request.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+{
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
+
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* If Memory address size is 8Bit */
+ if(MemAddSize == FMPI2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hfmpi2c->Instance->TXDR = __HAL_FMPI2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hfmpi2c->Instance->TXDR = __HAL_FMPI2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send LSB of Memory Address */
+ hfmpi2c->Instance->TXDR = __HAL_FMPI2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ /* Wait until TCR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for read request.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+{
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE);
+
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* If Memory address size is 8Bit */
+ if(MemAddSize == FMPI2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hfmpi2c->Instance->TXDR = __HAL_FMPI2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Mememory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hfmpi2c->Instance->TXDR = __HAL_FMPI2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send LSB of Memory Address */
+ hfmpi2c->Instance->TXDR = __HAL_FMPI2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ /* Wait until TC flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DMA FMPI2C master transmit process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ uint16_t DevAddress;
+ FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Check if last DMA request was done with RELOAD */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ /* Wait until TCR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, FMPI2C_TIMEOUT_TCR) != HAL_OK)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+ if(hfmpi2c->XferCount > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ }
+
+ DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ }
+
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_TXIS) != HAL_OK)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+ }
+ }
+ }
+ else
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ HAL_FMPI2C_MasterTxCpltCallback(hfmpi2c);
+ }
+ }
+}
+
+/**
+ * @brief DMA FMPI2C slave transmit process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Wait until STOP flag is set */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Normal Use case, a AF is generated by master */
+ /* to inform slave the end of transfer */
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY) != HAL_OK)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
+ }
+}
+
+/**
+ * @brief DMA FMPI2C master receive process complete callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ uint16_t DevAddress;
+
+ /* Check if last DMA request was done with RELOAD */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ /* Wait until TCR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, FMPI2C_TIMEOUT_TCR) != HAL_OK)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+ if(hfmpi2c->XferCount > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ }
+
+ DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)hfmpi2c->pBuffPtr, hfmpi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, FMPI2C_TIMEOUT_RXNE) != HAL_OK)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+ }
+ }
+ }
+ else
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ HAL_FMPI2C_MasterRxCpltCallback(hfmpi2c);
+ }
+ }
+}
+
+/**
+ * @brief DMA FMPI2C slave receive process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOPF flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY) != HAL_OK)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ HAL_FMPI2C_SlaveRxCpltCallback(hfmpi2c);
+ }
+}
+
+/**
+ * @brief DMA FMPI2C Memory Write process complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void FMPI2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ uint16_t DevAddress;
+ FMPI2C_HandleTypeDef* hfmpi2c = ( FMPI2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Check if last DMA request was done with RELOAD */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ /* Wait until TCR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, FMPI2C_TIMEOUT_TCR) != HAL_OK)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+ if(hfmpi2c->XferCount > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ }
+
+ DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ }
+
+ /* Wait until TXIS flag is set */
+ if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_TXIS) != HAL_OK)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+ }
+ }
+ }
+ else
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ HAL_FMPI2C_MemTxCpltCallback(hfmpi2c);
+ }
+ }
+}
+
+/**
+ * @brief DMA FMPI2C Memory Read process complete callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void FMPI2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ FMPI2C_HandleTypeDef* hfmpi2c = ( FMPI2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ uint16_t DevAddress;
+
+ /* Check if last DMA request was done with RELOAD */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ /* Wait until TCR flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, FMPI2C_TIMEOUT_TCR) != HAL_OK)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+ if(hfmpi2c->XferCount > 255)
+ {
+ hfmpi2c->XferSize = 255;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ }
+
+ DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)hfmpi2c->pBuffPtr, hfmpi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hfmpi2c->XferSize == 255) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, FMPI2C_TIMEOUT_RXNE) != HAL_OK)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+ }
+ }
+ }
+ else
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ else
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+ else
+ {
+ HAL_FMPI2C_MemRxCpltCallback(hfmpi2c);
+ }
+ }
+}
+
+/**
+ * @brief DMA FMPI2C communication error callback.
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+ FMPI2C_HandleTypeDef* hfmpi2c = ( FMPI2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ hfmpi2c->XferCount = 0;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA;
+
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+}
+
+/**
+ * @brief This function handles FMPI2C Communication Timeout.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param Flag: specifies the FMPI2C flag to check.
+ * @param Status: The new Flag status (SET or RESET).
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles FMPI2C Communication Timeout for specific usage of TXIS flag.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == RESET)
+ {
+ /* Check if a NACK is detected */
+ if(FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles FMPI2C Communication Timeout for specific usage of STOP flag.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
+{
+ uint32_t tickstart = 0x00;
+ tickstart = HAL_GetTick();
+
+ while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)
+ {
+ /* Check if a NACK is detected */
+ if(FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles FMPI2C Communication Timeout for specific usage of RXNE flag.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
+{
+ uint32_t tickstart = 0x00;
+ tickstart = HAL_GetTick();
+
+ while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET)
+ {
+ /* Check if a STOPF is detected */
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET)
+ {
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+ hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles Acknowledge failed detection during an FMPI2C Communication.
+ * @param hfmpi2c : Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
+{
+ uint32_t tickstart = 0x00;
+ tickstart = HAL_GetTick();
+
+ if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET)
+ {
+ /* Generate stop if necessary only in case of FMPI2C peripheral in MASTER mode */
+ if((hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_MEM_BUSY_TX)
+ || (hfmpi2c->State == HAL_FMPI2C_STATE_MEM_BUSY_RX))
+ {
+ /* No need to generate the STOP condition if AUTOEND mode is enabled */
+ /* Generate the STOP condition only in case of SOFTEND mode is enabled */
+ if((hfmpi2c->Instance->CR2 & FMPI2C_AUTOEND_MODE) != FMPI2C_AUTOEND_MODE)
+ {
+ /* Generate Stop */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
+ }
+ }
+
+ /* Wait until STOP Flag is reset */
+ /* AutoEnd should be initiate after AF */
+ while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear NACKF Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_AF;
+ hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles FMPI2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @param hfmpi2c: FMPI2C handle.
+ * @param DevAddress: specifies the slave address to be programmed.
+ * @param Size: specifies the number of bytes to be programmed.
+ * This parameter must be a value between 0 and 255.
+ * @param Mode: new state of the FMPI2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg FMPI2C_RELOAD_MODE: Enable Reload mode .
+ * @arg FMPI2C_AUTOEND_MODE: Enable Automatic end mode.
+ * @arg FMPI2C_SOFTEND_MODE: Enable Software end mode.
+ * @param Request: new state of the FMPI2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg FMPI2C_NO_STARTSTOP: Don't Generate stop and start condition.
+ * @arg FMPI2C_GENERATE_STOP: Generate stop condition (Size should be set to 0).
+ * @arg FMPI2C_GENERATE_START_READ: Generate Restart for read request.
+ * @arg FMPI2C_GENERATE_START_WRITE: Generate Restart for write request.
+ * @retval None
+ */
+static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
+ assert_param(IS_TRANSFER_MODE(Mode));
+ assert_param(IS_TRANSFER_REQUEST(Request));
+
+ /* Get the CR2 register value */
+ tmpreg = hfmpi2c->Instance->CR2;
+
+ /* clear tmpreg specific bits */
+ tmpreg &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_RD_WRN | FMPI2C_CR2_START | FMPI2C_CR2_STOP));
+
+ /* update tmpreg */
+ tmpreg |= (uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | (((uint32_t)Size << 16 ) & FMPI2C_CR2_NBYTES) | \
+ (uint32_t)Mode | (uint32_t)Request);
+
+ /* update CR2 register */
+ hfmpi2c->Instance->CR2 = tmpreg;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F410xx || STM32F446xx */
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/src/stm32f4xx_hal_fmpi2c_ex.c b/f4/src/stm32f4xx_hal_fmpi2c_ex.c
new file mode 100644
index 0000000..ea2f0ca
--- /dev/null
+++ b/f4/src/stm32f4xx_hal_fmpi2c_ex.c
@@ -0,0 +1,326 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_fmpi2c_ex.c
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief Extended FMPI2C HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Inter Integrated Circuit (FMPI2C) peripheral:
+ * + Extended Control methods
+ *
+ @verbatim
+ ==============================================================================
+ ##### FMPI2C peripheral extended features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the FMPI2C interface for STM32L4XX
+ devices contains the following additional features
+
+ (+) Possibility to disable or enable Analog Noise Filter
+ (+) Use of a configured Digital Noise Filter
+ (+) Disable or enable wakeup from Stop mode
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure Noise Filter
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FMPI2CEx FMPI2CEx
+ * @brief FMPI2C HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup FMPI2CEx_Exported_Functions FMPI2C Extended Exported Functions
+ * @{
+ */
+
+
+/** @defgroup FMPI2CEx_Exported_Functions_Group1 Peripheral Control methods
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extension features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Noise Filters
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures FMPI2C Analog noise filter.
+ * @param hfmpi2c : pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2Cx peripheral.
+ * @param AnalogFilter : new state of the Analog filter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2CEx_AnalogFilter_Config(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t AnalogFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
+ assert_param(IS_FMPI2C_ANALOG_FILTER(AnalogFilter));
+
+ if((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY) || (hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_RX)
+ || (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_RX))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
+
+ /* Disable the selected FMPI2C peripheral */
+ __HAL_FMPI2C_DISABLE(hfmpi2c);
+
+ /* Reset FMPI2Cx ANOFF bit */
+ hfmpi2c->Instance->CR1 &= ~(FMPI2C_CR1_ANFOFF);
+
+ /* Set analog filter bit*/
+ hfmpi2c->Instance->CR1 |= AnalogFilter;
+
+ __HAL_FMPI2C_ENABLE(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures FMPI2C Digital noise filter.
+ * @param hfmpi2c : pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2Cx peripheral.
+ * @param DigitalFilter : Coefficient of digital noise filter between 0x00 and 0x0F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2CEx_DigitalFilter_Config(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t DigitalFilter)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
+ assert_param(IS_FMPI2C_DIGITAL_FILTER(DigitalFilter));
+
+ if((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY) || (hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_RX)
+ || (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_RX))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
+
+ /* Disable the selected FMPI2C peripheral */
+ __HAL_FMPI2C_DISABLE(hfmpi2c);
+
+ /* Get the old register value */
+ tmpreg = hfmpi2c->Instance->CR1;
+
+ /* Reset FMPI2Cx DNF bits [11:8] */
+ tmpreg &= ~(FMPI2C_CR1_DFN);
+
+ /* Set FMPI2Cx DNF coefficient */
+ tmpreg |= DigitalFilter << 8;
+
+ /* Store the new register value */
+ hfmpi2c->Instance->CR1 = tmpreg;
+
+ __HAL_FMPI2C_ENABLE(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables FMPI2C wakeup from stop mode.
+ * @param hfmpi2c : pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2Cx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2CEx_EnableWakeUp (FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
+
+ if((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY) || (hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_RX)
+ || (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_RX))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
+
+ /* Disable the selected FMPI2C peripheral */
+ __HAL_FMPI2C_DISABLE(hfmpi2c);
+
+ /* Enable wakeup from stop mode */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_WUPEN;
+
+ __HAL_FMPI2C_ENABLE(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Disables FMPI2C wakeup from stop mode.
+ * @param hfmpi2c : pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2Cx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2CEx_DisableWakeUp (FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
+
+ if((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY) || (hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_MASTER_BUSY_RX)
+ || (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_SLAVE_BUSY_RX))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
+
+ /* Disable the selected FMPI2C peripheral */
+ __HAL_FMPI2C_DISABLE(hfmpi2c);
+
+ /* Enable wakeup from stop mode */
+ hfmpi2c->Instance->CR1 &= ~(FMPI2C_CR1_WUPEN);
+
+ __HAL_FMPI2C_ENABLE(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the FMPI2C1 fast mode plus driving capability.
+ * @param ConfigFastModePlus: selects the pin.
+ * This parameter can be one of the @ref FMPI2CEx_FastModePlus values
+ * @retval None
+ */
+void HAL_FMPI2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_FMPI2C_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Enable fast mode plus driving capability for selected pin */
+ SET_BIT(SYSCFG->CFGR, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+ * @brief Disable the FMPI2C1 fast mode plus driving capability.
+ * @param ConfigFastModePlus: selects the pin.
+ * This parameter can be one of the @ref FMPI2CEx_FastModePlus values
+ * @retval None
+ */
+void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_FMPI2C_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Disable fast mode plus driving capability for selected pin */
+ CLEAR_BIT(SYSCFG->CFGR, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F410xx || STM32F446xx */
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/src/stm32f4xx_hal_gpio.c b/f4/src/stm32f4xx_hal_gpio.c
index d658b91..4de3acc 100755
--- a/f4/src/stm32f4xx_hal_gpio.c
+++ b/f4/src/stm32f4xx_hal_gpio.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_gpio.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
@@ -95,7 +95,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -348,17 +348,22 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
/*------------------------- EXTI Mode Configuration --------------------*/
- /* Configure the External Interrupt or event for the current IO */
- tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
- SYSCFG->EXTICR[position >> 2] &= ~tmp;
-
- /* Clear EXTI line configuration */
- EXTI->IMR &= ~((uint32_t)iocurrent);
- EXTI->EMR &= ~((uint32_t)iocurrent);
+ tmp = SYSCFG->EXTICR[position >> 2];
+ tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
+ if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
+ {
+ /* Configure the External Interrupt or event for the current IO */
+ tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
+ SYSCFG->EXTICR[position >> 2] &= ~tmp;
- /* Clear Rising Falling edge configuration */
- EXTI->RTSR &= ~((uint32_t)iocurrent);
- EXTI->FTSR &= ~((uint32_t)iocurrent);
+ /* Clear EXTI line configuration */
+ EXTI->IMR &= ~((uint32_t)iocurrent);
+ EXTI->EMR &= ~((uint32_t)iocurrent);
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RTSR &= ~((uint32_t)iocurrent);
+ EXTI->FTSR &= ~((uint32_t)iocurrent);
+ }
}
}
}
diff --git a/f4/src/stm32f4xx_hal_hash.c b/f4/src/stm32f4xx_hal_hash.c
index 5f4986f..47c7bf4 100755
--- a/f4/src/stm32f4xx_hal_hash.c
+++ b/f4/src/stm32f4xx_hal_hash.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_hash.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral:
@@ -68,7 +68,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -109,7 +109,7 @@
#ifdef HAL_HASH_MODULE_ENABLED
-#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx)
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -176,8 +176,8 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
buffersize = hhash->Init.KeySize;
}
/* Configure the number of valid bits in last word of the message */
- HASH->STR |= 8 * (buffersize % 4);
-
+ MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));
+
/* Set the HASH DMA transfer complete */
hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
@@ -355,6 +355,8 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
if(hhash->State == HAL_HASH_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hhash->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_HASH_MspInit(hhash);
}
@@ -712,10 +714,14 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
+ /* Check the parameters */
+ assert_param(IS_HASH_SHA1_BUFFER_SIZE(Size));
+
/* Process Locked */
__HAL_LOCK(hhash);
@@ -790,14 +796,6 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
/* Process Locked */
__HAL_LOCK(hhash);
- if(hhash->HashITCounter == 0)
- {
- hhash->HashITCounter = 1;
- }
- else
- {
- hhash->HashITCounter = 0;
- }
if(hhash->State == HAL_HASH_STATE_READY)
{
/* Change the HASH state */
@@ -816,6 +814,8 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
the message digest of a new message */
HASH->CR |= HASH_CR_INIT;
}
+ /* Reset interrupt counter */
+ hhash->HashITCounter = 0;
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
@@ -849,11 +849,17 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
hhash->State = HAL_HASH_STATE_READY;
/* Call digest computation complete callback */
HAL_HASH_DgstCpltCallback(hhash);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
}
}
if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
- if(hhash->HashInCount > 64)
+ if(hhash->HashInCount >= 68)
{
inputaddr = (uint32_t)hhash->pHashInBuffPtr;
/* Write the Input block in the Data IN register */
@@ -874,8 +880,11 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
}
else
{
- hhash->HashInCount -= 64;
+ hhash->HashInCount = 0;
+ hhash->pHashInBuffPtr+= hhash->HashInCount;
}
+ /* Set Interrupt counter */
+ hhash->HashITCounter = 1;
}
else
{
@@ -899,7 +908,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
{
inputcounter = (inputcounter+4-inputcounter%4);
}
-
+ else if ((inputcounter < 4) && (inputcounter != 0))
+ {
+ inputcounter = 4;
+ }
/* Write the Input block in the Data IN register */
for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
{
@@ -910,9 +922,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
__HAL_HASH_START_DIGEST();
/* Reset buffer counter */
hhash->HashInCount = 0;
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
}
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
}
/* Process Unlocked */
@@ -943,14 +955,6 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
/* Process Locked */
__HAL_LOCK(hhash);
- if(hhash->HashITCounter == 0)
- {
- hhash->HashITCounter = 1;
- }
- else
- {
- hhash->HashITCounter = 0;
- }
if(hhash->State == HAL_HASH_STATE_READY)
{
/* Change the HASH state */
@@ -969,6 +973,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
the message digest of a new message */
HASH->CR |= HASH_CR_INIT;
}
+ /* Reset interrupt counter */
+ hhash->HashITCounter = 0;
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
@@ -1003,11 +1009,17 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
hhash->State = HAL_HASH_STATE_READY;
/* Call digest computation complete callback */
HAL_HASH_DgstCpltCallback(hhash);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
}
}
if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
- if(hhash->HashInCount > 64)
+ if(hhash->HashInCount >= 68)
{
inputaddr = (uint32_t)hhash->pHashInBuffPtr;
/* Write the Input block in the Data IN register */
@@ -1019,7 +1031,6 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
if(hhash->HashITCounter == 0)
{
HASH->DIN = *(uint32_t*)inputaddr;
-
if(hhash->HashInCount >= 68)
{
/* Decrement buffer counter */
@@ -1028,8 +1039,11 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
}
else
{
- hhash->HashInCount -= 64;
+ hhash->HashInCount = 0;
+ hhash->pHashInBuffPtr+= hhash->HashInCount;
}
+ /* Set Interrupt counter */
+ hhash->HashITCounter = 1;
}
else
{
@@ -1053,7 +1067,10 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
{
inputcounter = (inputcounter+4-inputcounter%4);
}
-
+ else if ((inputcounter < 4) && (inputcounter != 0))
+ {
+ inputcounter = 4;
+ }
/* Write the Input block in the Data IN register */
for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
{
@@ -1064,9 +1081,9 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
__HAL_HASH_START_DIGEST();
/* Reset buffer counter */
hhash->HashInCount = 0;
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
}
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
}
/* Process Unlocked */
@@ -1828,7 +1845,7 @@ HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
* @}
*/
-#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx || STM32F479xx */
#endif /* HAL_HASH_MODULE_ENABLED */
/**
* @}
diff --git a/f4/src/stm32f4xx_hal_hash_ex.c b/f4/src/stm32f4xx_hal_hash_ex.c
index 842c538..29ad155 100755
--- a/f4/src/stm32f4xx_hal_hash_ex.c
+++ b/f4/src/stm32f4xx_hal_hash_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_hash_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief HASH HAL Extension module driver.
* This file provides firmware functions to manage the following
* functionalities of HASH peripheral:
@@ -65,7 +65,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -106,7 +106,7 @@
#ifdef HAL_HASH_MODULE_ENABLED
-#if defined(STM32F437xx) || defined(STM32F439xx)
+#if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -265,8 +265,8 @@ static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma)
buffersize = hhash->Init.KeySize;
}
/* Configure the number of valid bits in last word of the message */
- HASH->STR |= 8 * (buffersize % 4);
-
+ MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));
+
/* Set the HASH DMA transfer complete */
hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
@@ -926,14 +926,6 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
/* Process Locked */
__HAL_LOCK(hhash);
- if(hhash->HashITCounter == 0)
- {
- hhash->HashITCounter = 1;
- }
- else
- {
- hhash->HashITCounter = 0;
- }
if(hhash->State == HAL_HASH_STATE_READY)
{
/* Change the HASH state */
@@ -952,6 +944,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
the message digest of a new message */
HASH->CR |= HASH_CR_INIT;
}
+ /* Reset interrupt counter */
+ hhash->HashITCounter = 0;
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
@@ -977,11 +971,17 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
hhash->State = HAL_HASH_STATE_READY;
/* Call digest computation complete callback */
HAL_HASH_DgstCpltCallback(hhash);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
}
}
if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
- if(hhash->HashInCount > 64)
+ if(hhash->HashInCount >= 68)
{
inputaddr = (uint32_t)hhash->pHashInBuffPtr;
/* Write the Input block in the Data IN register */
@@ -993,6 +993,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
if(hhash->HashITCounter == 0)
{
HASH->DIN = *(uint32_t*)inputaddr;
+
if(hhash->HashInCount >= 68)
{
/* Decrement buffer counter */
@@ -1001,8 +1002,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
}
else
{
- hhash->HashInCount -= 64;
+ hhash->HashInCount = 0;
+ hhash->pHashInBuffPtr+= hhash->HashInCount;
}
+ /* Set Interrupt counter */
+ hhash->HashITCounter = 1;
}
else
{
@@ -1026,7 +1030,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
{
inputcounter = (inputcounter+4-inputcounter%4);
}
-
+ else if ((inputcounter < 4) && (inputcounter != 0))
+ {
+ inputcounter = 4;
+ }
/* Write the Input block in the Data IN register */
for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
{
@@ -1037,9 +1044,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
__HAL_HASH_START_DIGEST();
/* Reset buffer counter */
hhash->HashInCount = 0;
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
}
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
}
/* Process Unlocked */
@@ -1070,14 +1077,6 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
/* Process Locked */
__HAL_LOCK(hhash);
- if(hhash->HashITCounter == 0)
- {
- hhash->HashITCounter = 1;
- }
- else
- {
- hhash->HashITCounter = 0;
- }
if(hhash->State == HAL_HASH_STATE_READY)
{
/* Change the HASH state */
@@ -1096,6 +1095,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
the message digest of a new message */
HASH->CR |= HASH_CR_INIT;
}
+ /* Reset interrupt counter */
+ hhash->HashITCounter = 0;
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
@@ -1121,11 +1122,17 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
hhash->State = HAL_HASH_STATE_READY;
/* Call digest computation complete callback */
HAL_HASH_DgstCpltCallback(hhash);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
}
}
if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
- if(hhash->HashInCount > 64)
+ if(hhash->HashInCount >= 68)
{
inputaddr = (uint32_t)hhash->pHashInBuffPtr;
/* Write the Input block in the Data IN register */
@@ -1137,7 +1144,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
if(hhash->HashITCounter == 0)
{
HASH->DIN = *(uint32_t*)inputaddr;
-
+
if(hhash->HashInCount >= 68)
{
/* Decrement buffer counter */
@@ -1146,8 +1153,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
}
else
{
- hhash->HashInCount -= 64;
+ hhash->HashInCount = 0;
+ hhash->pHashInBuffPtr+= hhash->HashInCount;
}
+ /* Set Interrupt counter */
+ hhash->HashITCounter = 1;
}
else
{
@@ -1171,7 +1181,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
{
inputcounter = (inputcounter+4-inputcounter%4);
}
-
+ else if ((inputcounter < 4) && (inputcounter != 0))
+ {
+ inputcounter = 4;
+ }
/* Write the Input block in the Data IN register */
for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
{
@@ -1182,9 +1195,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
__HAL_HASH_START_DIGEST();
/* Reset buffer counter */
hhash->HashInCount = 0;
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
}
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
}
/* Process Unlocked */
@@ -1611,7 +1624,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @}
*/
-#endif /* STM32F437xx || STM32F439xx */
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
#endif /* HAL_HASH_MODULE_ENABLED */
/**
diff --git a/f4/src/stm32f4xx_hal_hcd.c b/f4/src/stm32f4xx_hal_hcd.c
index f6c23a2..ac4b230 100755
--- a/f4/src/stm32f4xx_hal_hcd.c
+++ b/f4/src/stm32f4xx_hal_hcd.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_hcd.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief HCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -26,8 +26,9 @@
(#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
(##) Enable the HCD/USB Low Level interface clock using the following macros
- (+++) __OTGFS-OTG_CLK_ENABLE() or __OTGHS-OTG_CLK_ENABLE()
- (+++) __OTGHSULPI_CLK_ENABLE() For High Speed Mode
+ (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+ (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
+ (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode)
(##) Initialize the related GPIO clocks
(##) Configure HCD pin-out
@@ -43,7 +44,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -77,18 +78,22 @@
* @{
*/
-/** @addtogroup HCD
+/** @defgroup HCD HCD
+ * @brief HCD HAL module driver
* @{
*/
#ifdef HAL_HCD_MODULE_ENABLED
-
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/* Private function ----------------------------------------------------------*/
-/** @addtogroup HCD_Private_Functions
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HCD_Private_Functions HCD Private Functions
* @{
*/
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
@@ -100,12 +105,12 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HCD_Exported_Functions
+/** @defgroup HCD_Exported_Functions HCD Exported Functions
* @{
*/
-/** @addtogroup HCD_Exported_Functions_Group1
- * @brief Initialization and de-initialization functions
+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
@@ -118,7 +123,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
*/
/**
- * @brief Initialize the host driver
+ * @brief Initialize the host driver.
* @param hhcd: HCD handle
* @retval HAL status
*/
@@ -156,7 +161,7 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
}
/**
- * @brief Initialize a host channel
+ * @brief Initialize a host channel.
* @param hhcd: HCD handle
* @param ch_num: Channel number.
* This parameter can be a value from 1 to 15
@@ -212,7 +217,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
}
/**
- * @brief Halt a host channel
+ * @brief Halt a host channel.
* @param hhcd: HCD handle
* @param ch_num: Channel number.
* This parameter can be a value from 1 to 15
@@ -230,7 +235,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
}
/**
- * @brief DeInitialize the host driver
+ * @brief DeInitialize the host driver.
* @param hhcd: HCD handle
* @retval HAL status
*/
@@ -255,7 +260,7 @@ HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
}
/**
- * @brief Initializes the HCD MSP.
+ * @brief Initialize the HCD MSP.
* @param hhcd: HCD handle
* @retval None
*/
@@ -267,7 +272,7 @@ __weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
}
/**
- * @brief DeInitializes HCD MSP.
+ * @brief DeInitialize the HCD MSP.
* @param hhcd: HCD handle
* @retval None
*/
@@ -282,14 +287,14 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
* @}
*/
-/** @addtogroup HCD_Exported_Functions_Group2
+/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions
* @brief HCD IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
- This subsection provides a set of functions allowing to manage the USB Host Data
+ [..] This subsection provides a set of functions allowing to manage the USB Host Data
Transfer
@endverbatim
@@ -297,7 +302,7 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
*/
/**
- * @brief Submit a new URB for processing
+ * @brief Submit a new URB for processing.
* @param hhcd: HCD handle
* @param ch_num: Channel number.
* This parameter can be a value from 1 to 15
@@ -440,7 +445,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
}
/**
- * @brief This function handles HCD interrupt request.
+ * @brief Handle HCD interrupt request.
* @param hhcd: HCD handle
* @retval None
*/
@@ -555,7 +560,7 @@ __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
}
/**
- * @brief Connexion Event callback.
+ * @brief Connection Event callback.
* @param hhcd: HCD handle
* @retval None
*/
@@ -567,7 +572,7 @@ __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
}
/**
- * @brief Disconnexion Event callback.
+ * @brief Disconnection Event callback.
* @param hhcd: HCD handle
* @retval None
*/
@@ -604,8 +609,8 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t
* @}
*/
-/** @addtogroup HCD_Exported_Functions_Group3
- * @brief Peripheral State functions
+/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Management functions
*
@verbatim
===============================================================================
@@ -620,7 +625,7 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t
*/
/**
- * @brief Start the host driver
+ * @brief Start the host driver.
* @param hhcd: HCD handle
* @retval HAL status
*/
@@ -634,7 +639,7 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
}
/**
- * @brief Stop the host driver
+ * @brief Stop the host driver.
* @param hhcd: HCD handle
* @retval HAL status
*/
@@ -648,7 +653,7 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
}
/**
- * @brief Reset the host port
+ * @brief Reset the host port.
* @param hhcd: HCD handle
* @retval HAL status
*/
@@ -661,7 +666,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
* @}
*/
-/** @addtogroup HCD_Exported_Functions_Group4
+/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
@@ -677,7 +682,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
*/
/**
- * @brief Return the HCD state
+ * @brief Return the HCD handle state.
* @param hhcd: HCD handle
* @retval HAL state
*/
@@ -687,7 +692,7 @@ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
}
/**
- * @brief Return URB state for a channel
+ * @brief Return URB state for a channel.
* @param hhcd: HCD handle
* @param chnum: Channel number.
* This parameter can be a value from 1 to 15
@@ -698,7 +703,7 @@ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
* URB_NOTREADY/
* URB_NYET/
* URB_ERROR/
- * URB_STALL/
+ * URB_STALL
*/
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
@@ -707,7 +712,7 @@ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnu
/**
- * @brief Return the last host transfer size
+ * @brief Return the last host transfer size.
* @param hhcd: HCD handle
* @param chnum: Channel number.
* This parameter can be a value from 1 to 15
@@ -719,12 +724,12 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
}
/**
- * @brief Return the Host Channel state
+ * @brief Return the Host Channel state.
* @param hhcd: HCD handle
* @param chnum: Channel number.
* This parameter can be a value from 1 to 15
* @retval Host channel state
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* HC_IDLE/
* HC_XFRC/
* HC_HALTED/
@@ -733,7 +738,7 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
* HC_STALL/
* HC_XACTERR/
* HC_BBLERR/
- * HC_DATATGLERR/
+ * HC_DATATGLERR
*/
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
@@ -741,7 +746,7 @@ HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
}
/**
- * @brief Return the current Host frame number
+ * @brief Return the current Host frame number.
* @param hhcd: HCD handle
* @retval Current Host frame number
*/
@@ -751,7 +756,7 @@ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
}
/**
- * @brief Return the Host enumeration speed
+ * @brief Return the Host enumeration speed.
* @param hhcd: HCD handle
* @retval Enumeration speed
*/
@@ -759,6 +764,7 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
{
return (USB_GetHostSpeed(hhcd->Instance));
}
+
/**
* @}
*/
@@ -771,7 +777,7 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
* @{
*/
/**
- * @brief This function handles Host Channel IN interrupt requests.
+ * @brief Handle Host Channel IN interrupt requests.
* @param hhcd: HCD handle
* @param chnum: Channel number.
* This parameter can be a value from 1 to 15
@@ -780,6 +786,7 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ uint32_t tmpreg = 0;
if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
{
@@ -874,8 +881,10 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
}
/* re-activate the channel */
- USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
- USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ tmpreg = USBx_HC(chnum)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(chnum)->HCCHAR = tmpreg;
}
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
@@ -899,10 +908,11 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
{
- /* re-activate the channel */
- USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
- USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
-
+ /* re-activate the channel */
+ tmpreg = USBx_HC(chnum)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(chnum)->HCCHAR = tmpreg;
}
hhcd->hc[chnum].state = HC_NAK;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
@@ -910,7 +920,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
}
/**
- * @brief This function handles Host Channel OUT interrupt requests.
+ * @brief Handle Host Channel OUT interrupt requests.
* @param hhcd: HCD handle
* @param chnum: Channel number.
* This parameter can be a value from 1 to 15
@@ -919,6 +929,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ uint32_t tmpreg = 0;
if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
{
@@ -1042,8 +1053,10 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
}
/* re-activate the channel */
- USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
- USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ tmpreg = USBx_HC(chnum)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(chnum)->HCCHAR = tmpreg;
}
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
@@ -1052,7 +1065,7 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
}
/**
- * @brief This function handles Rx Queue Level interrupt requests.
+ * @brief Handle Rx Queue Level interrupt requests.
* @param hhcd: HCD handle
* @retval None
*/
@@ -1063,6 +1076,7 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
uint32_t pktsts;
uint32_t pktcnt;
uint32_t temp = 0;
+ uint32_t tmpreg = 0;
temp = hhcd->Instance->GRXSTSP;
channelnum = temp & USB_OTG_GRXSTSP_EPNUM;
@@ -1085,8 +1099,10 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)
{
/* re-activate the channel when more packets are expected */
- USBx_HC(channelnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
- USBx_HC(channelnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ tmpreg = USBx_HC(channelnum)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(channelnum)->HCCHAR = tmpreg;
hhcd->hc[channelnum].toggle_in ^= 1;
}
}
@@ -1102,7 +1118,7 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
}
/**
- * @brief This function handles Host Port interrupt requests.
+ * @brief Handle Host Port interrupt requests.
* @param hhcd: HCD handle
* @retval None
*/
@@ -1185,7 +1201,8 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
/**
* @}
*/
-
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
#endif /* HAL_HCD_MODULE_ENABLED */
/**
* @}
diff --git a/f4/src/stm32f4xx_hal_i2c.c b/f4/src/stm32f4xx_hal_i2c.c
index eb1eeae..4de074c 100755
--- a/f4/src/stm32f4xx_hal_i2c.c
+++ b/f4/src/stm32f4xx_hal_i2c.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2c.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
@@ -153,7 +153,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -201,6 +201,7 @@
*/
#define I2C_TIMEOUT_FLAG ((uint32_t)35) /* 35 ms */
#define I2C_TIMEOUT_ADDR_SLAVE ((uint32_t)10000) /* 10 s */
+#define I2C_TIMEOUT_BUSY_FLAG ((uint32_t)10000) /* 10 s */
/**
* @}
*/
@@ -309,6 +310,8 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
if(hi2c->State == HAL_I2C_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hi2c->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_I2C_MspInit(hi2c);
}
@@ -500,13 +503,17 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -560,12 +567,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
/* Generate Stop */
hi2c->Instance->CR1 |= I2C_CR1_STOP;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
@@ -598,13 +599,17 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
-
+
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -749,15 +754,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
}
}
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
@@ -789,13 +785,17 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -857,12 +857,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
/* Disable Address Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
@@ -894,13 +888,17 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -949,12 +947,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
/* Disable Address Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
@@ -986,13 +978,17 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1057,13 +1053,17 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1155,13 +1155,17 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1208,13 +1212,17 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1262,13 +1270,17 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1338,13 +1350,17 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1424,13 +1440,17 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1509,13 +1529,17 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1582,13 +1606,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1639,12 +1667,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
/* Generate Stop */
hi2c->Instance->CR1 |= I2C_CR1_STOP;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
@@ -1682,13 +1704,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1830,15 +1856,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
}
}
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
@@ -1874,13 +1891,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -1947,13 +1968,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2050,13 +2075,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2128,13 +2157,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2213,13 +2246,17 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2268,7 +2305,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -2289,10 +2326,11 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
{
return HAL_TIMEOUT;
}
+
}
}while(I2C_Trials++ < Trials);
@@ -2665,12 +2703,6 @@ static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
/* Generate Stop */
hi2c->Instance->CR1 |= I2C_CR1_STOP;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
{
hi2c->State = HAL_I2C_STATE_READY;
@@ -2718,15 +2750,6 @@ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
hi2c->XferCount--;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
@@ -2776,15 +2799,6 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
/* Disable EVT and ERR interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
@@ -2906,12 +2920,6 @@ static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
/* Disable Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
HAL_I2C_SlaveRxCpltCallback(hi2c);
@@ -2935,12 +2943,6 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
/* Disable Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
HAL_I2C_SlaveTxCpltCallback(hi2c);
@@ -3301,12 +3303,6 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
hi2c->XferCount = 0;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Check if Errors has been detected during transfer */
@@ -3346,12 +3342,6 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
hi2c->XferCount = 0;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Check if Errors has been detected during transfer */
@@ -3374,26 +3364,20 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
{
I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
/* Generate Stop */
hi2c->Instance->CR1 |= I2C_CR1_STOP;
/* Disable Last DMA */
hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
/* Disable DMA Request */
hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
hi2c->XferCount = 0;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Check if Errors has been detected during transfer */
@@ -3433,12 +3417,6 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
hi2c->XferCount = 0;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Check if Errors has been detected during transfer */
@@ -3475,12 +3453,6 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
hi2c->XferCount = 0;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Check if Errors has been detected during transfer */
@@ -3503,26 +3475,20 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
{
I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
/* Generate Stop */
hi2c->Instance->CR1 |= I2C_CR1_STOP;
/* Disable Last DMA */
hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
/* Disable DMA Request */
hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
hi2c->XferCount = 0;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
-
hi2c->State = HAL_I2C_STATE_READY;
/* Check if Errors has been detected during transfer */
diff --git a/f4/src/stm32f4xx_hal_i2c_ex.c b/f4/src/stm32f4xx_hal_i2c_ex.c
index cdda3be..40f73be 100755
--- a/f4/src/stm32f4xx_hal_i2c_ex.c
+++ b/f4/src/stm32f4xx_hal_i2c_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2c_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief I2C Extension HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C extension peripheral:
@@ -30,7 +30,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -71,8 +71,9 @@
#ifdef HAL_I2C_MODULE_ENABLED
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -190,7 +191,8 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
/**
* @}
*/
-#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC || STM32F401xE */
+#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\
+ STM32F401xE || STM32F446xx || STM32F469xx || STM32F479xx */
#endif /* HAL_I2C_MODULE_ENABLED */
/**
diff --git a/f4/src/stm32f4xx_hal_i2s.c b/f4/src/stm32f4xx_hal_i2s.c
index d518184..7147d99 100755
--- a/f4/src/stm32f4xx_hal_i2s.c
+++ b/f4/src/stm32f4xx_hal_i2s.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2s.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
@@ -109,7 +109,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -158,8 +158,7 @@
/** @addtogroup I2S_Private_Functions
* @{
*/
-static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
-static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
+
/**
* @}
*/
@@ -190,7 +189,6 @@ static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
(++) MCLK Output
(++) Audio frequency
(++) Polarity
- (++) Full duplex mode
(+) Call the function HAL_I2S_DeInit() to restore the default configuration
of the selected I2Sx peripheral.
@@ -205,7 +203,7 @@ static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
* the configuration information for I2S module
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
+__weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
{
uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
uint32_t tmp = 0, i2sclk = 0;
@@ -225,10 +223,11 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
- assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
if(hi2s->State == HAL_I2S_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hi2s->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2S_MspInit(hi2s);
}
@@ -259,47 +258,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
/* Get I2S source Clock frequency ****************************************/
/* If an external I2S clock has to be used, the specific define should be set
in the project configuration or in the stm32f4xx_conf.h file */
- if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
- {
- /* Set external clock as I2S clock source */
- if((RCC->CFGR & RCC_CFGR_I2SSRC) == 0)
- {
- RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
- }
-
- /* Set the I2S clock to the external clock value */
- i2sclk = EXTERNAL_CLOCK_VALUE;
- }
- else
- {
- /* Check if PLLI2S is enabled or Not */
- if((RCC->CR & RCC_CR_PLLI2SON) != RCC_CR_PLLI2SON)
- {
- hi2s->State= HAL_I2S_STATE_READY;
-
- return HAL_ERROR;
- }
-
- /* Set PLLI2S as I2S clock source */
- if((RCC->CFGR & RCC_CFGR_I2SSRC) != 0)
- {
- RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;
- }
-
- /* Get the PLLM value */
- if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
- {
- /* Get the I2S source clock value */
- i2sclk = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
- }
- else
- {
- /* Get the I2S source clock value */
- i2sclk = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
- }
- i2sclk *= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6));
- i2sclk /= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28));
- }
+ i2sclk = I2S_GetInputClock(hi2s);
/* Compute the Real divider depending on the MCLK output state, with a floating point */
if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
@@ -340,40 +299,21 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
/* Configure the I2S with the I2S_InitStruct values */
tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
+#if defined(SPI_I2SCFGR_ASTRTEN)
+ if (hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT)
+ {
/* Write to SPIx I2SCFGR */
- hi2s->Instance->I2SCFGR = tmpreg;
-
- /* Configure the I2S extended if the full duplex mode is enabled */
- if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
- {
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
- SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
- SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
- I2SxEXT(hi2s->Instance)->I2SPR = 2;
-
- /* Get the I2SCFGR register value */
- tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
-
- /* Get the mode to be configured for the extended I2S */
- if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
- {
- tmp = I2S_MODE_SLAVE_RX;
- }
- else
- {
- if((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
- {
- tmp = I2S_MODE_SLAVE_TX;
- }
- }
-
- /* Configure the I2S Slave with the I2S Master parameter values */
- tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | tmp | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
-
- /* Write to SPIx I2SCFGR */
- I2SxEXT(hi2s->Instance)->I2SCFGR = tmpreg;
+ hi2s->Instance->I2SCFGR = tmpreg | SPI_I2SCFGR_ASTRTEN;
+ }
+ else
+ {
+ /* Write to SPIx I2SCFGR */
+ hi2s->Instance->I2SCFGR = tmpreg;
}
+#else
+ /* Write to SPIx I2SCFGR */
+ hi2s->Instance->I2SCFGR = tmpreg;
+#endif
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->State= HAL_I2S_STATE_READY;
@@ -541,12 +481,15 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
return HAL_TIMEOUT;
}
}
- /* Wait until Busy flag is reset */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
+ /* Check if Slave mode is selected */
+ if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
{
- return HAL_TIMEOUT;
+ /* Wait until Busy flag is reset */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
}
-
hi2s->State = HAL_I2S_STATE_READY;
/* Process Unlocked */
@@ -963,7 +906,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
* the configuration information for I2S module
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
+__weak HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
{
/* Process Locked */
__HAL_LOCK(hi2s);
@@ -984,15 +927,11 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
{
/* Disable the I2S DMA Tx request */
hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
- /* Disable the I2SEx Rx DMA Request */
- I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
}
else
{
/* Disable the I2S DMA Rx request */
hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
- /* Disable the I2SEx Tx DMA Request */
- I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
}
}
@@ -1008,7 +947,7 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
* the configuration information for I2S module
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
+__weak HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
{
/* Process Locked */
__HAL_LOCK(hi2s);
@@ -1029,15 +968,11 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
{
/* Enable the I2S DMA Tx request */
hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
- /* Disable the I2SEx Rx DMA Request */
- I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
}
else
{
/* Enable the I2S DMA Rx request */
hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
- /* Enable the I2SEx Tx DMA Request */
- I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
}
}
@@ -1060,7 +995,7 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
* the configuration information for I2S module
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
+__weak HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
{
/* Process Locked */
__HAL_LOCK(hi2s);
@@ -1068,14 +1003,7 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
/* Disable the I2S Tx/Rx DMA requests */
hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
-
- if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
- {
- /* Disable the I2S extended Tx/Rx DMA requests */
- I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
- I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
- }
-
+
/* Abort the I2S DMA Stream tx */
if(hi2s->hdmatx != NULL)
{
@@ -1090,12 +1018,6 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
/* Disable I2S peripheral */
__HAL_I2S_DISABLE(hi2s);
- if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
- {
- /* Disable the I2Sext peripheral */
- I2SxEXT(hi2s->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
- }
-
hi2s->State = HAL_I2S_STATE_READY;
/* Process Unlocked */
@@ -1110,13 +1032,10 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
* the configuration information for I2S module
* @retval None
*/
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
{
uint32_t tmp1 = 0, tmp2 = 0;
- __IO uint16_t tmpreg1 = 0;
-
- if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE)
- {
+
if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
@@ -1145,64 +1064,6 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
if((tmp1 != RESET) && (tmp2 != RESET))
{
I2S_Transmit_IT(hi2s);
- }
-
- tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
- tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
- /* I2S Underrun error interrupt occurred --------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
- {
- __HAL_I2S_CLEAR_UDRFLAG(hi2s);
- hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
- }
- }
- }
- else
- {
- tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
- if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
- {
- tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE;
- tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_RXNE;
- /* I2Sext in mode Receiver ---------------------------------------------*/
- if((tmp1 == SPI_SR_RXNE) && (tmp2 == I2S_IT_RXNE))
- {
- tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
- the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
- if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
- {
- I2SEx_TransmitReceive_IT(hi2s);
- }
- }
-
- tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_OVR;
- tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
- /* I2Sext Overrun error interrupt occurred ------------------------------*/
- if((tmp1 == SPI_SR_OVR) && (tmp2 == I2S_IT_ERR))
- {
- /* Clear I2Sext OVR Flag */
- tmpreg1 = I2SxEXT(hi2s->Instance)->DR;
- tmpreg1 = I2SxEXT(hi2s->Instance)->SR;
- hi2s->ErrorCode |= HAL_I2SEX_ERROR_OVR;
- }
-
- tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
- tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
- /* I2S in mode Transmitter -----------------------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
- {
- tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
- the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
- if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
- {
- I2SEx_TransmitReceive_IT(hi2s);
- }
}
tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
@@ -1212,60 +1073,6 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
{
__HAL_I2S_CLEAR_UDRFLAG(hi2s);
hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
- }
- }
- /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
- else
- {
- tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
- tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
- /* I2S in mode Receiver ------------------------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
- {
- tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
- the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
- if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX))
- {
- I2SEx_TransmitReceive_IT(hi2s);
- }
- }
-
- tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
- tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
- /* I2S Overrun error interrupt occurred ---------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
- {
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
- }
-
- tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE;
- tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_TXE;
- /* I2Sext in mode Transmitter --------------------------------------------*/
- if((tmp1 == SPI_SR_TXE) && (tmp2 == I2S_IT_TXE))
- {
- tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
- the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
- if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX))
- {
- I2SEx_TransmitReceive_IT(hi2s);
- }
- }
-
- tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_UDR;
- tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
- /* I2Sext Underrun error interrupt occurred -----------------------------*/
- if((tmp1 == SPI_SR_UDR) && (tmp2 == I2S_IT_ERR))
- {
- /* Clear I2Sext UDR Flag */
- tmpreg1 = I2SxEXT(hi2s->Instance)->SR;
- hi2s->ErrorCode |= HAL_I2SEX_ERROR_UDR;
- UNUSED(tmpreg1);
- }
}
}
@@ -1386,44 +1193,6 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
* @}
*/
-/**
- * @brief DMA I2S transmit process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
- {
- hi2s->TxXferCount = 0;
-
- /* Disable Tx DMA Request */
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-
- if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
- {
- /* Disable Rx DMA Request for the slave*/
- I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
- }
-
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
- {
- if(hi2s->RxXferCount == 0)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- }
- }
- else
- {
- hi2s->State = HAL_I2S_STATE_READY;
- }
- }
- HAL_I2S_TxCpltCallback(hi2s);
-}
-
/**
* @brief DMA I2S transmit process half complete callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
@@ -1437,43 +1206,6 @@ void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
HAL_I2S_TxHalfCpltCallback(hi2s);
}
-/**
- * @brief DMA I2S receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
- {
- /* Disable Rx DMA Request */
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-
- if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
- {
- /* Disable Tx DMA Request for the slave*/
- I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
- }
-
- hi2s->RxXferCount = 0;
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
- {
- if(hi2s->TxXferCount == 0)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- }
- }
- else
- {
- hi2s->State = HAL_I2S_STATE_READY;
- }
- }
- HAL_I2S_RxCpltCallback(hi2s);
-}
-
/**
* @brief DMA I2S receive process half complete callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
@@ -1512,7 +1244,7 @@ void I2S_DMAError(DMA_HandleTypeDef *hdma)
* the configuration information for I2S module
* @retval HAL status
*/
-static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
+HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
{
if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
{
@@ -1556,7 +1288,7 @@ static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
* the configuration information for I2S module
* @retval HAL status
*/
-static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
+HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
{
if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
diff --git a/f4/src/stm32f4xx_hal_i2s_ex.c b/f4/src/stm32f4xx_hal_i2s_ex.c
index 169d384..9029978 100755
--- a/f4/src/stm32f4xx_hal_i2s_ex.c
+++ b/f4/src/stm32f4xx_hal_i2s_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2s_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2S extension peripheral:
@@ -74,7 +74,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -114,7 +114,6 @@
*/
#ifdef HAL_I2S_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -171,6 +170,164 @@
@endverbatim
* @{
*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
+/**
+ * @brief Initializes the I2S according to the specified parameters
+ * in the I2S_InitTypeDef and create the associated handle.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
+{
+ uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+ uint32_t tmp = 0, i2sclk = 0;
+
+ /* Check the I2S handle allocation */
+ if(hi2s == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_MODE(hi2s->Init.Mode));
+ assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
+ assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
+ assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
+ assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
+ assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
+ assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
+
+ if(hi2s->State == HAL_I2S_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hi2s->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+ HAL_I2S_MspInit(hi2s);
+ }
+
+ hi2s->State = HAL_I2S_STATE_BUSY;
+
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
+ hi2s->Instance->I2SPR = 0x0002;
+
+ /* Get the I2SCFGR register value */
+ tmpreg = hi2s->Instance->I2SCFGR;
+
+ /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
+ /* If the requested audio frequency is not the default, compute the prescaler */
+ if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
+ {
+ /* Check the frame length (For the Prescaler computing) *******************/
+ if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2;
+ }
+
+ /* Get I2S source Clock frequency ****************************************/
+ i2sclk = I2S_GetInputClock(hi2s);
+
+ /* Compute the Real divider depending on the MCLK output state, with a floating point */
+ if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
+ {
+ /* MCLK output is enabled */
+ tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
+ }
+
+ /* Remove the flatting point */
+ tmp = tmp / 10;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint32_t)(tmp & (uint32_t)1);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (uint32_t) (i2sodd << 8);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if((i2sdiv < 2) || (i2sdiv > 0xFF))
+ {
+ /* Set the default values */
+ i2sdiv = 2;
+ i2sodd = 0;
+ }
+
+ /* Write to SPIx I2SPR register the computed value */
+ hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
+
+ /* Configure the I2S with the I2S_InitStruct values */
+ tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
+
+#if defined(SPI_I2SCFGR_ASTRTEN)
+ if (hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT)
+ {
+ /* Write to SPIx I2SCFGR */
+ hi2s->Instance->I2SCFGR = tmpreg | SPI_I2SCFGR_ASTRTEN;
+ }
+ else
+ {
+ /* Write to SPIx I2SCFGR */
+ hi2s->Instance->I2SCFGR = tmpreg;
+ }
+#else
+ /* Write to SPIx I2SCFGR */
+ hi2s->Instance->I2SCFGR = tmpreg;
+#endif
+
+ /* Configure the I2S extended if the full duplex mode is enabled */
+ assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
+ if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
+ {
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
+ I2SxEXT(hi2s->Instance)->I2SPR = 2;
+
+ /* Get the I2SCFGR register value */
+ tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
+
+ /* Get the mode to be configured for the extended I2S */
+ if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
+ {
+ tmp = I2S_MODE_SLAVE_RX;
+ }
+ else
+ {
+ if((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
+ {
+ tmp = I2S_MODE_SLAVE_TX;
+ }
+ }
+
+ /* Configure the I2S Slave with the I2S Master parameter values */
+ tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | tmp | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
+
+ /* Write to SPIx I2SCFGR */
+ I2SxEXT(hi2s->Instance)->I2SCFGR = tmpreg;
+ }
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ return HAL_OK;
+}
/**
* @brief Full-Duplex Transmit/Receive data in blocking mode.
@@ -625,9 +782,328 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_
}
/**
- * @}
+ * @brief Pauses the audio stream playing from the Media.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Disable the I2S DMA Tx request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Disable the I2S DMA Rx request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
+ {
+ /* Disable the I2S DMA Tx request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ /* Disable the I2SEx Rx DMA Request */
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ }
+ else
+ {
+ /* Disable the I2S DMA Rx request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ /* Disable the I2SEx Tx DMA Request */
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio stream playing from the Media.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Enable the I2S DMA Tx request */
+ hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Enable the I2S DMA Rx request */
+ hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
+ {
+ /* Enable the I2S DMA Tx request */
+ hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+ /* Disable the I2SEx Rx DMA Request */
+ I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
+ }
+ else
+ {
+ /* Enable the I2S DMA Rx request */
+ hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+ /* Enable the I2SEx Tx DMA Request */
+ I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
+ }
+ }
+
+ /* If the I2S peripheral is still not enabled, enable it */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio stream playing from the Media.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
*/
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ /* Disable the I2S Tx/Rx DMA requests */
+ hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
+ hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
+
+ if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
+ {
+ /* Disable the I2S extended Tx/Rx DMA requests */
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ }
+
+ /* Abort the I2S DMA Stream tx */
+ if(hi2s->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hi2s->hdmatx);
+ }
+ /* Abort the I2S DMA Stream rx */
+ if(hi2s->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hi2s->hdmarx);
+ }
+
+ /* Disable I2S peripheral */
+ __HAL_I2S_DISABLE(hi2s);
+
+ if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
+ {
+ /* Disable the I2Sext peripheral */
+ I2SxEXT(hi2s->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
+ }
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2S interrupt request.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
+{
+ uint32_t tmp1 = 0, tmp2 = 0;
+ __IO uint32_t tmpreg1 = 0;
+ if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE)
+ {
+ if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
+ /* I2S in mode Receiver ------------------------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ I2S_Receive_IT(hi2s);
+ }
+
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
+ /* I2S Overrun error interrupt occurred ---------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ }
+ }
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
+ /* I2S in mode Tramitter -----------------------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ I2S_Transmit_IT(hi2s);
+ }
+
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
+ /* I2S Underrun error interrupt occurred --------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ }
+ }
+ }
+ else
+ {
+ tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+ if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
+ {
+ tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE;
+ tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_RXNE;
+ /* I2Sext in mode Receiver ---------------------------------------------*/
+ if((tmp1 == SPI_SR_RXNE) && (tmp2 == I2S_IT_RXNE))
+ {
+ tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
+ the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
+ if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
+ {
+ I2SEx_TransmitReceive_IT(hi2s);
+ }
+ }
+
+ tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_OVR;
+ tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
+ /* I2Sext Overrun error interrupt occurred -----------------------------*/
+ if((tmp1 == SPI_SR_OVR) && (tmp2 == I2S_IT_ERR))
+ {
+ /* Clear I2Sext OVR Flag */
+ tmpreg1 = I2SxEXT(hi2s->Instance)->DR;
+ tmpreg1 = I2SxEXT(hi2s->Instance)->SR;
+ hi2s->ErrorCode |= HAL_I2SEX_ERROR_OVR;
+ UNUSED(tmpreg1);
+ }
+
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
+ /* I2S in mode Tramitter -----------------------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
+ the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
+ if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
+ {
+ I2SEx_TransmitReceive_IT(hi2s);
+ }
+ }
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
+ /* I2S Underrun error interrupt occurred -------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ }
+ }
+ /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
+ else
+ {
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
+ /* I2S in mode Receiver ------------------------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
+ the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
+ if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX))
+ {
+ I2SEx_TransmitReceive_IT(hi2s);
+ }
+ }
+
+ tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
+ tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
+ /* I2S Overrun error interrupt occurred --------------------------------*/
+ if((tmp1 != RESET) && (tmp2 != RESET))
+ {
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ }
+
+ tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE;
+ tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_TXE;
+ /* I2Sext in mode Tramitter --------------------------------------------*/
+ if((tmp1 == SPI_SR_TXE) && (tmp2 == I2S_IT_TXE))
+ {
+ tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
+ the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
+ if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX))
+ {
+ I2SEx_TransmitReceive_IT(hi2s);
+ }
+ }
+
+ tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_UDR;
+ tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
+ /* I2Sext Underrun error interrupt occurred ----------------------------*/
+ if((tmp1 == SPI_SR_UDR) && (tmp2 == I2S_IT_ERR))
+ {
+ /* Clear I2Sext UDR Flag */
+ tmpreg1 = I2SxEXT(hi2s->Instance)->SR;
+ hi2s->ErrorCode |= HAL_I2SEX_ERROR_UDR;
+ UNUSED(tmpreg1);
+ }
+ }
+ }
+
+ /* Call the Error call Back in case of Errors */
+ if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
+ {
+ /* Set the I2S state ready to be able to start again the process */
+ hi2s->State= HAL_I2S_STATE_READY;
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+}
+
+/**
+ * @}
+ */
/**
* @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
@@ -742,11 +1218,258 @@ HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s)
return HAL_BUSY;
}
}
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx ||\
+ STM32F411xx || STM32F469xx || STM32F479xx */
+/**
+ * @brief DMA I2S transmit process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ {
+ hi2s->TxXferCount = 0;
+
+ /* Disable Tx DMA Request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
+ if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
+ {
+ /* Disable Rx DMA Request for the slave*/
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ }
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx || STM32F411xx ||\
+ STM32F469xx || STM32F479xx */
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ if(hi2s->RxXferCount == 0)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ }
+ else
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ }
+ HAL_I2S_TxCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ {
+ /* Disable Rx DMA Request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
+ if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
+ {
+ /* Disable Tx DMA Request for the slave*/
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ }
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx || STM32F411xx ||\
+ STM32F469xx || STM32F479xx */
+ hi2s->RxXferCount = 0;
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ if(hi2s->TxXferCount == 0)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ }
+ else
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ }
+ HAL_I2S_RxCpltCallback(hi2s);
+}
+/**
+ * @brief Get I2S clock Input based on Source clock selection in RCC
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval I2S Clock Input
+ */
+uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s)
+{
+ /* This variable used to store the VCO Input (value in Hz) */
+ uint32_t vcoinput = 0;
+ /* This variable used to store the VCO Output (value in Hz) */
+ uint32_t vcooutput = 0;
+ /* This variable used to store the I2S_CK_x (value in Hz) */
+ uint32_t i2ssourceclock = 0;
+
+ /* Configure 12S Clock based on I2S source clock selection */
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx)
+ switch(hi2s->Init.ClockSource)
+ {
+ case I2S_CLOCK_EXTERNAL :
+ {
+ /* Set the I2S clock to the external clock value */
+ i2ssourceclock = EXTERNAL_CLOCK_VALUE;
+ break;
+ }
+#if defined(STM32F446xx)
+ case I2S_CLOCK_PLL :
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6)));
+ /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+ i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28)));
+ break;
+ }
+#endif /* STM32F446xx */
+ case I2S_CLOCK_PLLR :
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLL_VCO Input = PLL_SOURCE/PLLM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+
+ /* PLL_VCO Output = PLL_VCO Input * PLLN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6) & (RCC_PLLCFGR_PLLN >> 6)));
+ /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+ i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28) & (RCC_PLLCFGR_PLLR >> 28)));
+ break;
+ }
+ case I2S_CLOCK_PLLSRC :
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLL_VCO Input = PLL_SOURCE/PLLM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ i2ssourceclock = (uint32_t)(HSE_VALUE);
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ i2ssourceclock = (uint32_t)(HSI_VALUE);
+ }
+ break;
+ }
+ default :
+ {
+ break;
+ }
+ }
+#endif /* STM32F410xx || STM32F446xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F469xx) || defined(STM32F479xx)
+
+ /* If an external I2S clock has to be used, the specific define should be set
+ in the project configuration or in the stm32f4xx_conf.h file */
+ if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
+ {
+ /* Set the I2S clock to the external clock value */
+ i2ssourceclock = EXTERNAL_CLOCK_VALUE;
+ }
+ else
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6)));
+ /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+ i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28)));
+ }
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F411xE)
+
+ /* If an external I2S clock has to be used, the specific define should be set
+ in the project configuration or in the stm32f4xx_conf.h file */
+ if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
+ {
+ /* Set the I2S clock to the external clock value */
+ i2ssourceclock = EXTERNAL_CLOCK_VALUE;
+ }
+ else
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6)));
+ /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+ i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28)));
+ }
+#endif /* STM32F411xE */
+
+ /* the return result is the value of SAI clock */
+ return i2ssourceclock;
+}
/**
* @}
*/
+/**
+ * @}
+ */
+
#endif /* HAL_I2S_MODULE_ENABLED */
/**
* @}
diff --git a/f4/src/stm32f4xx_hal_irda.c b/f4/src/stm32f4xx_hal_irda.c
index 14ab83d..a636486 100755
--- a/f4/src/stm32f4xx_hal_irda.c
+++ b/f4/src/stm32f4xx_hal_irda.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_irda.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA SIR ENDEC block (IrDA):
@@ -97,7 +97,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -225,6 +225,8 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
if(hirda->State == HAL_IRDA_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hirda->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_IRDA_MspInit(hirda);
}
diff --git a/f4/src/stm32f4xx_hal_iwdg.c b/f4/src/stm32f4xx_hal_iwdg.c
index cec0307..d37c6ba 100755
--- a/f4/src/stm32f4xx_hal_iwdg.c
+++ b/f4/src/stm32f4xx_hal_iwdg.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_iwdg.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
@@ -82,7 +82,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -180,6 +180,8 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
if(hiwdg->State == HAL_IWDG_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hiwdg->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_IWDG_MspInit(hiwdg);
}
diff --git a/f4/src/stm32f4xx_hal_lptim.c b/f4/src/stm32f4xx_hal_lptim.c
new file mode 100644
index 0000000..36b598f
--- /dev/null
+++ b/f4/src/stm32f4xx_hal_lptim.c
@@ -0,0 +1,1655 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_lptim.c
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief LPTIM HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Low Power Timer (LPTIM) peripheral:
+ * + Initialization and de-initialization functions.
+ * + Start/Stop operation functions in polling mode.
+ * + Start/Stop operation functions in interrupt mode.
+ * + Reading operation functions.
+ * + Peripheral State functions.
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LPTIM HAL driver can be used as follows:
+
+ (#)Initialize the LPTIM low level resources by implementing the
+ HAL_LPTIM_MspInit():
+ (##) Enable the LPTIM interface clock using __LPTIMx_CLK_ENABLE().
+ (##) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
+ (+) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
+ (+) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
+ (+) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
+
+ (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
+ configures mainly:
+ (##) The instance: LPTIM1.
+ (##) Clock: the counter clock.
+ - Source : it can be either the ULPTIM input (IN1) or one of
+ the internal clock; (APB, LSE, LSI or MSI).
+ - Prescaler: select the clock divider.
+ (##) UltraLowPowerClock : To be used only if the ULPTIM is selected
+ as counter clock source.
+ - Polarity: polarity of the active edge for the counter unit
+ if the ULPTIM input is selected.
+ - SampleTime: clock sampling time to configure the clock glitch
+ filter.
+ (##) Trigger: How the counter start.
+ - Source: trigger can be software or one of the hardware triggers.
+ - ActiveEdge : only for hardware trigger.
+ - SampleTime : trigger sampling time to configure the trigger
+ glitch filter.
+ (##) OutputPolarity : 2 opposite polarities are possibles.
+ (##) UpdateMode: specifies whether the update of the autoreload and
+ the compare values is done immediately or after the end of current
+ period.
+
+ (#)Six modes are available:
+
+ (##) PWM Mode: To generate a PWM signal with specified period and pulse,
+ call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
+ mode.
+
+ (##) One Pulse Mode: To generate pulse with specified width in response
+ to a stimulus, call HAL_LPTIM_OnePulse_Start() or
+ HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
+
+ (##) Set once Mode: In this mode, the output changes the level (from
+ low level to high level if the output polarity is configured high, else
+ the opposite) when a compare match occurs. To start this mode, call
+ HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
+ interruption mode.
+
+ (##) Encoder Mode: To use the encoder interface call
+ HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
+ interruption mode.
+
+ (##) Time out Mode: an active edge on one selected trigger input rests
+ the counter. The first trigger event will start the timer, any
+ successive trigger event will reset the counter and the timer will
+ restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
+ HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
+
+ (##) Counter Mode: counter can be used to count external events on
+ the LPTIM Input1 or it can be used to count internal clock cycles.
+ To start this mode, call HAL_LPTIM_Counter_Start() or
+ HAL_LPTIM_Counter_Start_IT() for interruption mode.
+
+ (#) User can stop any process by calling the corresponding API:
+ HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
+ already started in interruption mode.
+
+ (#)Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup LPTIM LPTIM
+ * @brief LPTIM HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/* Private types -------------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Types LPTIM Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Defines LPTIM Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup LPTIM_Private_Variables LPTIM Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup LPTIM_Private_Constants LPTIM Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup LPTIM_Private_Macros LPTIM Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup LPTIM_Private_Functions_Prototypes LPTIM Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup LPTIM_Private_Functions LPTIM Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
+ * @{
+ */
+
+/** @defgroup LPTIM_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the LPTIM according to the specified parameters in the
+ LPTIM_InitTypeDef and creates the associated handle.
+ (+) DeInitialize the LPTIM peripheral.
+ (+) Initialize the LPTIM MSP.
+ (+) DeInitialize LPTIM MSP.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the LPTIM according to the specified parameters in the
+ * LPTIM_InitTypeDef and creates the associated handle.
+ * @param hlptim: LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
+{
+ uint32_t tmpcfgr = 0;
+
+ /* Check the LPTIM handle allocation */
+ if(hlptim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
+ assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
+ if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
+ {
+ assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+ assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
+ }
+ assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
+ assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
+ }
+ assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
+ assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
+ assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
+
+ if(hlptim->State == HAL_LPTIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hlptim->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_LPTIM_MspInit(hlptim);
+ }
+
+ /* Change the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Get the LPTIMx CFGR value */
+ tmpcfgr = hlptim->Instance->CFGR;
+
+ if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
+ {
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
+ }
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
+ }
+
+ /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
+ LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE ));
+
+ /* Set initialization parameters */
+ tmpcfgr |= (hlptim->Init.Clock.Source |
+ hlptim->Init.Clock.Prescaler |
+ hlptim->Init.OutputPolarity |
+ hlptim->Init.UpdateMode |
+ hlptim->Init.CounterSource);
+
+ if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
+ {
+ tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
+ hlptim->Init.UltraLowPowerClock.SampleTime);
+ }
+
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Enable External trigger and set the trigger source */
+ tmpcfgr |= (hlptim->Init.Trigger.Source |
+ hlptim->Init.Trigger.ActiveEdge |
+ hlptim->Init.Trigger.SampleTime);
+ }
+
+ /* Write to LPTIMx CFGR */
+ hlptim->Instance->CFGR = tmpcfgr;
+
+ /* Change the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the LPTIM peripheral.
+ * @param hlptim: LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the LPTIM handle allocation */
+ if(hlptim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Change the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the LPTIM Peripheral Clock */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ HAL_LPTIM_MspDeInit(hlptim);
+
+ /* Change the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hlptim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the LPTIM MSP.
+ * @param hlptim: LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_LPTIM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes LPTIM MSP.
+ * @param hlptim: LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_LPTIM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Group2 LPTIM Start-Stop operation functions
+ * @brief Start-Stop operation functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### LPTIM Start Stop operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start the PWM mode.
+ (+) Stop the PWM mode.
+ (+) Start the One pulse mode.
+ (+) Stop the One pulse mode.
+ (+) Start the Set once mode.
+ (+) Stop the Set once mode.
+ (+) Start the Encoder mode.
+ (+) Stop the Encoder mode.
+ (+) Start the Timeout mode.
+ (+) Stop the Timeout mode.
+ (+) Start the Counter mode.
+ (+) Stop the Counter mode.
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the LPTIM PWM generation.
+ * @param hlptim : LPTIM handle
+ * @param Period : Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @param Pulse : Specifies the compare value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(IS_LPTIM_PULSE(Pulse));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Reset WAVE bit to set PWM mode */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the LPTIM PWM generation.
+ * @param hlptim : LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the LPTIM PWM generation in interrupt mode.
+ * @param hlptim : LPTIM handle
+ * @param Period : Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF
+ * @param Pulse : Specifies the compare value.
+ * This parameter must be a value between 0x0000 and 0xFFFF
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(IS_LPTIM_PULSE(Pulse));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Reset WAVE bit to set PWM mode */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+
+ /* Enable Autoreload write complete interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
+
+ /* Enable Compare write complete interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
+
+ /* Enable Autoreload match interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
+
+ /* Enable Compare match interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
+
+ /* If external trigger source is used, then enable external trigger interrupt */
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Enable external trigger interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the LPTIM PWM generation in interrupt mode.
+ * @param hlptim : LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Disable Autoreload write complete interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
+
+ /* Disable Compare write complete interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
+
+ /* Disable Autoreload match interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
+
+ /* Disable Compare match interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
+
+ /* If external trigger source is used, then disable external trigger interrupt */
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Disable external trigger interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+ }
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the LPTIM One pulse generation.
+ * @param hlptim : LPTIM handle
+ * @param Period : Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @param Pulse : Specifies the compare value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(IS_LPTIM_PULSE(Pulse));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Reset WAVE bit to set one pulse mode */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_SINGLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the LPTIM One pulse generation.
+ * @param hlptim : LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the LPTIM One pulse generation in interrupt mode.
+ * @param hlptim : LPTIM handle
+ * @param Period : Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @param Pulse : Specifies the compare value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(IS_LPTIM_PULSE(Pulse));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Reset WAVE bit to set one pulse mode */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+
+ /* Enable Autoreload write complete interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
+
+ /* Enable Compare write complete interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
+
+ /* Enable Autoreload match interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
+
+ /* Enable Compare match interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
+
+ /* If external trigger source is used, then enable external trigger interrupt */
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Enable external trigger interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_SINGLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the LPTIM One pulse generation in interrupt mode.
+ * @param hlptim : LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Disable Autoreload write complete interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
+
+ /* Disable Compare write complete interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
+
+ /* Disable Autoreload match interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
+
+ /* Disable Compare match interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
+
+ /* If external trigger source is used, then disable external trigger interrupt */
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Disable external trigger interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+ }
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the LPTIM in Set once mode.
+ * @param hlptim : LPTIM handle
+ * @param Period : Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @param Pulse : Specifies the compare value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(IS_LPTIM_PULSE(Pulse));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Set WAVE bit to enable the set once mode */
+ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Start timer in single mode */
+ __HAL_LPTIM_START_SINGLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the LPTIM Set once mode.
+ * @param hlptim : LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the LPTIM Set once mode in interrupt mode.
+ * @param hlptim : LPTIM handle
+ * @param Period : Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @param Pulse : Specifies the compare value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(IS_LPTIM_PULSE(Pulse));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Set WAVE bit to enable the set once mode */
+ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
+
+ /* Enable Autoreload write complete interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
+
+ /* Enable Compare write complete interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
+
+ /* Enable Autoreload match interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
+
+ /* Enable Compare match interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
+
+ /* If external trigger source is used, then enable external trigger interrupt */
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Enable external trigger interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Start timer in single mode */
+ __HAL_LPTIM_START_SINGLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the LPTIM Set once mode in interrupt mode.
+ * @param hlptim : LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Disable Autoreload write complete interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
+
+ /* Disable Compare write complete interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
+
+ /* Disable Autoreload match interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
+
+ /* Disable Compare match interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
+
+ /* If external trigger source is used, then disable external trigger interrupt */
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Disable external trigger interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+ }
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the Encoder interface.
+ * @param hlptim : LPTIM handle
+ * @param Period : Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
+{
+ uint32_t tmpcfgr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
+ assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
+ assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Get the LPTIMx CFGR value */
+ tmpcfgr = hlptim->Instance->CFGR;
+
+ /* Clear CKPOL bits */
+ tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
+
+ /* Set Input polarity */
+ tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
+
+ /* Write to LPTIMx CFGR */
+ hlptim->Instance->CFGR = tmpcfgr;
+
+ /* Set ENC bit to enable the encoder interface */
+ hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the Encoder interface.
+ * @param hlptim : LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Reset ENC bit to disable the encoder interface */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the Encoder interface in interrupt mode.
+ * @param hlptim : LPTIM handle
+ * @param Period : Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
+{
+ uint32_t tmpcfgr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
+ assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
+ assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Configure edge sensitivity for encoder mode */
+ /* Get the LPTIMx CFGR value */
+ tmpcfgr = hlptim->Instance->CFGR;
+
+ /* Clear CKPOL bits */
+ tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
+
+ /* Set Input polarity */
+ tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
+
+ /* Write to LPTIMx CFGR */
+ hlptim->Instance->CFGR = tmpcfgr;
+
+ /* Set ENC bit to enable the encoder interface */
+ hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
+
+ /* Enable "switch to down direction" interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
+
+ /* Enable "switch to up direction" interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the Encoder interface in interrupt mode.
+ * @param hlptim : LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Reset ENC bit to disable the encoder interface */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
+
+ /* Disable "switch to down direction" interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);
+
+ /* Disable "switch to up direction" interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the Timeout function. The first trigger event will start the
+ * timer, any successive trigger event will reset the counter and
+ * the timer restarts.
+ * @param hlptim : LPTIM handle
+ * @param Period : Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @param Timeout : Specifies the TimeOut value to rest the counter.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(IS_LPTIM_PULSE(Timeout));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Set TIMOUT bit to enable the timeout function */
+ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Load the Timeout value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the Timeout function.
+ * @param hlptim : LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Reset TIMOUT bit to enable the timeout function */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the Timeout function in interrupt mode. The first trigger
+ * event will start the timer, any successive trigger event will reset
+ * the counter and the timer restarts.
+ * @param hlptim : LPTIM handle
+ * @param Period : Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @param Timeout : Specifies the TimeOut value to rest the counter.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(IS_LPTIM_PULSE(Timeout));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Set TIMOUT bit to enable the timeout function */
+ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
+
+ /* Enable Compare match interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Load the Timeout value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the Timeout function in interrupt mode.
+ * @param hlptim : LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Reset TIMOUT bit to enable the timeout function */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
+
+ /* Disable Compare match interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the Counter mode.
+ * @param hlptim : LPTIM handle
+ * @param Period : Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
+ if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ {
+ /* Check if clock is prescaled */
+ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
+ /* Set clock prescaler to 0 */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
+ }
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the Counter mode.
+ * @param hlptim : LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the Counter mode in interrupt mode.
+ * @param hlptim : LPTIM handle
+ * @param Period : Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
+ if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ {
+ /* Check if clock is prescaled */
+ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
+ /* Set clock prescaler to 0 */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
+ }
+
+ /* Enable Autoreload write complete interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
+
+ /* Enable Autoreload match interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the Counter mode in interrupt mode.
+ * @param hlptim : LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Disable Autoreload write complete interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
+
+ /* Disable Autoreload match interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Group3 LPTIM Read operation functions
+ * @brief Read operation functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### LPTIM Read operation functions #####
+ ==============================================================================
+[..] This section provides LPTIM Reading functions.
+ (+) Read the counter value.
+ (+) Read the period (Auto-reload) value.
+ (+) Read the pulse (Compare)value.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function returns the current counter value.
+ * @param hlptim: LPTIM handle
+ * @retval Counter value.
+ */
+uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ return (hlptim->Instance->CNT);
+}
+
+/**
+ * @brief This function return the current Autoreload (Period) value.
+ * @param hlptim: LPTIM handle
+ * @retval Autoreload value.
+ */
+uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ return (hlptim->Instance->ARR);
+}
+
+/**
+ * @brief This function return the current Compare (Pulse) value.
+ * @param hlptim: LPTIM handle
+ * @retval Compare value.
+ */
+uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ return (hlptim->Instance->CMP);
+}
+
+/**
+ * @}
+ */
+
+
+
+/** @defgroup LPTIM_Group4 LPTIM IRQ handler
+ * @brief LPTIM IRQ handler.
+ *
+@verbatim
+ ==============================================================================
+ ##### LPTIM IRQ handler #####
+ ==============================================================================
+[..] This section provides LPTIM IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles LPTIM interrupt request.
+ * @param hlptim: LPTIM handle
+ * @retval None
+ */
+void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Compare match interrupt */
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
+ {
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) !=RESET)
+ {
+ /* Clear Compare match flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
+ /* Compare match Callback */
+ HAL_LPTIM_CompareMatchCallback(hlptim);
+ }
+ }
+
+ /* Autoreload match interrupt */
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
+ {
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) !=RESET)
+ {
+ /* Clear Autoreload match flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
+ /* Autoreload match Callback */
+ HAL_LPTIM_AutoReloadMatchCallback(hlptim);
+ }
+ }
+
+ /* Trigger detected interrupt */
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
+ {
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) !=RESET)
+ {
+ /* Clear Trigger detected flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
+ /* Trigger detected callback */
+ HAL_LPTIM_TriggerCallback(hlptim);
+ }
+ }
+
+ /* Compare write interrupt */
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
+ {
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CMPM) !=RESET)
+ {
+ /* Clear Compare write flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+ /* Compare write Callback */
+ HAL_LPTIM_CompareWriteCallback(hlptim);
+ }
+ }
+
+ /* Autoreload write interrupt */
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
+ {
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) !=RESET)
+ {
+ /* Clear Autoreload write flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+ /* Autoreload write Callback */
+ HAL_LPTIM_AutoReloadWriteCallback(hlptim);
+ }
+ }
+
+ /* Direction counter changed from Down to Up interrupt */
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
+ {
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) !=RESET)
+ {
+ /* Clear Direction counter changed from Down to Up flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
+ /* Direction counter changed from Down to Up Callback */
+ HAL_LPTIM_DirectionUpCallback(hlptim);
+ }
+ }
+
+ /* Direction counter changed from Up to Down interrupt */
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
+ {
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) !=RESET)
+ {
+ /* Clear Direction counter changed from Up to Down flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
+ /* Direction counter changed from Up to Down Callback */
+ HAL_LPTIM_DirectionDownCallback(hlptim);
+ }
+ }
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG();
+}
+
+/**
+ * @brief Compare match callback in non blocking mode
+ * @param hlptim : LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Autoreload match callback in non blocking mode
+ * @param hlptim : LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Trigger detected callback in non blocking mode
+ * @param hlptim : LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_LPTIM_TriggerCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Compare write callback in non blocking mode
+ * @param hlptim : LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Autoreload write callback in non blocking mode
+ * @param hlptim : LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Direction counter changed from Down to Up callback in non blocking mode
+ * @param hlptim : LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Direction counter changed from Up to Down callback in non blocking mode
+ * @param hlptim : LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Group5 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the LPTIM state.
+ * @param hlptim: LPTIM handle
+ * @retval HAL state
+ */
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
+{
+ return hlptim->State;
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/src/stm32f4xx_hal_ltdc.c b/f4/src/stm32f4xx_hal_ltdc.c
index 95f6fc2..afc998f 100755
--- a/f4/src/stm32f4xx_hal_ltdc.c
+++ b/f4/src/stm32f4xx_hal_ltdc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_ltdc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief LTDC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the LTDC peripheral:
@@ -69,7 +69,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -109,7 +109,7 @@
#ifdef HAL_LTDC_MODULE_ENABLED
-#if defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -172,6 +172,8 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
if(hltdc->State == HAL_LTDC_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hltdc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_LTDC_MspInit(hltdc);
}
@@ -370,7 +372,7 @@ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
__HAL_UNLOCK(hltdc);
/* Line interrupt Callback */
- HAL_LTDC_LineEvenCallback(hltdc);
+ HAL_LTDC_LineEventCallback(hltdc);
}
}
}
@@ -394,10 +396,10 @@ __weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
* the configuration information for the LTDC.
* @retval None
*/
-__weak void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc)
+__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_LTDC_LineEvenCallback could be implemented in the user file
+ the HAL_LTDC_LineEventCallback could be implemented in the user file
*/
}
@@ -870,7 +872,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
/* Sets the Reload type */
- hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+ hltdc->Instance->SRCR = LTDC_SRCR_VBR;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1014,6 +1016,80 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Addres
return HAL_OK;
}
+/**
+ * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is
+ * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we
+ * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels
+ * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
+ * Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
+ * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param LinePitchInPixels: New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
+ * @param LayerIdx: LTDC layer index concerned by the modification of line pitch.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
+{
+ uint32_t tmp = 0;
+ uint32_t pitchUpdate = 0;
+ uint32_t pixelFormat = 0;
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* get LayerIdx used pixel format */
+ pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
+
+ if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
+ {
+ tmp = 4;
+ }
+ else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
+ {
+ tmp = 3;
+ }
+ else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
+ {
+ tmp = 2;
+ }
+ else
+ {
+ tmp = 1;
+ }
+
+ pitchUpdate = ((LinePitchInPixels * tmp) << 16);
+
+ /* Clear previously set standard pitch */
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
+
+ /* Sets the Reload type as immediate update of LTDC pitch configured above */
+ LTDC->SRCR |= LTDC_SRCR_IMR;
+
+ /* Set new line pitch value */
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
+
+ /* Sets the Reload type as immediate update of LTDC pitch configured above */
+ LTDC->SRCR |= LTDC_SRCR_IMR;
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
/**
* @brief Define the position of the line interrupt .
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
@@ -1163,7 +1239,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
/* Configures the color frame buffer pitch in byte */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
- LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16) | ((pLayerCfg->ImageWidth * tmp) + 3));
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3));
/* Configures the frame buffer line number */
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);
@@ -1176,7 +1252,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
/**
* @}
*/
-#endif /* STM32F429xx || STM32F439xx */
+#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#endif /* HAL_LTDC_MODULE_ENABLED */
/**
* @}
diff --git a/f4/src/stm32f4xx_hal_ltdc_ex.c b/f4/src/stm32f4xx_hal_ltdc_ex.c
new file mode 100644
index 0000000..558c409
--- /dev/null
+++ b/f4/src/stm32f4xx_hal_ltdc_ex.c
@@ -0,0 +1,164 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_ltdc_ex.c
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief LTDC Extension HAL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+/** @defgroup LTDCEx LTDCEx
+ * @brief LTDC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the LTDC
+
+@endverbatim
+ * @{
+ */
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Retrieve common parameters from DSI Video mode configuration structure
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains
+ * the DSI video mode configuration parameters
+ * @note The implementation of this function is taking into account the LTDC
+ * polarities inversion as described in the current LTDC specification
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg)
+{
+ /* Retrieve signal polarities from DSI */
+
+ /* The following polarities are inverted:
+ LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH
+ LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
+ LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
+
+ /* Note 1 : Code in line w/ Current LTDC specification */
+ hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
+ hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
+ hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
+
+ /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
+ /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
+ hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
+ hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */
+
+ /* Retrieve vertical timing parameters from DSI */
+ hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1;
+ hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1;
+ hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1;
+ hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Retrieve common parameters from DSI Adapted command mode configuration structure
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains
+ * the DSI command mode configuration parameters
+ * @note The implementation of this function is taking into account the LTDC
+ * polarities inversion as described in the current LTDC specification
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg)
+{
+ /* Retrieve signal polarities from DSI */
+
+ /* The following polarities are inverted:
+ LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH
+ LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
+ LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
+
+ /* Note 1 : Code in line w/ Current LTDC specification */
+ hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
+ hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
+ hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
+
+ /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
+ /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
+ hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
+ hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */
+
+ return HAL_OK;
+}
+#endif /* STM32F469xx || STM32F479xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DCMI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/src/stm32f4xx_hal_nand.c b/f4/src/stm32f4xx_hal_nand.c
index d3268a4..8c9f2fb 100755
--- a/f4/src/stm32f4xx_hal_nand.c
+++ b/f4/src/stm32f4xx_hal_nand.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_nand.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief NAND HAL module driver.
* This file provides a generic firmware to drive NAND memories mounted
* as external device.
@@ -55,7 +55,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -92,7 +92,9 @@
#ifdef HAL_NAND_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup NAND NAND
* @brief NAND HAL module driver
@@ -157,6 +159,8 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT
if(hnand->State == HAL_NAND_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hnand->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_NAND_MspInit(hnand);
}
@@ -362,7 +366,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
+ __HAL_UNLOCK(hnand);
return HAL_OK;
}
@@ -376,17 +380,17 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
{
uint32_t deviceaddress = 0;
-
+
/* Process Locked */
__HAL_LOCK(hnand);
-
+
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
- /* Identify the device address */
+ /* Identify the device address */
if(hnand->Init.NandBank == FMC_NAND_BANK2)
{
deviceaddress = NAND_DEVICE1;
@@ -396,21 +400,21 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
deviceaddress = NAND_DEVICE2;
}
- /* Update the NAND controller state */
+ /* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Send NAND reset command */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
-
-
- /* Update the NAND controller state */
+
+
+ /* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
-
+ __HAL_UNLOCK(hnand);
+
return HAL_OK;
-
+
}
/**
@@ -448,16 +452,16 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType
deviceaddress = NAND_DEVICE2;
}
- /* Update the NAND controller state */
+ /* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Save the content of pAddress as it will be modified */
nandaddress.Block = pAddress->Block;
nandaddress.Page = pAddress->Page;
nandaddress.Zone = pAddress->Zone;
-
+
/* Page(s) read loop */
- while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
{
/* update the buffer size */
size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
@@ -466,14 +470,14 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType
addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
/* Send read page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
- /* for 512 and 1 GB devices, 4th cycle is required */
+ /* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
@@ -482,7 +486,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
/* Get Data into Buffer */
- for(; index < size; index++)
+ for(index = size; index != 0; index--)
{
*(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
}
@@ -497,12 +501,12 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType
addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
}
- /* Update the NAND controller state */
+ /* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
-
+ __HAL_UNLOCK(hnand);
+
return HAL_OK;
}
@@ -553,7 +557,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp
/* Page(s) write loop */
while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
- {
+ {
/* update the buffer size */
size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
@@ -565,8 +569,8 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
/* for 512 and 1 GB devices, 4th cycle is required */
@@ -576,7 +580,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp
}
/* Write data to memory */
- for(; index < size; index++)
+ for(index = size; index != 0; index--)
{
*(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
}
@@ -592,8 +596,8 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
- }
- }
+ }
+ }
/* Increment written pages number */
numpageswritten++;
@@ -609,7 +613,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
+ __HAL_UNLOCK(hnand);
return HAL_OK;
}
@@ -661,7 +665,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres
while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
{
/* update the buffer size */
- size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
+ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
/* Get the address offset */
addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
@@ -670,8 +674,8 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
/* for 512 and 1 GB devices, 4th cycle is required */
@@ -680,10 +684,10 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
}
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
/* Get Data into Buffer */
- for ( ;index < size; index++)
+ for (index = size ;index != 0; index--)
{
*(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
}
@@ -702,7 +706,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
+ __HAL_UNLOCK(hnand);
return HAL_OK;
}
@@ -753,7 +757,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre
/* Spare area(s) write loop */
while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
- {
+ {
/* update the buffer size */
size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
@@ -765,9 +769,9 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
@@ -811,7 +815,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre
/* Process unlocked */
__HAL_UNLOCK(hnand);
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -1006,7 +1010,7 @@ HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
/* Update the NAND state */
hnand->State = HAL_NAND_STATE_READY;
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -1015,7 +1019,7 @@ HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
* the configuration information for NAND module.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
{
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
@@ -1064,7 +1068,7 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
return status;
}
-
+
/**
* @}
*/
@@ -1108,7 +1112,9 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F446xx || STM32F469xx || STM32F479xx */
#endif /* HAL_NAND_MODULE_ENABLED */
/**
diff --git a/f4/src/stm32f4xx_hal_nor.c b/f4/src/stm32f4xx_hal_nor.c
index 3880643..1afa12f 100755
--- a/f4/src/stm32f4xx_hal_nor.c
+++ b/f4/src/stm32f4xx_hal_nor.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_nor.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.
@@ -55,7 +55,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -94,10 +94,49 @@
* @{
*/
#ifdef HAL_NOR_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup NOR_Private_Defines NOR Private Defines
+ * @{
+ */
+
+/* Constants to define address to set to write a command */
+#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
+#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
+
+/* Constants to define data to program a command */
+#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
+#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
+#define NOR_CMD_DATA_SECOND (uint16_t)0x0055
+#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
+#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
+#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
+#define NOR_CMD_DATA_CFI (uint16_t)0x0098
+
+#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
+#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
+#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
+
+/* Mask on NOR STATUS REGISTER */
+#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
+#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
+
+/**
+ * @}
+ */
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
@@ -138,10 +177,12 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
if(hnor->State == HAL_NOR_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hnor->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_NOR_MspInit(hnor);
}
-
+
/* Initialize NOR control Interface */
FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
@@ -152,7 +193,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
/* Enable the NORSRAM device */
- __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
+ __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -249,7 +290,7 @@ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
*/
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
{
- uint32_t deviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -263,34 +304,34 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
- deviceAddress = NOR_MEMORY_ADRESS1;
+ deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
- deviceAddress = NOR_MEMORY_ADRESS2;
+ deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
- deviceAddress = NOR_MEMORY_ADRESS3;
+ deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
- deviceAddress = NOR_MEMORY_ADRESS4;
+ deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send read ID command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0090);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
/* Read the NOR IDs */
- pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, MC_ADDRESS);
- pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);
- pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);
- pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);
+ pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, MC_ADDRESS);
+ pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);
+ pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);
+ pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -308,7 +349,7 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
*/
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
{
- uint32_t deviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -322,22 +363,22 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
- deviceAddress = NOR_MEMORY_ADRESS1;
+ deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
- deviceAddress = NOR_MEMORY_ADRESS2;
+ deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
- deviceAddress = NOR_MEMORY_ADRESS3;
+ deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
- deviceAddress = NOR_MEMORY_ADRESS4;
+ deviceaddress = NOR_MEMORY_ADRESS4;
}
- NOR_WRITE(deviceAddress, 0x00F0);
+ NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -357,7 +398,7 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
*/
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
{
- uint32_t deviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -371,31 +412,31 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
- deviceAddress = NOR_MEMORY_ADRESS1;
+ deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
- deviceAddress = NOR_MEMORY_ADRESS2;
+ deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
- deviceAddress = NOR_MEMORY_ADRESS3;
+ deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
- deviceAddress = NOR_MEMORY_ADRESS4;
+ deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send read data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x00555), 0x00AA);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x002AA), 0x0055);
- NOR_WRITE(pAddress, 0x00F0);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
/* Read the data */
- *pData = *(__IO uint32_t *)pAddress;
+ *pData = *(__IO uint32_t *)(uint32_t)pAddress;
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -415,7 +456,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
*/
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
{
- uint32_t deviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -429,28 +470,28 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
- deviceAddress = NOR_MEMORY_ADRESS1;
+ deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
- deviceAddress = NOR_MEMORY_ADRESS2;
+ deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
- deviceAddress = NOR_MEMORY_ADRESS3;
+ deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
- deviceAddress = NOR_MEMORY_ADRESS4;
+ deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send program data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00A0);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
/* Write the data */
NOR_WRITE(pAddress, *pData);
@@ -475,7 +516,7 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
*/
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
{
- uint32_t deviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -489,27 +530,27 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
- deviceAddress = NOR_MEMORY_ADRESS1;
+ deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
- deviceAddress = NOR_MEMORY_ADRESS2;
+ deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
- deviceAddress = NOR_MEMORY_ADRESS3;
+ deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
- deviceAddress = NOR_MEMORY_ADRESS4;
+ deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send read data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x00555), 0x00AA);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x002AA), 0x0055);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(uwAddress, 0x00F0);
/* Read buffer */
@@ -540,10 +581,9 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
*/
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
{
- uint32_t lastloadedaddress = 0;
- uint32_t currentaddress = 0;
- uint32_t endaddress = 0;
- uint32_t deviceAddress = 0;
+ uint16_t * p_currentaddress = (uint16_t *)NULL;
+ uint16_t * p_endaddress = (uint16_t *)NULL;
+ uint32_t lastloadedaddress = 0, deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -557,49 +597,49 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
- deviceAddress = NOR_MEMORY_ADRESS1;
+ deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
- deviceAddress = NOR_MEMORY_ADRESS2;
+ deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
- deviceAddress = NOR_MEMORY_ADRESS3;
+ deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
- deviceAddress = NOR_MEMORY_ADRESS4;
+ deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Initialize variables */
- currentaddress = uwAddress;
- endaddress = uwAddress + uwBufferSize - 1;
- lastloadedaddress = uwAddress;
+ p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
+ p_endaddress = p_currentaddress + (uwBufferSize-1);
+ lastloadedaddress = (uint32_t)(uwAddress);
/* Issue unlock command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
/* Write Buffer Load Command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), 0x25);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1));
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1));
/* Load Data into NOR Buffer */
- while(currentaddress <= endaddress)
+ while(p_currentaddress <= p_endaddress)
{
/* Store last loaded address & data value (for polling) */
- lastloadedaddress = currentaddress;
+ lastloadedaddress = (uint32_t)p_currentaddress;
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, currentaddress), *pData++);
+ NOR_WRITE(p_currentaddress, *pData++);
- currentaddress += 1;
+ p_currentaddress ++;
}
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, lastloadedaddress), 0x29);
+ NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -620,7 +660,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
*/
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
{
- uint32_t deviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -634,31 +674,31 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
- deviceAddress = NOR_MEMORY_ADRESS1;
+ deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
- deviceAddress = NOR_MEMORY_ADRESS2;
+ deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
- deviceAddress = NOR_MEMORY_ADRESS3;
+ deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
- deviceAddress = NOR_MEMORY_ADRESS4;
+ deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send block erase command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0080);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
- NOR_WRITE((uint32_t)(BlockAddress + Address), 0x30);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
/* Check the NOR memory status and update the controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -678,7 +718,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
*/
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
{
- uint32_t deviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -692,31 +732,31 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
- deviceAddress = NOR_MEMORY_ADRESS1;
+ deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
- deviceAddress = NOR_MEMORY_ADRESS2;
+ deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
- deviceAddress = NOR_MEMORY_ADRESS3;
+ deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
- deviceAddress = NOR_MEMORY_ADRESS4;
+ deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send NOR chip erase command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0080);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0010);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
/* Check the NOR memory status and update the controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -735,7 +775,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
*/
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
{
- uint32_t deviceAddress = 0;
+ uint32_t deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -749,32 +789,32 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
- deviceAddress = NOR_MEMORY_ADRESS1;
+ deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
- deviceAddress = NOR_MEMORY_ADRESS2;
+ deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
- deviceAddress = NOR_MEMORY_ADRESS3;
+ deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
- deviceAddress = NOR_MEMORY_ADRESS4;
+ deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Send read CFI query command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0055), 0x0098);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
/* read the NOR CFI information */
- pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI1_ADDRESS);
- pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI2_ADDRESS);
- pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI3_ADDRESS);
- pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI4_ADDRESS);
+ pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI1_ADDRESS);
+ pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI2_ADDRESS);
+ pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI3_ADDRESS);
+ pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI4_ADDRESS);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -917,12 +957,12 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
tmpSR2 = *(__IO uint16_t *)Address;
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
- if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040))
+ if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
{
return HAL_NOR_STATUS_SUCCESS ;
}
- if((tmpSR1 & 0x0020) == 0x0020)
+ if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
{
status = HAL_NOR_STATUS_ONGOING;
}
@@ -931,11 +971,11 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
tmpSR2 = *(__IO uint16_t *)Address;
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
- if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040))
+ if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
{
return HAL_NOR_STATUS_SUCCESS;
}
- if((tmpSR1 & 0x0020) == 0x0020)
+ if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
{
return HAL_NOR_STATUS_ERROR;
}
@@ -953,7 +993,9 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
+ STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
+ STM32F479xx */
#endif /* HAL_NOR_MODULE_ENABLED */
/**
* @}
diff --git a/f4/src/stm32f4xx_hal_pccard.c b/f4/src/stm32f4xx_hal_pccard.c
index 573e1d8..86c6ecb 100755
--- a/f4/src/stm32f4xx_hal_pccard.c
+++ b/f4/src/stm32f4xx_hal_pccard.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pccard.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief PCCARD HAL module driver.
* This file provides a generic firmware to drive PCCARD memories mounted
* as external device.
@@ -50,7 +50,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -85,13 +85,29 @@
*/
#ifdef HAL_PCCARD_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/** @defgroup PCCARD PCCARD
* @brief PCCARD HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
-/* Private define ---------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup PCCARD_Private_Defines PCCARD Private Defines
+ * @{
+ */
+#define PCCARD_TIMEOUT_READ_ID (uint32_t)0x0000FFFF
+#define PCCARD_TIMEOUT_READ_WRITE_SECTOR (uint32_t)0x0000FFFF
+#define PCCARD_TIMEOUT_ERASE_SECTOR (uint32_t)0x00000400
+#define PCCARD_TIMEOUT_STATUS (uint32_t)0x01000000
+
+#define PCCARD_STATUS_OK (uint8_t)0x58
+#define PCCARD_STATUS_WRITE_OK (uint8_t)0x50
+/**
+ * @}
+ */
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function ----------------------------------------------------------*/
@@ -134,6 +150,8 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_Ti
if(hpccard->State == HAL_PCCARD_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hpccard->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_PCCARD_MspInit(hpccard);
}
@@ -241,8 +259,8 @@ __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
*/
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
{
- uint32_t timeout = 0xFFFF, index;
- uint8_t status;
+ uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0;
+ uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -269,7 +287,7 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
- }while((status != 0x58) && timeout);
+ }while((status != PCCARD_STATUS_OK) && timeout);
if(timeout == 0)
{
@@ -304,8 +322,8 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp
*/
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
{
- uint32_t timeout = 0xFFFF, index = 0;
- uint8_t status;
+ uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0;
+ uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -339,14 +357,14 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t
*pStatus = PCCARD_TIMEOUT_ERROR;
}
- timeout = 0xFFFF;
+ timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR;
do
{
- /* wait till the Status = 0x58 */
+ /* wait till the Status = PCCARD_STATUS_OK */
status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
- }while((status != 0x58) && timeout);
+ }while((status != PCCARD_STATUS_OK) && timeout);
if(timeout == 0)
{
@@ -380,8 +398,8 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t
*/
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
{
- uint32_t timeout = 0xFFFF, index = 0;
- uint8_t status;
+ uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0;
+ uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -405,10 +423,10 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_
do
{
- /* Wait till the Status = 0x58 */
+ /* Wait till the Status = PCCARD_STATUS_OK */
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
- }while((status != 0x58) && timeout);
+ }while((status != PCCARD_STATUS_OK) && timeout);
if(timeout == 0)
{
@@ -423,10 +441,10 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_
do
{
- /* Wait till the Status = 0x50 */
+ /* Wait till the Status = PCCARD_STATUS_WRITE_OK */
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
- }while((status != 0x50) && timeout);
+ }while((status != PCCARD_STATUS_WRITE_OK) && timeout);
if(timeout == 0)
{
@@ -453,8 +471,8 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_
*/
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
{
- uint32_t timeout = 0x400;
- uint8_t status;
+ uint32_t timeout = PCCARD_TIMEOUT_ERASE_SECTOR;
+ uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -482,7 +500,7 @@ HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16
/* wait till the PCCARD is ready */
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
- while((status != 0x50) && timeout)
+ while((status != PCCARD_STATUS_WRITE_OK) && timeout)
{
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
@@ -510,7 +528,6 @@ HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16
*/
HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
{
-
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -522,15 +539,15 @@ HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
/* Provide a SW reset and Read and verify the:
- PCCard Configuration Option Register at address 0x98000200 --> 0x80
- - Card Configuration and Status Register at address 0x98000202 --> 0x00
- - Pin Replacement Register at address 0x98000204 --> 0x0C
+ - Card Configuration and Status Register at address 0x98000202 --> 0x00
+ - Pin Replacement Register at address 0x98000204 --> 0x0C
- Socket and Copy Register at address 0x98000206 --> 0x00
*/
/* Check the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
- *(__IO uint8_t *)(0x98000202) = 0x01;
+ *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION ) = 0x01;
/* Check the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_READY;
@@ -588,7 +605,6 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
/* Clear PCCARD interrupt FIFO empty pending bit */
__FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FEMPT);
}
-
}
/**
@@ -645,7 +661,7 @@ HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
*/
HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
{
- uint32_t timeout = 0x1000000, status_pccard;
+ uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_pccard = 0;
/* Check the PCCARD controller state */
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
@@ -711,7 +727,8 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#endif /* HAL_PCCARD_MODULE_ENABLED */
/**
diff --git a/f4/src/stm32f4xx_hal_pcd.c b/f4/src/stm32f4xx_hal_pcd.c
index 8769ae5..ab6411a 100755
--- a/f4/src/stm32f4xx_hal_pcd.c
+++ b/f4/src/stm32f4xx_hal_pcd.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pcd.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -24,12 +24,12 @@
(#) Fill parameters of Init structure in HCD handle
- (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...)
+ (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
(#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
(##) Enable the PCD/USB Low Level interface clock using
- (+++) __OTGFS-OTG_CLK_ENABLE()/__OTGHS-OTG_CLK_ENABLE();
- (+++) __OTGHSULPI_CLK_ENABLE(); (For High Speed Mode)
+ (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+ (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
(##) Initialize the related GPIO clocks
(##) Configure PCD pin-out
@@ -38,14 +38,14 @@
(#)Associate the Upper USB device stack to the HAL PCD Driver:
(##) hpcd.pData = pdev;
- (#)Enable HCD transmission and reception:
+ (#)Enable PCD transmission and reception:
(##) HAL_PCD_Start();
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -85,7 +85,10 @@
*/
#ifdef HAL_PCD_MODULE_ENABLED
-
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
@@ -128,7 +131,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
/**
* @brief Initializes the PCD according to the specified
- * parameters in the PCD_InitTypeDef and create the associated handle.
+ * parameters in the PCD_InitTypeDef and initialize the associated handle.
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -192,12 +195,28 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->State= HAL_PCD_STATE_READY;
+#ifdef USB_OTG_GLPMCFG_LPMEN
+ /* Activate LPM */
+ if (hpcd->Init.lpm_enable == 1)
+ {
+ HAL_PCDEx_ActivateLPM(hpcd);
+ }
+#endif /* USB_OTG_GLPMCFG_LPMEN */
+
+#ifdef USB_OTG_GCCFG_BCDEN
+ /* Activate Battery charging */
+ if (hpcd->Init.battery_charging_enable ==1)
+ {
+ HAL_PCDEx_ActivateBCD(hpcd);
+ }
+#endif /* USB_OTG_GCCFG_BCDEN */
+
USB_DevDisconnect (hpcd->Instance);
return HAL_OK;
}
/**
- * @brief DeInitializes the PCD peripheral
+ * @brief DeInitializes the PCD peripheral.
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -250,7 +269,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
* @}
*/
-/** @defgroup PCD_Exported_Functions_Group2 IO operation functions
+/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
* @brief Data transfers functions
*
@verbatim
@@ -295,7 +314,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
}
/**
- * @brief This function handles PCD interrupt request.
+ * @brief Handles PCD interrupt request.
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -438,18 +457,27 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/* Handle Resume Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
{
- /* Clear the Remote Wake-up Signaling */
+ /* Clear the Remote Wake-up Signaling */
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
-
- HAL_PCD_ResumeCallback(hpcd);
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
+#ifdef USB_OTG_GLPMCFG_LPMEN
+ if(hpcd->LPM_State == LPM_L1)
+ {
+ hpcd->LPM_State = LPM_L0;
+ HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
+ }
+ else
+#endif /* USB_OTG_GLPMCFG_LPMEN */
+ {
+ HAL_PCD_ResumeCallback(hpcd);
+ }
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
}
/* Handle Suspend Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
{
-
if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
{
@@ -457,7 +485,25 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
}
-
+
+#ifdef USB_OTG_GLPMCFG_LPMEN
+ /* Handle LPM Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
+ if( hpcd->LPM_State == LPM_L0)
+ {
+ hpcd->LPM_State = LPM_L1;
+ hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ;
+ HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
+ }
+ else
+ {
+ HAL_PCD_SuspendCallback(hpcd);
+ }
+ }
+#endif /* USB_OTG_GLPMCFG_LPMEN */
+
/* Handle Reset Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
{
@@ -502,13 +548,13 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
hpcd->Init.speed = USB_OTG_SPEED_HIGH;
hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE ;
- hpcd->Instance->GUSBCFG |= (USB_OTG_GUSBCFG_TRDT_0 | USB_OTG_GUSBCFG_TRDT_3);
+ hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);
}
else
{
hpcd->Init.speed = USB_OTG_SPEED_FULL;
hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ;
- hpcd->Instance->GUSBCFG |= (USB_OTG_GUSBCFG_TRDT_0 | USB_OTG_GUSBCFG_TRDT_2);
+ hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);
}
HAL_PCD_ResetCallback(hpcd);
@@ -520,7 +566,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
{
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+
temp = USBx->GRXSTSP;
+
ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
@@ -583,7 +631,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
/**
- * @brief Data OUT stage callbacks
+ * @brief Data OUT stage callback.
* @param hpcd: PCD handle
* @param epnum: endpoint number
* @retval None
@@ -596,7 +644,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
/**
- * @brief Data IN stage callbacks
+ * @brief Data IN stage callback.
* @param hpcd: PCD handle
* @param epnum: endpoint number
* @retval None
@@ -604,72 +652,71 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implemented in the user file
+ the HAL_PCD_DataInStageCallback could be implemented in the user file
*/
}
/**
- * @brief Setup stage callback
+ * @brief Setup stage callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implemented in the user file
+ the HAL_PCD_SetupStageCallback could be implemented in the user file
*/
}
/**
- * @brief USB Start Of Frame callbacks
+ * @brief USB Start Of Frame callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implemented in the user file
+ the HAL_PCD_SOFCallback could be implemented in the user file
*/
}
/**
- * @brief USB Reset callbacks
+ * @brief USB Reset callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implemented in the user file
+ the HAL_PCD_ResetCallback could be implemented in the user file
*/
}
-
/**
- * @brief Suspend event callbacks
+ * @brief Suspend event callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implemented in the user file
+ the HAL_PCD_SuspendCallback could be implemented in the user file
*/
}
/**
- * @brief Resume event callbacks
+ * @brief Resume event callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implemented in the user file
+ the HAL_PCD_ResumeCallback could be implemented in the user file
*/
}
/**
- * @brief Incomplete ISO OUT callbacks
+ * @brief Incomplete ISO OUT callback.
* @param hpcd: PCD handle
* @param epnum: endpoint number
* @retval None
@@ -677,12 +724,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implemented in the user file
+ the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
*/
}
/**
- * @brief Incomplete ISO IN callbacks
+ * @brief Incomplete ISO IN callback.
* @param hpcd: PCD handle
* @param epnum: endpoint number
* @retval None
@@ -690,31 +737,31 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implemented in the user file
+ the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
*/
}
/**
- * @brief Connection event callbacks
+ * @brief Connection event callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implemented in the user file
+ the HAL_PCD_ConnectCallback could be implemented in the user file
*/
}
/**
- * @brief Disconnection event callbacks
+ * @brief Disconnection event callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implemented in the user file
+ the HAL_PCD_DisconnectCallback could be implemented in the user file
*/
}
@@ -738,7 +785,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
*/
/**
- * @brief Connect the USB device
+ * @brief Connect the USB device.
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -751,7 +798,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
}
/**
- * @brief Disconnect the USB device
+ * @brief Disconnect the USB device.
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -764,7 +811,7 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
}
/**
- * @brief Set the USB Device address
+ * @brief Set the USB Device address.
* @param hpcd: PCD handle
* @param address: new device address
* @retval HAL status
@@ -777,7 +824,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
return HAL_OK;
}
/**
- * @brief Open and configure an endpoint
+ * @brief Open and configure an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @param ep_mps: endpoint max packet size
@@ -821,7 +868,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
/**
- * @brief Deactivate an endpoint
+ * @brief Deactivate an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval HAL status
@@ -850,7 +897,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
/**
- * @brief Receive an amount of data
+ * @brief Receive an amount of data.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @param pBuf: pointer to the reception buffer
@@ -891,7 +938,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
}
/**
- * @brief Get Received Data Size
+ * @brief Get Received Data Size.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval Data Size
@@ -901,7 +948,7 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
}
/**
- * @brief Send an amount of data
+ * @brief Send an amount of data.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @param pBuf: pointer to the transmission buffer
@@ -943,7 +990,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
}
/**
- * @brief Set a STALL condition over an endpoint
+ * @brief Set a STALL condition over an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval HAL status
@@ -978,7 +1025,7 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
/**
- * @brief Clear a STALL condition over in an endpoint
+ * @brief Clear a STALL condition over in an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval HAL status
@@ -1008,7 +1055,7 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
/**
- * @brief Flush an endpoint
+ * @brief Flush an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval HAL status
@@ -1032,7 +1079,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
/**
- * @brief HAL_PCD_ActivateRemoteWakeup : active remote wake-up signalling
+ * @brief Activate remote wakeup signalling.
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -1042,14 +1089,14 @@ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
{
- /* active Remote wake-up signaling */
+ /* Activate Remote wakeup signaling */
USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
}
return HAL_OK;
}
/**
- * @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wake-up signalling
+ * @brief De-activate remote wakeup signalling.
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -1057,7 +1104,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
- /* Active Remote wake-up signaling */
+ /* De-activate Remote wakeup signaling */
USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
return HAL_OK;
}
@@ -1081,7 +1128,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
*/
/**
- * @brief Return the PCD state
+ * @brief Return the PCD handle state.
* @param hpcd: PCD handle
* @retval HAL state
*/
@@ -1103,8 +1150,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
*/
/**
- * @brief DCD_WriteEmptyTxFifo
- * check FIFO for the next packet to be loaded
+ * @brief Check FIFO for the next packet to be loaded.
* @param hpcd: PCD handle
* @param epnum : endpoint number
* @retval HAL status
@@ -1160,7 +1206,8 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
/**
* @}
*/
-
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
#endif /* HAL_PCD_MODULE_ENABLED */
/**
* @}
diff --git a/f4/src/stm32f4xx_hal_pcd_ex.c b/f4/src/stm32f4xx_hal_pcd_ex.c
index 7f31caa..71b5d87 100755
--- a/f4/src/stm32f4xx_hal_pcd_ex.c
+++ b/f4/src/stm32f4xx_hal_pcd_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pcd_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -51,7 +51,10 @@
* @{
*/
#ifdef HAL_PCD_MODULE_ENABLED
-
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
@@ -59,7 +62,7 @@
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
+/** @defgroup PCDEx_Exported_Functions PCD Extended Exported Functions
* @{
*/
@@ -103,7 +106,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin
if(fifo == 0)
{
- hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset;
+ hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
}
else
{
@@ -114,8 +117,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin
}
/* Multiply Tx_Size by 2 to get higher performance */
- hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset;
-
+ hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
}
return HAL_OK;
@@ -134,6 +136,51 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
return HAL_OK;
}
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Activate LPM feature
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+ hpcd->lpm_active = ENABLE;
+ hpcd->LPM_State = LPM_L0;
+ USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
+ USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate LPM feature.
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+ hpcd->lpm_active = DISABLE;
+ USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
+ USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Send LPM message to user layer callback.
+ * @param hpcd: PCD handle
+ * @param msg: LPM message
+ * @retval HAL status
+ */
+__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
+{
+}
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+
/**
* @}
*/
@@ -142,6 +189,8 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
* @}
*/
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
#endif /* HAL_PCD_MODULE_ENABLED */
/**
* @}
diff --git a/f4/src/stm32f4xx_hal_pwr.c b/f4/src/stm32f4xx_hal_pwr.c
index 60fb6da..019de36 100755
--- a/f4/src/stm32f4xx_hal_pwr.c
+++ b/f4/src/stm32f4xx_hal_pwr.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pwr.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -166,7 +166,9 @@ void HAL_PWR_DisableBkUpAccess(void)
[..]
(+) Wake-up pin is used to wake up the system from Standby mode. This pin is
forced in input pull-down configuration and is active on rising edges.
- (+) There is only one Wake-up pin: Wake-up Pin 1 on PA.00.
+ (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
+ (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
+ (++) For STM32F410xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01
*** Low Power modes configuration ***
=====================================
@@ -327,13 +329,17 @@ void HAL_PWR_DisablePVD(void)
* @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1
+ * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx devices
+ * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx devices
* @retval None
*/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
{
/* Check the parameter */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
- *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)ENABLE;
+
+ /* Enable the wake up pin */
+ SET_BIT(PWR->CSR, WakeUpPinx);
}
/**
@@ -341,13 +347,17 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1
+ * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx devices
+ * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx devices
* @retval None
*/
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
{
/* Check the parameter */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
- *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)DISABLE;
+
+ /* Disable the wake up pin */
+ CLEAR_BIT(PWR->CSR, WakeUpPinx);
}
/**
diff --git a/f4/src/stm32f4xx_hal_pwr_ex.c b/f4/src/stm32f4xx_hal_pwr_ex.c
index 9b5e54f..cc9184b 100755
--- a/f4/src/stm32f4xx_hal_pwr_ex.c
+++ b/f4/src/stm32f4xx_hal_pwr_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pwr_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of PWR extension peripheral:
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -61,10 +61,12 @@
#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000
#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000
#define PWR_BKPREG_TIMEOUT_VALUE 1000
+#define PWR_VOSRDY_TIMEOUT_VALUE 1000
/**
* @}
*/
-
+
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -120,7 +122,7 @@
is in power down mode, an additional startup delay is incurred when
waking up from Stop mode.
- (+) For STM32F42xxx/43xxx Devices, the scale can be modified only when the PLL
+ (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL
is OFF and the HSI or HSE clock source is selected as system clock.
The new value programmed is active only when the PLL is ON.
When the PLL is OFF, the voltage scale 3 is automatically selected.
@@ -129,7 +131,7 @@
*** Over-Drive and Under-Drive configuration ****
=================================================
[..]
- (+) For STM32F42xxx/43xxx Devices, in Run mode: the main regulator has
+ (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has
2 operating modes available:
(++) Normal mode: The CPU and core logic operate at maximum frequency at a given
voltage scaling (scale 1, scale 2 or scale 3)
@@ -139,7 +141,7 @@
disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
the sequence described in Reference manual.
- (+) For STM32F42xxx/43xxx Devices, in Stop mode: the main regulator or low power regulator
+ (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator
supplies a low power voltage to the 1.2V domain, thus preserving the content of registers
and internal SRAM. 2 operating modes are available:
(++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
@@ -218,10 +220,177 @@ void HAL_PWREx_DisableFlashPowerDown(void)
*(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;
}
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+/**
+ * @brief Return Voltage Scaling Range.
+ * @retval The configured scale for the regulator voltage(VOS bit field).
+ * The returned value can be one of the following:
+ * - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
+ * - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
+ * - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
+ */
+uint32_t HAL_PWREx_GetVoltageRange(void)
+{
+ return (PWR->CR & PWR_CR_VOS);
+}
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+/**
+ * @brief Configures the main internal regulator output voltage.
+ * @param VoltageScaling: specifies the regulator output voltage to achieve
+ * a tradeoff between performance and power consumption.
+ * This parameter can be one of the following values:
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
+ * the maximum value of fHCLK = 168 MHz.
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
+ * the maximum value of fHCLK = 144 MHz.
+ * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
+ * a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API.
+ * When moving from Range 2 to Range 1, the system frequency can be increased to
+ * a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
+{
+ uint32_t tickstart = 0;
+
+ assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
+
+ /* Enable PWR RCC Clock Peripheral */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Set Range */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
+ {
+ if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \
+ defined(STM32F479xx)
+/**
+ * @brief Configures the main internal regulator output voltage.
+ * @param VoltageScaling: specifies the regulator output voltage to achieve
+ * a tradeoff between performance and power consumption.
+ * This parameter can be one of the following values:
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
+ * the maximum value of fHCLK is 168 MHz. It can be extended to
+ * 180 MHz by activating the over-drive mode.
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
+ * the maximum value of fHCLK is 144 MHz. It can be extended to,
+ * 168 MHz by activating the over-drive mode.
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode,
+ * the maximum value of fHCLK is 120 MHz.
+ * @note To update the system clock frequency(SYSCLK):
+ * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
+ * - Call the HAL_RCC_OscConfig() to configure the PLL.
+ * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
+ * - Set the new system clock frequency using the HAL_RCC_ClockConfig().
+ * @note The scale can be modified only when the HSI or HSE clock source is selected
+ * as system clock source, otherwise the API returns HAL_ERROR.
+ * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
+ * value in the PWR_CR1 register are not taken in account.
+ * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
+ * @note The new voltage scale is active only when the PLL is ON.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
+{
+ uint32_t tickstart = 0;
+
+ assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
+
+ /* Enable PWR RCC Clock Peripheral */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Check if the PLL is used as system clock or not */
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+ {
+ /* Disable the main PLL */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLL is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set Range */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
+
+ /* Enable the main PLL */
+ __HAL_RCC_PLL_ENABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+ while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
+ {
+ if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Enables Wakeup Pin Detection on high level (rising edge).
+ * @retval None
+ */
+void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void)
+{
+ *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)DISABLE;
+}
+
+/**
+ * @brief Enables Wakeup Pin Detection on low level (falling edge).
+ * @retval None
+ */
+void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void)
+{
+ *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)ENABLE;
+}
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+ defined(STM32F411xE)
/**
* @brief Enables Main Regulator low voltage mode.
- * @note This mode is only available for STM32F401xx/STM32F411xx devices.
+ * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
* @retval None
*/
void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
@@ -231,7 +400,7 @@ void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
/**
* @brief Disables Main Regulator low voltage mode.
- * @note This mode is only available for STM32F401xx/STM32F411xx devices.
+ * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
* @retval None
*/
void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
@@ -241,7 +410,7 @@ void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
/**
* @brief Enables Low Power Regulator low voltage mode.
- * @note This mode is only available for STM32F401xx/STM32F411xx devices.
+ * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
* @retval None
*/
void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
@@ -251,7 +420,7 @@ void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
/**
* @brief Disables Low Power Regulator low voltage mode.
- * @note This mode is only available for STM32F401xx/STM32F411xx devices.
+ * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
* @retval None
*/
void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
@@ -259,12 +428,13 @@ void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
*(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
}
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Activates the Over-Drive mode.
- * @note This function can be used only for STM32F42xx/STM32F43xx devices.
+ * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
* This mode allows the CPU and the core logic to operate at a higher frequency
* than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
* @note It is recommended to enter or exit Over-drive mode when the application is not running
@@ -311,7 +481,7 @@ HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
/**
* @brief Deactivates the Over-Drive mode.
- * @note This function can be used only for STM32F42xx/STM32F43xx devices.
+ * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
* This mode allows the CPU and the core logic to operate at a higher frequency
* than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
* @note It is recommended to enter or exit Over-drive mode when the application is not running
@@ -360,7 +530,7 @@ HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
/**
* @brief Enters in Under-Drive STOP mode.
*
- * @note This mode is only available for STM32F42xxx/STM324F3xxx devices.
+ * @note This mode is only available for STM32F42xxx/STM324F3xxx/STM32F446xx/STM32F469xx/STM32F479xx devices.
*
* @note This mode can be selected only when the Under-Drive is already active
*
@@ -398,7 +568,7 @@ HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
*/
HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0;
uint32_t tickstart = 0;
/* Check the parameters */
@@ -427,15 +597,15 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t
}
/* Select the regulator state in STOP mode ---------------------------------*/
- tmpreg = PWR->CR;
+ tmpreg1 = PWR->CR;
/* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
- tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS);
+ tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS);
/* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
- tmpreg |= Regulator;
+ tmpreg1 |= Regulator;
/* Store the new value */
- PWR->CR = tmpreg;
+ PWR->CR = tmpreg1;
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
@@ -457,7 +627,7 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t
return HAL_OK;
}
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
diff --git a/f4/src/stm32f4xx_hal_qspi.c b/f4/src/stm32f4xx_hal_qspi.c
new file mode 100644
index 0000000..f0bc3eb
--- /dev/null
+++ b/f4/src/stm32f4xx_hal_qspi.c
@@ -0,0 +1,1945 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_qspi.c
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief QSPI HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the QuadSPI interface (QSPI).
+ * + Initialization and de-initialization functions
+ * + Indirect functional mode management
+ * + Memory-mapped functional mode management
+ * + Auto-polling functional mode management
+ * + Interrupts and flags management
+ * + DMA channel configuration for indirect functional mode
+ * + Errors management and abort functionality
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ *** Initialization ***
+ ======================
+ [..]
+ (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
+ (+) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
+ (+) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
+ (+) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+ (+) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
+ (+) If interrupt mode is used, enable and configure QuadSPI global
+ interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+ (+) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
+ with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
+ link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
+ DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+ (#) Configure the flash size, the clock prescaler, the fifo threshold, the
+ clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
+
+ *** Indirect functional mode ***
+ ================================
+ [..]
+ (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
+ functions :
+ (+) Instruction phase : the mode used and if present the instruction opcode.
+ (+) Address phase : the mode used and if present the size and the address value.
+ (+) Alternate-bytes phase : the mode used and if present the size and the alternate
+ bytes values.
+ (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+ (+) Data phase : the mode used and if present the number of bytes.
+ (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+ if activated.
+ (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+ (#) If no data is required for the command, it is sent directly to the memory :
+ (+) In polling mode, the output of the function is done when the transfer is complete.
+ (+) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
+ (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
+ HAL_QSPI_Transmit_IT() after the command configuration :
+ (+) In polling mode, the output of the function is done when the transfer is complete.
+ (+) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
+ is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
+ (+) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
+ HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
+ (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
+ HAL_QSPI_Receive_IT() after the command configuration :
+ (+) In polling mode, the output of the function is done when the transfer is complete.
+ (+) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
+ is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
+ (+) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
+ HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
+
+ *** Auto-polling functional mode ***
+ ====================================
+ [..]
+ (#) Configure the command sequence and the auto-polling functional mode using the
+ HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
+ (+) Instruction phase : the mode used and if present the instruction opcode.
+ (+) Address phase : the mode used and if present the size and the address value.
+ (+) Alternate-bytes phase : the mode used and if present the size and the alternate
+ bytes values.
+ (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+ (+) Data phase : the mode used.
+ (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+ if activated.
+ (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+ (+) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
+ the polling interval and the automatic stop activation.
+ (#) After the configuration :
+ (+) In polling mode, the output of the function is done when the status match is reached. The
+ automatic stop is activated to avoid an infinite loop.
+ (+) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
+
+ *** Memory-mapped functional mode ***
+ =====================================
+ [..]
+ (#) Configure the command sequence and the memory-mapped functional mode using the
+ HAL_QSPI_MemoryMapped() functions :
+ (+) Instruction phase : the mode used and if present the instruction opcode.
+ (+) Address phase : the mode used and the size.
+ (+) Alternate-bytes phase : the mode used and if present the size and the alternate
+ bytes values.
+ (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+ (+) Data phase : the mode used.
+ (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+ if activated.
+ (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+ (+) The timeout activation and the timeout period.
+ (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
+ the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
+
+ *** Errors management and abort functionality ***
+ ==================================================
+ [..]
+ (#) HAL_QSPI_GetError() function gives the error rised during the last operation.
+ (#) HAL_QSPI_Abort() function aborts any on-going operation and flushes the fifo.
+ (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
+
+ *** Workarounds linked to Silicon Limitation ***
+ ====================================================
+ [..]
+ (#) Workarounds Implemented inside HAL Driver
+ (+) Extra data written in the FIFO at the end of a read transfer
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup QSPI QSPI
+ * @brief HAL QSPI module driver
+ * @{
+ */
+#ifdef HAL_QSPI_MODULE_ENABLED
+
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup QSPI_Private_Constants
+ * @{
+ */
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!<Indirect write mode*/
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
+#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
+#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /*!<Memory-mapped mode*/
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @addtogroup QSPI_Private_Macros QSPI Private Macros
+ * @{
+ */
+#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
+ ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \
+ ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \
+ ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup QSPI_Private_Functions QSPI Private Functions
+ * @{
+ */
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout);
+static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
+ * @{
+ */
+
+/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to :
+ (+) Initialize the QuadSPI.
+ (+) De-initialize the QuadSPI.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the QSPI mode according to the specified parameters
+ * in the QSPI_InitTypeDef and creates the associated handle.
+ * @param hqspi: qspi handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the QSPI handle allocation */
+ if(hqspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
+ assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
+ assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
+ assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
+ assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
+ assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
+ assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
+ assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
+
+ if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
+ {
+ assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hqspi->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_QSPI_MspInit(hqspi);
+
+ /* Configure the default timeout for the QSPI memory access */
+ HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
+ }
+
+ /* Configure QSPI FIFO Threshold */
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8));
+
+ /* Wait till BUSY flag reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
+
+ if(status == HAL_OK)
+ {
+
+ /* Configure QSPI Clock Prescaler and Sample Shift */
+ MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));
+
+ /* Configure QSPI Flash Size, CS High Time and Clock Mode */
+ MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
+ ((hqspi->Init.FlashSize << 16) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
+
+ /* Enable the QSPI peripheral */
+ __HAL_QSPI_ENABLE(hqspi);
+
+ /* Set QSPI error code to none */
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Initialize the QSPI state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hqspi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief DeInitializes the QSPI peripheral
+ * @param hqspi: qspi handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
+{
+ /* Check the QSPI handle allocation */
+ if(hqspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ /* Disable the QSPI Peripheral Clock */
+ __HAL_QSPI_DISABLE(hqspi);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_QSPI_MspDeInit(hqspi);
+
+ /* Set QSPI error code to none */
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Initialize the QSPI state */
+ hqspi->State = HAL_QSPI_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hqspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief QSPI MSP Init
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_QSPI_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief QSPI MSP DeInit
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_QSPI_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
+ * @brief QSPI Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to :
+ (+) Handle the interrupts.
+ (+) Handle the command sequence.
+ (+) Transmit data in blocking, interrupt or DMA mode.
+ (+) Receive data in blocking, interrupt or DMA mode.
+ (+) Manage the auto-polling functional mode.
+ (+) Manage the memory-mapped functional mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles QSPI interrupt request.
+ * @param hqspi: QSPI handle
+ * @retval None.
+ */
+void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
+{
+ __IO uint32_t *data_reg;
+ uint32_t flag = 0, itsource = 0;
+
+ /* QSPI FIFO Threshold interrupt occurred ----------------------------------*/
+ flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT);
+ itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_FT);
+
+ if((flag != RESET) && (itsource != RESET))
+ {
+ data_reg = &hqspi->Instance->DR;
+
+ if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+ {
+ /* Transmission process */
+ while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
+ {
+ if (hqspi->TxXferCount > 0)
+ {
+ /* Fill the FIFO until it is full */
+ *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
+ hqspi->TxXferCount--;
+ }
+ else
+ {
+ /* No more data available for the transfer */
+ break;
+ }
+ }
+ }
+ else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
+ {
+ /* Receiving Process */
+ while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
+ {
+ if (hqspi->RxXferCount > 0)
+ {
+ /* Read the FIFO until it is empty */
+ *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
+ hqspi->RxXferCount--;
+ }
+ else
+ {
+ /* All data have been received for the transfer */
+ break;
+ }
+ }
+ }
+
+ /* FIFO Threshold callback */
+ HAL_QSPI_FifoThresholdCallback(hqspi);
+ }
+
+ /* QSPI Transfer Complete interrupt occurred -------------------------------*/
+ flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TC);
+ itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TC);
+
+ if((flag != RESET) && (itsource != RESET))
+ {
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
+ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
+
+ /* Transfer complete callback */
+ if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+ {
+ /* Clear Busy bit */
+ HAL_QSPI_Abort(hqspi);
+
+ /* TX Complete callback */
+ HAL_QSPI_TxCpltCallback(hqspi);
+ }
+ else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
+ {
+ data_reg = &hqspi->Instance->DR;
+ while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
+ {
+ if (hqspi->RxXferCount > 0)
+ {
+ /* Read the last data received in the FIFO until it is empty */
+ *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
+ hqspi->RxXferCount--;
+ }
+ else
+ {
+ /* All data have been received for the transfer */
+ break;
+ }
+ }
+
+ /* Workaround - Extra data written in the FIFO at the end of a read transfer */
+ HAL_QSPI_Abort(hqspi);
+
+ /* RX Complete callback */
+ HAL_QSPI_RxCpltCallback(hqspi);
+ }
+ else if(hqspi->State == HAL_QSPI_STATE_BUSY)
+ {
+ /* Command Complete callback */
+ HAL_QSPI_CmdCpltCallback(hqspi);
+ }
+
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+
+ /* QSPI Status Match interrupt occurred ------------------------------------*/
+ flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_SM);
+ itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_SM);
+
+ if((flag != RESET) && (itsource != RESET))
+ {
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
+
+ /* Check if the automatic poll mode stop is activated */
+ if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
+ {
+ /* Disable the QSPI FIFO Threshold, Transfer Error and Status Match Interrupts */
+ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TE);
+
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+
+ /* Status match callback */
+ HAL_QSPI_StatusMatchCallback(hqspi);
+ }
+
+ /* QSPI Transfer Error interrupt occurred ----------------------------------*/
+ flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TE);
+ itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TE);
+
+ if((flag != RESET) && (itsource != RESET))
+ {
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE);
+
+ /* Disable all the QSPI Interrupts */
+ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
+
+ /* Set error code */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
+
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_ERROR;
+
+ /* Error callback */
+ HAL_QSPI_ErrorCallback(hqspi);
+ }
+
+ /* QSPI Time out interrupt occurred -----------------------------------------*/
+ flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TO);
+ itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TO);
+
+ if((flag != RESET) && (itsource != RESET))
+ {
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
+
+ /* Time out callback */
+ HAL_QSPI_TimeOutCallback(hqspi);
+ }
+}
+
+/**
+ * @brief Sets the command configuration.
+ * @param hqspi: QSPI handle
+ * @param cmd : structure that contains the command configuration information
+ * @param Timeout : Time out duration
+ * @note This function is used only in Indirect Read or Write Modes
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+ {
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+ }
+
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+ }
+
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+ }
+
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_BUSY;
+
+ /* Wait till BUSY flag reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Call the configuration function */
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+ if (cmd->DataMode == QSPI_DATA_NONE)
+ {
+ /* When there is no data phase, the transfer start as soon as the configuration is done
+ so wait until TC flag is set to go back in idle state */
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+
+ }
+ else
+ {
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Sets the command configuration in interrupt mode.
+ * @param hqspi: QSPI handle
+ * @param cmd : structure that contains the command configuration information
+ * @note This function is used only in Indirect Read or Write Modes
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+ {
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+ }
+
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+ }
+
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+ }
+
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_BUSY;
+
+ /* Wait till BUSY flag reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
+
+ if (status == HAL_OK)
+ {
+ if (cmd->DataMode == QSPI_DATA_NONE)
+ {
+ /* When there is no data phase, the transfer start as soon as the configuration is done
+ so activate TC and TE interrupts */
+ /* Enable the QSPI Transfer Error Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
+ }
+
+ /* Call the configuration function */
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+ if (cmd->DataMode != QSPI_DATA_NONE)
+ {
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Transmit an amount of data in blocking mode.
+ * @param hqspi: QSPI handle
+ * @param pData: pointer to data buffer
+ * @param Timeout : Time out duration
+ * @note This function is used only in Indirect Write Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ __IO uint32_t *data_reg = &hqspi->Instance->DR;
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ if(pData != NULL )
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+
+ /* Configure counters and size of the handle */
+ hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->pTxBuffPtr = pData;
+
+ /* Configure QSPI: CCR register with functional as indirect write */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+ while(hqspi->TxXferCount > 0)
+ {
+ /* Wait until FT flag is set to send data */
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, Timeout) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ break;
+ }
+
+ *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
+ hqspi->TxXferCount--;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Wait until TC flag is set to go back in idle state */
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Clear Transfer Complete bit */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Clear Busy bit */
+ status = HAL_QSPI_Abort(hqspi);
+ }
+ }
+
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ return status;
+}
+
+
+/**
+ * @brief Receive an amount of data in blocking mode
+ * @param hqspi: QSPI handle
+ * @param pData: pointer to data buffer
+ * @param Timeout : Time out duration
+ * @note This function is used only in Indirect Read Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+ __IO uint32_t *data_reg = &hqspi->Instance->DR;
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ if(pData != NULL )
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+
+ /* Configure counters and size of the handle */
+ hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->pRxBuffPtr = pData;
+
+ /* Configure QSPI: CCR register with functional as indirect read */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+ /* Start the transfer by re-writing the address in AR register */
+ WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+ while(hqspi->RxXferCount > 0)
+ {
+ /* Wait until FT or TC flag is set to read received data */
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, Timeout) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ break;
+ }
+
+ *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
+ hqspi->RxXferCount--;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Wait until TC flag is set to go back in idle state */
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Clear Transfer Complete bit */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Workaround - Extra data written in the FIFO at the end of a read transfer */
+ status = HAL_QSPI_Abort(hqspi);
+ }
+ }
+
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ return status;
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode
+ * @param hqspi: QSPI handle
+ * @param pData: pointer to data buffer
+ * @note This function is used only in Indirect Write Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ if(pData != NULL )
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+
+ /* Configure counters and size of the handle */
+ hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->pTxBuffPtr = pData;
+
+ /* Configure QSPI: CCR register with functional as indirect write */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+ /* Enable the QSPI transfer error, FIFO threshold and transfert complete Interrupts */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
+
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ return status;
+}
+
+/**
+ * @brief Receive an amount of data in no-blocking mode with Interrupt
+ * @param hqspi: QSPI handle
+ * @param pData: pointer to data buffer
+ * @note This function is used only in Indirect Read Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ if(pData != NULL )
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+
+ /* Configure counters and size of the handle */
+ hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->pRxBuffPtr = pData;
+
+ /* Configure QSPI: CCR register with functional as indirect read */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+ /* Start the transfer by re-writing the address in AR register */
+ WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+ /* Enable the QSPI transfer error, FIFO threshold and transfert complete Interrupts */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ return status;
+}
+
+/**
+ * @brief Sends an amount of data in non blocking mode with DMA.
+ * @param hqspi: QSPI handle
+ * @param pData: pointer to data buffer
+ * @note This function is used only in Indirect Write Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t *tmp;
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ if(pData != NULL )
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+
+ /* Configure counters and size of the handle */
+ hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->pTxBuffPtr = pData;
+
+ /* Configure QSPI: CCR register with functional mode as indirect write */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+ /* Set the QSPI DMA transfer complete callback */
+ hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
+
+ /* Set the QSPI DMA Half transfer complete callback */
+ hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
+
+ /* Set the DMA error callback */
+ hqspi->hdma->XferErrorCallback = QSPI_DMAError;
+
+ /* Configure the direction of the DMA */
+ hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
+ MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
+
+ /* Enable the QSPI transmit DMA Channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
+
+ /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_OK;
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ return status;
+}
+
+/**
+ * @brief Receives an amount of data in non blocking mode with DMA.
+ * @param hqspi: QSPI handle
+ * @param pData: pointer to data buffer.
+ * @note This function is used only in Indirect Read Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t *tmp;
+ uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ if(pData != NULL )
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+
+ /* Configure counters and size of the handle */
+ hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
+ hqspi->pRxBuffPtr = pData;
+
+ /* Set the QSPI DMA transfer complete callback */
+ hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
+
+ /* Set the QSPI DMA Half transfer complete callback */
+ hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
+
+ /* Set the DMA error callback */
+ hqspi->hdma->XferErrorCallback = QSPI_DMAError;
+
+ /* Configure the direction of the DMA */
+ hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
+ MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
+
+ /* Enable the DMA Channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
+
+ /* Configure QSPI: CCR register with functional as indirect read */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+ /* Start the transfer by re-writing the address in AR register */
+ WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+ /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ return status;
+}
+
+/**
+ * @brief Configure the QSPI Automatic Polling Mode in blocking mode.
+ * @param hqspi: QSPI handle
+ * @param cmd: structure that contains the command configuration information.
+ * @param cfg: structure that contains the polling configuration information.
+ * @param Timeout : Time out duration
+ * @note This function is used only in Automatic Polling Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+ {
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+ }
+
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+ }
+
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+ }
+
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+ assert_param(IS_QSPI_INTERVAL(cfg->Interval));
+ assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
+ assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
+
+ /* Wait till BUSY flag reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Configure QSPI: PSMAR register with the status match value */
+ WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
+
+ /* Configure QSPI: PSMKR register with the status mask value */
+ WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
+
+ /* Configure QSPI: PIR register with the interval value */
+ WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
+
+ /* Configure QSPI: CR register with Match mode and Automatic stop enabled
+ (otherwise there will be an infinite loop in blocking mode) */
+ MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
+ (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
+
+ /* Call the configuration function */
+ cmd->NbData = cfg->StatusBytesSize;
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
+
+ /* Wait until SM flag is set to go back in idle state */
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, Timeout) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
+ * @param hqspi: QSPI handle
+ * @param cmd: structure that contains the command configuration information.
+ * @param cfg: structure that contains the polling configuration information.
+ * @note This function is used only in Automatic Polling Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+ {
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+ }
+
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+ }
+
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+ }
+
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+ assert_param(IS_QSPI_INTERVAL(cfg->Interval));
+ assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
+ assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
+ assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
+
+ /* Wait till BUSY flag reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Configure QSPI: PSMAR register with the status match value */
+ WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
+
+ /* Configure QSPI: PSMKR register with the status mask value */
+ WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
+
+ /* Configure QSPI: PIR register with the interval value */
+ WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
+
+ /* Configure QSPI: CR register with Match mode and Automatic stop mode */
+ MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
+ (cfg->MatchMode | cfg->AutomaticStop));
+
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
+
+ /* Enable the QSPI Transfer Error and status match Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
+
+ /* Call the configuration function */
+ cmd->NbData = cfg->StatusBytesSize;
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Configure the Memory Mapped mode.
+ * @param hqspi: QSPI handle
+ * @param cmd: structure that contains the command configuration information.
+ * @param cfg: structure that contains the memory mapped configuration information.
+ * @note This function is used only in Memory mapped Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+ {
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+ }
+
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+ }
+
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+ }
+
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+ assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
+
+ /* Wait till BUSY flag reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Configure QSPI: CR register with time out counter enable */
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
+
+ if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
+ {
+ assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
+
+ /* Configure QSPI: LPTR register with the low-power time out value */
+ WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
+
+ /* Enable the QSPI TimeOut Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
+ }
+
+ /* Call the configuration function */
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
+
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Transfer Error callbacks
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Command completed callbacks.
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_CmdCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks.
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Transfer completed callbacks.
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callbacks.
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callbacks.
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FIFO Threshold callbacks
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Status Match callbacks
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_StatusMatchCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timeout callbacks
+ * @param hqspi: QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_TimeOutCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
+ * @brief QSPI control and State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control and State functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to :
+ (+) Check in run-time the state of the driver.
+ (+) Check the error code set during last operation.
+ (+) Abort any operation.
+.....
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the QSPI state.
+ * @param hqspi: QSPI handle
+ * @retval HAL state
+ */
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
+{
+ return hqspi->State;
+}
+
+/**
+* @brief Return the QSPI error code
+* @param hqspi: QSPI handle
+* @retval QSPI Error Code
+*/
+uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
+{
+ return hqspi->ErrorCode;
+}
+
+/**
+* @brief Abort the current transmission
+* @param hqspi: QSPI handle
+* @retval HAL status
+*/
+HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Configure QSPI: CR register with Abort request */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+
+ /* Wait until TC flag is set to go back in idle state */
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Wait until BUSY flag is reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+
+ return status;
+}
+
+/** @brief Set QSPI timeout
+ * @param hqspi: QSPI handle.
+ * @param Timeout: Timeout for the QSPI memory access.
+ * @retval None
+ */
+void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
+{
+ hqspi->Timeout = Timeout;
+}
+
+/**
+* @}
+*/
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief DMA QSPI receive process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hqspi->RxXferCount = 0;
+
+ /* Wait for QSPI TC Flag */
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
+ {
+ /* Time out Occurred */
+ HAL_QSPI_ErrorCallback(hqspi);
+ }
+ else
+ {
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+ /* Disable the DMA channel */
+ HAL_DMA_Abort(hdma);
+
+ /* Clear Transfer Complete bit */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Workaround - Extra data written in the FIFO at the end of a read transfer */
+ HAL_QSPI_Abort(hqspi);
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ HAL_QSPI_RxCpltCallback(hqspi);
+ }
+}
+
+/**
+ * @brief DMA QSPI transmit process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hqspi->TxXferCount = 0;
+
+ /* Wait for QSPI TC Flag */
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
+ {
+ /* Time out Occurred */
+ HAL_QSPI_ErrorCallback(hqspi);
+ }
+ else
+ {
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+ /* Disable the DMA channel */
+ HAL_DMA_Abort(hdma);
+
+ /* Clear Transfer Complete bit */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Clear Busy bit */
+ HAL_QSPI_Abort(hqspi);
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ HAL_QSPI_TxCpltCallback(hqspi);
+ }
+}
+
+/**
+ * @brief DMA QSPI receive process half complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_QSPI_RxHalfCpltCallback(hqspi);
+}
+
+/**
+ * @brief DMA QSPI transmit process half complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_QSPI_TxHalfCpltCallback(hqspi);
+}
+
+/**
+ * @brief DMA QSPI communication error callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hqspi->RxXferCount = 0;
+ hqspi->TxXferCount = 0;
+ hqspi->State = HAL_QSPI_STATE_ERROR;
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+
+ HAL_QSPI_ErrorCallback(hqspi);
+}
+
+/**
+ * @brief This function wait a flag state until time out.
+ * @param hqspi: QSPI handle
+ * @param Flag: Flag checked
+ * @param State: Value of the flag expected
+ * @param Timeout: Duration of the time out
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
+ FlagStatus State, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is in expected state */
+ while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hqspi->State = HAL_QSPI_STATE_ERROR;
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function configures the communication registers
+ * @param hqspi: QSPI handle
+ * @param cmd: structure that contains the command configuration information
+ * @param FunctionalMode: functional mode to configured
+ * This parameter can be one of the following values:
+ * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
+ * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
+ * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
+ * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
+ * @retval None
+ */
+static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
+{
+ assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
+
+ if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
+ {
+ /* Configure QSPI: DLR register with the number of data to read or write */
+ WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
+ }
+
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+ {
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ /* Configure QSPI: ABR register with alternate bytes value */
+ WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
+
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ /*---- Command with instruction, address and alternate bytes ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
+ cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
+ cmd->InstructionMode | cmd->Instruction | FunctionalMode));
+
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+ {
+ /* Configure QSPI: AR register with address value */
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);
+ }
+ }
+ else
+ {
+ /*---- Command with instruction and alternate bytes ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
+ cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
+ cmd->Instruction | FunctionalMode));
+ }
+ }
+ else
+ {
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ /*---- Command with instruction and address ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
+ cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
+ cmd->Instruction | FunctionalMode));
+
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+ {
+ /* Configure QSPI: AR register with address value */
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);
+ }
+ }
+ else
+ {
+ /*---- Command with only instruction ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
+ cmd->AddressMode | cmd->InstructionMode | cmd->Instruction |
+ FunctionalMode));
+ }
+ }
+ }
+ else
+ {
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ /* Configure QSPI: ABR register with alternate bytes value */
+ WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
+
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ /*---- Command with address and alternate bytes ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
+ cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
+ cmd->InstructionMode | FunctionalMode));
+
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+ {
+ /* Configure QSPI: AR register with address value */
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);
+ }
+ }
+ else
+ {
+ /*---- Command with only alternate bytes ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
+ cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
+ FunctionalMode));
+ }
+ }
+ else
+ {
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ /*---- Command with only address ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
+ cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
+ FunctionalMode));
+
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+ {
+ /* Configure QSPI: AR register with address value */
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);
+ }
+ }
+ else
+ {
+ /*---- Command with only data phase ----*/
+ if (cmd->DataMode != QSPI_DATA_NONE)
+ {
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
+ cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
+ }
+ }
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+
+#endif /* HAL_QSPI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/src/stm32f4xx_hal_rcc.c b/f4/src/stm32f4xx_hal_rcc.c
index 1a95e89..a5f6570 100755
--- a/f4/src/stm32f4xx_hal_rcc.c
+++ b/f4/src/stm32f4xx_hal_rcc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rcc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -58,7 +58,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -104,10 +104,6 @@
/** @addtogroup RCC_Private_Constants
* @{
*/
-#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
/* Private macro -------------------------------------------------------------*/
@@ -218,6 +214,12 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7,
PCLK2 84 MHz and PCLK1 42 MHz.
Depending on the device voltage range, the maximum frequency should
be adapted accordingly (refer to the product datasheets for more details).
+
+ (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
+ PCLK2 100 MHz and PCLK1 50 MHz.
+ Depending on the device voltage range, the maximum frequency should
+ be adapted accordingly (refer to the product datasheets for more details).
+
@endverbatim
* @{
*/
@@ -226,7 +228,7 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7,
* @brief Resets the RCC clock configuration to the default reset state.
* @note The default reset state of the clock configuration is given below:
* - HSI ON and used as system clock source
- * - HSE, PLL and PLLI2S OFF
+ * - HSE and PLL OFF
* - AHB, APB1 and APB2 prescaler set to 1.
* - CSS, MCO1 and MCO2 OFF
* - All interrupts disabled
@@ -235,31 +237,8 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7,
* - LSI, LSE and RTC clocks
* @retval None
*/
-void HAL_RCC_DeInit(void)
-{
- /* Set HSION bit */
- SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
-
- /* Reset CFGR register */
- CLEAR_REG(RCC->CFGR);
-
- /* Reset HSEON, CSSON, PLLON, PLLI2S */
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON);
-
- /* Reset PLLCFGR register */
- CLEAR_REG(RCC->PLLCFGR);
- SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2);
-
- /* Reset PLLI2SCFGR register */
- CLEAR_REG(RCC->PLLI2SCFGR);
- SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
-
- /* Reset HSEBYP bit */
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-
- /* Disable all interrupts */
- CLEAR_REG(RCC->CIR);
-}
+__weak void HAL_RCC_DeInit(void)
+{}
/**
* @brief Initializes the RCC Oscillators according to the specified parameters in the
@@ -269,9 +248,9 @@ void HAL_RCC_DeInit(void)
* @note The PLL is not disabled when used as system clock.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
@@ -281,7 +260,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
{
@@ -346,8 +326,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
- /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
@@ -486,7 +467,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
/* Check the LSE State */
- if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
+ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
@@ -531,7 +512,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
-
+
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
@@ -548,11 +529,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Configure the main PLL clock source, multiplication and division factors. */
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- RCC_OscInitStruct->PLL.PLLM,
- RCC_OscInitStruct->PLL.PLLN,
- RCC_OscInitStruct->PLL.PLLP,
- RCC_OscInitStruct->PLL.PLLQ);
+ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
+ RCC_OscInitStruct->PLL.PLLM | \
+ (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
+ (((RCC_OscInitStruct->PLL.PLLP >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
+ (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
@@ -666,7 +647,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
}
/* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
+ (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
@@ -683,14 +665,14 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
return HAL_ERROR;
}
}
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
-
+
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
/* Get Start Tick*/
tickstart = HAL_GetTick();
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
@@ -700,7 +682,17 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLRCLK)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
@@ -710,7 +702,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
else
{
- while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
+ while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
@@ -745,7 +737,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
}
/* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
+ (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
@@ -762,14 +755,13 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
return HAL_ERROR;
}
}
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
-
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
/* Get Start Tick*/
tickstart = HAL_GetTick();
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
@@ -779,7 +771,17 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLRCLK)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
@@ -789,7 +791,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
else
{
- while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
+ while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
@@ -863,7 +865,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
* @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
* @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
* @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
- * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
+ * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
+ * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
* @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
* @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
* @param RCC_MCODiv: specifies the MCOx prescaler.
@@ -873,6 +876,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+ * @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
+ * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
* @retval None
*/
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
@@ -899,6 +904,11 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
/* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
+
+ /* This RCC MCO1 enable feature is available only on STM32F410xx devices */
+#if defined(RCC_CFGR_MCO1EN)
+ __HAL_RCC_MCO1_ENABLE();
+#endif /* RCC_CFGR_MCO1EN */
}
else
{
@@ -917,6 +927,11 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
/* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
+
+ /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */
+#if defined(RCC_CFGR_MCO2EN)
+ __HAL_RCC_MCO2_ENABLE();
+#endif /* RCC_CFGR_MCO2EN */
}
}
@@ -973,7 +988,7 @@ void HAL_RCC_DisableCSS(void)
*
* @retval SYSCLK frequency
*/
-uint32_t HAL_RCC_GetSysClockFreq(void)
+__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
uint32_t pllm = 0, pllvco = 0, pllp = 0;
uint32_t sysclockfreq = 0;
@@ -1066,7 +1081,7 @@ uint32_t HAL_RCC_GetPCLK2Freq(void)
* will be configured.
* @retval None
*/
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+__weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
/* Set all possible values for the Oscillator type parameter ---------------*/
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
diff --git a/f4/src/stm32f4xx_hal_rcc_ex.c b/f4/src/stm32f4xx_hal_rcc_ex.c
index 5c150d4..9f2c8b9 100755
--- a/f4/src/stm32f4xx_hal_rcc_ex.c
+++ b/f4/src/stm32f4xx_hal_rcc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rcc_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief Extension RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -58,8 +58,6 @@
/** @addtogroup RCCEx_Private_Constants
* @{
*/
-#define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
-#define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
/**
* @}
*/
@@ -77,7 +75,7 @@
@verbatim
===============================================================================
##### Extended Peripheral Control functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides a set of functions allowing to control the RCC Clocks
frequencies.
@@ -90,7 +88,89 @@
@endverbatim
* @{
*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE, PLL and PLLI2S OFF
+ * - AHB, APB1 and APB2 prescaler set to 1.
+ * - CSS, MCO1 and MCO2 OFF
+ * - All interrupts disabled
+ * @note This function doesn't modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval None
+ */
+void HAL_RCC_DeInit(void)
+{
+ /* Set HSION bit */
+ SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
+
+ /* Reset CFGR register */
+ CLEAR_REG(RCC->CFGR);
+
+ /* Reset HSEON, CSSON, PLLON, PLLI2S */
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON);
+
+ /* Reset PLLCFGR register */
+ CLEAR_REG(RCC->PLLCFGR);
+ SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2);
+
+ /* Reset PLLI2SCFGR register */
+ CLEAR_REG(RCC->PLLI2SCFGR);
+ SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
+
+ /* Reset HSEBYP bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+
+ /* Disable all interrupts */
+ CLEAR_REG(RCC->CIR);
+}
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE and PLL OFF
+ * - AHB, APB1 and APB2 prescaler set to 1.
+ * - CSS, MCO1 and MCO2 OFF
+ * - All interrupts disabled
+ * @note This function doesn't modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval None
+ */
+void HAL_RCC_DeInit(void)
+{
+ /* Set HSION bit */
+ SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
+
+ /* Reset CFGR register */
+ CLEAR_REG(RCC->CFGR);
+
+ /* Reset HSEON, CSSON, PLLON */
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
+
+ /* Reset PLLCFGR register */
+ CLEAR_REG(RCC->PLLCFGR);
+ SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2);
+
+ /* Reset HSEBYP bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+
+ /* Disable all interrupts */
+ CLEAR_REG(RCC->CIR);
+}
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F446xx)
/**
* @brief Initializes the RCC extended peripherals clocks according to the specified
* parameters in the RCC_PeriphCLKInitTypeDef.
@@ -108,22 +188,222 @@
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t tickstart = 0;
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0;
+ uint32_t plli2sp = 0;
+ uint32_t plli2sq = 0;
+ uint32_t plli2sr = 0;
+ uint32_t pllsaip = 0;
+ uint32_t pllsaiq = 0;
+ uint32_t plli2sused = 0;
+ uint32_t pllsaiused = 0;
- /* Check the parameters */
+ /* Check the peripheral clock selection parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
- /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------------*/
-
- /*----------------------- Common configuration SAI/I2S ---------------------------*/
- /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
- factor is common parameters for both peripherals */
- if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
- (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
+
+ /*------------------------ I2S APB1 configuration --------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
{
- /* check for Parameters */
- assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
+
+ /* Configure I2S Clock source */
+ __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
+ /* Enable the PLLI2S when it's used as clock source for I2S */
+ if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
+ {
+ plli2sused = 1;
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- I2S APB2 configuration ----------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
+
+ /* Configure I2S Clock source */
+ __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
+ /* Enable the PLLI2S when it's used as clock source for I2S */
+ if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
+ {
+ plli2sused = 1;
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*--------------------------- SAI1 configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
+
+ /* Configure SAI1 Clock source */
+ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+ /* Enable the PLLI2S when it's used as clock source for SAI */
+ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
+ {
+ plli2sused = 1;
+ }
+ /* Enable the PLLSAI when it's used as clock source for SAI */
+ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
+ {
+ pllsaiused = 1;
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*-------------------------- SAI2 configuration ----------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
+
+ /* Configure SAI2 Clock source */
+ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
+
+ /* Enable the PLLI2S when it's used as clock source for SAI */
+ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
+ {
+ plli2sused = 1;
+ }
+ /* Enable the PLLSAI when it's used as clock source for SAI */
+ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
+ {
+ pllsaiused = 1;
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*----------------------------- RTC configuration --------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+ {
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ PWR->CR |= PWR_CR_DBP;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Reset the Backup domain only if the RTC Clock source selction is modified */
+ if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
+ {
+ /* Store the content of BDCR register before the reset of Backup Domain */
+ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of BDCR register */
+ RCC->BDCR = tmpreg1;
+
+ /* Wait for LSERDY if LSE was enabled */
+ if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- TIM configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+ {
+ /* Configure Timer Prescaler */
+ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- FMPI2C1 Configuration -----------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
+
+ /* Configure the FMPI2C1 clock source */
+ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*------------------------------ CEC Configuration -------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
+
+ /* Configure the CEC clock source */
+ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*------------------------------ CK48 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_CK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
+
+ /* Configure the CK48 clock source */
+ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
+
+ /* Enable the PLLSAI when it's used as clock source for CK48 */
+ if(PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP)
+ {
+ pllsaiused = 1;
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*----------------------------- SDIO Configuration -------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
+
+ /* Configure the SDIO clock source */
+ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*------------------------------ SPDIFRX Configuration ---------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
+
+ /* Configure the SPDIFRX clock source */
+ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
+ /* Enable the PLLI2S when it's used as clock source for SPDIFRX */
+ if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
+ {
+ plli2sused = 1;
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- PLLI2S Configuration ------------------------*/
+ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
+ I2S on APB2 or SPDIFRX */
+ if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
+ {
/* Disable the PLLI2S */
__HAL_RCC_PLLI2S_DISABLE();
/* Get tick */
@@ -135,42 +415,78 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
- }
+ }
}
- /*---------------------------- I2S configuration -------------------------------*/
- /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
- only for I2S configuration */
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+ /* check for common PLLI2S Parameters */
+ assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
+ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+
+ /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+
+ /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
+ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
+ plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
/* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
}
- /*---------------------------- SAI configuration -------------------------------*/
- /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
- be added only for SAI configuration */
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
+ /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
{
- /* Check the PLLI2S division factors */
+ /* Check for PLLI2S Parameters */
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+ /* Check for PLLI2S/DIVQ parameters */
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
-
- /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
- tmpreg = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+
+ /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
+ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
+ plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
/* Configure the PLLI2S division factors */
- /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
- __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg);
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
+
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
- __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
- }
+ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+ }
+
+ /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
+ /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
+ plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
+ plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr);
+ }
+ /*----------------- In Case of PLLI2S is just selected -----------------*/
+ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+ {
+ /* Check for Parameters */
+ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+ }
+
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
/* Get tick */
@@ -184,19 +500,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
return HAL_TIMEOUT;
}
}
- }
-
- /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
-
- /*----------------------- Common configuration SAI/LTDC --------------------*/
- /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
- factor is common parameters for both peripherals */
- if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
- (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*----------------------------- PLLSAI Configuration -----------------------*/
+ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CK48 or SDIO */
+ if(pllsaiused == 1)
{
- /* Check the PLLSAI division factors */
- assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
-
/* Disable PLLSAI Clock */
__HAL_RCC_PLLSAI_DISABLE();
/* Get tick */
@@ -211,39 +521,44 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
}
- /*---------------------------- SAI configuration -------------------------*/
- /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
- be added only for SAI configuration */
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
+ /* Check the PLLSAI division factors */
+ assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
+ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
+
+ /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
{
+ /* check for PLLSAIQ Parameter */
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
+ /* check for PLLSAI/DIVQ Parameter */
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
-
- /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
- tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
+
+ /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
+ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1);
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg);
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0);
+
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
- }
-
- /*---------------------------- LTDC configuration ------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
+ }
+
+ /*------ In Case of PLLSAI is selected as source clock for CK48 ----------*/
+ /* In Case of PLLI2S is selected as source clock for CK48 */
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP))
{
- assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
- assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
-
- /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
- tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
- /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
- /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
- /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg, PeriphClkInit->PLLSAI.PLLSAIR);
- /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
- __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
- }
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
+ /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
+ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
+ /* Configure the PLLSAI division factors */
+ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */
+ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0);
+ }
+
/* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE();
/* Get tick */
@@ -258,69 +573,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
}
}
-
-
- /*---------------------------- RTC configuration ---------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
- {
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
-
- /* Enable write access to Backup domain */
- PWR->CR |= PWR_CR_DBP;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((PWR->CR & PWR_CR_DBP) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Reset the Backup domain only if the RTC Clock source selection is modified */
- if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
- {
- /* Store the content of BDCR register before the reset of Backup Domain */
- tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
- /* RTC Clock selection can be changed only if the Backup Domain is reset */
- __HAL_RCC_BACKUPRESET_FORCE();
- __HAL_RCC_BACKUPRESET_RELEASE();
- /* Restore the Content of BDCR register */
- RCC->BDCR = tmpreg;
- }
-
- /* If LSE is selected as RTC clock source, wait for LSE reactivation */
- if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
- }
-
- /*---------------------------- TIM configuration ---------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
- {
- __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
- }
return HAL_OK;
}
/**
- * @brief Configures the RCC_OscInitStruct according to the internal
- * RCC configuration registers.
+ * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
+ * RCC configuration registers.
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
* will be configured.
* @retval None
@@ -330,24 +588,60 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
uint32_t tempreg;
/* Set all possible values for the extended clock type parameter------------*/
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\
+ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMPI2C1 |\
+ RCC_PERIPHCLK_CK48 | RCC_PERIPHCLK_SDIO |\
+ RCC_PERIPHCLK_SPDIFRX;
- /* Get the PLLI2S Clock configuration -----------------------------------------------*/
+ /* Get the PLLI2S Clock configuration --------------------------------------*/
+ PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM));
PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
- PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+ PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
- /* Get the PLLSAI Clock configuration -----------------------------------------------*/
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+ /* Get the PLLSAI Clock configuration --------------------------------------*/
+ PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIM));
PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
- PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
+ PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1);
PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
- /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
+ /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
- PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
- /* Get the RTC Clock configuration -----------------------------------------------*/
+
+ /* Get the SAI1 clock configuration ----------------------------------------*/
+ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
+
+ /* Get the SAI2 clock configuration ----------------------------------------*/
+ PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
+
+ /* Get the I2S APB1 clock configuration ------------------------------------*/
+ PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
+
+ /* Get the I2S APB2 clock configuration ------------------------------------*/
+ PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
+
+ /* Get the RTC Clock configuration -----------------------------------------*/
tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+ /* Get the CEC clock configuration -----------------------------------------*/
+ PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
+
+ /* Get the FMPI2C1 clock configuration -------------------------------------*/
+ PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
+
+ /* Get the CK48 clock configuration ----------------------------------------*/
+ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
+
+ /* Get the SDIO clock configuration ----------------------------------------*/
+ PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
+
+ /* Get the SPDIFRX clock configuration -------------------------------------*/
+ PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
+
+ /* Get the TIM Prescaler configuration -------------------------------------*/
if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
{
PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
@@ -357,41 +651,194 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
}
}
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
/**
- * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
- * RCC_PeriphCLKInitTypeDef.
+ * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
+ * @note Return 0 if peripheral clock identifier not managed by this API
+ * @param PeriphClk: Peripheral clock identifier
+ * This parameter can be one of the following values:
+ * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
+ * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
+ * @retval Frequency in KHz
+ */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+ uint32_t tmpreg1 = 0;
+ /* This variable used to store the SAI clock frequency (value in Hz) */
+ uint32_t frequency = 0;
+ /* This variable used to store the VCO Input (value in Hz) */
+ uint32_t vcoinput = 0;
+ /* This variable used to store the SAI clock source */
+ uint32_t saiclocksource = 0;
+ if ((PeriphClk == RCC_PERIPHCLK_SAI1) || (PeriphClk == RCC_PERIPHCLK_SAI2))
+ {
+ saiclocksource = RCC->DCKCFGR;
+ saiclocksource &= (RCC_DCKCFGR_SAI1SRC | RCC_DCKCFGR_SAI2SRC);
+ switch (saiclocksource)
+ {
+ case 0: /* PLLSAI is the clock source for SAI*/
+ {
+ /* Configure the PLLSAI division factor */
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ {
+ /* In Case the PLL Source is HSI (Internal Clock) */
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM));
+ }
+ else
+ {
+ /* In Case the PLL Source is HSE (External Clock) */
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)));
+ }
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+ tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
+ frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg1);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+ tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8) + 1);
+ frequency = frequency/(tmpreg1);
+ break;
+ }
+ case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/
+ case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ {
+ /* In Case the PLL Source is HSI (Internal Clock) */
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+ else
+ {
+ /* In Case the PLL Source is HSE (External Clock) */
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)));
+ }
+
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+ tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
+ frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg1);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+ tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1);
+ frequency = frequency/(tmpreg1);
+ break;
+ }
+ case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/
+ case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLL_VCO Input = PLL_SOURCE/PLLM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ {
+ /* In Case the PLL Source is HSI (Internal Clock) */
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* In Case the PLL Source is HSE (External Clock) */
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+ }
+
+ /* PLL_VCO Output = PLL_VCO Input * PLLN */
+ /* SAI_CLK_x = PLL_VCO Output/PLLR */
+ tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28;
+ frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6))/(tmpreg1);
+ break;
+ }
+ case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/
+ {
+ frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+ }
+ case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/
+ {
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ {
+ /* In Case the PLL Source is HSI (Internal Clock) */
+ frequency = (uint32_t)(HSI_VALUE);
+ }
+ else
+ {
+ /* In Case the PLL Source is HSE (External Clock) */
+ frequency = (uint32_t)(HSE_VALUE);
+ }
+ break;
+ }
+ default :
+ {
+ break;
+ }
+ }
+ }
+ return frequency;
+}
+
+#endif /* STM32F446xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Initializes the RCC extended peripherals clocks according to the specified
+ * parameters in the RCC_PeriphCLKInitTypeDef.
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
- * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
+ * contains the configuration information for the Extended Peripherals
+ * clocks(I2S, SAI, LTDC, RTC and TIM).
*
- * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
- * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
- * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
- *
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source; in this case the Backup domain will be reset in
+ * order to modify the RTC Clock source, as consequence RTC registers (including
+ * the backup registers) and RCC_BDCR register are set to their reset values.
+ *
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t tickstart = 0;
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0;
+ uint32_t pllsaip = 0;
+ uint32_t pllsaiq = 0;
+ uint32_t pllsair = 0;
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
- /*---------------------------- I2S configuration ---------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+
+ /*--------------------------- CLK48 Configuration --------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_CK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
+
+ /* Configure the CLK48 clock source */
+ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*------------------------------ SDIO Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
+
+ /* Configure the SDIO clock source */
+ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
+ /*------------------- Common configuration SAI/I2S -------------------------*/
+ /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
+ factor is common parameters for both peripherals */
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
+ (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
+ (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
{
/* check for Parameters */
- assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-#if defined(STM32F411xE)
- assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
-#endif /* STM32F411xE */
+
/* Disable the PLLI2S */
- __HAL_RCC_PLLI2S_DISABLE();
+ __HAL_RCC_PLLI2S_DISABLE();
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLI2S is disabled */
@@ -401,20 +848,52 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
- }
+ }
}
-
-#if defined(STM32F411xE)
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */
- /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
- __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
-#else
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
- /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
-#endif /* STM32F411xE */
+
+ /*---------------------- I2S configuration -------------------------------*/
+ /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
+ only for I2S configuration */
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
+ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
+ }
+
+ /*---------------------------- SAI configuration -------------------------*/
+ /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
+ be added only for SAI configuration */
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
+ {
+ /* Check the PLLI2S division factors */
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
+
+ /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+ }
+
+ /*----------------- In Case of PLLI2S is just selected -----------------*/
+ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+ {
+ /* Check for Parameters */
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+
+ /* Configure the PLLI2S multiplication and division factors */
+ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+ }
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
@@ -430,7 +909,106 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
}
}
-
+ /*--------------------------------------------------------------------------*/
+
+ /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
+ /*----------------------- Common configuration SAI/LTDC --------------------*/
+ /* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division
+ factor is common parameters for these peripherals */
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
+ (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) ||
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48) &&
+ (PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP)))
+ {
+ /* Check the PLLSAI division factors */
+ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
+
+ /* Disable PLLSAI Clock */
+ __HAL_RCC_PLLSAI_DISABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLSAI is disabled */
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /*---------------------------- SAI configuration -------------------------*/
+ /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
+ be added only for SAI configuration */
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
+ {
+ assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
+ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
+
+ /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
+ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1);
+ /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
+ pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair);
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
+ }
+
+ /*---------------------------- LTDC configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
+ {
+ assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
+ assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
+
+ /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
+ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1);
+ /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
+ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR);
+ /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
+ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
+ }
+
+ /*---------------------------- CLK48 configuration ------------------------*/
+ /* Configure the PLLSAI when it is used as clock source for CLK48 */
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == (RCC_PERIPHCLK_CK48)) &&
+ (PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP))
+ {
+ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
+
+ /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
+ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
+ /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
+ pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair);
+ }
+
+ /* Enable PLLSAI Clock */
+ __HAL_RCC_PLLSAI_ENABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLSAI is ready */
+ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /*--------------------------------------------------------------------------*/
+
/*---------------------------- RTC configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
@@ -439,10 +1017,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Enable write access to Backup domain */
PWR->CR |= PWR_CR_DBP;
-
+
/* Get tick */
tickstart = HAL_GetTick();
-
+
while((PWR->CR & PWR_CR_DBP) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
@@ -450,45 +1028,50 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
return HAL_TIMEOUT;
}
}
-
/* Reset the Backup domain only if the RTC Clock source selection is modified */
if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
{
/* Store the content of BDCR register before the reset of Backup Domain */
- tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
__HAL_RCC_BACKUPRESET_RELEASE();
/* Restore the Content of BDCR register */
- RCC->BDCR = tmpreg;
- }
-
- /* If LSE is selected as RTC clock source, wait for LSE reactivation */
- if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
+ RCC->BDCR = tmpreg1;
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ /* Wait for LSERDY if LSE was enabled */
+ if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
{
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
- return HAL_TIMEOUT;
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
}
- }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
-
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- TIM configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+ {
+ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+ }
return HAL_OK;
}
/**
- * @brief Configures the RCC_OscInitStruct according to the internal
+ * @brief Configures the RCC_PeriphCLKInitTypeDef according to the internal
* RCC configuration registers.
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
- * will be configured.
+ * will be configured.
* @retval None
*/
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
@@ -496,28 +1079,1055 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
uint32_t tempreg;
/* Set all possible values for the extended clock type parameter------------*/
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI |\
+ RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC |\
+ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
+ RCC_PERIPHCLK_CK48 | RCC_PERIPHCLK_SDIO;
- /* Get the PLLI2S Clock configuration -----------------------------------------------*/
+ /* Get the PLLI2S Clock configuration --------------------------------------*/
PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
-#if defined(STM32F411xE)
- PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);
-#endif /* STM32F411xE */
- /* Get the RTC Clock configuration -----------------------------------------------*/
+ PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
+ /* Get the PLLSAI Clock configuration --------------------------------------*/
+ PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
+ PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
+ PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
+ /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
+ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
+ PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
+ PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
+ /* Get the RTC Clock configuration -----------------------------------------*/
tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
-}
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
-
-#if defined(STM32F411xE)
-/**
- * @brief Select LSE mode
- *
- * @note This mode is only available for STM32F411xx devices.
- *
- * @param Mode: specifies the LSE mode.
+ /* Get the CK48 clock configuration --------------------------------------*/
+ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
+
+ /* Get the SDIO clock configuration ----------------------------------------*/
+ PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
+
+ if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+ }
+ else
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+ }
+}
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/**
+ * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
+ * RCC_PeriphCLKInitTypeDef.
+ * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
+ *
+ * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
+ * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
+ * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tickstart = 0;
+ uint32_t tmpreg1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*---------------------------- RTC configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+ {
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ PWR->CR |= PWR_CR_DBP;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */
+ if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
+ {
+ /* Store the content of BDCR register before the reset of Backup Domain */
+ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of BDCR register */
+ RCC->BDCR = tmpreg1;
+
+ /* Wait for LSERDY if LSE was enabled */
+ if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- TIM configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+ {
+ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- FMPI2C1 Configuration -----------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
+
+ /* Configure the FMPI2C1 clock source */
+ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- LPTIM1 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
+
+ /* Configure the LPTIM1 clock source */
+ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+ }
+
+ /*---------------------------- I2S Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection));
+
+ /* Configure the I2S clock source */
+ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the RCC_OscInitStruct according to the internal
+ * RCC configuration registers.
+ * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tempreg;
+
+ /* Set all possible values for the extended clock type parameter------------*/
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
+
+ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+ PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+ if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+ }
+ else
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+ }
+ /* Get the FMPI2C1 clock configuration -------------------------------------*/
+ PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
+
+ /* Get the I2S clock configuration -----------------------------------------*/
+ PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE();
+
+
+}
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/**
+ * @brief Initializes the RCC extended peripherals clocks according to the specified
+ * parameters in the RCC_PeriphCLKInitTypeDef.
+ * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * contains the configuration information for the Extended Peripherals
+ * clocks(I2S, SAI, LTDC RTC and TIM).
+ *
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source; in this case the Backup domain will be reset in
+ * order to modify the RTC Clock source, as consequence RTC registers (including
+ * the backup registers) and RCC_BDCR register are set to their reset values.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tickstart = 0;
+ uint32_t tmpreg1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
+ /*----------------------- Common configuration SAI/I2S ----------------------*/
+ /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
+ factor is common parameters for both peripherals */
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
+ (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+
+ /* Disable the PLLI2S */
+ __HAL_RCC_PLLI2S_DISABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLI2S is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /*---------------------------- I2S configuration -------------------------------*/
+ /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
+ only for I2S configuration */
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
+ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
+ }
+
+ /*---------------------------- SAI configuration -------------------------------*/
+ /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
+ be added only for SAI configuration */
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
+ {
+ /* Check the PLLI2S division factors */
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
+
+ /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+ }
+
+ /* Enable the PLLI2S */
+ __HAL_RCC_PLLI2S_ENABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLI2S is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
+ /*----------------------- Common configuration SAI/LTDC --------------------*/
+ /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
+ factor is common parameters for both peripherals */
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
+ (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
+ {
+ /* Check the PLLSAI division factors */
+ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
+
+ /* Disable PLLSAI Clock */
+ __HAL_RCC_PLLSAI_DISABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLSAI is disabled */
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /*---------------------------- SAI configuration -------------------------*/
+ /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
+ be added only for SAI configuration */
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
+ {
+ assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
+ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
+
+ /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
+ }
+
+ /*---------------------------- LTDC configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
+ {
+ assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
+ assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
+
+ /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
+ /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
+ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
+ }
+ /* Enable PLLSAI Clock */
+ __HAL_RCC_PLLSAI_ENABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLSAI is ready */
+ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- RTC configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+ {
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ PWR->CR |= PWR_CR_DBP;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */
+ if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
+ {
+ /* Store the content of BDCR register before the reset of Backup Domain */
+ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of BDCR register */
+ RCC->BDCR = tmpreg1;
+
+ /* Wait for LSERDY if LSE was enabled */
+ if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- TIM configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+ {
+ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the PeriphClkInit according to the internal
+ * RCC configuration registers.
+ * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tempreg;
+
+ /* Set all possible values for the extended clock type parameter------------*/
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
+
+ /* Get the PLLI2S Clock configuration -----------------------------------------------*/
+ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+ PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
+ /* Get the PLLSAI Clock configuration -----------------------------------------------*/
+ PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
+ PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
+ PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
+ /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
+ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
+ PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
+ PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
+ /* Get the RTC Clock configuration -----------------------------------------------*/
+ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+ PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+ if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+ }
+ else
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+ }
+}
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+/**
+ * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
+ * RCC_PeriphCLKInitTypeDef.
+ * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
+ *
+ * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
+ * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
+ * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tickstart = 0;
+ uint32_t tmpreg1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*---------------------------- I2S configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+#if defined(STM32F411xE)
+ assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
+#endif /* STM32F411xE */
+ /* Disable the PLLI2S */
+ __HAL_RCC_PLLI2S_DISABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLI2S is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+#if defined(STM32F411xE)
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+ __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
+#else
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
+ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
+#endif /* STM32F411xE */
+
+ /* Enable the PLLI2S */
+ __HAL_RCC_PLLI2S_ENABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLI2S is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /*---------------------------- RTC configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+ {
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ PWR->CR |= PWR_CR_DBP;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */
+ if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
+ {
+ /* Store the content of BDCR register before the reset of Backup Domain */
+ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of BDCR register */
+ RCC->BDCR = tmpreg1;
+
+ /* Wait for LSERDY if LSE was enabled */
+ if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the RCC_OscInitStruct according to the internal
+ * RCC configuration registers.
+ * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tempreg;
+
+ /* Set all possible values for the extended clock type parameter------------*/
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;
+
+ /* Get the PLLI2S Clock configuration --------------------------------------*/
+ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+#if defined(STM32F411xE)
+ PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);
+#endif /* STM32F411xE */
+ /* Get the RTC Clock configuration -----------------------------------------*/
+ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+ PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+}
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Initializes the RCC Oscillators according to the specified parameters in the
+ * RCC_OscInitTypeDef.
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC Oscillators.
+ * @note The PLL is not disabled when used as system clock.
+ * @note This function add the PLL/PLLR factor management during PLL configuration this feature
+ * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx devices
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+ /*------------------------------- HSE Configuration ------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+ /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
+#if defined(STM32F446xx)
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+#else
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+#endif /* STM32F446xx */
+ {
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the new HSE configuration ---------------------------------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+ /* Check the HSE State */
+ if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is bypassed or disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*----------------------------- HSI Configuration --------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+#if defined(STM32F446xx)
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+#else
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+#endif /* STM32F446xx */
+ {
+ /* When HSI is used as system clock it will not disabled */
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ {
+ return HAL_ERROR;
+ }
+ /* Otherwise, just the calibration is allowed */
+ else
+ {
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ }
+ else
+ {
+ /* Check the HSI State */
+ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+ {
+ /* Enable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*------------------------------ LSI Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+ /* Check the LSI State */
+ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+ {
+ /* Enable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /*------------------------------ LSE Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ PWR->CR |= PWR_CR_DBP;
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the new LSE configuration -----------------------------------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ /* Check the LSE State */
+ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /*-------------------------------- PLL Configuration -----------------------*/
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+ if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ {
+ /* Check if the PLL is used as system clock or not */
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+ {
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+ assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+ assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+ assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+ assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+ assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the main PLL clock source, multiplication and division factors. */
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ RCC_OscInitStruct->PLL.PLLM,
+ RCC_OscInitStruct->PLL.PLLN,
+ RCC_OscInitStruct->PLL.PLLP,
+ RCC_OscInitStruct->PLL.PLLQ,
+ RCC_OscInitStruct->PLL.PLLR);
+
+ /* Enable the main PLL. */
+ __HAL_RCC_PLL_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the RCC_OscInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that will be configured.
+ *
+ * @note This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
+ * @note This function add the PLL/PLLR factor management
+ * @retval None
+ */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ /* Set all possible values for the Oscillator type parameter ---------------*/
+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+
+ /* Get the HSE configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+ }
+ else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+ }
+
+ /* Get the HSI configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+ }
+
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
+
+ /* Get the LSE configuration -----------------------------------------------*/
+ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+ }
+ else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+ }
+
+ /* Get the LSI configuration -----------------------------------------------*/
+ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+ }
+
+ /* Get the PLL configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+ }
+ RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+ RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
+ RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
+ RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
+ RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
+ RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
+}
+#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Select LSE mode
+ *
+ * @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
+ *
+ * @param Mode: specifies the LSE mode.
* This parameter can be one of the following values:
* @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection
* @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection
@@ -537,7 +2147,112 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
}
}
-#endif /* STM32F411xE */
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F446xx)
+/**
+ * @brief Returns the SYSCLK frequency
+ *
+ * @note This function implementation is valide only for STM32F446xx devices.
+ * @note This function add the PLL/PLLR System clock source
+ *
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+ * @note If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * @note The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @note This function can be used by the user application to compute the
+ * baudrate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time SYSCLK changes, this function must be called to update the
+ * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ *
+ * @retval SYSCLK frequency
+ */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+ uint32_t pllm = 0;
+ uint32_t pllvco = 0;
+ uint32_t pllp = 0;
+ uint32_t pllr = 0;
+ uint32_t sysclockfreq = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
+ {
+ sysclockfreq = HSI_VALUE;
+ break;
+ }
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
+ {
+ sysclockfreq = HSE_VALUE;
+ break;
+ }
+ case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */
+ {
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLP */
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+ if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+ }
+ pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
+
+ sysclockfreq = pllvco/pllp;
+ break;
+ }
+ case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */
+ {
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR */
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+ if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+ }
+ pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
+
+ sysclockfreq = pllvco/pllr;
+ break;
+ }
+ default:
+ {
+ sysclockfreq = HSI_VALUE;
+ break;
+ }
+ }
+ return sysclockfreq;
+}
+#endif /* STM32F446xx */
/**
* @}
diff --git a/f4/src/stm32f4xx_hal_rng.c b/f4/src/stm32f4xx_hal_rng.c
index 108fc61..9cb9d0f 100755
--- a/f4/src/stm32f4xx_hal_rng.c
+++ b/f4/src/stm32f4xx_hal_rng.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rng.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
@@ -29,7 +29,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -70,7 +70,9 @@
#ifdef HAL_RNG_MODULE_ENABLED
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
/* Private types -------------------------------------------------------------*/
@@ -129,6 +131,8 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
if(hrng->State == HAL_RNG_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hrng->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_RNG_MspInit(hrng);
}
@@ -498,7 +502,8 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F410xx || STM32F469xx || STM32F479xx */
#endif /* HAL_RNG_MODULE_ENABLED */
diff --git a/f4/src/stm32f4xx_hal_rtc.c b/f4/src/stm32f4xx_hal_rtc.c
index b0f0290..8418c23 100755
--- a/f4/src/stm32f4xx_hal_rtc.c
+++ b/f4/src/stm32f4xx_hal_rtc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rtc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
@@ -108,7 +108,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -218,6 +218,8 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
if(hrtc->State == HAL_RTC_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hrtc->Lock = HAL_UNLOCKED;
/* Initialize RTC MSP */
HAL_RTC_MspInit(hrtc);
}
@@ -545,9 +547,13 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
+ * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
+ * value in second fraction ratio with time unit following generic formula:
+ * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
+ * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
* @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
- * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
- * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers until current date is read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
@@ -557,8 +563,11 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
- /* Get subseconds values from the correspondent registers*/
+ /* Get subseconds structure field from the corresponding register */
sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
+
+ /* Get SecondFraction structure field from the corresponding register field*/
+ sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
/* Get the TR register */
tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
@@ -1126,7 +1135,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
}
/**
- * @brief Deactive the specified RTC Alarm
+ * @brief Deactivate the specified RTC Alarm
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param Alarm: Specifies the Alarm.
diff --git a/f4/src/stm32f4xx_hal_rtc_ex.c b/f4/src/stm32f4xx_hal_rtc_ex.c
index c549ac9..d25413e 100755
--- a/f4/src/stm32f4xx_hal_rtc_ex.c
+++ b/f4/src/stm32f4xx_hal_rtc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rtc_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extension peripheral:
@@ -40,7 +40,7 @@
(+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
function.
(+) The TIMESTAMP alternate function can be mapped either to RTC_AF1 (PC13)
- or RTC_AF2 (PI8) depending on the value of TSINSEL bit in
+ or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TSINSEL bit in
RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTimeStamp()
or HAL_RTC_SetTimeStamp_IT() function.
@@ -53,7 +53,7 @@
HAL_RTC_SetTamper() function. You can configure RTC Tamper in interrupt
mode using HAL_RTC_SetTamper_IT() function.
(+) The TAMPER1 alternate function can be mapped either to RTC_AF1 (PC13)
- or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in
+ or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TAMP1INSEL bit in
RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTamper()
or HAL_RTC_SetTamper_IT() function.
@@ -69,7 +69,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -149,8 +149,10 @@
* falling edge of the related pin.
* @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
- * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPPIN_POS1: PI8/PA0 is selected as RTC TimeStamp Pin.
+ * (PI8 for all STM32 devices except for STM32F446xx devices the PA0 is used)
+ * @arg RTC_TIMESTAMPPIN_PA0: PA0 is selected as RTC TimeStamp Pin only for STM32F446xx devices
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
@@ -208,8 +210,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS
* falling edge of the related pin.
* @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
- * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. (not applicable in the case of STM32F446xx devices)
+ * @arg RTC_TIMESTAMPPIN_PA0: PA0 is selected as RTC TimeStamp Pin only for STM32F446xx devices
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
@@ -741,10 +744,32 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
+
+ /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
+ if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
+ {
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
- /* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
@@ -754,14 +779,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
-
+
return HAL_TIMEOUT;
- }
+ }
}
/* Clear the Wake-up Timer clock source bits in CR register */
@@ -810,10 +835,32 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
+
+ /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
+ if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
+ {
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
- /* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
@@ -823,14 +870,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
+
hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
-
+
return HAL_TIMEOUT;
- }
+ }
}
/* Configure the Wake-up Timer counter */
diff --git a/f4/src/stm32f4xx_hal_sai.c b/f4/src/stm32f4xx_hal_sai.c
index a18b47d..4c63b2a 100755
--- a/f4/src/stm32f4xx_hal_sai.c
+++ b/f4/src/stm32f4xx_hal_sai.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sai.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief SAI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Audio Interface (SAI) peripheral:
@@ -47,7 +47,15 @@
-@- The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
will be managed using the macros __SAI_ENABLE_IT() and __SAI_DISABLE_IT()
inside the transmit and receive process.
-
+
+ [..]
+ (@) SAI Clock Source configuration is managed differently depending on the selected
+ STM32F4 devices :
+ (+@) For STM32F446xx devices, the configuration is managed through RCCEx_PeriphCLKConfig()
+ function in the HAL RCC drivers
+ (+@) For STM32F439xx/STM32F437xx/STM32F429xx/STM32F427xx devices, the configuration
+ is managed within HAL SAI drivers through HAL_SAI_Init() function using
+ ClockSource field of SAI_InitTypeDef structure.
[..]
(@) Make sure that either:
(+@) I2S PLL is configured or
@@ -124,7 +132,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -165,12 +173,32 @@
#ifdef HAL_SAI_MODULE_ENABLED
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
+/** @defgroup SAI_Private_Typedefs SAI Private Typedefs
+ * @{
+ */
+typedef enum {
+ SAI_MODE_DMA,
+ SAI_MODE_IT
+}SAI_ModeTypedef;
+/**
+ * @}
+ */
/* Private define ------------------------------------------------------------*/
+/** @defgroup SAI_Private_Constants SAI Private Constants
+ * @{
+ */
+#define SAI_FIFO_SIZE 8
+#define SAI_DEFAULT_TIMEOUT 4
+/**
+ * @}
+ */
+
/* SAI registers Masks */
-#define CR1_CLEAR_MASK ((uint32_t)0xFF07C010)
+#define CR1_CLEAR_MASK ((uint32_t)0xFF04C010)
#define FRCR_CLEAR_MASK ((uint32_t)0xFFF88000)
#define SLOTR_CLEAR_MASK ((uint32_t)0x0000F020)
@@ -178,15 +206,28 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+static void SAI_FillFifo(SAI_HandleTypeDef *hsai);
+static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode);
+static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+
+static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai);
+
static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma);
static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);
static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void SAI_DMAError(DMA_HandleTypeDef *hdma);
-/* Private functions ---------------------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
-/** @defgroup SAI_Private_Functions SAI Private Functions
+/** @defgroup SAI_Exported_Functions SAI Exported Functions
* @{
*/
@@ -221,6 +262,50 @@ static void SAI_DMAError(DMA_HandleTypeDef *hdma);
* @{
*/
+/**
+ * @brief Initializes the structure FrameInit, SlotInit and the low part of
+ * Init according to the specified parameters and call the function
+ * HAL_SAI_Init to initialize the SAI block.
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param protocol : one of the supported protocol @ref SAI_Protocol
+ * @param datasize : one of the supported datasize @ref SAI_Protocol_DataSize
+ * the configuration information for SAI module.
+ * @param nbslot : Number of slot.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
+ assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
+
+ switch(protocol)
+ {
+ case SAI_I2S_STANDARD :
+ case SAI_I2S_MSBJUSTIFIED :
+ case SAI_I2S_LSBJUSTIFIED :
+ status = SAI_InitI2S(hsai, protocol, datasize, nbslot);
+ break;
+ case SAI_PCM_LONG :
+ case SAI_PCM_SHORT :
+ status = SAI_InitPCM(hsai, protocol, datasize, nbslot);
+ break;
+ default :
+ status = HAL_ERROR;
+ break;
+ }
+
+ if(status == HAL_OK)
+ {
+ status = HAL_SAI_Init(hsai);
+ }
+
+ return status;
+}
+
/**
* @brief Initializes the SAI according to the specified parameters
* in the SAI_InitTypeDef and create the associated handle.
@@ -230,12 +315,10 @@ static void SAI_DMAError(DMA_HandleTypeDef *hdma);
*/
HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
{
- uint32_t tmpreg = 0;
- uint32_t tmpclock = 0, tmp2clock = 0;
- /* This variable used to store the VCO Input (value in Hz) */
- uint32_t vcoinput = 0;
+ uint32_t tmpclock = 0;
+
/* This variable used to store the SAI_CK_x (value in Hz) */
- uint32_t saiclocksource = 0;
+ uint32_t freq = 0;
/* Check the SAI handle allocation */
if(hsai == NULL)
@@ -244,8 +327,10 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
}
/* Check the SAI Block parameters */
+ assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));
assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));
assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));
+ assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt));
assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize));
assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));
assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));
@@ -253,7 +338,9 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));
assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));
assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));
- assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));
+ assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode));
+ assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode));
+ assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState));
/* Check the SAI Block Frame parameters */
assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));
@@ -270,6 +357,9 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
if(hsai->State == HAL_SAI_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hsai->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_SAI_MspInit(hsai);
}
@@ -277,179 +367,76 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
hsai->State = HAL_SAI_STATE_BUSY;
/* Disable the selected SAI peripheral */
- __HAL_SAI_DISABLE(hsai);
-
- /* SAI Block Configuration ------------------------------------------------------------*/
- /* SAI Block_x CR1 Configuration */
- /* Get the SAI Block_x CR1 value */
- tmpreg = hsai->Instance->CR1;
- /* Clear MODE, PRTCFG, DS, LSBFIRST, CKSTR, SYNCEN, OUTDRIV, NODIV, and MCKDIV bits */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure SAI_Block_x: Audio Protocol, Data Size, first transmitted bit, Clock strobing
- edge, Synchronization mode, Output drive, Master Divider and FIFO level */
- /* Set PRTCFG bits according to Protocol value */
- /* Set DS bits according to DataSize value */
- /* Set LSBFIRST bit according to FirstBit value */
- /* Set CKSTR bit according to ClockStrobing value */
- /* Set SYNCEN bit according to Synchro value */
- /* Set OUTDRIV bit according to OutputDrive value */
- /* Set NODIV bit according to NoDivider value */
- tmpreg |= (uint32_t)(hsai->Init.Protocol |
- hsai->Init.AudioMode |
- hsai->Init.DataSize |
- hsai->Init.FirstBit |
- hsai->Init.ClockStrobing |
- hsai->Init.Synchro |
- hsai->Init.OutputDrive |
- hsai->Init.NoDivider);
- /* Write to SAI_Block_x CR1 */
- hsai->Instance->CR1 = tmpreg;
-
- /* SAI Block_x CR2 Configuration */
- /* Get the SAIBlock_x CR2 value */
- tmpreg = hsai->Instance->CR2;
- /* Clear FTH bits */
- tmpreg &= ~(SAI_xCR2_FTH);
- /* Configure the FIFO Level */
- /* Set FTH bits according to SAI_FIFOThreshold value */
- tmpreg |= (uint32_t)(hsai->Init.FIFOThreshold);
- /* Write to SAI_Block_x CR2 */
- hsai->Instance->CR2 = tmpreg;
-
- /* SAI Block_x Frame Configuration -----------------------------------------*/
- /* Get the SAI Block_x FRCR value */
- tmpreg = hsai->Instance->FRCR;
- /* Clear FRL, FSALL, FSDEF, FSPOL, FSOFF bits */
- tmpreg &= FRCR_CLEAR_MASK;
- /* Configure SAI_Block_x Frame: Frame Length, Active Frame Length, Frame Synchronization
- Definition, Frame Synchronization Polarity and Frame Synchronization Polarity */
- /* Set FRL bits according to SAI_FrameLength value */
- /* Set FSALL bits according to SAI_ActiveFrameLength value */
- /* Set FSDEF bit according to SAI_FSDefinition value */
- /* Set FSPOL bit according to SAI_FSPolarity value */
- /* Set FSOFF bit according to SAI_FSOffset value */
- tmpreg |= (uint32_t)((uint32_t)(hsai->FrameInit.FrameLength - 1) |
- hsai->FrameInit.FSOffset |
- hsai->FrameInit.FSDefinition |
- hsai->FrameInit.FSPolarity |
- (uint32_t)((hsai->FrameInit.ActiveFrameLength - 1) << 8));
-
- /* Write to SAI_Block_x FRCR */
- hsai->Instance->FRCR = tmpreg;
-
- /* SAI Block_x SLOT Configuration ------------------------------------------*/
- /* Get the SAI Block_x SLOTR value */
- tmpreg = hsai->Instance->SLOTR;
- /* Clear FBOFF, SLOTSZ, NBSLOT, SLOTEN bits */
- tmpreg &= SLOTR_CLEAR_MASK;
- /* Configure SAI_Block_x Slot: First bit offset, Slot size, Number of Slot in
- audio frame and slots activated in audio frame */
- /* Set FBOFF bits according to SAI_FirstBitOffset value */
- /* Set SLOTSZ bits according to SAI_SlotSize value */
- /* Set NBSLOT bits according to SAI_SlotNumber value */
- /* Set SLOTEN bits according to SAI_SlotActive value */
- tmpreg |= (uint32_t)(hsai->SlotInit.FirstBitOffset |
- hsai->SlotInit.SlotSize |
- hsai->SlotInit.SlotActive |
- (uint32_t)((hsai->SlotInit.SlotNumber - 1) << 8));
-
- /* Write to SAI_Block_x SLOTR */
- hsai->Instance->SLOTR = tmpreg;
-
- /* SAI Block_x Clock Configuration -----------------------------------------*/
- /* Check the Clock parameters */
- assert_param(IS_SAI_CLK_SOURCE(hsai->Init.ClockSource));
-
- /* SAI Block clock source selection */
- if(hsai->Instance == SAI1_Block_A)
- {
- __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(hsai->Init.ClockSource);
- }
- else
- {
- __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG((uint32_t)(hsai->Init.ClockSource << 2));
- }
+ SAI_Disable(hsai);
- /* VCO Input Clock value calculation */
- if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
- {
- /* In Case the PLL Source is HSI (Internal Clock) */
- vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
- }
- else
- {
- /* In Case the PLL Source is HSE (External Clock) */
- vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
- }
-
- /* SAI_CLK_x : SAI Block Clock configuration for different clock sources selected */
- if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLSAI)
- {
- /* Configure the PLLI2S division factor */
- /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
- /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
- /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
- tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
- saiclocksource = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
-
- /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
- tmpreg = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8) + 1);
- saiclocksource = saiclocksource/(tmpreg);
-
- }
- else if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLI2S)
- {
- /* Configure the PLLI2S division factor */
- /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
- /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
- /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
- tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
- saiclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
-
- /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
- tmpreg = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1);
- saiclocksource = saiclocksource/(tmpreg);
- }
- else /* sConfig->ClockSource == SAI_CLKSource_Ext */
- {
- /* Enable the External Clock selection */
- __HAL_RCC_I2S_CONFIG(RCC_I2SCLKSOURCE_EXT);
+ /* SAI Block Synchro Configuration -----------------------------------------*/
+ SAI_BlockSynchroConfig(hsai);
- saiclocksource = EXTERNAL_CLOCK_VALUE;
- }
-
/* Configure Master Clock using the following formula :
MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2) with MCLK_x = 256 * FS
FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256
MCKDIV[3:0] = SAI_CK_x / FS * 512 */
- if(hsai->Init.NoDivider == SAI_MASTERDIVIDER_ENABLE)
+ if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)
{
+ /* Get SAI clock source based on Source clock selection from RCC */
+ freq = SAI_GetInputClock(hsai);
+
/* (saiclocksource x 10) to keep Significant digits */
- tmpclock = (((saiclocksource * 10) / ((hsai->Init.AudioFrequency) * 512)));
+ tmpclock = (((freq * 10) / ((hsai->Init.AudioFrequency) * 512)));
- /* Get the result of modulo division */
- tmp2clock = (tmpclock % 10);
+ hsai->Init.Mckdiv = tmpclock / 10;
- /* Round result to the nearest integer*/
- if (tmp2clock > 8)
- {
- tmpclock = ((tmpclock / 10) + 1);
- }
- else
+ /* Round result to the nearest integer */
+ if((tmpclock % 10) > 8)
{
- tmpclock = (tmpclock / 10);
+ hsai->Init.Mckdiv+= 1;
}
- /*Set MCKDIV value in CR1 register*/
- hsai->Instance->CR1 |= (tmpclock << 20);
-
}
- /* Initialize the error code */
+ /* SAI Block Configuration ------------------------------------------------------------*/
+ /* SAI CR1 Configuration */
+ hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \
+ SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\
+ SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \
+ SAI_xCR1_NODIV | SAI_xCR1_MCKDIV);
+
+ hsai->Instance->CR1|= (hsai->Init.AudioMode | hsai->Init.Protocol | \
+ hsai->Init.DataSize | hsai->Init.FirstBit | \
+ hsai->Init.ClockStrobing | hsai->Init.Synchro | \
+ hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \
+ hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) | hsai->Init.CompandingMode);
+
+ /* SAI CR2 Configuration */
+ hsai->Instance->CR2&= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP);
+ hsai->Instance->CR2|= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);
+
+
+ /* SAI Frame Configuration -----------------------------------------*/
+ hsai->Instance->FRCR&=(~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \
+ SAI_xFRCR_FSPO | SAI_xFRCR_FSOFF));
+ hsai->Instance->FRCR|=((hsai->FrameInit.FrameLength - 1) |
+ hsai->FrameInit.FSOffset |
+ hsai->FrameInit.FSDefinition |
+ hsai->FrameInit.FSPolarity |
+ ((hsai->FrameInit.ActiveFrameLength - 1) << 8));
+
+ /* SAI Block_x SLOT Configuration ------------------------------------------*/
+ /* This register has no meaning in AC 97 and SPDIF audio protocol */
+ hsai->Instance->SLOTR&= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \
+ SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN ));
+
+ hsai->Instance->SLOTR|= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize
+ | hsai->SlotInit.SlotActive | ((hsai->SlotInit.SlotNumber - 1) << 8);
+
+ /* Initialise the error code */
hsai->ErrorCode = HAL_SAI_ERROR_NONE;
-
+
/* Initialize the SAI state */
hsai->State= HAL_SAI_STATE_READY;
-
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsai);
+
return HAL_OK;
}
@@ -469,6 +456,16 @@ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
hsai->State = HAL_SAI_STATE_BUSY;
+ /* Disabled All interrupt and clear all the flag */
+ hsai->Instance->IMR = 0;
+ hsai->Instance->CLRFR = 0xFFFFFFFF;
+
+ /* Disable the SAI */
+ SAI_Disable(hsai);
+
+ /* Flush the fifo */
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_SAI_MspDeInit(hsai);
@@ -568,7 +565,7 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
* @param Timeout: Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint16_t* pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart = 0;
@@ -583,22 +580,45 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint16_t* pData, uin
__HAL_LOCK(hsai);
hsai->State = HAL_SAI_STATE_BUSY_TX;
-
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+ hsai->pBuffPtr = pData;
+
/* Check if the SAI is already enabled */
if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
{
+ /* fill the fifo with data before to enabled the SAI */
+ SAI_FillFifo(hsai);
/* Enable SAI peripheral */
__HAL_SAI_ENABLE(hsai);
}
- while(Size > 0)
+ while(hsai->XferCount > 0)
{
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait the FIFO to be empty */
- while(__HAL_SAI_GET_FLAG(hsai, SAI_xSR_FREQ) == RESET)
+ /* Write data if the FIFO is not full */
+ if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
{
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ hsai->Instance->DR = (*hsai->pBuffPtr++);
+ }
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr);
+ hsai->pBuffPtr+= 2;
+ }
+ else
+ {
+ hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
+ hsai->pBuffPtr+= 4;
+ }
+ hsai->XferCount--;
+ }
+ else
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
@@ -616,11 +636,9 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint16_t* pData, uin
return HAL_TIMEOUT;
}
}
- }
- hsai->Instance->DR = (*pData++);
- Size--;
+ }
}
-
+
hsai->State = HAL_SAI_STATE_READY;
/* Process Unlocked */
@@ -643,10 +661,10 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint16_t* pData, uin
* @param Timeout: Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart = 0;
-
+
if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
@@ -658,23 +676,44 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint16_t *pData, uint
__HAL_LOCK(hsai);
hsai->State = HAL_SAI_STATE_BUSY_RX;
-
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+
/* Check if the SAI is already enabled */
if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
{
/* Enable SAI peripheral */
__HAL_SAI_ENABLE(hsai);
}
-
+
/* Receive data */
- while(Size > 0)
+ while(hsai->XferCount > 0)
{
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until RXNE flag is set */
- while(__HAL_SAI_GET_FLAG(hsai, SAI_xSR_FREQ) == RESET)
+
+ if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)
{
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ (*hsai->pBuffPtr++) = hsai->Instance->DR;
+ }
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ *((uint16_t*)hsai->pBuffPtr) = hsai->Instance->DR;
+ hsai->pBuffPtr+= 2;
+ }
+ else
+ {
+ *((uint32_t*)hsai->pBuffPtr) = hsai->Instance->DR;
+ hsai->pBuffPtr+= 4;
+ }
+ hsai->XferCount--;
+ }
+ else
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
@@ -693,11 +732,8 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint16_t *pData, uint
}
}
}
-
- (*pData++) = hsai->Instance->DR;
- Size--;
}
-
+
hsai->State = HAL_SAI_STATE_READY;
/* Process Unlocked */
@@ -719,70 +755,54 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint16_t *pData, uint
* @param Size: Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size)
-{
- if(hsai->State == HAL_SAI_STATE_READY)
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+ if(hsai->State == HAL_SAI_STATE_READY)
{
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
- hsai->pTxBuffPtr = pData;
- hsai->TxXferSize = Size;
- hsai->TxXferCount = Size;
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
/* Process Locked */
__HAL_LOCK(hsai);
hsai->State = HAL_SAI_STATE_BUSY_TX;
- /* Transmit data */
- hsai->Instance->DR = (*hsai->pTxBuffPtr++);
- hsai->TxXferCount--;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsai);
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit;
+ }
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit;
+ }
+ else
+ {
+ hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit;
+ }
/* Enable FRQ and OVRUDR interrupts */
- __HAL_SAI_ENABLE_IT(hsai, (SAI_IT_FREQ | SAI_IT_OVRUDR));
-
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
/* Check if the SAI is already enabled */
if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
{
+ /* Fill the fifo before starting the communication */
+ SAI_FillFifo(hsai);
+
/* Enable SAI peripheral */
__HAL_SAI_ENABLE(hsai);
}
-
-
- return HAL_OK;
- }
- else if(hsai->State == HAL_SAI_STATE_BUSY_TX)
- {
- /* Process Locked */
- __HAL_LOCK(hsai);
-
- /* Transmit data */
- hsai->Instance->DR = (*hsai->pTxBuffPtr++);
-
- hsai->TxXferCount--;
-
- if(hsai->TxXferCount == 0)
- {
- /* Disable FREQ and OVRUDR interrupts */
- __HAL_SAI_DISABLE_IT(hsai, (SAI_IT_FREQ | SAI_IT_OVRUDR));
-
- hsai->State = HAL_SAI_STATE_READY;
-
- HAL_SAI_TxCpltCallback(hsai);
- }
-
/* Process Unlocked */
__HAL_UNLOCK(hsai);
return HAL_OK;
}
-
else
{
return HAL_BUSY;
@@ -797,8 +817,9 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint16_t *pData,
* @param Size: Amount of data to be received
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
{
+
if(hsai->State == HAL_SAI_STATE_READY)
{
if((pData == NULL) || (Size == 0))
@@ -806,17 +827,29 @@ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, u
return HAL_ERROR;
}
- hsai->pRxBuffPtr = pData;
- hsai->RxXferSize = Size;
- hsai->RxXferCount = Size;
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
/* Process Locked */
__HAL_LOCK(hsai);
hsai->State = HAL_SAI_STATE_BUSY_RX;
-
+
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit;
+ }
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit;
+ }
+ else
+ {
+ hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit;
+ }
/* Enable TXE and OVRUDR interrupts */
- __HAL_SAI_ENABLE_IT(hsai, (SAI_IT_FREQ | SAI_IT_OVRUDR));
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
/* Check if the SAI is already enabled */
if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
@@ -830,31 +863,6 @@ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, u
return HAL_OK;
}
- else if(hsai->State == HAL_SAI_STATE_BUSY_RX)
- {
- /* Process Locked */
- __HAL_LOCK(hsai);
-
- /* Receive data */
- (*hsai->pRxBuffPtr++) = hsai->Instance->DR;
-
- hsai->RxXferCount--;
-
- if(hsai->RxXferCount == 0)
- {
- /* Disable TXE and OVRUDR interrupts */
- __HAL_SAI_DISABLE_IT(hsai, (SAI_IT_FREQ | SAI_IT_OVRUDR));
-
- hsai->State = HAL_SAI_STATE_READY;
- HAL_SAI_RxCpltCallback(hsai);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsai);
-
- return HAL_OK;
- }
-
else
{
return HAL_BUSY;
@@ -875,7 +883,6 @@ HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)
/* Pause the audio file playing by disabling the SAI DMA requests */
hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
-
/* Process Unlocked */
__HAL_UNLOCK(hsai);
@@ -896,9 +903,8 @@ HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
/* Enable the SAI DMA requests */
hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
-
/* If the SAI peripheral is still not enabled, enable it */
- if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0)
+ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
{
/* Enable SAI peripheral */
__HAL_SAI_ENABLE(hsai);
@@ -912,7 +918,7 @@ HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
/**
* @brief Stops the audio stream playing from the Media.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL status
*/
@@ -936,7 +942,47 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
}
/* Disable SAI peripheral */
- __HAL_SAI_DISABLE(hsai);
+ SAI_Disable(hsai);
+
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort the current transfer and disbaled the SAI.
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
+{
+ /* Disable the SAI DMA request */
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+ /* Abort the SAI DMA Tx Stream */
+ if(hsai->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hsai->hdmatx);
+ }
+ /* Abort the SAI DMA Rx Stream */
+ if(hsai->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hsai->hdmarx);
+ }
+
+ /* Disabled All interrupt and clear all the flag */
+ hsai->Instance->IMR = 0;
+ hsai->Instance->CLRFR = 0xFFFFFFFF;
+
+ /* Disable SAI peripheral */
+ SAI_Disable(hsai);
+
+ /* Flush the fifo */
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
hsai->State = HAL_SAI_STATE_READY;
@@ -945,6 +991,7 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
return HAL_OK;
}
+
/**
* @brief Transmits an amount of data in no-blocking mode with DMA.
* @param hsai: pointer to a SAI_HandleTypeDef structure that contains
@@ -953,52 +1000,55 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
* @param Size: Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
{
uint32_t *tmp;
-
+
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
-
+
if(hsai->State == HAL_SAI_STATE_READY)
{
- hsai->pTxBuffPtr = pData;
- hsai->TxXferSize = Size;
- hsai->TxXferCount = Size;
-
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+
/* Process Locked */
__HAL_LOCK(hsai);
-
+
hsai->State = HAL_SAI_STATE_BUSY_TX;
-
+
/* Set the SAI Tx DMA Half transfer complete callback */
hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt;
-
+
/* Set the SAI TxDMA transfer complete callback */
hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt;
-
+
/* Set the DMA error callback */
hsai->hdmatx->XferErrorCallback = SAI_DMAError;
-
+
/* Enable the Tx DMA Stream */
tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hsai->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsai->Instance->DR, hsai->TxXferSize);
-
+ HAL_DMA_Start_IT(hsai->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsai->Instance->DR, hsai->XferSize);
+
/* Check if the SAI is already enabled */
if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
{
/* Enable SAI peripheral */
__HAL_SAI_ENABLE(hsai);
}
-
+
+ /* Enable the interrupts for error handling */
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
/* Enable SAI Tx DMA Request */
hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hsai);
-
+
return HAL_OK;
}
else
@@ -1015,7 +1065,7 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData,
* @param Size: Amount of data to be received
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
{
uint32_t *tmp;
@@ -1023,44 +1073,47 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData,
{
return HAL_ERROR;
}
-
+
if(hsai->State == HAL_SAI_STATE_READY)
{
- hsai->pRxBuffPtr = pData;
- hsai->RxXferSize = Size;
- hsai->RxXferCount = Size;
-
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+
/* Process Locked */
__HAL_LOCK(hsai);
hsai->State = HAL_SAI_STATE_BUSY_RX;
-
+
/* Set the SAI Rx DMA Half transfer complete callback */
hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt;
-
+
/* Set the SAI Rx DMA transfer complete callback */
hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt;
-
+
/* Set the DMA error callback */
hsai->hdmarx->XferErrorCallback = SAI_DMAError;
-
+
/* Enable the Rx DMA Stream */
tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, *(uint32_t*)tmp, hsai->RxXferSize);
-
+ HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, *(uint32_t*)tmp, hsai->XferSize);
+
/* Check if the SAI is already enabled */
if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
{
/* Enable SAI peripheral */
__HAL_SAI_ENABLE(hsai);
}
-
+
+ /* Enable the interrupts for error handling */
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
/* Enable SAI Rx DMA Request */
hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hsai);
-
+
return HAL_OK;
}
else
@@ -1070,66 +1123,158 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData,
}
/**
- * @brief This function handles SAI interrupt request.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @brief Enable the tx mute mode.
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
+ * @param val : value sent during the mute @ref SAI_Block_Mute_Value
* @retval HAL status
*/
-void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
+HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)
{
- uint32_t tmp1 = 0, tmp2 = 0;
+ assert_param(IS_SAI_BLOCK_MUTE_VALUE(val));
- if(hsai->State == HAL_SAI_STATE_BUSY_RX)
+ if(hsai->State != HAL_SAI_STATE_RESET)
{
- tmp1 = __HAL_SAI_GET_FLAG(hsai, SAI_xSR_FREQ);
- tmp2 = __HAL_SAI_GET_IT_SOURCE(hsai, SAI_IT_FREQ);
- /* SAI in mode Receiver --------------------------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
- {
- HAL_SAI_Receive_IT(hsai, NULL, 0);
- }
-
- tmp1 = __HAL_SAI_GET_FLAG(hsai, SAI_FLAG_OVRUDR);
- tmp2 = __HAL_SAI_GET_IT_SOURCE(hsai, SAI_IT_OVRUDR);
- /* SAI Overrun error interrupt occurred ----------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
- {
- /* Change the SAI error code */
- hsai->ErrorCode = HAL_SAI_ERROR_OVR;
+ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | val);
+ return HAL_OK;
+ }
+ return HAL_ERROR;
+}
- /* Clear the SAI Overrun flag */
- __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
- /* Set the SAI state ready to be able to start again the process */
- hsai->State = HAL_SAI_STATE_READY;
- HAL_SAI_ErrorCallback(hsai);
- }
+/**
+ * @brief Disable the tx mute mode.
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)
+{
+ if(hsai->State != HAL_SAI_STATE_RESET)
+ {
+ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
+ return HAL_OK;
}
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Enable the rx mute detection.
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param callback : function called when the mute is detected
+ * @param counter : number a data before mute detection max 63.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
+{
+ assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter));
- if(hsai->State == HAL_SAI_STATE_BUSY_TX)
- {
- tmp1 = __HAL_SAI_GET_FLAG(hsai, SAI_xSR_FREQ);
- tmp2 = __HAL_SAI_GET_IT_SOURCE(hsai, SAI_IT_FREQ);
- /* SAI in mode Transmitter -----------------------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
- {
- HAL_SAI_Transmit_IT(hsai, NULL, 0);
- }
+ if(hsai->State != HAL_SAI_STATE_RESET)
+ {
+ /* set the mute counter */
+ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);
+ SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << 6));
+ hsai->mutecallback = callback;
+ /* enable the IT interrupt */
+ __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);
+ return HAL_OK;
+ }
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Disable the rx mute detection.
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)
+{
+ if(hsai->State != HAL_SAI_STATE_RESET)
+ {
+ /* set the mutecallback to NULL */
+ hsai->mutecallback = (SAIcallback)NULL;
+ /* enable the IT interrupt */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET);
+ return HAL_OK;
+ }
+ return HAL_ERROR;
+}
+
+/**
+ * @brief This function handles SAI interrupt request.
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
+{
+ if(hsai->State != HAL_SAI_STATE_RESET)
+ {
+ uint32_t tmpFlag = hsai->Instance->SR;
+ uint32_t tmpItSource = hsai->Instance->IMR;
+
+ if(((tmpFlag & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((tmpItSource & SAI_IT_FREQ) == SAI_IT_FREQ))
+ {
+ hsai->InterruptServiceRoutine(hsai);
+ }
- tmp1 = __HAL_SAI_GET_FLAG(hsai, SAI_FLAG_OVRUDR);
- tmp2 = __HAL_SAI_GET_IT_SOURCE(hsai, SAI_IT_OVRUDR);
- /* SAI Underrun error interrupt occurred ---------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
+ /* check the flag only if one of them is set */
+ if(tmpFlag != 0x00000000)
{
- /* Change the SAI error code */
- hsai->ErrorCode = HAL_SAI_ERROR_UDR;
+ /* SAI Overrun error interrupt occurred ----------------------------------*/
+ if(((tmpFlag & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((tmpItSource & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))
+ {
+ /* Clear the SAI Overrun flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+ /* Change the SAI error code */
+ hsai->ErrorCode = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR);
+ /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
+ HAL_SAI_ErrorCallback(hsai);
+ }
+
+ /* SAI mutedet interrupt occurred ----------------------------------*/
+ if(((tmpFlag & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((tmpItSource & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))
+ {
+ /* Clear the SAI mutedet flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);
+ /* call the call back function */
+ if(hsai->mutecallback != (SAIcallback)NULL)
+ {
+ /* inform the user that an RX mute event has been detected */
+ hsai->mutecallback();
+ }
+ }
+
+ /* SAI AFSDET interrupt occurred ----------------------------------*/
+ if(((tmpFlag & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((tmpItSource & SAI_IT_AFSDET) == SAI_IT_AFSDET))
+ {
+ /* Change the SAI error code */
+ hsai->ErrorCode = HAL_SAI_ERROR_AFSDET;
+ HAL_SAI_Abort(hsai);
+ HAL_SAI_ErrorCallback(hsai);
+ }
+
+ /* SAI LFSDET interrupt occurred ----------------------------------*/
+ if(((tmpFlag & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((tmpItSource & SAI_IT_LFSDET) == SAI_IT_LFSDET))
+ {
+ /* Change the SAI error code */
+ hsai->ErrorCode = HAL_SAI_ERROR_LFSDET;
+ HAL_SAI_Abort(hsai);
+ HAL_SAI_ErrorCallback(hsai);
+ }
- /* Clear the SAI Underrun flag */
- __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
- /* Set the SAI state ready to be able to start again the process */
- hsai->State = HAL_SAI_STATE_READY;
- HAL_SAI_ErrorCallback(hsai);
+ /* SAI WCKCFG interrupt occurred ----------------------------------*/
+ if(((tmpFlag & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((tmpItSource & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
+ {
+ /* Change the SAI error code */
+ hsai->ErrorCode = HAL_SAI_ERROR_WCKCFG;
+ HAL_SAI_Abort(hsai);
+ HAL_SAI_ErrorCallback(hsai);
+ }
}
- }
+ }
}
/**
@@ -1242,6 +1387,398 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
* @}
*/
+/**
+ * @brief Initializes the SAI I2S protocol according to the specified parameters
+ * in the SAI_InitTypeDef and create the associated handle.
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param protocol : one of the supported protocol
+ * @param datasize : one of the supported datasize @ref SAI_Protocol_DataSize
+ * the configuration information for SAI module.
+ * @param nbslot : number of slot minimum value is 2 and max is 16.
+ * the value must be a multiple of 2.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+ /* Check the parameters */
+ assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
+ assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
+
+ hsai->Init.Protocol = SAI_FREE_PROTOCOL;
+ hsai->Init.FirstBit = SAI_FIRSTBIT_MSB;
+ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;
+ hsai->FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION;
+ hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL;
+ hsai->SlotInit.FirstBitOffset = 0;
+ hsai->SlotInit.SlotNumber = nbslot;
+
+ /* in IS2 the number of slot must be even */
+ if((nbslot & 0x1) != 0 )
+ {
+ return HAL_ERROR;
+ }
+
+ switch(protocol)
+ {
+ case SAI_I2S_STANDARD :
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
+ hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;
+ break;
+ case SAI_I2S_MSBJUSTIFIED :
+ case SAI_I2S_LSBJUSTIFIED :
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
+ hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT;
+ break;
+ default :
+ return HAL_ERROR;
+ }
+
+ /* Frame definition */
+ hsai->Init.DataSize = 0xFFFFFFFF;
+ switch(datasize)
+ {
+ case SAI_PROTOCOL_DATASIZE_16BIT:
+ hsai->Init.DataSize = SAI_DATASIZE_16;
+ hsai->FrameInit.FrameLength = 32*(nbslot/2);
+ hsai->FrameInit.ActiveFrameLength = 16*(nbslot/2);
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
+ break;
+ case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
+ if(hsai->Init.DataSize == 0xFFFFFFFF)
+ {
+ hsai->Init.DataSize = SAI_DATASIZE_16;
+ }
+ break;
+ case SAI_PROTOCOL_DATASIZE_24BIT:
+ if(hsai->Init.DataSize == 0xFFFFFFFF)
+ {
+ hsai->Init.DataSize = SAI_DATASIZE_24;
+ }
+ break;
+ case SAI_PROTOCOL_DATASIZE_32BIT:
+ if(hsai->Init.DataSize == 0xFFFFFFFF)
+ {
+ hsai->Init.DataSize = SAI_DATASIZE_32;
+ }
+ hsai->FrameInit.FrameLength = 64*(nbslot/2);
+ hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+ if(protocol == SAI_I2S_LSBJUSTIFIED)
+ {
+ if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)
+ {
+ hsai->SlotInit.FirstBitOffset = 16;
+ }
+ if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)
+ {
+ hsai->SlotInit.FirstBitOffset = 8;
+ }
+ }
+ break;
+ default :
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the SAI PCM protocol according to the specified parameters
+ * in the SAI_InitTypeDef and create the associated handle.
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param protocol : one of the supported protocol
+ * @param datasize : one of the supported datasize @ref SAI_Protocol_DataSize
+ * @param nbslot : number of slot minimum value is 1 and the max is 16.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+ /* Check the parameters */
+ assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
+ assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
+
+ hsai->Init.Protocol = SAI_FREE_PROTOCOL;
+ hsai->Init.FirstBit = SAI_FIRSTBIT_MSB;
+ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;
+ hsai->FrameInit.FSDefinition = SAI_FS_STARTFRAME;
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
+ hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;
+ hsai->SlotInit.FirstBitOffset = 0;
+ hsai->SlotInit.SlotNumber = nbslot;
+ hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL;
+
+ switch(protocol)
+ {
+ case SAI_PCM_SHORT :
+ hsai->FrameInit.ActiveFrameLength = 1;
+ break;
+ case SAI_PCM_LONG :
+ hsai->FrameInit.ActiveFrameLength = 13;
+ break;
+ default :
+ return HAL_ERROR;
+ }
+
+ switch(datasize)
+ {
+ case SAI_PROTOCOL_DATASIZE_16BIT:
+ hsai->Init.DataSize = SAI_DATASIZE_16;
+ hsai->FrameInit.FrameLength = 16 * nbslot;
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
+ break;
+ case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
+ hsai->Init.DataSize = SAI_DATASIZE_16;
+ hsai->FrameInit.FrameLength = 32 * nbslot;
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+ break;
+
+ case SAI_PROTOCOL_DATASIZE_32BIT:
+ hsai->Init.DataSize = SAI_DATASIZE_32;
+ hsai->FrameInit.FrameLength = 32 * nbslot;
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+ break;
+ default :
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Fill the fifo
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None.
+ */
+static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
+{
+ /* fill the fifo with data before to enabled the SAI */
+ while((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
+ {
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ hsai->Instance->DR = (*hsai->pBuffPtr++);
+ }
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
+ hsai->pBuffPtr+= 2;
+ }
+ else
+ {
+ hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
+ hsai->pBuffPtr+= 4;
+ }
+ hsai->XferCount--;
+ }
+}
+
+/**
+ * @brief return the interrupt flag to set according the SAI setup
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param mode : SAI_MODE_DMA or SAI_MODE_IT
+ * @retval the list of the IT flag to enable
+ */
+static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode)
+{
+ uint32_t tmpIT = SAI_IT_OVRUDR;
+
+ if(mode == SAI_MODE_IT)
+ {
+ tmpIT|= SAI_IT_FREQ;
+ }
+
+ if((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+ {
+ tmpIT|= SAI_IT_AFSDET | SAI_IT_LFSDET;
+ }
+ else
+ {
+ /* hsai has been configured in master mode */
+ tmpIT|= SAI_IT_WCKCFG;
+ }
+ return tmpIT;
+}
+
+/**
+ * @brief Disable the SAI and wait the disabling
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None.
+ */
+static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
+{
+ uint32_t tickstart = HAL_GetTick();
+ HAL_StatusTypeDef status = HAL_OK;
+
+ __HAL_SAI_DISABLE(hsai);
+ while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > SAI_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+
+ status = HAL_TIMEOUT;
+
+ /* Change the SAI state */
+ HAL_SAI_ErrorCallback(hsai);
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Tx Handler for Transmit in Interrupt mode 8Bit transfer
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None.
+ */
+static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
+{
+ /* Write data on DR register */
+ hsai->Instance->DR = (*hsai->pBuffPtr++);
+ hsai->XferCount--;
+
+ /* Handle the end of the transmission */
+ if(hsai->XferCount == 0)
+ {
+ /* Disable FREQ and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+ hsai->State = HAL_SAI_STATE_READY;
+ HAL_SAI_TxCpltCallback(hsai);
+ }
+}
+
+/**
+ * @brief Tx Handler for Transmit in Interrupt mode for 16Bit transfer
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None.
+ */
+static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
+{
+ /* Write data on DR register */
+ hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr;
+ hsai->pBuffPtr+=2;
+ hsai->XferCount--;
+
+ /* Handle the end of the transmission */
+ if(hsai->XferCount == 0)
+ {
+ /* Disable FREQ and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+ hsai->State = HAL_SAI_STATE_READY;
+ HAL_SAI_TxCpltCallback(hsai);
+ }
+}
+
+/**
+ * @brief Tx Handler for Transmit in Interrupt mode for 32Bit transfer
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None.
+ */
+static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
+{
+ /* Write data on DR register */
+ hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr;
+ hsai->pBuffPtr+=4;
+ hsai->XferCount--;
+
+ /* Handle the end of the transmission */
+ if(hsai->XferCount == 0)
+ {
+ /* Disable FREQ and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+ hsai->State = HAL_SAI_STATE_READY;
+ HAL_SAI_TxCpltCallback(hsai);
+ }
+}
+
+/**
+ * @brief Rx Handler for Receive in Interrupt mode 8Bit transfer
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None.
+ */
+static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
+{
+ /* Receive data */
+ (*hsai->pBuffPtr++) = hsai->Instance->DR;
+ hsai->XferCount--;
+
+ /* Check end of the transfer */
+ if(hsai->XferCount == 0)
+ {
+ /* Disable TXE and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+ /* Clear the SAI Overrun flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+ hsai->State = HAL_SAI_STATE_READY;
+ HAL_SAI_RxCpltCallback(hsai);
+ }
+}
+
+/**
+ * @brief Rx Handler for Receive in Interrupt mode for 16Bit transfer
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None.
+ */
+static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
+{
+ /* Receive data */
+ *(uint16_t*)hsai->pBuffPtr = hsai->Instance->DR;
+ hsai->pBuffPtr+=2;
+ hsai->XferCount--;
+
+ /* Check end of the transfer */
+ if(hsai->XferCount == 0)
+ {
+ /* Disable TXE and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+ /* Clear the SAI Overrun flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+ hsai->State = HAL_SAI_STATE_READY;
+ HAL_SAI_RxCpltCallback(hsai);
+ }
+}
+/**
+ * @brief Rx Handler for Receive in Interrupt mode for 32Bit transfer
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None.
+ */
+static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
+{
+ /* Receive data */
+ *(uint32_t*)hsai->pBuffPtr = hsai->Instance->DR;
+ hsai->pBuffPtr+=4;
+ hsai->XferCount--;
+
+ /* Check end of the transfer */
+ if(hsai->XferCount == 0)
+ {
+ /* Disable TXE and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+ /* Clear the SAI Overrun flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+ hsai->State = HAL_SAI_STATE_READY;
+ HAL_SAI_RxCpltCallback(hsai);
+ }
+}
+
/**
* @brief DMA SAI transmit process complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
@@ -1253,18 +1790,17 @@ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
uint32_t tickstart = 0;
SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent;
-
+
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
{
- hsai->TxXferCount = 0;
- hsai->RxXferCount = 0;
+ hsai->XferCount = 0;
/* Disable SAI Tx DMA Request */
hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
-
+
/* Get tick */
tickstart = HAL_GetTick();
-
+
/* Set timeout: 10 is the max delay to send the remaining data in the SAI FIFO */
/* Wait until FIFO is empty */
while(__HAL_SAI_GET_FLAG(hsai, SAI_xSR_FLVL) != RESET)
@@ -1280,6 +1816,9 @@ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
}
}
+ /* Stop the interrupts error handling */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
hsai->State= HAL_SAI_STATE_READY;
}
HAL_SAI_TxCpltCallback(hsai);
@@ -1311,7 +1850,10 @@ static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
{
/* Disable Rx DMA Request */
hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
- hsai->RxXferCount = 0;
+ hsai->XferCount = 0;
+
+ /* Stop the interrupts error handling */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
hsai->State = HAL_SAI_STATE_READY;
}
@@ -1339,19 +1881,22 @@ static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
static void SAI_DMAError(DMA_HandleTypeDef *hdma)
{
SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Stop the DMA transfer */
+ HAL_SAI_DMAStop(hsai);
+
/* Set the SAI state ready to be able to start again the process */
hsai->State= HAL_SAI_STATE_READY;
HAL_SAI_ErrorCallback(hsai);
- hsai->TxXferCount = 0;
- hsai->RxXferCount = 0;
+ hsai->XferCount = 0;
}
/**
* @}
*/
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
#endif /* HAL_SAI_MODULE_ENABLED */
/**
* @}
diff --git a/f4/src/stm32f4xx_hal_sai_ex.c b/f4/src/stm32f4xx_hal_sai_ex.c
new file mode 100644
index 0000000..66c0e2f
--- /dev/null
+++ b/f4/src/stm32f4xx_hal_sai_ex.c
@@ -0,0 +1,272 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sai_ex.c
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief SAI Extension HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of SAI extension peripheral:
+ * + Extension features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### SAI peripheral extension features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the SAI interface for STM32F446xx
+ devices contains the following additional features :
+
+ (+) Possibility to be clocked from PLLR
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to manage several sources to clock SAI
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SAIEx SAIEx
+ * @brief SAI Extension HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* SAI registers Masks */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SAI_Private_Functions SAI Private Functions
+ * @{
+ */
+ /**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SAIEx_Exported_Functions SAI Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup SAIEx_Exported_Functions_Group1 Extension features functions
+ * @brief Extension features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extension features Functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the possible
+ SAI clock sources.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure SAI Block synchronization mode
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval SAI Clock Input
+ */
+void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai)
+{
+ uint32_t tmpregisterGCR = 0;
+
+#if defined(STM32F446xx)
+ /* This setting must be done with both audio block (A & B) disabled */
+ switch(hsai->Init.SynchroExt)
+ {
+ case SAI_SYNCEXT_DISABLE :
+ tmpregisterGCR = 0;
+ break;
+ case SAI_SYNCEXT_IN_ENABLE :
+ tmpregisterGCR = SAI_GCR_SYNCIN_0;
+ break;
+ case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
+ tmpregisterGCR = SAI_GCR_SYNCOUT_0;
+ break;
+ case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
+ tmpregisterGCR = SAI_GCR_SYNCOUT_1;
+ break;
+ }
+
+ if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
+ {
+ SAI1->GCR = tmpregisterGCR;
+ }
+ else
+ {
+ SAI2->GCR = tmpregisterGCR;
+ }
+#endif /* STM32F446xx */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+ /* This setting must be done with both audio block (A & B) disabled */
+ switch(hsai->Init.SynchroExt)
+ {
+ case SAI_SYNCEXT_DISABLE :
+ tmpregisterGCR = 0;
+ break;
+ case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
+ tmpregisterGCR = SAI_GCR_SYNCOUT_0;
+ break;
+ case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
+ tmpregisterGCR = SAI_GCR_SYNCOUT_1;
+ break;
+ }
+ SAI1->GCR = tmpregisterGCR;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+}
+ /**
+ * @brief Get SAI Input Clock based on SAI source clock selection
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval SAI Clock Input
+ */
+uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai)
+{
+ /* This variable used to store the SAI_CK_x (value in Hz) */
+ uint32_t saiclocksource = 0;
+
+#if defined(STM32F446xx)
+ if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
+ {
+ saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);
+ }
+ else /* SAI2_Block_A || SAI2_Block_B*/
+ {
+ saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2);
+ }
+#endif /* STM32F446xx */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+ uint32_t vcoinput = 0, tmpreg = 0;
+
+ /* Check the SAI Block parameters */
+ assert_param(IS_SAI_CLK_SOURCE(hsai->Init.ClockSource));
+
+ /* SAI Block clock source selection */
+ if(hsai->Instance == SAI1_Block_A)
+ {
+ __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(hsai->Init.ClockSource);
+ }
+ else
+ {
+ __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG((uint32_t)(hsai->Init.ClockSource << 2));
+ }
+
+ /* VCO Input Clock value calculation */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ {
+ /* In Case the PLL Source is HSI (Internal Clock) */
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* In Case the PLL Source is HSE (External Clock) */
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+ }
+
+ /* SAI_CLK_x : SAI Block Clock configuration for different clock sources selected */
+ if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLSAI)
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+ tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
+ saiclocksource = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+ tmpreg = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8) + 1);
+ saiclocksource = saiclocksource/(tmpreg);
+
+ }
+ else if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLI2S)
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+ tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
+ saiclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+ tmpreg = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1);
+ saiclocksource = saiclocksource/(tmpreg);
+ }
+ else /* sConfig->ClockSource == SAI_CLKSource_Ext */
+ {
+ /* Enable the External Clock selection */
+ __HAL_RCC_I2S_CONFIG(RCC_I2SCLKSOURCE_EXT);
+
+ saiclocksource = EXTERNAL_CLOCK_VALUE;
+ }
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+ /* the return result is the value of SAI clock */
+ return saiclocksource;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* HAL_SAI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/f4/src/stm32f4xx_hal_sd.c b/f4/src/stm32f4xx_hal_sd.c
index 4da6dcb..c1be1e1 100755
--- a/f4/src/stm32f4xx_hal_sd.c
+++ b/f4/src/stm32f4xx_hal_sd.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sd.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief SD card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:
@@ -149,7 +149,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -180,7 +180,10 @@
#include "stm32f4xx_hal.h"
#ifdef HAL_SD_MODULE_ENABLED
-
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
@@ -340,6 +343,8 @@ HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *S
__IO HAL_SD_ErrorTypedef errorstate = SD_OK;
SD_InitTypeDef tmpinit;
+ /* Allocate lock resource and initialize it */
+ hsd->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_SD_MspInit(hsd);
@@ -524,7 +529,11 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff
}
/* Poll on SDIO flags */
+#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
+#endif /* SDIO_STA_STBITERR */
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
{
@@ -549,7 +558,11 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff
}
/* In case of single block transfer, no need of stop transfer at all */
+#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
+#endif /* SDIO_STA_STBITERR */
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
{
@@ -601,6 +614,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff
return errorstate;
}
+#ifdef SDIO_STA_STBITERR
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
@@ -609,6 +623,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff
return errorstate;
}
+#endif /* SDIO_STA_STBITERR */
else
{
/* No error flag set */
@@ -719,7 +734,11 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu
/* Write block(s) in polling mode */
if(NumberOfBlocks > 1)
{
+#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
+#endif /* SDIO_STA_STBITERR */
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
{
@@ -751,8 +770,12 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu
}
else
{
- /* In case of single data block transfer no need of stop command at all */
+ /* In case of single data block transfer no need of stop command at all */
+#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
+#endif /* SDIO_STA_STBITERR */
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
{
@@ -819,6 +842,7 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu
return errorstate;
}
+#ifdef SDIO_STA_STBITERR
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
@@ -827,6 +851,7 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu
return errorstate;
}
+#endif /* SDIO_STA_STBITERR */
else
{
/* No error flag set */
@@ -884,11 +909,18 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pRead
}
/* Enable transfer interrupts */
+#ifdef SDIO_STA_STBITERR
__HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
SDIO_IT_DTIMEOUT |\
SDIO_IT_DATAEND |\
SDIO_IT_RXOVERR |\
SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+ __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
+ SDIO_IT_DTIMEOUT |\
+ SDIO_IT_DATAEND |\
+ SDIO_IT_RXOVERR));
+#endif /* SDIO_STA_STBITERR */
/* Enable SDIO DMA transfer */
__HAL_SD_SDIO_DMA_ENABLE();
@@ -1001,11 +1033,18 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWri
}
/* Enable transfer interrupts */
+#ifdef SDIO_STA_STBITERR
__HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
SDIO_IT_DTIMEOUT |\
SDIO_IT_DATAEND |\
SDIO_IT_TXUNDERR |\
- SDIO_IT_STBITERR));
+ SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+ __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
+ SDIO_IT_DTIMEOUT |\
+ SDIO_IT_DATAEND |\
+ SDIO_IT_TXUNDERR));
+#endif /* SDIO_STA_STBITERR */
/* Configure DMA user callbacks */
hsd->hdmatx->XferCpltCallback = SD_DMA_TxCplt;
@@ -1367,6 +1406,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
HAL_SD_XferErrorCallback(hsd);
}
+#ifdef SDIO_STA_STBITERR
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
@@ -1375,15 +1415,22 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
HAL_SD_XferErrorCallback(hsd);
}
+#endif /* SDIO_STA_STBITERR */
else
{
/* No error flag set */
}
/* Disable all SDIO peripheral interrupt sources */
+#ifdef SDIO_STA_STBITERR
+ __HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND |\
+ SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |\
+ SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
+#else /* SDIO_STA_STBITERR not defined */
__HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND |\
SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |\
- SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
+ SDIO_IT_RXOVERR);
+#endif /* SDIO_STA_STBITERR */
}
@@ -1850,8 +1897,11 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
{
return errorstate;
}
-
+#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+#else /* SDIO_STA_STBITERR */
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
+#endif /* SDIO_STA_STBITERR */
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
{
@@ -1888,6 +1938,7 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
return errorstate;
}
+#ifdef SDIO_STA_STBITERR
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
@@ -1896,6 +1947,7 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
return errorstate;
}
+#endif /* SDIO_STA_STBITERR */
else
{
/* No error flag set */
@@ -2016,7 +2068,11 @@ HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstat
}
/* Get status data */
+#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
+#endif /* SDIO_STA_STBITERR */
{
if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
{
@@ -2053,6 +2109,7 @@ HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstat
return errorstate;
}
+#ifdef SDIO_STA_STBITERR
else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
@@ -2061,6 +2118,7 @@ HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstat
return errorstate;
}
+#endif /* SDIO_STA_STBITERR */
else
{
/* No error flag set */
@@ -3187,8 +3245,11 @@ static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
{
return errorstate;
}
-
+#ifdef SDIO_STA_STBITERR
while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
+#endif /* SDIO_STA_STBITERR */
{
if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
{
@@ -3221,6 +3282,7 @@ static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
return errorstate;
}
+#ifdef SDIO_STA_STBITERR
else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
{
__HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
@@ -3229,6 +3291,7 @@ static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
return errorstate;
}
+#endif /* SDIO_STA_STBITERR */
else
{
/* No error flag set */
@@ -3414,7 +3477,8 @@ static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *
/**
* @}
*/
-
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
#endif /* HAL_SD_MODULE_ENABLED */
/**
diff --git a/f4/src/stm32f4xx_hal_sdram.c b/f4/src/stm32f4xx_hal_sdram.c
index c88b3be..3e86587 100755
--- a/f4/src/stm32f4xx_hal_sdram.c
+++ b/f4/src/stm32f4xx_hal_sdram.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sdram.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief SDRAM HAL module driver.
* This file provides a generic firmware to drive SDRAM memories mounted
* as external device.
@@ -63,7 +63,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -102,7 +102,8 @@
* @{
*/
#ifdef HAL_SDRAM_MODULE_ENABLED
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -146,6 +147,8 @@ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTy
if(hsdram->State == HAL_SDRAM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hsdram->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_SDRAM_MspInit(hsdram);
}
@@ -827,7 +830,7 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
/**
* @}
*/
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
#endif /* HAL_SDRAM_MODULE_ENABLED */
/**
* @}
diff --git a/f4/src/stm32f4xx_hal_smartcard.c b/f4/src/stm32f4xx_hal_smartcard.c
index 5829fd8..fb0d23e 100755
--- a/f4/src/stm32f4xx_hal_smartcard.c
+++ b/f4/src/stm32f4xx_hal_smartcard.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_smartcard.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief SMARTCARD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:
@@ -100,7 +100,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -247,6 +247,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
if(hsc->State == HAL_SMARTCARD_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hsc->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_SMARTCARD_MspInit(hsc);
}
@@ -444,34 +446,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
hsc->TxXferCount = Size;
while(hsc->TxXferCount > 0)
{
- hsc->TxXferCount--;
- if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
+ hsc->TxXferCount--;
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
{
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- tmp = (uint16_t*) pData;
- hsc->Instance->DR = (*tmp & (uint16_t)0x01FF);
- if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
- {
- pData +=2;
- }
- else
- {
- pData +=1;
- }
- }
- else
- {
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- hsc->Instance->DR = (*pData++ & (uint8_t)0xFF);
+ return HAL_TIMEOUT;
}
+ tmp = (uint16_t*) pData;
+ hsc->Instance->DR = (*tmp & (uint16_t)0x01FF);
+ pData +=1;
}
-
+
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
@@ -536,43 +520,18 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
hsc->RxXferSize = Size;
hsc->RxXferCount = Size;
+
/* Check the remain data to be received */
while(hsc->RxXferCount > 0)
{
hsc->RxXferCount--;
- if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
{
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- tmp = (uint16_t*) pData;
- if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
- {
- *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x01FF);
- pData +=2;
- }
- else
- {
- *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
- pData +=1;
- }
- }
- else
- {
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
- {
- *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
- }
- else
- {
- *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x007F);
- }
+ return HAL_TIMEOUT;
}
+ tmp = (uint16_t*) pData;
+ *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
+ pData +=1;
}
/* Check if a non-blocking transmit process is ongoing or not */
@@ -640,8 +599,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_
/* Enable the SMARTCARD Parity Error Interrupt */
__HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
- /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
/* Enable the SMARTCARD Transmit data register empty Interrupt */
__HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TXE);
@@ -902,7 +861,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC);
/* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
+ if(((tmp1 & SMARTCARD_FLAG_TC) != RESET) && (tmp2 != RESET))
{
SMARTCARD_EndTransmit_IT(hsc);
}
@@ -1146,23 +1105,9 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
tmp1 = hsc->State;
if((tmp1 == HAL_SMARTCARD_STATE_BUSY_TX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX))
{
- if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
- {
- tmp = (uint16_t*) hsc->pTxBuffPtr;
- hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
- if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
- {
- hsc->pTxBuffPtr += 2;
- }
- else
- {
- hsc->pTxBuffPtr += 1;
- }
- }
- else
- {
- hsc->Instance->DR = (uint8_t)(*hsc->pTxBuffPtr++ & (uint8_t)0x00FF);
- }
+ tmp = (uint16_t*) hsc->pTxBuffPtr;
+ hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
+ hsc->pTxBuffPtr += 1;
if(--hsc->TxXferCount == 0)
{
@@ -1224,31 +1169,9 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
tmp1 = hsc->State;
if((tmp1 == HAL_SMARTCARD_STATE_BUSY_RX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX))
{
- if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
- {
- tmp = (uint16_t*) hsc->pRxBuffPtr;
- if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
- {
- *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x01FF);
- hsc->pRxBuffPtr += 2;
- }
- else
- {
- *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
- hsc->pRxBuffPtr += 1;
- }
- }
- else
- {
- if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
- {
- *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
- }
- else
- {
- *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x007F);
- }
- }
+ tmp = (uint16_t*) hsc->pRxBuffPtr;
+ *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
+ hsc->pRxBuffPtr += 1;
if(--hsc->RxXferCount == 0)
{
diff --git a/f4/src/stm32f4xx_hal_spdifrx.c b/f4/src/stm32f4xx_hal_spdifrx.c
new file mode 100644
index 0000000..5600036
--- /dev/null
+++ b/f4/src/stm32f4xx_hal_spdifrx.c
@@ -0,0 +1,1210 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_spdifrx.c
+ * @author MCD Application Team
+ * @version V1.4.1
+ * @date 09-October-2015
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the SPDIFRX audio interface:
+ * + Initialization and Configuration
+ * + Data transfers functions
+ * + DMA transfers management
+ * + Interrupts and flags management
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The SPDIFRX HAL driver can be used as follow:
+
+ (#) Declare SPDIFRX_HandleTypeDef handle structure.
+ (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API:
+ (##) Enable the SPDIFRX interface clock.
+ (##) SPDIFRX pins configuration:
+ (+++) Enable the clock for the SPDIFRX GPIOs.
+ (+++) Configure these SPDIFRX pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's).
+ (+++) Configure the SPDIFRX interrupt priority.
+ (+++) Enable the NVIC SPDIFRX IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveControlFlow_DMA() API's).
+ (+++) Declare a DMA handle structure for the reception of the Data Flow channel.
+ (+++) Declare a DMA handle structure for the reception of the Control Flow channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters.
+ (+++) Configure the DMA Channel.
+ (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
+ DMA CtrlRx/DataRx channel.
+
+ (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits
+ using HAL_SPDIFRX_Init() function.
+
+ -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros
+ __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process.
+ -@- Make sure that ck_spdif clock is configured.
+
+ (#) Three operation modes are available within this driver :
+
+ *** Polling mode for reception operation (for debug purpose) ***
+ ================================================================
+ [..]
+ (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow()
+ (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow()
+
+ *** Interrupt mode for reception operation ***
+ =========================================
+ [..]
+ (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT()
+ (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT()
+ (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
+ (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
+
+ *** DMA mode for reception operation ***
+ ========================================
+ [..]
+ (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA()
+ (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA()
+ (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
+ (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
+ (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop()
+
+ *** SPDIFRX HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in USART HAL driver.
+ (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State)
+ (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State)
+ (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)
+ (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts
+ (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts
+ (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not.
+
+ [..]
+ (@) You can refer to the SPDIFRX HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+/** @defgroup SPDIFRX SPDIFRX
+ * @brief SPDIFRX HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+
+#if defined(STM32F446xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define SPDIFRX_TIMEOUT_VALUE 0xFFFF
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SPDIFRX_Private_Functions
+ * @{
+ */
+static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma);
+static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma);
+static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
+static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
+static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+/**
+ * @}
+ */
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SPDIFRX_Exported_Functions SPDIFRX Exported Functions
+ * @{
+ */
+
+/** @defgroup SPDIFRX_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the SPDIFRX peripheral:
+
+ (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with
+ the selected configuration:
+ (++) Input Selection (IN0, IN1,...)
+ (++) Maximum allowed re-tries during synchronization phase
+ (++) Wait for activity on SPDIF selected input
+ (++) Channel status selection (from channel A or B)
+ (++) Data format (LSB, MSB, ...)
+ (++) Stereo mode
+ (++) User bits masking (PT,C,U,V,...)
+
+ (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration
+ of the selected SPDIFRXx peripheral.
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the SPDIFRX according to the specified parameters
+ * in the SPDIFRX_InitTypeDef and create the associated handle.
+ * @param hspdif: SPDIFRX handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the SPDIFRX handle allocation */
+ if(hspdif == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the SPDIFRX parameters */
+ assert_param(IS_STEREO_MODE(hspdif->Init.StereoMode));
+ assert_param(IS_SPDIFRX_INPUT_SELECT(hspdif->Init.InputSelection));
+ assert_param(IS_SPDIFRX_MAX_RETRIES(hspdif->Init.Retries));
+ assert_param(IS_SPDIFRX_WAIT_FOR_ACTIVITY(hspdif->Init.WaitForActivity));
+ assert_param(IS_SPDIFRX_CHANNEL(hspdif->Init.ChannelSelection));
+ assert_param(IS_SPDIFRX_DATA_FORMAT(hspdif->Init.DataFormat));
+ assert_param(IS_PREAMBLE_TYPE_MASK(hspdif->Init.PreambleTypeMask));
+ assert_param(IS_CHANNEL_STATUS_MASK(hspdif->Init.ChannelStatusMask));
+ assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask));
+ assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask));
+
+ if(hspdif->State == HAL_SPDIFRX_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hspdif->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_SPDIFRX_MspInit(hspdif);
+ }
+
+ /* SPDIFRX peripheral state is BUSY*/
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+
+ /* Disable SPDIFRX interface (IDLE State) */
+ __HAL_SPDIFRX_IDLE(hspdif);
+
+ /* Reset the old SPDIFRX CR configuration */
+ tmpreg = hspdif->Instance->CR;
+
+ tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |
+ SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK |
+ SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA |
+ SPDIFRX_CR_INSEL);
+
+ /* Sets the new configuration of the SPDIFRX peripheral */
+ tmpreg |= ((uint16_t) hspdif->Init.StereoMode |
+ hspdif->Init.InputSelection |
+ hspdif->Init.Retries |
+ hspdif->Init.WaitForActivity |
+ hspdif->Init.ChannelSelection |
+ hspdif->Init.DataFormat |
+ hspdif->Init.PreambleTypeMask |
+ hspdif->Init.ChannelStatusMask |
+ hspdif->Init.ValidityBitMask |
+ hspdif->Init.ParityErrorMask);
+
+ hspdif->Instance->CR = tmpreg;
+
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+
+ /* SPDIFRX peripheral state is READY*/
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the SPDIFRX peripheral
+ * @param hspdif: SPDIFRX handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* Check the SPDIFRX handle allocation */
+ if(hspdif == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPDIFRX_ALL_INSTANCE(hspdif->Instance));
+
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+
+ /* Disable SPDIFRX interface (IDLE state) */
+ __HAL_SPDIFRX_IDLE(hspdif);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_SPDIFRX_MspDeInit(hspdif);
+
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+
+ /* SPDIFRX peripheral state is RESET*/
+ hspdif->State = HAL_SPDIFRX_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief SPDIFRX MSP Init
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPDIFRX MSP DeInit
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Sets the SPDIFRX dtat format according to the specified parameters
+ * in the SPDIFRX_InitTypeDef.
+ * @param hspdif: SPDIFRX handle
+ * @param sDataFormat: SPDIFRX data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the SPDIFRX handle allocation */
+ if(hspdif == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the SPDIFRX parameters */
+ assert_param(IS_STEREO_MODE(sDataFormat.StereoMode));
+ assert_param(IS_SPDIFRX_DATA_FORMAT(sDataFormat.DataFormat));
+ assert_param(IS_PREAMBLE_TYPE_MASK(sDataFormat.PreambleTypeMask));
+ assert_param(IS_CHANNEL_STATUS_MASK(sDataFormat.ChannelStatusMask));
+ assert_param(IS_VALIDITY_MASK(sDataFormat.ValidityBitMask));
+ assert_param(IS_PARITY_ERROR_MASK(sDataFormat.ParityErrorMask));
+
+ /* Reset the old SPDIFRX CR configuration */
+ tmpreg = hspdif->Instance->CR;
+
+ if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) &&
+ (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||
+ ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode)))
+ {
+ return HAL_ERROR;
+ }
+
+ tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |
+ SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK);
+
+ /* Sets the new configuration of the SPDIFRX peripheral */
+ tmpreg |= ((uint16_t) sDataFormat.StereoMode |
+ sDataFormat.DataFormat |
+ sDataFormat.PreambleTypeMask |
+ sDataFormat.ChannelStatusMask |
+ sDataFormat.ValidityBitMask |
+ sDataFormat.ParityErrorMask);
+
+ hspdif->Instance->CR = tmpreg;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+===============================================================================
+##### IO operation functions #####
+===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SPDIFRX data
+ transfers.
+
+ (#) There is two mode of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer start-up.
+ The end of the data processing will be indicated through the
+ dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_SPDIFRX_ReceiveDataFlow()
+ (++) HAL_SPDIFRX_ReceiveControlFlow()
+ (+@) Do not use blocking mode to receive both control and data flow at the same time.
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_SPDIFRX_ReceiveControlFlow_IT()
+ (++) HAL_SPDIFRX_ReceiveDataFlow_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_SPDIFRX_ReceiveControlFlow_DMA()
+ (++) HAL_SPDIFRX_ReceiveDataFlow_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (++) HAL_SPDIFRX_RxCpltCallback()
+ (++) HAL_SPDIFRX_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Receives an amount of data (Data Flow) in blocking mode.
+ * @param hspdif: pointer to SPDIFRX_HandleTypeDef structure that contains
+ * the configuration information for SPDIFRX module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be received
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
+{
+
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hspdif->State == HAL_SPDIFRX_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+
+ /* Start synchronisation */
+ __HAL_SPDIFRX_SYNC(hspdif);
+
+ /* Wait until SYNCD flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start reception */
+ __HAL_SPDIFRX_RCV(hspdif);
+
+ /* Receive data flow */
+ while(Size > 0)
+ {
+ /* Wait until RXNE flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ (*pData++) = hspdif->Instance->DR;
+ Size--;
+ }
+
+ /* SPDIFRX ready */
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives an amount of data (Control Flow) in blocking mode.
+ * @param hspdif: pointer to a SPDIFRX_HandleTypeDef structure that contains
+ * the configuration information for SPDIFRX module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be received
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
+{
+
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hspdif->State == HAL_SPDIFRX_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+
+ /* Start synchronization */
+ __HAL_SPDIFRX_SYNC(hspdif);
+
+ /* Wait until SYNCD flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start reception */
+ __HAL_SPDIFRX_RCV(hspdif);
+
+ /* Receive control flow */
+ while(Size > 0)
+ {
+ /* Wait until CSRNE flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ (*pData++) = hspdif->Instance->CSR;
+ Size--;
+ }
+
+ /* SPDIFRX ready */
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt
+ * @param hspdif: SPDIFRX handle
+ * @param pData: a 32-bit pointer to the Receive data buffer.
+ * @param Size: number of data sample to be received .
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
+{
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ hspdif->pRxBuffPtr = pData;
+ hspdif->RxXferSize = Size;
+ hspdif->RxXferCount = Size;
+
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+
+ /* Check if a receive process is ongoing or not */
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
+
+
+ /* Enable the SPDIFRX PE Error Interrupt */
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+
+ /* Enable the SPDIFRX OVR Error Interrupt */
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ /* Enable the SPDIFRX RXNE interrupt */
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+
+ if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00)
+ {
+ /* Start synchronization */
+ __HAL_SPDIFRX_SYNC(hspdif);
+
+ /* Wait until SYNCD flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start reception */
+ __HAL_SPDIFRX_RCV(hspdif);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data (Control Flow) with Interrupt
+ * @param hspdif: SPDIFRX handle
+ * @param pData: a 32-bit pointer to the Receive data buffer.
+ * @param Size: number of data sample (Control Flow) to be received :
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
+{
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ hspdif->pCsBuffPtr = pData;
+ hspdif->CsXferSize = Size;
+ hspdif->CsXferCount = Size;
+
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+
+ /* Check if a receive process is ongoing or not */
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
+
+
+ /* Enable the SPDIFRX PE Error Interrupt */
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+
+ /* Enable the SPDIFRX OVR Error Interrupt */
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ /* Enable the SPDIFRX CSRNE interrupt */
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+
+ if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00)
+ {
+ /* Start synchronization */
+ __HAL_SPDIFRX_SYNC(hspdif);
+
+ /* Wait until SYNCD flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start reception */
+ __HAL_SPDIFRX_RCV(hspdif);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data (Data Flow) mode with DMA
+ * @param hspdif: SPDIFRX handle
+ * @param pData: a 32-bit pointer to the Receive data buffer.
+ * @param Size: number of data sample to be received :
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
+{
+
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
+ {
+ hspdif->pRxBuffPtr = pData;
+ hspdif->RxXferSize = Size;
+ hspdif->RxXferCount = Size;
+
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
+
+ /* Set the SPDIFRX Rx DMA Half transfer complete callback */
+ hspdif->hdmaDrRx->XferHalfCpltCallback = SPDIFRX_DMARxHalfCplt;
+
+ /* Set the SPDIFRX Rx DMA transfer complete callback */
+ hspdif->hdmaDrRx->XferCpltCallback = SPDIFRX_DMARxCplt;
+
+ /* Set the DMA error callback */
+ hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError;
+
+ /* Enable the DMA request */
+ HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size);
+
+ /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/
+ hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN;
+
+ if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00)
+ {
+ /* Start synchronization */
+ __HAL_SPDIFRX_SYNC(hspdif);
+
+ /* Wait until SYNCD flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start reception */
+ __HAL_SPDIFRX_RCV(hspdif);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data (Control Flow) with DMA
+ * @param hspdif: SPDIFRX handle
+ * @param pData: a 32-bit pointer to the Receive data buffer.
+ * @param Size: number of data (Control Flow) sample to be received :
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
+{
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
+ {
+ hspdif->pCsBuffPtr = pData;
+ hspdif->CsXferSize = Size;
+ hspdif->CsXferCount = Size;
+
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
+
+ /* Set the SPDIFRX Rx DMA Half transfer complete callback */
+ hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt;
+
+ /* Set the SPDIFRX Rx DMA transfer complete callback */
+ hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt;
+
+ /* Set the DMA error callback */
+ hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;
+
+ /* Enable the DMA request */
+ HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size);
+
+ /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/
+ hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;
+
+ if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00)
+ {
+ /* Start synchronization */
+ __HAL_SPDIFRX_SYNC(hspdif);
+
+ /* Wait until SYNCD flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start reception */
+ __HAL_SPDIFRX_RCV(hspdif);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief stop the audio stream receive from the Media.
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ /* Disable the SPDIFRX DMA requests */
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
+
+ /* Disable the SPDIFRX DMA channel */
+ __HAL_DMA_DISABLE(hspdif->hdmaDrRx);
+ __HAL_DMA_DISABLE(hspdif->hdmaCsRx);
+
+ /* Disable SPDIFRX peripheral */
+ __HAL_SPDIFRX_IDLE(hspdif);
+
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles SPDIFRX interrupt request.
+ * @param hspdif: SPDIFRX handle
+ * @retval HAL status
+ */
+void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* SPDIFRX in mode Data Flow Reception ------------------------------------------------*/
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_RXNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_RXNE) != RESET))
+ {
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE);
+ SPDIFRX_ReceiveDataFlow_IT(hspdif);
+ }
+
+ /* SPDIFRX in mode Control Flow Reception ------------------------------------------------*/
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_CSRNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_CSRNE) != RESET))
+ {
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE);
+ SPDIFRX_ReceiveControlFlow_IT(hspdif);
+ }
+
+ /* SPDIFRX Overrun error interrupt occurred ---------------------------------*/
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_OVR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_OVRIE) != RESET))
+ {
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_OVR);
+
+ /* Change the SPDIFRX error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR;
+
+ /* the transfer is not stopped */
+ HAL_SPDIFRX_ErrorCallback(hspdif);
+ }
+
+ /* SPDIFRX Parity error interrupt occurred ---------------------------------*/
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_PERR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_PERRIE) != RESET))
+ {
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_PERR);
+
+ /* Change the SPDIFRX error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE;
+
+ /* the transfer is not stopped */
+ HAL_SPDIFRX_ErrorCallback(hspdif);
+ }
+
+}
+
+/**
+ * @brief Rx Transfer (Data flow) half completed callbacks
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer (Data flow) completed callbacks
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx (Control flow) Transfer half completed callbacks
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer (Control flow) completed callbacks
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPDIFRX error callbacks
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+===============================================================================
+##### Peripheral State and Errors functions #####
+===============================================================================
+[..]
+This subsection permit to get in run-time the status of the peripheral
+and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SPDIFRX state
+ * @param hspdif : SPDIFRX handle
+ * @retval HAL state
+ */
+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif)
+{
+ return hspdif->State;
+}
+
+/**
+ * @brief Return the SPDIFRX error code
+ * @param hspdif : SPDIFRX handle
+ * @retval SPDIFRX Error Code
+ */
+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif)
+{
+ return hspdif->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief DMA SPDIFRX receive process (Data flow) complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+ SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Rx DMA Request */
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
+ hspdif->RxXferCount = 0;
+
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+ HAL_SPDIFRX_RxCpltCallback(hspdif);
+}
+
+/**
+ * @brief DMA SPDIFRX receive process (Data flow) half complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_SPDIFRX_RxHalfCpltCallback(hspdif);
+}
+
+
+/**
+ * @brief DMA SPDIFRX receive process (Control flow) complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)
+{
+ SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Cb DMA Request */
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
+ hspdif->CsXferCount = 0;
+
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+ HAL_SPDIFRX_CxCpltCallback(hspdif);
+}
+
+/**
+ * @brief DMA SPDIFRX receive process (Control flow) half complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_SPDIFRX_CxHalfCpltCallback(hspdif);
+}
+
+/**
+ * @brief DMA SPDIFRX communication error callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Rx and Cb DMA Request */
+ hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN));
+ hspdif->RxXferCount = 0;
+
+ hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA;
+ HAL_SPDIFRX_ErrorCallback(hspdif);
+}
+
+
+/**
+ * @brief Receive an amount of data (Data Flow) with Interrupt
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* Receive data */
+ (*hspdif->pRxBuffPtr++) = hspdif->Instance->DR;
+ hspdif->RxXferCount--;
+
+ if(hspdif->RxXferCount == 0)
+ {
+ /* Disable RXNE/PE and OVR interrupts */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE);
+
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ HAL_SPDIFRX_RxCpltCallback(hspdif);
+ }
+}
+
+/**
+ * @brief Receive an amount of data (Control Flow) with Interrupt
+ * @param hspdif: SPDIFRX handle
+ * @retval None
+ */
+static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* Receive data */
+ (*hspdif->pCsBuffPtr++) = hspdif->Instance->CSR;
+ hspdif->CsXferCount--;
+
+ if(hspdif->CsXferCount == 0)
+ {
+ /* Disable CSRNE interrupt */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ HAL_SPDIFRX_CxCpltCallback(hspdif);
+ }
+}
+
+/**
+ * @brief This function handles SPDIFRX Communication Timeout.
+ * @param hspdif: SPDIFRX handle
+ * @param Flag: Flag checked
+ * @param Status: Value of the flag expected
+ * @param Timeout: Duration of the timeout
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+ hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+ hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx */
+
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/f4/src/stm32f4xx_hal_spi.c b/f4/src/stm32f4xx_hal_spi.c
index 4397ab1..84b119c 100755
--- a/f4/src/stm32f4xx_hal_spi.c
+++ b/f4/src/stm32f4xx_hal_spi.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_spi.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief SPI HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -59,7 +59,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -114,6 +114,7 @@ static void SPI_TxISR(SPI_HandleTypeDef *hspi);
static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
static void SPI_RxISR(SPI_HandleTypeDef *hspi);
+static void SPI_DMAEndTransmitReceive(SPI_HandleTypeDef *hspi);
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
@@ -194,6 +195,8 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
if(hspi->State == HAL_SPI_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hspi->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
}
@@ -310,27 +313,8 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
will be executed respectively at the end of the transmit or Receive process
The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
- (#) Blocking mode APIs are :
- (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_TransmitReceive() in full duplex mode
-
- (#) Non Blocking mode API's with Interrupt are :
- (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_TransmitReceive_IT()in full duplex mode
- (++) HAL_SPI_IRQHandler()
-
- (#) Non Blocking mode functions with DMA are :
- (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_TransmitReceie_DMA() in full duplex mode
-
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_SPI_TxCpltCallback()
- (++) HAL_SPI_RxCpltCallback()
- (++) HAL_SPI_ErrorCallback()
- (++) HAL_SPI_TxRxCpltCallback()
+ (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
+ exist for 1Line (simplex) and 2Lines (full duplex) modes.
@endverbatim
* @{
@@ -1196,9 +1180,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
/* Enable the Tx DMA Stream */
HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
- /* Enable Tx DMA Request */
- hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
-
/* Process Unlocked */
__HAL_UNLOCK(hspi);
@@ -1209,6 +1190,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
__HAL_SPI_ENABLE(hspi);
}
+ /* Enable Tx DMA Request */
+ hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
+
return HAL_OK;
}
else
@@ -1220,7 +1204,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
/**
* @brief Receive an amount of data in no-blocking mode with DMA
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
* @note When the CRC feature is enabled the pData Length must be Size + 1.
* @param Size: amount of data to be sent
@@ -1284,9 +1268,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Enable the Rx DMA Stream */
HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
- /* Enable Rx DMA Request */
- hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
-
/* Process Unlocked */
__HAL_UNLOCK(hspi);
@@ -1297,6 +1278,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
__HAL_SPI_ENABLE(hspi);
}
+ /* Enable Rx DMA Request */
+ hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
+
return HAL_OK;
}
else
@@ -1402,6 +1386,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
/* Enable the Tx DMA Stream */
HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
/* Check if the SPI is already enabled */
if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
{
@@ -1412,8 +1399,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
/* Enable Tx DMA Request */
hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
return HAL_OK;
}
else
@@ -2003,47 +1988,54 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
/* DMA Normal mode */
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
{
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
{
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
+ SPI_DMAEndTransmitReceive(hspi);
}
-
- /* Disable Rx DMA Request */
- hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
- /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
- hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-
- hspi->RxXferCount = 0;
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ /* SPI_DIRECTION_1LINE or SPI_DIRECTION_2LINES_RXONLY */
+ else
{
- /* Wait until RXNE flag is set to send data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
}
- /* Read CRC */
- tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg);
+ /* Disable Rx DMA Request */
+ hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
- /* Wait until RXNE flag is set */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
- }
+ hspi->RxXferCount = 0;
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ /* Wait until RXNE flag is set to send data */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Read CRC */
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+
+ /* Wait until RXNE flag is set */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
}
}
+ hspi->State = HAL_SPI_STATE_READY;
+
/* Check if Errors has been detected during transfer */
if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
@@ -2061,65 +2053,75 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
}
/**
- * @brief DMA SPI transmit receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @brief End DMA SPI transmit receive process
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval None
*/
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+static void SPI_DMAEndTransmitReceive(SPI_HandleTypeDef *hspi)
{
__IO uint16_t tmpreg;
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ /* Check if CRC is done on going (RXNE flag set) */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
{
- /* Check if CRC is done on going (RXNE flag set) */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
- {
- /* Wait until RXNE flag is set to send data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
- }
- }
- /* Read CRC */
- tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg);
-
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ /* Wait until RXNE flag is set to send data */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
}
}
-
- /* Wait until TXE flag is set to send data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
- }
- /* Disable Tx DMA Request */
- hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ /* Read CRC */
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
- /* Wait until Busy flag is reset before disabling SPI */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
-
- /* Disable Rx DMA Request */
- hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-
- hspi->TxXferCount = 0;
- hspi->RxXferCount = 0;
+ }
+
+ /* Wait until TXE flag is set to send data */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ }
+ /* Disable Tx DMA Request */
+ hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+
+ /* Wait until Busy flag is reset before disabling SPI */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Disable Rx DMA Request */
+ hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+
+ hspi->TxXferCount = 0;
+ hspi->RxXferCount = 0;
+}
+
+/**
+ * @brief DMA SPI transmit receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ { /**/
+ SPI_DMAEndTransmitReceive(hspi);
hspi->State = HAL_SPI_STATE_READY;
-
/* Check if Errors has been detected during transfer */
if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
diff --git a/f4/src/stm32f4xx_hal_sram.c b/f4/src/stm32f4xx_hal_sram.c
index 731a695..e2cbd39 100755
--- a/f4/src/stm32f4xx_hal_sram.c
+++ b/f4/src/stm32f4xx_hal_sram.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sram.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief SRAM HAL module driver.
* This file provides a generic firmware to drive SRAM memories
* mounted as external device.
@@ -64,7 +64,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -104,7 +104,9 @@
*/
#ifdef HAL_SRAM_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -148,6 +150,8 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp
if(hsram->State == HAL_SRAM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hsram->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_SRAM_MspInit(hsram);
}
@@ -665,7 +669,8 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
#endif /* HAL_SRAM_MODULE_ENABLED */
/**
* @}
diff --git a/f4/src/stm32f4xx_hal_tim.c b/f4/src/stm32f4xx_hal_tim.c
index 15284b4..20e5db1 100755
--- a/f4/src/stm32f4xx_hal_tim.c
+++ b/f4/src/stm32f4xx_hal_tim.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_tim.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
@@ -98,7 +98,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -220,6 +220,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
if(htim->State == HAL_TIM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
}
@@ -495,7 +497,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OC_MspInit(htim);
}
@@ -1002,6 +1006,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
if(htim->State == HAL_TIM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
}
@@ -1510,7 +1516,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_IC_MspInit(htim);
}
@@ -1987,7 +1995,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul
assert_param(IS_TIM_OPM_MODE(OnePulseMode));
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OnePulse_MspInit(htim);
}
@@ -2268,6 +2278,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
if(htim->State == HAL_TIM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_Encoder_MspInit(htim);
}
diff --git a/f4/src/stm32f4xx_hal_tim_ex.c b/f4/src/stm32f4xx_hal_tim_ex.c
index e1e3539..3379b17 100755
--- a/f4/src/stm32f4xx_hal_tim_ex.c
+++ b/f4/src/stm32f4xx_hal_tim_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_tim_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer extension peripheral:
@@ -69,7 +69,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -1723,6 +1723,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
return HAL_OK;
}
+
/**
* @}
*/
diff --git a/f4/src/stm32f4xx_hal_uart.c b/f4/src/stm32f4xx_hal_uart.c
index 44e7361..61dd735 100755
--- a/f4/src/stm32f4xx_hal_uart.c
+++ b/f4/src/stm32f4xx_hal_uart.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_uart.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
@@ -126,7 +126,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -261,6 +261,8 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
if(huart->State == HAL_UART_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
@@ -310,7 +312,9 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
if(huart->State == HAL_UART_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
@@ -368,7 +372,9 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));
if(huart->State == HAL_UART_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
@@ -432,7 +438,9 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
if(huart->State == HAL_UART_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
diff --git a/f4/src/stm32f4xx_hal_usart.c b/f4/src/stm32f4xx_hal_usart.c
index 4296654..54223c8 100755
--- a/f4/src/stm32f4xx_hal_usart.c
+++ b/f4/src/stm32f4xx_hal_usart.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_usart.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief USART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
@@ -105,7 +105,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -232,6 +232,8 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
if(husart->State == HAL_USART_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ husart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_USART_MspInit(husart);
}
diff --git a/f4/src/stm32f4xx_hal_wwdg.c b/f4/src/stm32f4xx_hal_wwdg.c
index 9292270..910c71b 100755
--- a/f4/src/stm32f4xx_hal_wwdg.c
+++ b/f4/src/stm32f4xx_hal_wwdg.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_wwdg.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief WWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Window Watchdog (WWDG) peripheral:
@@ -70,7 +70,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -163,6 +163,8 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
if(hwwdg->State == HAL_WWDG_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hwwdg->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_WWDG_MspInit(hwwdg);
}
diff --git a/f4/src/stm32f4xx_ll_fmc.c b/f4/src/stm32f4xx_ll_fmc.c
index 94522d9..1a17dfb 100755
--- a/f4/src/stm32f4xx_ll_fmc.c
+++ b/f4/src/stm32f4xx_ll_fmc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_fmc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief FMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -46,7 +46,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -86,7 +86,8 @@
*/
#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -159,18 +160,25 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini
assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
- assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
-
+ assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
+#if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
+ assert_param(IS_FMC_PAGESIZE(Init->PageSize));
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+
/* Get the BTCR register value */
tmpr = Device->BTCR[Init->NSBank];
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
@@ -193,6 +201,32 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini
Init->AsynchronousWait |\
Init->WriteBurst |\
Init->ContinuousClock);
+#else /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
+ /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, CPSIZE, WAITCFG, WREN,
+ WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW, CCLKEN and WFDIS bits */
+ tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
+ FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \
+ FMC_BCR1_WAITPOL | FMC_BCR1_WAITCFG | FMC_BCR1_CPSIZE | \
+ FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \
+ FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | \
+ FMC_BCR1_WFDIS));
+
+ /* Set NORSRAM device control parameters */
+ tmpr |= (uint32_t)(Init->DataAddressMux |\
+ Init->MemoryType |\
+ Init->MemoryDataWidth |\
+ Init->BurstAccessMode |\
+ Init->WaitSignalPolarity |\
+ Init->WaitSignalActive |\
+ Init->WriteOperation |\
+ Init->WaitSignal |\
+ Init->ExtendedMode |\
+ Init->AsynchronousWait |\
+ Init->WriteBurst |\
+ Init->ContinuousClock |\
+ Init->PageSize |\
+ Init->WriteFifo);
+#endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
{
@@ -206,8 +240,15 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini
{
Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE;
Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\
- Init->ContinuousClock);
- }
+ Init->ContinuousClock);
+ }
+
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ if(Init->NSBank != FMC_NORSRAM_BANK1)
+ {
+ Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
+ }
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
return HAL_OK;
}
@@ -233,12 +274,12 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EX
/* FMC_NORSRAM_BANK1 */
if(Bank == FMC_NORSRAM_BANK1)
{
- Device->BTCR[Bank] = 0x000030DB;
+ Device->BTCR[Bank] = 0x000030DB;
}
/* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
else
{
- Device->BTCR[Bank] = 0x000030D2;
+ Device->BTCR[Bank] = 0x000030D2;
}
Device->BTCR[Bank + 1] = 0x0FFFFFFF;
@@ -318,20 +359,23 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
{
- /* Check the parameters */
+ /* Check the parameters */
assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
assert_param(IS_FMC_NORSRAM_BANK(Bank));
/* Get the BWTR register value */
tmpr = Device->BWTR[Bank];
-
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \
FMC_BWTR1_BUSTURN | FMC_BWTR1_CLKDIV | FMC_BWTR1_DATLAT | \
@@ -344,6 +388,17 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef
(((Timing->CLKDivision)-1) << 20) |\
(((Timing->DataLatency)-2) << 24) |\
(Timing->AccessMode));
+#else /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */
+ tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \
+ FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));
+
+ tmpr |= (uint32_t)(Timing->AddressSetupTime |\
+ ((Timing->AddressHoldTime) << 4) |\
+ ((Timing->DataSetupTime) << 8) |\
+ ((Timing->BusTurnAroundDuration) << 16) |\
+ (Timing->AccessMode));
+#endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
Device->BWTR[Bank] = tmpr;
}
@@ -417,7 +472,7 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device
*/
/** @addtogroup FMC_LL_NAND
- * @brief PCCARD Controller functions
+ * @brief NAND Controller functions
*
@verbatim
==============================================================================
@@ -440,10 +495,279 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device
@endverbatim
* @{
*/
+
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the FMC NAND interface
+ (+) De-initialize the FMC NAND interface
+ (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the FMC_NAND device according to the specified
+ * control parameters in the FMC_NAND_HandleTypeDef
+ * @param Device: Pointer to NAND device instance
+ * @param Init: Pointer to NAND Initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
+{
+ uint32_t tmpr = 0;
-/** @addtogroup FMC_LL_NAND_Private_Functions_Group1
- * @brief Initialization and Configuration functions
- *
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Init->NandBank));
+ assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
+ assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
+ assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
+ assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
+ assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
+ assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
+
+ /* Get the NAND bank register value */
+ tmpr = Device->PCR;
+
+ /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
+ tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \
+ FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \
+ FMC_PCR_TAR | FMC_PCR_ECCPS));
+
+ /* Set NAND device control parameters */
+ tmpr |= (uint32_t)(Init->Waitfeature |\
+ FMC_PCR_MEMORY_TYPE_NAND |\
+ Init->MemoryDataWidth |\
+ Init->EccComputation |\
+ Init->ECCPageSize |\
+ ((Init->TCLRSetupTime) << 9) |\
+ ((Init->TARSetupTime) << 13));
+
+ /* NAND bank registers configuration */
+ Device->PCR = tmpr;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_NAND Common space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device: Pointer to NAND device instance
+ * @param Timing: Pointer to NAND timing structure
+ * @param Bank: NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+ uint32_t tmpr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Get the NAND bank 2 register value */
+ tmpr = Device->PMEM;
+
+
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
+ tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET2 | FMC_PMEM_MEMWAIT2 | FMC_PMEM_MEMHOLD2 | \
+ FMC_PMEM_MEMHIZ2));
+
+ /* Set FMC_NAND device timing parameters */
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8) |\
+ ((Timing->HoldSetupTime) << 16) |\
+ ((Timing->HiZSetupTime) << 24)
+ );
+
+ /* NAND bank registers configuration */
+ Device->PMEM = tmpr;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device: Pointer to NAND device instance
+ * @param Timing: Pointer to NAND timing structure
+ * @param Bank: NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+ uint32_t tmpr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Get the NAND bank register value */
+ tmpr = Device->PATT;
+
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
+ tmpr &= ((uint32_t)~(FMC_PATT_ATTSET2 | FMC_PATT_ATTWAIT2 | FMC_PATT_ATTHOLD2 | \
+ FMC_PATT_ATTHIZ2));
+
+ /* Set FMC_NAND device timing parameters */
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8) |\
+ ((Timing->HoldSetupTime) << 16) |\
+ ((Timing->HiZSetupTime) << 24));
+
+ /* NAND bank registers configuration */
+ Device->PATT = tmpr;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DeInitializes the FMC_NAND device
+ * @param Device: Pointer to NAND device instance
+ * @param Bank: NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Disable the NAND Bank */
+ __FMC_NAND_DISABLE(Device, Bank);
+
+ /* De-initialize the NAND Bank */
+ /* Set the FMC_NAND_BANK registers to their reset values */
+ Device->PCR = 0x00000018;
+ Device->SR = 0x00000040;
+ Device->PMEM = 0xFCFCFCFC;
+ Device->PATT = 0xFCFCFCFC;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_FMC_NAND_Group2 Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### FMC_NAND Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the FMC NAND interface.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Enables dynamically FMC_NAND ECC feature.
+ * @param Device: Pointer to NAND device instance
+ * @param Bank: NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Enable ECC feature */
+ Device->PCR |= FMC_PCR_ECCEN;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Disables dynamically FMC_NAND ECC feature.
+ * @param Device: Pointer to NAND device instance
+ * @param Bank: NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Disable ECC feature */
+ Device->PCR &= ~FMC_PCR_ECCEN;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FMC_NAND ECC feature.
+ * @param Device: Pointer to NAND device instance
+ * @param ECCval: Pointer to ECC value
+ * @param Bank: NAND bank number
+ * @param Timeout: Timeout wait value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until FIFO is empty */
+ while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Get the ECCR register value */
+ *ECCval = (uint32_t)Device->ECCR;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+#else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
+/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
@@ -783,11 +1107,13 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui
/**
* @}
*/
-
+
+#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
/**
* @}
*/
-
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/** @addtogroup FMC_LL_PCCARD
* @brief PCCARD Controller functions
*
@@ -995,6 +1321,7 @@ HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
/**
* @}
*/
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
/** @addtogroup FMC_LL_SDRAM
@@ -1298,7 +1625,7 @@ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Com
/* Get tick */
tickstart = HAL_GetTick();
- /* wait until command is send */
+ /* Wait until command is send */
while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
{
/* Check for the Timeout */
@@ -1308,18 +1635,16 @@ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Com
{
return HAL_TIMEOUT;
}
- }
-
- return HAL_ERROR;
+ }
}
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
* @brief Program the SDRAM Memory Refresh rate.
* @param Device: Pointer to SDRAM device instance
- * @param RefreshRate: The SDRAM refresh rate value.
+ * @param RefreshRate: The SDRAM refresh rate value.
* @retval HAL state
*/
HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
@@ -1394,7 +1719,7 @@ uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
/**
* @}
*/
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */
/**
diff --git a/f4/src/stm32f4xx_ll_fsmc.c b/f4/src/stm32f4xx_ll_fsmc.c
index 2efba1b..778bb0e 100755
--- a/f4/src/stm32f4xx_ll_fsmc.c
+++ b/f4/src/stm32f4xx_ll_fsmc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_fsmc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief FSMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -44,7 +44,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -84,7 +84,7 @@
*/
#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -377,7 +377,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi
/**
* @}
*/
-
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
/** @addtogroup FSMC_LL_NAND
* @brief NAND Controller functions
*
@@ -938,11 +939,12 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
/**
* @}
*/
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
/**
diff --git a/f4/src/stm32f4xx_ll_sdmmc.c b/f4/src/stm32f4xx_ll_sdmmc.c
index 166b718..a07fd56 100755
--- a/f4/src/stm32f4xx_ll_sdmmc.c
+++ b/f4/src/stm32f4xx_ll_sdmmc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_sdmmc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief SDMMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -138,7 +138,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -177,8 +177,11 @@
* @{
*/
-#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
-
+#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -492,7 +495,8 @@ HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
/**
* @}
*/
-
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
#endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */
/**
* @}
diff --git a/f4/src/stm32f4xx_ll_usb.c b/f4/src/stm32f4xx_ll_usb.c
index 55b137a..184b775 100755
--- a/f4/src/stm32f4xx_ll_usb.c
+++ b/f4/src/stm32f4xx_ll_usb.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_usb.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 26-December-2014
+ * @version V1.4.1
+ * @date 09-October-2015
* @brief USB Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -22,13 +22,13 @@
(#) Call USB_CoreInit() API to initialize the USB Core peripheral.
- (#) The upper HAL HCD/PCD driver will call the righ routines for its internal processes.
+ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -62,8 +62,11 @@
* @{
*/
-#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
-
+#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -72,7 +75,9 @@
/* Private functions ---------------------------------------------------------*/
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
-/** @defgroup PCD_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions
* @{
*/
@@ -117,7 +122,6 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
}
else /* FS interface (embedded Phy) */
{
-
/* Select FS Embedded PHY */
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
@@ -166,7 +170,7 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
* @brief USB_SetCurrentMode : Set functional mode
* @param USBx : Selected device
* @param mode : current core mode
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* @arg USB_OTG_DEVICE_MODE: Peripheral mode
* @arg USB_OTG_HOST_MODE: Host mode
* @arg USB_OTG_DRD_MODE: Dual Role Device mode
@@ -202,13 +206,27 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
uint32_t i = 0;
/*Activate VBUS Sensing B */
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
+
+ if (cfg.vbus_sensing_enable == 0)
+ {
+ /* Deactivate VBUS Sensing B */
+ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+
+ /* B-peripheral session valid override enable*/
+ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
+ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+ }
+#else
USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
if (cfg.vbus_sensing_enable == 0)
{
USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
}
-
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+
/* Restart the Phy Clock */
USBx_PCGCCTL = 0;
@@ -237,7 +255,6 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
/* Flush the FIFOs */
USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */
USB_FlushRxFifo(USBx);
-
/* Clear all pending Device Interrupts */
USBx_DEVICE->DIEPMSK = 0;
@@ -330,7 +347,7 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
{
uint32_t count = 0;
- USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 5 ));
+ USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6));
do
{
@@ -373,7 +390,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
* depending the PHY type and the enumeration speed of the device.
* @param USBx : Selected device
* @param speed : device speed
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
@@ -390,7 +407,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
* @brief USB_GetDevSpeed :Return the Dev Speed
* @param USBx : Selected device
* @retval speed : device speed
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @arg USB_OTG_SPEED_LOW: Low speed mode
@@ -507,7 +524,6 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP
}
else
{
-
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
@@ -542,7 +558,7 @@ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, U
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @param dma: USB dma enabled or disabled
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @retval HAL status
@@ -664,7 +680,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @param dma: USB dma enabled or disabled
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @retval HAL status
@@ -753,7 +769,7 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD
* @param ch_ep_num : endpoint or host channel number
* @param len : Number of bytes to write
* @param dma: USB dma enabled or disabled
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @retval HAL status
@@ -781,7 +797,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin
* @param ch_ep_num : endpoint or host channel number
* @param len : Number of bytes to read
* @param dma: USB dma enabled or disabled
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @retval pointer to destination buffer
@@ -1012,7 +1028,7 @@ void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
* @brief Returns USB core mode
* @param USBx : Selected device
* @retval return core mode : Host or Device
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : Host
* 1 : Device
*/
@@ -1046,7 +1062,7 @@ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
* @brief Prepare the EP0 to start the first control setup
* @param USBx : Selected device
* @param dma: USB dma enabled or disabled
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @param psetup : pointer to setup packet
@@ -1121,11 +1137,15 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
/* Restart the Phy Clock */
USBx_PCGCCTL = 0;
- /* no VBUS sensing*/
+ /* Activate VBUS Sensing B */
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
+#else
USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSASEN);
USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSBSEN);
USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+
/* Disable the FS/LS support mode only */
if((cfg.speed == USB_OTG_SPEED_FULL)&&
(USBx != USB_OTG_FS))
@@ -1158,7 +1178,6 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
/* Clear any pending interrupts */
USBx->GINTSTS = 0xFFFFFFFF;
-
if(USBx == USB_OTG_FS)
{
@@ -1166,9 +1185,7 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
USBx->GRXFSIZ = (uint32_t )0x80;
USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80);
USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0);
-
}
-
else
{
/* set Rx FIFO size */
@@ -1196,7 +1213,7 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
* HCFG register on the PHY type and set the right frame interval
* @param USBx : Selected device
* @param freq : clock frequency
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* HCFG_48_MHZ : Full Speed 48 MHz Clock
* HCFG_6_MHZ : Low Speed 6 MHz Clock
* @retval HAL status
@@ -1221,7 +1238,7 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq
* @brief USB_OTG_ResetPort : Reset Host Port
* @param USBx : Selected device
* @retval HAL status
- * @note : (1)The application must wait at least 10 ms
+ * @note (1)The application must wait at least 10 ms
* before clearing the reset bit.
*/
HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
@@ -1242,7 +1259,7 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
/**
* @brief USB_DriveVbus : activate or de-activate vbus
* @param state : VBUS state
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : VBUS Active
* 1 : VBUS Inactive
* @retval HAL status
@@ -1270,7 +1287,7 @@ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
* @brief Return Host Core speed
* @param USBx : Selected device
* @retval speed : Host speed
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @arg USB_OTG_SPEED_LOW: Low speed mode
@@ -1303,12 +1320,12 @@ uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
* @param dev_address : Current device address
* This parameter can be a value from 0 to 255
* @param speed : Current device speed
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @arg USB_OTG_SPEED_LOW: Low speed mode
* @param ep_type : Endpoint Type
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* @arg EP_TYPE_CTRL: Control type
* @arg EP_TYPE_ISOC: Isochronous type
* @arg EP_TYPE_BULK: Bulk type
@@ -1354,6 +1371,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
}
}
break;
+
case EP_TYPE_INTR:
USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
@@ -1411,7 +1429,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
* @param USBx : Selected device
* @param hc : pointer to host channel structure
* @param dma: USB dma enabled or disabled
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @retval HAL state
@@ -1427,7 +1445,8 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
uint16_t len_words = 0;
uint16_t num_packets = 0;
uint16_t max_hc_pkt_count = 256;
-
+ uint32_t tmpreg = 0;
+
if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))
{
if((dma == 0) && (hc->do_ping == 1))
@@ -1462,8 +1481,6 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
hc->xfer_len = num_packets * hc->max_packet;
}
-
-
/* Initialize the HCTSIZn register */
USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\
((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
@@ -1480,8 +1497,10 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);
/* Set host channel enable */
- USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
- USBx_HC(hc->ch_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ tmpreg = USBx_HC(hc->ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hc->ch_num)->HCCHAR = tmpreg;
if (dma == 0) /* Slave mode */
{
@@ -1608,13 +1627,16 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
{
uint8_t num_packets = 1;
+ uint32_t tmpreg = 0;
USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
USB_OTG_HCTSIZ_DOPING;
/* Set host channel enable */
- USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
- USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ tmpreg = USBx_HC(ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(ch_num)->HCCHAR = tmpreg;
return HAL_OK;
}
@@ -1649,8 +1671,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
/* Halt all channels to put them into a known state. */
for (i = 0; i <= 15; i++)
- {
-
+ {
value = USBx_HC(i)->HCCHAR ;
value |= USB_OTG_HCCHAR_CHDIS;
@@ -1677,8 +1698,9 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
/**
* @}
*/
-
-#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) */
/**
* @}
--
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