diff --git a/Makefile b/Makefile
index a31bfbc860871d44e4b610875ecd7a6baaf99b47..bb0fa5f9cc1cd754f5716e5ba69777ee29fd331d 100755
--- a/Makefile
+++ b/Makefile
@@ -2,22 +2,25 @@
 # modified by zerom for WinARM 8/2010
 
 PROJECT_NAME=darwin_firmware
-TARGET_FILES=$(wildcard src/*.c)
+#TARGET_FILES=$(wildcard src/*.c)
+TARGET_FILES=src/cm730_fw.c
+TARGET_FILES+=src/gpio.c
+TARGET_FILES+=src/ram.c
+TARGET_FILES+=src/stm32f1xx_hal_msp.c
 TARGET_PROCESSOR=STM32F103RE
 
-include ../../STM32_processor/libraries/f1/select_processor.mk
+HAL_PATH=../../STM32_processor/hal/f1
 
-STM32_LIB_PATH = ../../STM32_processor/libraries/f1/stm32_lib
-DYNAMIXEL_LIB_PATH = ../../STM32_processor/libraries/
-STM32_STARTUP_FILES_PATH = ../../STM32_processor/startup/f1
+include $(HAL_PATH)/select_processor.mk
+
+STM32_STARTUP_FILES_PATH = $(HAL_PATH)/startup_code/
 STM32_LINKER_SCRIPTS_PATH = ./linker_script
 BUILD_PATH=build
 
 COMPILE_OPTS = -mlittle-endian -mcpu=cortex-m3 -mthumb -mthumb-interwork 
 COMPILE_OPTS += -Wall -g -O2 -fno-common -msoft-float 
-COMPILE_OPTS += -ffreestanding -nostdlib -D$(PROCESSOR_MACRO) -DHSE_VALUE=8000000
-INCLUDE_DIRS = -I$(STM32_LIB_PATH)/include -I$(STM32_LIB_PATH)/include/core -I$(STM32_LIB_PATH)/include/devices -I${DYNAMIXEL_LIB_PATH}/include/dynamixel -I./include
-LIBRARY_DIRS = -L$(STM32_LIB_PATH)/lib -L$(STM32_DSP_LIB_PATH)/lib -L$(DYNAMIXEL_LIB_PATH)/lib 
+COMPILE_OPTS += -ffreestanding -nostdlib -D$(PROCESSOR_MACRO) 
+INCLUDE_DIRS = -I$(HAL_PATH)/include -I$(HAL_PATH)/include/core -I$(HAL_PATH)/include/devices -I./include
 
 TCHAIN_PREFIX=arm-none-eabi-
 
@@ -28,7 +31,7 @@ AS = $(TCHAIN_PREFIX)gcc
 ASFLAGS = $(COMPILE_OPTS) -c 
 
 LD = $(TCHAIN_PREFIX)gcc
-LDFLAGS = -mthumb -mcpu=cortex-m3 -Wl,-Map=$@.map,-cref $(INCLUDE_DIRS) $(LIBRARY_DIRS) -T $(STM32_LINKER_SCRIPTS_PATH)/darwin.ld -nostartfiles 
+LDFLAGS = -mthumb -mcpu=cortex-m3 -Wl,-Map=$@.map,-cref $(INCLUDE_DIRS) -T $(STM32_LINKER_SCRIPTS_PATH)/darwin.ld --specs=nosys.specs
 
 OBJCP = $(TCHAIN_PREFIX)objcopy
 OBJCPFLAGS_HEX = -O ihex
@@ -41,8 +44,21 @@ MAIN_OUT_HEX = $(BUILD_PATH)/$(PROJECT_NAME).hex
 MAIN_OUT_BIN = $(BUILD_PATH)/$(PROJECT_NAME).bin
 MAIN_OUT_LSS = $(BUILD_PATH)/$(PROJECT_NAME).lss
 
-BIOLOID_OBJS_TMP = $(notdir $(TARGET_FILES:.c=.o))
-BIOLOID_OBJS = $(patsubst %,$(BUILD_PATH)/%,$(BIOLOID_OBJS_TMP))
+# add STM32 src files
+TARGET_FILES+=$(HAL_PATH)/src/devices/system_stm32f1xx.c
+TARGET_FILES+=$(HAL_PATH)/src/stm32f1xx_hal_gpio.c
+TARGET_FILES+=$(HAL_PATH)/src/stm32f1xx_hal_cortex.c
+TARGET_FILES+=$(HAL_PATH)/src/stm32f1xx_hal_rcc.c
+TARGET_FILES+=$(HAL_PATH)/src/stm32f1xx_hal_pwr.c
+TARGET_FILES+=$(HAL_PATH)/src/stm32f1xx_hal_tim.c
+TARGET_FILES+=$(HAL_PATH)/src/stm32f1xx_hal_tim_ex.c
+TARGET_FILES+=$(HAL_PATH)/src/stm32f1xx_hal_dma.c
+TARGET_FILES+=$(HAL_PATH)/src/stm32f1xx_hal_flash.c
+TARGET_FILES+=$(HAL_PATH)/src/stm32f1xx_hal_flash_ex.c
+TARGET_FILES+=$(HAL_PATH)/src/stm32f1xx_hal.c
+
+DARWIN_OBJS_TMP = $(notdir $(TARGET_FILES:.c=.o))
+DARWIN_OBJS = $(patsubst %,$(BUILD_PATH)/%,$(DARWIN_OBJS_TMP))
 
 all: $(MAIN_OUT_ELF) $(MAIN_OUT_HEX) $(MAIN_OUT_BIN) $(MAIN_OUT_LSS)
 
@@ -51,9 +67,13 @@ mkdir_build:
 
 $(BUILD_PATH)/%.o: src/%.c 
 	$(CC) -c $(CFLAGS) -o $@ $<
+$(BUILD_PATH)/%.o: $(HAL_PATH)/src/devices/%.c
+	$(CC) -c $(CFLAGS) -o $@ $<
+$(BUILD_PATH)/%.o: $(HAL_PATH)/src/%.c
+	$(CC) -c $(CFLAGS) -o $@ $<
 
-$(MAIN_OUT_ELF): mkdir_build $(BIOLOID_OBJS) $(BUID_PATH)/$(STARTUP_FILE:.s=.o) $(STM32_LIB_PATH)/lib/$(LIBRARY) 
-	$(LD) $(LDFLAGS) $(BIOLOID_OBJS) $(BUILD_PATH)/$(STARTUP_FILE:.s=.o) $(STM32_LIB_PATH)/lib/$(LIBRARY) ${DYNAMIXEL_LIB_PATH}/lib/dynamixel.a -lm --output $@
+$(MAIN_OUT_ELF): mkdir_build $(DARWIN_OBJS) $(BUID_PATH)/$(STARTUP_FILE:.s=.o) 
+	$(LD) $(LDFLAGS) $(DARWIN_OBJS) $(BUILD_PATH)/$(STARTUP_FILE:.s=.o) --output $@
 
 $(MAIN_OUT_HEX): $(MAIN_OUT_ELF)	
 	$(OBJCP) $(OBJCPFLAGS_HEX) $< $@
diff --git a/include/adc_dma.h b/include/adc_dma.h
index 20308ccc2b4b25ec35a1a88a47c1bf546b57b117..073627d126cb2020bd36a2ea53707f723df9c7cd 100755
--- a/include/adc_dma.h
+++ b/include/adc_dma.h
@@ -1,7 +1,7 @@
 #ifndef _ADC_DMA_H
 #define _ADC_DMA_H
 
-#include "stm32f10x.h"
+#include "stm32f1xx_hal_conf.h"
 
 void adc_init(void);
 
diff --git a/include/eeprom.h b/include/eeprom.h
index 33c9ce9f2c6ee9cdbd4ee831d913b6351f9ff9cb..f24837912dbf5b76e1d83d7e9dffdb5908d3a9b8 100755
--- a/include/eeprom.h
+++ b/include/eeprom.h
@@ -25,7 +25,7 @@
 #define __EEPROM_H
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
+#include "stm32f1xx.h"
 
 /* Exported constants --------------------------------------------------------*/
 /* Define the size of the sectors to be used */
diff --git a/include/gpio.h b/include/gpio.h
index 755d91add31463bb3b7efef0bf24b1ecca075dd5..ae2b05b4f38e186f358ce604f3b450edbf31eca5 100755
--- a/include/gpio.h
+++ b/include/gpio.h
@@ -1,7 +1,7 @@
 #ifndef _GPIO_H
 #define _GPIO_H
 
-#include "stm32f10x.h"
+#include "stm32f1xx_hal.h"
 
 typedef enum {LED_TX,LED_RX,LED_2,LED_3,LED_4,LED_5_R,LED_5_G,LED_5_B,LED_6_R,LED_6_G,LED_6_B} led_t;
 
diff --git a/include/ram.h b/include/ram.h
index 737a71b94a99266b57b9156f03cc16cfebf2f419..2f300a33da6c35a9ce505788c57444cc626f8e13 100755
--- a/include/ram.h
+++ b/include/ram.h
@@ -1,7 +1,7 @@
 #ifndef _RAM_H
 #define _RAM_H
 
-#include "stm32f10x.h"
+#include "stm32f1xx_hal.h"
 #include "eeprom.h"
 
 #define      RAM_SUCCESS       0
diff --git a/include/stm32f1xx_hal_conf.h b/include/stm32f1xx_hal_conf.h
new file mode 100755
index 0000000000000000000000000000000000000000..4f2e8cfa12169afb99c46d2fe9f6daf6f9a0fe0d
--- /dev/null
+++ b/include/stm32f1xx_hal_conf.h
@@ -0,0 +1,367 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_conf.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    15-December-2014
+  * @brief   HAL configuration template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32f1xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_CONF_H
+#define __STM32F1xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+#define HAL_MODULE_ENABLED
+//#define HAL_ADC_MODULE_ENABLED
+//#define HAL_CAN_MODULE_ENABLED
+//#define HAL_CEC_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+//#define HAL_CRC_MODULE_ENABLED
+//#define HAL_DAC_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+//#define HAL_ETH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+//#define HAL_HCD_MODULE_ENABLED
+//#define HAL_I2C_MODULE_ENABLED
+//#define HAL_I2S_MODULE_ENABLED
+//#define HAL_IRDA_MODULE_ENABLED
+//#define HAL_IWDG_MODULE_ENABLED
+//#define HAL_NAND_MODULE_ENABLED
+//#define HAL_NOR_MODULE_ENABLED
+//#define HAL_PCCARD_MODULE_ENABLED
+//#define HAL_PCD_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+//#define HAL_RTC_MODULE_ENABLED
+//#define HAL_SD_MODULE_ENABLED
+//#define HAL_SMARTCARD_MODULE_ENABLED
+//#define HAL_SPI_MODULE_ENABLED
+//#define HAL_SRAM_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+//#define HAL_UART_MODULE_ENABLED
+//#define HAL_USART_MODULE_ENABLED
+//#define HAL_WWDG_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+#if defined(USE_STM3210C_EVAL)
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#else
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+   
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+   
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            ((uint32_t)0x000F)    /*!< tick interrupt priority */            
+#define  USE_RTOS                     0     
+#define  PREFETCH_ENABLE              1
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/*#define USE_FULL_ASSERT    1*/ 
+
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2
+#define MAC_ADDR1   0
+#define MAC_ADDR2   0
+#define MAC_ADDR3   0
+#define MAC_ADDR4   0
+#define MAC_ADDR5   0
+
+/* Definition of the Ethernet driver buffers size and count */   
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    ((uint32_t)8)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/ 
+#define DP83848_PHY_ADDRESS             0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
+ 
+#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
+  
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
+ 
+#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
+
+#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
+#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
+
+#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
+#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
+
+
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f1xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f1xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+   
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f1xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+   
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f1xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */  
+   
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f1xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f1xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f1xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f1xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f1xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f1xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f1xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f1xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f1xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f1xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f1xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f1xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f1xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f1xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f1xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */ 
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f1xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */  
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f1xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */     
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f1xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f1xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f1xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f1xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f1xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f1xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f1xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f1xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f1xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */   
+   
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/include/system_stm32f10x.h b/include/system_stm32f10x.h
deleted file mode 100755
index 739f33283e5a64b1913a5476d430ba11a8bbbd4e..0000000000000000000000000000000000000000
--- a/include/system_stm32f10x.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f10x.h
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32F10X_H
-#define __SYSTEM_STM32F10X_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup STM32F10x_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32F10x_System_Exported_types
-  * @{
-  */
-
-extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Exported_Functions
-  * @{
-  */
-  
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32F10X_H */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/src/cm730_fw.c b/src/cm730_fw.c
index c03b7fd7a1aaf9f8b6f73ef994b53ec89ba9cb6a..7221b7666fec488ddb9d3447e17c5333eeb36d44 100755
--- a/src/cm730_fw.c
+++ b/src/cm730_fw.c
@@ -1,45 +1,45 @@
-#include "stm32f10x.h"
+#include "stm32f1xx_hal.h"
 #include "gpio.h"
-#include "time.h"
-#include "eeprom.h"
-#include "motion_manager.h"
-#include "action.h"
-#include "walking.h"
-#include "joint_motion.h"
-#include "head_tracking.h"
-#include "grippers.h"
-#include "dynamixel_slave_uart_dma.h"
-#include "dynamixel_master_uart_dma.h"
-#include "ram.h"
-#include "imu.h"
-#include "adc_dma.h"
-#include "comm.h"
-#include <math.h>
+//#include "time.h"
+//#include "eeprom.h"
+//#include "motion_manager.h"
+//#include "action.h"
+//#include "walking.h"
+//#include "joint_motion.h"
+//#include "head_tracking.h"
+//#include "grippers.h"
+//#include "dynamixel_slave_uart_dma.h"
+//#include "dynamixel_master_uart_dma.h"
+//#include "ram.h"
+//#include "imu.h"
+//#include "adc_dma.h"
+//#include "comm.h"
+//#include <math.h>
 
 int main(void)
 {
-  uint16_t eeprom_data;
-  uint16_t period,count=0;
+//  uint16_t eeprom_data;
+//  uint16_t period,count=0;
 
   /* initialize EEPROM */
-  EE_Init();
+//  EE_Init();
   // initialize the Dynamixel RAM memory space
-  ram_init();
+//  ram_init();
   /* initialize the 1ms system timer */
-  time_init();
+//  time_init();
   /* initialize the gpio */
-  gpio_init();
+//  gpio_init();
   /* initialize the dynamixel master interface */
-  dyn_master_init();
-  dyn_master_set_timeout(50);
+//  dyn_master_init();
+//  dyn_master_set_timeout(50);
   /* initialize the dynamixel slave interface*/
-  dyn_slave_init();
-  EE_ReadVariable(DEVICE_ID_OFFSET,&eeprom_data);
-  dyn_slave_set_address((uint8_t)eeprom_data);
-  EE_ReadVariable(RETURN_DELAY_OFFSET,&eeprom_data);
-  dyn_slave_set_return_delay((uint8_t)eeprom_data);
-  EE_ReadVariable(RETURN_LEVEL_OFFSET,&eeprom_data);
-  dyn_slave_set_return_level((uint8_t)eeprom_data);
+//  dyn_slave_init();
+//  EE_ReadVariable(DEVICE_ID_OFFSET,&eeprom_data);
+//  dyn_slave_set_address((uint8_t)eeprom_data);
+//  EE_ReadVariable(RETURN_DELAY_OFFSET,&eeprom_data);
+//  dyn_slave_set_return_delay((uint8_t)eeprom_data);
+//  EE_ReadVariable(RETURN_LEVEL_OFFSET,&eeprom_data);
+//  dyn_slave_set_return_level((uint8_t)eeprom_data);
   // initialize motion manager
 //  EE_ReadVariable(MM_PERIOD_OFFSET,&eeprom_data);
 //  period=eeprom_data&0x00FF;
@@ -50,15 +50,21 @@ int main(void)
   // initialize imu
 //  imu_init();
   // initialize adc
-  adc_init();
-  gpio_blink_led(LED_5_R,1000);
-  comm_init();
+//  adc_init();
+//  gpio_blink_led(LED_5_R,1000);
+//  comm_init();
 
-  dyn_master_enable_power();
-  delay_ms(1000);
+//  dyn_master_enable_power();
+//  delay_ms(1000);
   
-  comm_start();
+//  comm_start();
+
+  /* initialize the HAL module */
+  HAL_Init();
+  /* initialize the GPIO module */
+  gpio_init();
 
+  gpio_blink_led(LED_2,1000);
   while(1);                             /* main function does not return */
 }
 
diff --git a/src/gpio.c b/src/gpio.c
index aaa06b20bd9a96155152ac3b5f79fc854e52c6c8..c86e0f8cd1724761082d103d8778b34105331685 100755
--- a/src/gpio.c
+++ b/src/gpio.c
@@ -1,89 +1,70 @@
 #include "gpio.h"
 #include "ram.h"
 
-#define LED_TX_GPIO_CLK             RCC_APB2Periph_GPIOC
-#define LED_TX_PIN                  GPIO_Pin_13                
+#define ENABLE_LED_TX_GPIO_CLK      __HAL_RCC_GPIOC_CLK_ENABLE()
+#define LED_TX_PIN                  GPIO_PIN_13                
 #define LED_TX_GPIO_PORT            GPIOC                       
-#define LED_TX_SOURCE               GPIO_PinSource13
 
-#define LED_RX_GPIO_CLK             RCC_APB2Periph_GPIOC
-#define LED_RX_PIN                  GPIO_Pin_14                
+#define ENABLE_LED_RX_GPIO_CLK      __HAL_RCC_GPIOC_CLK_ENABLE()
+#define LED_RX_PIN                  GPIO_PIN_14                
 #define LED_RX_GPIO_PORT            GPIOC                       
-#define LED_RX_SOURCE               GPIO_PinSource14
 
-#define LED_2_GPIO_CLK              RCC_APB2Periph_GPIOC
-#define LED_2_PIN                   GPIO_Pin_15            
+#define ENABLE_LED_2_GPIO_CLK       __HAL_RCC_GPIOC_CLK_ENABLE()
+#define LED_2_PIN                   GPIO_PIN_15            
 #define LED_2_GPIO_PORT             GPIOC                  
-#define LED_2_SOURCE                GPIO_PinSource15
  
-#define LED_3_GPIO_CLK              RCC_APB2Periph_GPIOC
-#define LED_3_PIN                   GPIO_Pin_6            
+#define ENABLE_LED_3_GPIO_CLK       __HAL_RCC_GPIOC_CLK_ENABLE()
+#define LED_3_PIN                   GPIO_PIN_6            
 #define LED_3_GPIO_PORT             GPIOC                       
-#define LED_3_SOURCE                GPIO_PinSource6
 
-#define LED_4_GPIO_CLK              RCC_APB2Periph_GPIOB
-#define LED_4_PIN                   GPIO_Pin_12            
+#define ENABLE_LED_4_GPIO_CLK       __HAL_RCC_GPIOB_CLK_ENABLE()
+#define LED_4_PIN                   GPIO_PIN_12            
 #define LED_4_GPIO_PORT             GPIOB                       
-#define LED_4_SOURCE                GPIO_PinSource12
 
-#define LED_5_R_GPIO_CLK            RCC_APB2Periph_GPIOC
-#define LED_5_R_PIN                 GPIO_Pin_7            
+#define ENABLE_LED_5_R_GPIO_CLK     __HAL_RCC_GPIOC_CLK_ENABLE()
+#define LED_5_R_PIN                 GPIO_PIN_7            
 #define LED_5_R_GPIO_PORT           GPIOC                       
-#define LED_5_R_SOURCE              GPIO_PinSource7
 
-#define LED_5_G_GPIO_CLK            RCC_APB2Periph_GPIOC
-#define LED_5_G_PIN                 GPIO_Pin_8            
+#define ENABLE_LED_5_G_GPIO_CLK     __HAL_RCC_GPIOC_CLK_ENABLE()
+#define LED_5_G_PIN                 GPIO_PIN_8            
 #define LED_5_G_GPIO_PORT           GPIOC                       
-#define LED_5_G_SOURCE              GPIO_PinSource8
 
-#define LED_5_B_GPIO_CLK            RCC_APB2Periph_GPIOC
-#define LED_5_B_PIN                 GPIO_Pin_9            
+#define ENABLE_LED_5_B_GPIO_CLK     __HAL_RCC_GPIOC_CLK_ENABLE()
+#define LED_5_B_PIN                 GPIO_PIN_9            
 #define LED_5_B_GPIO_PORT           GPIOC                       
-#define LED_5_B_SOURCE              GPIO_PinSource9
 
-#define LED_6_R_GPIO_CLK            RCC_APB2Periph_GPIOA
-#define LED_6_R_PIN                 GPIO_Pin_8            
+#define ENABLE_LED_6_R_GPIO_CLK     __HAL_RCC_GPIOA_CLK_ENABLE()
+#define LED_6_R_PIN                 GPIO_PIN_8            
 #define LED_6_R_GPIO_PORT           GPIOA                       
-#define LED_6_R_SOURCE              GPIO_PinSource8
 
-#define LED_6_G_GPIO_CLK            RCC_APB2Periph_GPIOA
-#define LED_6_G_PIN                 GPIO_Pin_11
+#define ENABLE_LED_6_G_GPIO_CLK     __HAL_RCC_GPIOA_CLK_ENABLE()
+#define LED_6_G_PIN                 GPIO_PIN_11
 #define LED_6_G_GPIO_PORT           GPIOA                       
-#define LED_6_G_SOURCE              GPIO_PinSource11
 
-#define LED_6_B_GPIO_CLK            RCC_APB2Periph_GPIOA
-#define LED_6_B_PIN                 GPIO_Pin_12            
+#define ENABLE_LED_6_B_GPIO_CLK     __HAL_RCC_GPIOA_CLK_ENABLE()
+#define LED_6_B_PIN                 GPIO_PIN_12            
 #define LED_6_B_GPIO_PORT           GPIOA                       
-#define LED_6_B_SOURCE              GPIO_PinSource12
 
-#define START_PB_GPIO_CLK           RCC_APB2Periph_GPIOA
-#define START_PB_PIN                GPIO_Pin_15                
+#define ENABLE_START_PB_GPIO_CLK    __HAL_RCC_GPIOA_CLK_ENABLE()
+#define START_PB_PIN                GPIO_PIN_15                
 #define START_PB_GPIO_PORT          GPIOA                       
-#define START_PB_SOURCE             GPIO_PinSource15
-#define START_PB_EXTI_PORT          EXTI_PortSourceGPIOA
-#define START_PB_EXTI_PIN           EXTI_PinSource15
-#define START_PB_EXTI_LINE          EXTI_Line15
 
-#define MODE_PB_GPIO_CLK            RCC_APB2Periph_GPIOA
-#define MODE_PB_PIN                 GPIO_Pin_14                
+#define ENABLE_MODE_PB_GPIO_CLK     __HAL_RCC_GPIOA_CLK_ENABLE() 
+#define MODE_PB_PIN                 GPIO_PIN_14                
 #define MODE_PB_GPIO_PORT           GPIOA                       
-#define MODE_PB_SOURCE              GPIO_PinSource14
-#define MODE_PB_EXTI_PORT           EXTI_PortSourceGPIOA
-#define MODE_PB_EXTI_PIN            EXTI_PinSource14
-#define MODE_PB_EXTI_LINE           EXTI_Line14
 
 #define GPO_TIMER1                  TIM2
-#define GPO_TIMER1_CLK              RCC_APB1Periph_TIM2
+#define ENABLE_GPO_TIMER1_CLK       __HAL_RCC_TIM2_CLK_ENABLE()
 #define GPO_TIMER1_IRQn             TIM2_IRQn
 #define GPO_TIMER1_IRQHandler       TIM2_IRQHandler
 
 #define GPO_TIMER2                  TIM3
-#define GPO_TIMER2_CLK              RCC_APB1Periph_TIM3
+#define ENABLE_GPO_TIMER2_CLK       __HAL_RCC_TIM3_CLK_ENABLE()
 #define GPO_TIMER2_IRQn             TIM3_IRQn
 #define GPO_TIMER2_IRQHandler       TIM3_IRQHandler
 
 #define GPO_TIMER3                  TIM4
-#define GPO_TIMER3_CLK              RCC_APB1Periph_TIM4
+#define ENABLE_GPO_TIMER3_CLK       __HAL_RCC_TIM4_CLK_ENABLE()
 #define GPO_TIMER3_IRQn             TIM4_IRQn
 #define GPO_TIMER3_IRQHandler       TIM4_IRQHandler
 
@@ -91,6 +72,9 @@
 #define GPI_EXTI1_IRQHandler        EXTI15_10_IRQHandler
 
 // private variables
+TIM_HandleTypeDef    GPO_TIM1Handle;
+TIM_HandleTypeDef    GPO_TIM2Handle;
+TIM_HandleTypeDef    GPO_TIM3Handle;
 // LED blink periods
 __IO uint16_t led_tx_period;
 __IO uint16_t led_rx_period;
@@ -110,69 +94,58 @@ void (*mode_pb_callback)(void);
 // IRQ handler functions
 void GPI_EXTI1_IRQHandler(void)
 {
-  if(EXTI_GetITStatus(START_PB_EXTI_LINE) != RESET)
-  {
-    if(start_pb_callback!=0)  
-      start_pb_callback();
-    /* Clear the EXTI line 0 pending bit */
-    EXTI_ClearITPendingBit(START_PB_EXTI_LINE);
-  }
-  if(EXTI_GetITStatus(MODE_PB_EXTI_LINE) != RESET)
-  {
-    if(mode_pb_callback!=0)  
-      mode_pb_callback();
-    /* Clear the EXTI line 0 pending bit */
-    EXTI_ClearITPendingBit(MODE_PB_EXTI_LINE);
-  }
+  HAL_GPIO_EXTI_IRQHandler(START_PB_PIN);
+  HAL_GPIO_EXTI_IRQHandler(MODE_PB_PIN);
+}
+
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  if(GPIO_Pin==START_PB_PIN && start_pb_callback!=0)
+    start_pb_callback();
+
+  if(GPIO_Pin==MODE_PB_PIN && mode_pb_callback!=0)
+    mode_pb_callback();
 }
 
 void GPO_TIMER1_IRQHandler(void)
 {
-  uint16_t capture;
+  HAL_TIM_IRQHandler(&GPO_TIM1Handle);
+}
 
-  if(TIM_GetITStatus(GPO_TIMER1, TIM_IT_CC1)!=RESET)
-  {
-    TIM_ClearITPendingBit(GPO_TIMER1,TIM_IT_CC1);
-    if(GPIO_ReadOutputDataBit(LED_TX_GPIO_PORT,LED_TX_PIN))
-      GPIO_ResetBits(LED_TX_GPIO_PORT,LED_TX_PIN);
-    else
-      GPIO_SetBits(LED_TX_GPIO_PORT,LED_TX_PIN);
-    capture = TIM_GetCapture1(GPO_TIMER1);
-    TIM_SetCompare1(GPO_TIMER1, capture + led_tx_period);
-  }
-  if(TIM_GetITStatus(GPO_TIMER1, TIM_IT_CC2)!=RESET)
-  {
-    TIM_ClearITPendingBit(GPO_TIMER1,TIM_IT_CC2);
-    if(GPIO_ReadOutputDataBit(LED_RX_GPIO_PORT,LED_RX_PIN))
-      GPIO_ResetBits(LED_RX_GPIO_PORT,LED_RX_PIN);
-    else
-      GPIO_SetBits(LED_RX_GPIO_PORT,LED_RX_PIN);
-    capture = TIM_GetCapture2(GPO_TIMER1);
-    TIM_SetCompare2(GPO_TIMER1, capture + led_rx_period);
-  }
-  if(TIM_GetITStatus(GPO_TIMER1, TIM_IT_CC3)!=RESET)
-  {
-    TIM_ClearITPendingBit(GPO_TIMER1,TIM_IT_CC3);
-    if(GPIO_ReadOutputDataBit(LED_2_GPIO_PORT,LED_2_PIN))
-      GPIO_ResetBits(LED_2_GPIO_PORT,LED_2_PIN);
-    else
-      GPIO_SetBits(LED_2_GPIO_PORT,LED_2_PIN);
-    capture = TIM_GetCapture3(GPO_TIMER1);
-    TIM_SetCompare3(GPO_TIMER1, capture + led_2_period);
-  }
-  if(TIM_GetITStatus(GPO_TIMER1, TIM_IT_CC4)!=RESET)
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  uint32_t capture;
+
+  if(htim->Instance==GPO_TIMER1)
   {
-    TIM_ClearITPendingBit(GPO_TIMER1,TIM_IT_CC4);
-    if(GPIO_ReadOutputDataBit(LED_3_GPIO_PORT,LED_3_PIN))
-      GPIO_ResetBits(LED_3_GPIO_PORT,LED_3_PIN);
-    else
-        GPIO_SetBits(LED_3_GPIO_PORT,LED_3_PIN);
-    capture = TIM_GetCapture4(GPO_TIMER1);
-    TIM_SetCompare4(GPO_TIMER1, capture + led_3_period);
+    if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_1)
+    {
+      capture = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_1);
+      __HAL_TIM_SET_COMPARE(htim, TIM_CHANNEL_1, (capture + led_tx_period));
+      HAL_GPIO_TogglePin(LED_TX_GPIO_PORT,LED_TX_PIN);
+    }
+    if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_2)
+    {
+      capture = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_2);
+      __HAL_TIM_SET_COMPARE(htim, TIM_CHANNEL_2, (capture + led_rx_period));
+       HAL_GPIO_TogglePin(LED_RX_GPIO_PORT,LED_RX_PIN);
+    }
+    if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_3)
+    {
+      capture = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_3);
+      __HAL_TIM_SET_COMPARE(htim, TIM_CHANNEL_3, (capture + led_2_period));
+       HAL_GPIO_TogglePin(LED_2_GPIO_PORT,LED_2_PIN);
+    }
+    if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_4)
+    {
+      capture = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_4);
+      __HAL_TIM_SET_COMPARE(htim, TIM_CHANNEL_4, (capture + led_3_period));
+      HAL_GPIO_TogglePin(LED_3_GPIO_PORT,LED_3_PIN);
+    } 
   }
 }
 
-void GPO_TIMER2_IRQHandler(void)
+/*void GPO_TIMER2_IRQHandler(void)
 {
   uint16_t capture;
 
@@ -180,7 +153,7 @@ void GPO_TIMER2_IRQHandler(void)
   {
     TIM_ClearITPendingBit(GPO_TIMER2,TIM_IT_CC1);
     if(GPIO_ReadOutputDataBit(LED_5_R_GPIO_PORT,LED_5_R_PIN))
-      GPIO_ResetBits(LED_5_R_GPIO_PORT,LED_5_R_PIN);
+      HAL_GPIO_WritePin(LED_5_R_GPIO_PORT,LED_5_R_PIN);
     else
       GPIO_SetBits(LED_5_R_GPIO_PORT,LED_5_R_PIN);
     capture = TIM_GetCapture1(GPO_TIMER2);
@@ -190,7 +163,7 @@ void GPO_TIMER2_IRQHandler(void)
   {
     TIM_ClearITPendingBit(GPO_TIMER2,TIM_IT_CC2);
     if(GPIO_ReadOutputDataBit(LED_5_G_GPIO_PORT,LED_5_G_PIN))
-      GPIO_ResetBits(LED_5_G_GPIO_PORT,LED_5_G_PIN);
+      HAL_GPIO_WritePin(LED_5_G_GPIO_PORT,LED_5_G_PIN);
     else
       GPIO_SetBits(LED_5_G_GPIO_PORT,LED_5_G_PIN);
     capture = TIM_GetCapture2(GPO_TIMER2);
@@ -200,7 +173,7 @@ void GPO_TIMER2_IRQHandler(void)
   {
     TIM_ClearITPendingBit(GPO_TIMER2,TIM_IT_CC3);
     if(GPIO_ReadOutputDataBit(LED_5_B_GPIO_PORT,LED_5_B_PIN))
-      GPIO_ResetBits(LED_5_B_GPIO_PORT,LED_5_B_PIN);
+      HAL_GPIO_WritePin(LED_5_B_GPIO_PORT,LED_5_B_PIN);
     else
       GPIO_SetBits(LED_5_B_GPIO_PORT,LED_5_B_PIN);
     capture = TIM_GetCapture3(GPO_TIMER2);
@@ -210,7 +183,7 @@ void GPO_TIMER2_IRQHandler(void)
   {
     TIM_ClearITPendingBit(GPO_TIMER2,TIM_IT_CC4);
     if(GPIO_ReadOutputDataBit(LED_4_GPIO_PORT,LED_4_PIN))
-      GPIO_ResetBits(LED_4_GPIO_PORT,LED_4_PIN);
+      HAL_GPIO_WritePin(LED_4_GPIO_PORT,LED_4_PIN);
     else
       GPIO_SetBits(LED_4_GPIO_PORT,LED_4_PIN);
     capture = TIM_GetCapture4(GPO_TIMER2);
@@ -226,7 +199,7 @@ void GPO_TIMER3_IRQHandler(void)
   {
     TIM_ClearITPendingBit(GPO_TIMER3,TIM_IT_CC1);
     if(GPIO_ReadOutputDataBit(LED_6_R_GPIO_PORT,LED_6_R_PIN))
-      GPIO_ResetBits(LED_6_R_GPIO_PORT,LED_6_R_PIN);
+      HAL_GPIO_WritePin(LED_6_R_GPIO_PORT,LED_6_R_PIN);
     else
       GPIO_SetBits(LED_6_R_GPIO_PORT,LED_6_R_PIN);
     capture = TIM_GetCapture1(GPO_TIMER3);
@@ -236,7 +209,7 @@ void GPO_TIMER3_IRQHandler(void)
   {
     TIM_ClearITPendingBit(GPO_TIMER3,TIM_IT_CC2);
     if(GPIO_ReadOutputDataBit(LED_6_G_GPIO_PORT,LED_6_G_PIN))
-      GPIO_ResetBits(LED_6_G_GPIO_PORT,LED_6_G_PIN);
+      HAL_GPIO_WritePin(LED_6_G_GPIO_PORT,LED_6_G_PIN);
     else
       GPIO_SetBits(LED_6_G_GPIO_PORT,LED_6_G_PIN);
     capture = TIM_GetCapture2(GPO_TIMER3);
@@ -246,13 +219,13 @@ void GPO_TIMER3_IRQHandler(void)
   {
     TIM_ClearITPendingBit(GPO_TIMER3,TIM_IT_CC3);
     if(GPIO_ReadOutputDataBit(LED_6_B_GPIO_PORT,LED_6_B_PIN))
-      GPIO_ResetBits(LED_6_B_GPIO_PORT,LED_6_B_PIN);
+      HAL_GPIO_WritePin(LED_6_B_GPIO_PORT,LED_6_B_PIN);
     else
       GPIO_SetBits(LED_6_B_GPIO_PORT,LED_6_B_PIN);
     capture = TIM_GetCapture3(GPO_TIMER3);
     TIM_SetCompare3(GPO_TIMER3, capture + led_6_B_period);
   }
-}
+}*/
 
 // private functions
 
@@ -260,61 +233,68 @@ void GPO_TIMER3_IRQHandler(void)
 void gpio_init(void)
 {
   GPIO_InitTypeDef GPIO_InitStructure;
-  TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
-  NVIC_InitTypeDef NVIC_InitStructure;
-  EXTI_InitTypeDef EXTI_InitStructure;
 
   /* enable clocks */
-  RCC_APB2PeriphClockCmd(LED_RX_GPIO_CLK | LED_TX_GPIO_CLK | LED_2_GPIO_CLK | LED_3_GPIO_CLK | LED_4_GPIO_CLK | 
-                         LED_5_R_GPIO_CLK | LED_5_G_GPIO_CLK | LED_5_B_GPIO_CLK | LED_6_R_GPIO_CLK | LED_6_G_GPIO_CLK | 
-                         LED_6_B_GPIO_CLK, ENABLE);
-  RCC_APB2PeriphClockCmd(START_PB_GPIO_CLK | MODE_PB_GPIO_CLK, ENABLE);
-  RCC_APB1PeriphClockCmd(GPO_TIMER1_CLK | GPO_TIMER2_CLK | GPO_TIMER3_CLK,ENABLE);
-  RCC_APB1PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
+  ENABLE_LED_RX_GPIO_CLK;
+  ENABLE_LED_TX_GPIO_CLK;
+  ENABLE_LED_2_GPIO_CLK;
+  ENABLE_LED_3_GPIO_CLK;
+  ENABLE_LED_4_GPIO_CLK;
+  ENABLE_LED_5_R_GPIO_CLK;
+  ENABLE_LED_5_G_GPIO_CLK;
+  ENABLE_LED_5_B_GPIO_CLK;
+  ENABLE_LED_6_R_GPIO_CLK;
+  ENABLE_LED_6_G_GPIO_CLK;
+  ENABLE_LED_6_B_GPIO_CLK;
+  ENABLE_START_PB_GPIO_CLK;
+  ENABLE_MODE_PB_GPIO_CLK;
+  ENABLE_GPO_TIMER1_CLK;
+  ENABLE_GPO_TIMER2_CLK;
+  ENABLE_GPO_TIMER3_CLK;
 
   /* GPIO Configuration */
-  GPIO_InitStructure.GPIO_Pin = LED_RX_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(LED_RX_GPIO_PORT, &GPIO_InitStructure);
+  GPIO_InitStructure.Pin = LED_RX_PIN;
+  GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
+  HAL_GPIO_Init(LED_RX_GPIO_PORT, &GPIO_InitStructure);
      
-  GPIO_InitStructure.GPIO_Pin = LED_TX_PIN;
-  GPIO_Init(LED_TX_GPIO_PORT, &GPIO_InitStructure);
+  GPIO_InitStructure.Pin = LED_TX_PIN;
+  HAL_GPIO_Init(LED_TX_GPIO_PORT, &GPIO_InitStructure);
 
-  GPIO_InitStructure.GPIO_Pin = LED_2_PIN;
-  GPIO_Init(LED_2_GPIO_PORT, &GPIO_InitStructure);
+  GPIO_InitStructure.Pin = LED_2_PIN;
+  HAL_GPIO_Init(LED_2_GPIO_PORT, &GPIO_InitStructure);
 
-  GPIO_InitStructure.GPIO_Pin = LED_3_PIN;
-  GPIO_Init(LED_3_GPIO_PORT, &GPIO_InitStructure);
+  GPIO_InitStructure.Pin = LED_3_PIN;
+  HAL_GPIO_Init(LED_3_GPIO_PORT, &GPIO_InitStructure);
 
-  GPIO_InitStructure.GPIO_Pin = LED_4_PIN;
-  GPIO_Init(LED_4_GPIO_PORT, &GPIO_InitStructure);
+  GPIO_InitStructure.Pin = LED_4_PIN;
+  HAL_GPIO_Init(LED_4_GPIO_PORT, &GPIO_InitStructure);
 
-  GPIO_InitStructure.GPIO_Pin = LED_5_R_PIN;
-  GPIO_Init(LED_5_R_GPIO_PORT, &GPIO_InitStructure);
+  GPIO_InitStructure.Pin = LED_5_R_PIN;
+  HAL_GPIO_Init(LED_5_R_GPIO_PORT, &GPIO_InitStructure);
 
-  GPIO_InitStructure.GPIO_Pin = LED_5_G_PIN;
-  GPIO_Init(LED_5_G_GPIO_PORT, &GPIO_InitStructure);
+  GPIO_InitStructure.Pin = LED_5_G_PIN;
+  HAL_GPIO_Init(LED_5_G_GPIO_PORT, &GPIO_InitStructure);
 
-  GPIO_InitStructure.GPIO_Pin = LED_5_B_PIN;
-  GPIO_Init(LED_5_B_GPIO_PORT, &GPIO_InitStructure);
+  GPIO_InitStructure.Pin = LED_5_B_PIN;
+  HAL_GPIO_Init(LED_5_B_GPIO_PORT, &GPIO_InitStructure);
 
-  GPIO_InitStructure.GPIO_Pin = LED_6_R_PIN;
-  GPIO_Init(LED_6_G_GPIO_PORT, &GPIO_InitStructure);
+  GPIO_InitStructure.Pin = LED_6_R_PIN;
+  HAL_GPIO_Init(LED_6_G_GPIO_PORT, &GPIO_InitStructure);
 
-  GPIO_InitStructure.GPIO_Pin = LED_6_G_PIN;
-  GPIO_Init(LED_6_G_GPIO_PORT, &GPIO_InitStructure);
+  GPIO_InitStructure.Pin = LED_6_G_PIN;
+  HAL_GPIO_Init(LED_6_G_GPIO_PORT, &GPIO_InitStructure);
 
-  GPIO_InitStructure.GPIO_Pin = LED_6_B_PIN;
-  GPIO_Init(LED_6_B_GPIO_PORT, &GPIO_InitStructure);
+  GPIO_InitStructure.Pin = LED_6_B_PIN;
+  HAL_GPIO_Init(LED_6_B_GPIO_PORT, &GPIO_InitStructure);
 
-  GPIO_InitStructure.GPIO_Pin = START_PB_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(START_PB_GPIO_PORT, &GPIO_InitStructure);
+  GPIO_InitStructure.Pin = START_PB_PIN;
+  GPIO_InitStructure.Mode = GPIO_MODE_IT_FALLING;
+  GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
+  HAL_GPIO_Init(START_PB_GPIO_PORT, &GPIO_InitStructure);
 
-  GPIO_InitStructure.GPIO_Pin = MODE_PB_PIN;
-  GPIO_Init(MODE_PB_GPIO_PORT, &GPIO_InitStructure);
+  GPIO_InitStructure.Pin = MODE_PB_PIN;
+  HAL_GPIO_Init(MODE_PB_GPIO_PORT, &GPIO_InitStructure);
 
   // initialize private variables
   led_rx_period=0;
@@ -332,68 +312,47 @@ void gpio_init(void)
   mode_pb_callback=0;
 
   // initialize the timer interrupts
-  NVIC_InitStructure.NVIC_IRQChannel = GPO_TIMER1_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 3;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
+  HAL_NVIC_SetPriority(GPO_TIMER1_IRQn, 3, 1);
+  HAL_NVIC_EnableIRQ(GPO_TIMER1_IRQn);
 
   /* LED's timer configuration */
-  TIM_TimeBaseStructure.TIM_Period = 0xFFFF;
-  TIM_TimeBaseStructure.TIM_Prescaler = 0;
-  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
-  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-  TIM_TimeBaseInit(GPO_TIMER1,&TIM_TimeBaseStructure);
-  TIM_Cmd(GPO_TIMER1, ENABLE);
-  TIM_PrescalerConfig(GPO_TIMER1, 36000, TIM_PSCReloadMode_Immediate);
-  TIM_SetClockDivision(GPO_TIMER1,TIM_CKD_DIV2);
+  GPO_TIM1Handle.Instance=GPO_TIMER1;
+  GPO_TIM1Handle.Init.Period = 0xFFFF;
+  GPO_TIM1Handle.Init.Prescaler = 36000;
+  GPO_TIM1Handle.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2;
+  GPO_TIM1Handle.Init.CounterMode = TIM_COUNTERMODE_UP;
+  GPO_TIM1Handle.Init.RepetitionCounter=0;
+  HAL_TIM_OC_Init(&GPO_TIM1Handle);
 
   // initialize the timer interrupts
-  NVIC_InitStructure.NVIC_IRQChannel = GPO_TIMER2_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 3;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
+  HAL_NVIC_SetPriority(GPO_TIMER2_IRQn, 3, 2);
+  HAL_NVIC_EnableIRQ(GPO_TIMER2_IRQn);
 
   /* LED's timer configuration */
-  TIM_TimeBaseStructure.TIM_Period = 0xFFFF;
-  TIM_TimeBaseStructure.TIM_Prescaler = 0;
-  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
-  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-  TIM_TimeBaseInit(GPO_TIMER2,&TIM_TimeBaseStructure);
-  TIM_Cmd(GPO_TIMER2, ENABLE);
-  TIM_PrescalerConfig(GPO_TIMER2, 36000, TIM_PSCReloadMode_Immediate);
-  TIM_SetClockDivision(GPO_TIMER2,TIM_CKD_DIV2);
+  GPO_TIM2Handle.Instance=GPO_TIMER2;
+  GPO_TIM2Handle.Init.Period = 0xFFFF;
+  GPO_TIM2Handle.Init.Prescaler = 36000;
+  GPO_TIM2Handle.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2;
+  GPO_TIM2Handle.Init.CounterMode = TIM_COUNTERMODE_UP;
+  GPO_TIM2Handle.Init.RepetitionCounter=0;
+  HAL_TIM_OC_Init(&GPO_TIM2Handle);
 
   // initialize the timer interrupts
-  NVIC_InitStructure.NVIC_IRQChannel = GPO_TIMER3_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 3;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
+  HAL_NVIC_SetPriority(GPO_TIMER3_IRQn, 3, 3);
+  HAL_NVIC_EnableIRQ(GPO_TIMER3_IRQn);
 
   /* LED's timer configuration */
-  TIM_TimeBaseStructure.TIM_Period = 0xFFFF;
-  TIM_TimeBaseStructure.TIM_Prescaler = 0;
-  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
-  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-  TIM_TimeBaseInit(GPO_TIMER3,&TIM_TimeBaseStructure);
-  TIM_Cmd(GPO_TIMER3, ENABLE);
-  TIM_PrescalerConfig(GPO_TIMER3, 36000, TIM_PSCReloadMode_Immediate);
-  TIM_SetClockDivision(GPO_TIMER3,TIM_CKD_DIV2);
-
-  /* configure external interrupts */
-  EXTI_InitStructure.EXTI_Line = START_PB_EXTI_LINE | MODE_PB_EXTI_LINE;
-  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
-  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
-  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
-  EXTI_Init(&EXTI_InitStructure);
-
-  NVIC_InitStructure.NVIC_IRQChannel = GPI_EXTI1_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
+  GPO_TIM3Handle.Instance=GPO_TIMER3;
+  GPO_TIM3Handle.Init.Period = 0xFFFF;
+  GPO_TIM3Handle.Init.Prescaler = 36000;
+  GPO_TIM3Handle.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2;
+  GPO_TIM3Handle.Init.CounterMode = TIM_COUNTERMODE_UP;
+  GPO_TIM3Handle.Init.RepetitionCounter=0;
+  HAL_TIM_OC_Init(&GPO_TIM3Handle);
+
+  /* enable external interrupts */
+  HAL_NVIC_SetPriority(GPI_EXTI1_IRQn, 2, 3);
+  HAL_NVIC_EnableIRQ(GPI_EXTI1_IRQn);
 
   // turn off all leds
   gpio_clear_led(LED_TX);
@@ -414,42 +373,42 @@ void gpio_set_led(led_t led_id)
   switch(led_id)
   {
     case LED_TX:
-      GPIO_ResetBits(LED_TX_GPIO_PORT,LED_TX_PIN);
+      HAL_GPIO_WritePin(LED_TX_GPIO_PORT,LED_TX_PIN,GPIO_PIN_RESET);
       ram_set_bit(DARWIN_LED_PANNEL,3);
       break;
     case LED_RX:
-      GPIO_ResetBits(LED_RX_GPIO_PORT,LED_RX_PIN);
+      HAL_GPIO_WritePin(LED_RX_GPIO_PORT,LED_RX_PIN,GPIO_PIN_RESET);
       ram_set_bit(DARWIN_LED_PANNEL,4);
       break;
     case LED_2:
-      GPIO_ResetBits(LED_2_GPIO_PORT,LED_2_PIN);
+      HAL_GPIO_WritePin(LED_2_GPIO_PORT,LED_2_PIN,GPIO_PIN_RESET);
       ram_set_bit(DARWIN_LED_PANNEL,0);
       break;
     case LED_3:
-      GPIO_ResetBits(LED_3_GPIO_PORT,LED_3_PIN);
+      HAL_GPIO_WritePin(LED_3_GPIO_PORT,LED_3_PIN,GPIO_PIN_RESET);
       ram_set_bit(DARWIN_LED_PANNEL,1);
       break;
     case LED_4:
-      GPIO_ResetBits(LED_4_GPIO_PORT,LED_4_PIN);
+      HAL_GPIO_WritePin(LED_4_GPIO_PORT,LED_4_PIN,GPIO_PIN_RESET);
       ram_set_bit(DARWIN_LED_PANNEL,2);
       break;
     case LED_5_R:
-      GPIO_ResetBits(LED_5_R_GPIO_PORT,LED_5_R_PIN);
+      HAL_GPIO_WritePin(LED_5_R_GPIO_PORT,LED_5_R_PIN,GPIO_PIN_RESET);
       break;
     case LED_5_G:
-      GPIO_ResetBits(LED_5_G_GPIO_PORT,LED_5_G_PIN);
+      HAL_GPIO_WritePin(LED_5_G_GPIO_PORT,LED_5_G_PIN,GPIO_PIN_RESET);
       break;
     case LED_5_B:
-      GPIO_ResetBits(LED_5_B_GPIO_PORT,LED_5_B_PIN);
+      HAL_GPIO_WritePin(LED_5_B_GPIO_PORT,LED_5_B_PIN,GPIO_PIN_RESET);
       break;
     case LED_6_R:
-      GPIO_ResetBits(LED_6_R_GPIO_PORT,LED_6_R_PIN);
+      HAL_GPIO_WritePin(LED_6_R_GPIO_PORT,LED_6_R_PIN,GPIO_PIN_RESET);
       break;
     case LED_6_G:
-      GPIO_ResetBits(LED_6_G_GPIO_PORT,LED_6_G_PIN);
+      HAL_GPIO_WritePin(LED_6_G_GPIO_PORT,LED_6_G_PIN,GPIO_PIN_RESET);
       break;
     case LED_6_B:
-      GPIO_ResetBits(LED_6_B_GPIO_PORT,LED_6_B_PIN);
+      HAL_GPIO_WritePin(LED_6_B_GPIO_PORT,LED_6_B_PIN,GPIO_PIN_RESET);
       break;
   }
 }
@@ -459,42 +418,42 @@ void gpio_clear_led(led_t led_id)
   switch(led_id)
   {
     case LED_TX:
-      GPIO_SetBits(LED_TX_GPIO_PORT,LED_TX_PIN);
+      HAL_GPIO_WritePin(LED_TX_GPIO_PORT,LED_TX_PIN,GPIO_PIN_SET);
       ram_clear_bit(DARWIN_LED_PANNEL,3);
       break;
     case LED_RX:
-      GPIO_SetBits(LED_RX_GPIO_PORT,LED_RX_PIN);
+      HAL_GPIO_WritePin(LED_RX_GPIO_PORT,LED_RX_PIN,GPIO_PIN_SET);
       ram_clear_bit(DARWIN_LED_PANNEL,4);
       break;
     case LED_2:
-      GPIO_SetBits(LED_2_GPIO_PORT,LED_2_PIN);
+      HAL_GPIO_WritePin(LED_2_GPIO_PORT,LED_2_PIN,GPIO_PIN_SET);
       ram_clear_bit(DARWIN_LED_PANNEL,0);
       break;
     case LED_3:
-      GPIO_SetBits(LED_3_GPIO_PORT,LED_3_PIN);
+      HAL_GPIO_WritePin(LED_3_GPIO_PORT,LED_3_PIN,GPIO_PIN_SET);
       ram_clear_bit(DARWIN_LED_PANNEL,1);
       break;
     case LED_4:
-      GPIO_SetBits(LED_4_GPIO_PORT,LED_4_PIN);
+      HAL_GPIO_WritePin(LED_4_GPIO_PORT,LED_4_PIN,GPIO_PIN_SET);
       ram_clear_bit(DARWIN_LED_PANNEL,2);
       break;
     case LED_5_R:
-      GPIO_SetBits(LED_5_R_GPIO_PORT,LED_5_R_PIN);
+      HAL_GPIO_WritePin(LED_5_R_GPIO_PORT,LED_5_R_PIN,GPIO_PIN_SET);
       break;
     case LED_5_G:
-      GPIO_SetBits(LED_5_G_GPIO_PORT,LED_5_G_PIN);
+      HAL_GPIO_WritePin(LED_5_G_GPIO_PORT,LED_5_G_PIN,GPIO_PIN_SET);
       break;
     case LED_5_B:
-      GPIO_SetBits(LED_5_B_GPIO_PORT,LED_5_B_PIN);
+      HAL_GPIO_WritePin(LED_5_B_GPIO_PORT,LED_5_B_PIN,GPIO_PIN_SET);
       break;
     case LED_6_R:
-      GPIO_SetBits(LED_6_R_GPIO_PORT,LED_6_R_PIN);
+      HAL_GPIO_WritePin(LED_6_R_GPIO_PORT,LED_6_R_PIN,GPIO_PIN_SET);
       break;
     case LED_6_G:
-      GPIO_SetBits(LED_6_G_GPIO_PORT,LED_6_G_PIN);
+      HAL_GPIO_WritePin(LED_6_G_GPIO_PORT,LED_6_G_PIN,GPIO_PIN_SET);
       break;
     case LED_6_B:
-      GPIO_SetBits(LED_6_B_GPIO_PORT,LED_6_B_PIN);
+      HAL_GPIO_WritePin(LED_6_B_GPIO_PORT,LED_6_B_PIN,GPIO_PIN_SET);
       break;
   }
 }
@@ -504,141 +463,94 @@ void gpio_toggle_led(led_t led_id)
   switch(led_id)
   {
     case LED_TX:
-      if(GPIO_ReadOutputDataBit(LED_TX_GPIO_PORT,LED_TX_PIN))
-        GPIO_ResetBits(LED_TX_GPIO_PORT,LED_TX_PIN);
-      else
-        GPIO_SetBits(LED_TX_GPIO_PORT,LED_TX_PIN);
+      HAL_GPIO_TogglePin(LED_TX_GPIO_PORT,LED_TX_PIN);
       break;
     case LED_RX:
-      if(GPIO_ReadOutputDataBit(LED_RX_GPIO_PORT,LED_RX_PIN))
-        GPIO_ResetBits(LED_RX_GPIO_PORT,LED_RX_PIN);
-      else
-        GPIO_SetBits(LED_RX_GPIO_PORT,LED_RX_PIN);
+      HAL_GPIO_TogglePin(LED_RX_GPIO_PORT,LED_RX_PIN);
       break;
     case LED_2:
-      if(GPIO_ReadOutputDataBit(LED_2_GPIO_PORT,LED_2_PIN))
-        GPIO_ResetBits(LED_2_GPIO_PORT,LED_2_PIN);
-      else
-        GPIO_SetBits(LED_2_GPIO_PORT,LED_2_PIN);
+      HAL_GPIO_TogglePin(LED_2_GPIO_PORT,LED_2_PIN);
       break;
     case LED_3:
-      if(GPIO_ReadOutputDataBit(LED_3_GPIO_PORT,LED_3_PIN))
-        GPIO_ResetBits(LED_3_GPIO_PORT,LED_3_PIN);
-      else
-        GPIO_SetBits(LED_3_GPIO_PORT,LED_3_PIN);
+      HAL_GPIO_TogglePin(LED_3_GPIO_PORT,LED_3_PIN);
       break;
     case LED_4:
-      if(GPIO_ReadOutputDataBit(LED_4_GPIO_PORT,LED_4_PIN))
-        GPIO_ResetBits(LED_4_GPIO_PORT,LED_4_PIN);
-      else
-        GPIO_SetBits(LED_4_GPIO_PORT,LED_4_PIN);
+      HAL_GPIO_TogglePin(LED_4_GPIO_PORT,LED_4_PIN);
       break;
     case LED_5_R:
-      if(GPIO_ReadOutputDataBit(LED_5_R_GPIO_PORT,LED_5_R_PIN))
-        GPIO_ResetBits(LED_5_R_GPIO_PORT,LED_5_R_PIN);
-      else
-        GPIO_SetBits(LED_5_R_GPIO_PORT,LED_5_R_PIN);
+      HAL_GPIO_TogglePin(LED_5_R_GPIO_PORT,LED_5_R_PIN);
       break;
     case LED_5_G:
-      if(GPIO_ReadOutputDataBit(LED_5_G_GPIO_PORT,LED_5_G_PIN))
-        GPIO_ResetBits(LED_5_G_GPIO_PORT,LED_5_G_PIN);
-      else
-        GPIO_SetBits(LED_5_G_GPIO_PORT,LED_5_G_PIN);
+      HAL_GPIO_TogglePin(LED_5_G_GPIO_PORT,LED_5_G_PIN);
       break;
     case LED_5_B:
-      if(GPIO_ReadOutputDataBit(LED_5_B_GPIO_PORT,LED_5_B_PIN))
-        GPIO_ResetBits(LED_5_B_GPIO_PORT,LED_5_B_PIN);
-      else
-        GPIO_SetBits(LED_5_B_GPIO_PORT,LED_5_B_PIN);
+      HAL_GPIO_TogglePin(LED_5_B_GPIO_PORT,LED_5_B_PIN);
       break;
     case LED_6_R:
-      if(GPIO_ReadOutputDataBit(LED_6_R_GPIO_PORT,LED_6_R_PIN))
-        GPIO_ResetBits(LED_6_R_GPIO_PORT,LED_6_R_PIN);
-      else
-        GPIO_SetBits(LED_6_R_GPIO_PORT,LED_6_R_PIN);
+      HAL_GPIO_TogglePin(LED_6_R_GPIO_PORT,LED_6_R_PIN);
       break;
     case LED_6_G:
-      if(GPIO_ReadOutputDataBit(LED_6_G_GPIO_PORT,LED_6_G_PIN))
-        GPIO_ResetBits(LED_6_G_GPIO_PORT,LED_6_G_PIN);
-      else
-        GPIO_SetBits(LED_6_G_GPIO_PORT,LED_6_G_PIN);
+      HAL_GPIO_TogglePin(LED_6_G_GPIO_PORT,LED_6_G_PIN);
       break;
     case LED_6_B:
-      if(GPIO_ReadOutputDataBit(LED_6_B_GPIO_PORT,LED_6_B_PIN))
-        GPIO_ResetBits(LED_6_B_GPIO_PORT,LED_6_B_PIN);
-      else
-        GPIO_SetBits(LED_6_B_GPIO_PORT,LED_6_B_PIN);
+      HAL_GPIO_TogglePin(LED_6_B_GPIO_PORT,LED_6_B_PIN);
       break;
   }
 }
 
 void gpio_blink_led(led_t led_id, int16_t period_ms)
 {
-  TIM_OCInitTypeDef  TIM_OCInitStructure;
-  uint16_t capture;
+  TIM_OC_InitTypeDef TIM_OCInitStructure;
 
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Disable;
-  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
+  TIM_OCInitStructure.OCMode = TIM_OCMODE_TIMING;
+  TIM_OCInitStructure.OCPolarity = TIM_OCPOLARITY_HIGH;
   switch(led_id)
   {
     case LED_TX:
       if(period_ms>1)
       {
         led_tx_period=period_ms;
-        TIM_OCInitStructure.TIM_Pulse = led_tx_period;
-        TIM_OC1Init(GPO_TIMER1, &TIM_OCInitStructure);
-        TIM_OC1PreloadConfig(GPO_TIMER1, TIM_OCPreload_Disable);
-        capture = TIM_GetCounter(GPO_TIMER1);
-        TIM_SetCompare1(GPO_TIMER1, capture + led_tx_period);
-        TIM_ITConfig(GPO_TIMER1, TIM_IT_CC1, ENABLE);
+        TIM_OCInitStructure.Pulse = led_tx_period;
+        HAL_TIM_OC_ConfigChannel(&GPO_TIM1Handle, &TIM_OCInitStructure,TIM_CHANNEL_1);
+        HAL_TIM_OC_Start_IT(&GPO_TIM1Handle, TIM_CHANNEL_1);
       }
       else
-        TIM_ITConfig(GPO_TIMER1, TIM_IT_CC1, DISABLE);
+        HAL_TIM_OC_Stop_IT(&GPO_TIM1Handle, TIM_CHANNEL_1);
       break;
     case LED_RX:
       if(period_ms>1)
       {
         led_rx_period=period_ms;
-        TIM_OCInitStructure.TIM_Pulse = led_rx_period;
-        TIM_OC2Init(GPO_TIMER1, &TIM_OCInitStructure);
-        TIM_OC2PreloadConfig(GPO_TIMER1, TIM_OCPreload_Disable);
-        capture = TIM_GetCounter(GPO_TIMER1);
-        TIM_SetCompare2(GPO_TIMER1, capture + led_rx_period);
-        TIM_ITConfig(GPO_TIMER1, TIM_IT_CC2, ENABLE);
+        TIM_OCInitStructure.Pulse = led_rx_period;
+        HAL_TIM_OC_ConfigChannel(&GPO_TIM1Handle, &TIM_OCInitStructure,TIM_CHANNEL_2);
+        HAL_TIM_OC_Start_IT(&GPO_TIM1Handle, TIM_CHANNEL_2);
       }
       else
-        TIM_ITConfig(GPO_TIMER1, TIM_IT_CC2, DISABLE);
+        HAL_TIM_OC_Stop_IT(&GPO_TIM1Handle, TIM_CHANNEL_2);
       break;
     case LED_2:
       if(period_ms>1)
       {
         led_2_period=period_ms;
-        TIM_OCInitStructure.TIM_Pulse = led_2_period;
-        TIM_OC3Init(GPO_TIMER1, &TIM_OCInitStructure);
-        TIM_OC3PreloadConfig(GPO_TIMER1, TIM_OCPreload_Disable);
-        capture = TIM_GetCounter(GPO_TIMER1);
-        TIM_SetCompare3(GPO_TIMER1, capture + led_2_period);
-        TIM_ITConfig(GPO_TIMER1, TIM_IT_CC3, ENABLE);
+        TIM_OCInitStructure.Pulse = led_2_period;
+        HAL_TIM_OC_ConfigChannel(&GPO_TIM1Handle, &TIM_OCInitStructure,TIM_CHANNEL_3);
+        HAL_TIM_OC_Start_IT(&GPO_TIM1Handle, TIM_CHANNEL_3);
       }
       else
-        TIM_ITConfig(GPO_TIMER1, TIM_IT_CC3, DISABLE);
+        HAL_TIM_OC_Stop_IT(&GPO_TIM1Handle, TIM_CHANNEL_3);
       break;
     case LED_3:
       if(period_ms>1)
       {
         led_3_period=period_ms;
-        TIM_OCInitStructure.TIM_Pulse = led_3_period;
-        TIM_OC4Init(GPO_TIMER1, &TIM_OCInitStructure);
-        TIM_OC4PreloadConfig(GPO_TIMER1, TIM_OCPreload_Disable);
-        capture = TIM_GetCounter(GPO_TIMER1);
-        TIM_SetCompare4(GPO_TIMER1, capture + led_3_period);
-        TIM_ITConfig(GPO_TIMER1, TIM_IT_CC4, ENABLE);
+        TIM_OCInitStructure.Pulse = led_3_period;
+        HAL_TIM_OC_ConfigChannel(&GPO_TIM1Handle, &TIM_OCInitStructure,TIM_CHANNEL_4);
+        HAL_TIM_OC_Start_IT(&GPO_TIM1Handle, TIM_CHANNEL_4);
       }
       else
-        TIM_ITConfig(GPO_TIMER1, TIM_IT_CC4, DISABLE);
+        HAL_TIM_OC_Stop_IT(&GPO_TIM1Handle, TIM_CHANNEL_4);
       break;
-    case LED_4:
+/*    case LED_4:
       if(period_ms>1)
       {
         led_4_period=period_ms;
@@ -735,12 +647,12 @@ void gpio_blink_led(led_t led_id, int16_t period_ms)
       }
       else
         TIM_ITConfig(GPO_TIMER3, TIM_IT_CC3, DISABLE);
-      break;
+      break;*/
     default: break;
   }
 }
 
-uint8_t gpio_is_pushbutton_pressed(pushbutton_t pb_id)
+/*uint8_t gpio_is_pushbutton_pressed(pushbutton_t pb_id)
 {
   switch(pb_id)
   {
@@ -772,4 +684,4 @@ void gpio_set_pushbutton_callback(pushbutton_t pb_id,void (*callback)(void))
       mode_pb_callback=callback;
       break;
   }
-}
+}*/
diff --git a/src/ram.c b/src/ram.c
index 65cf3bc6a3ffc215f9179f2d3f102e573a79d72e..521d8f821541cc9b73a081284e91c8f3afe5dfd8 100755
--- a/src/ram.c
+++ b/src/ram.c
@@ -9,7 +9,7 @@ void ram_init(void)
   for(i=0;i<RAM_SIZE;i++)
     ram_data[i]=0x00;
   // read contents from EEPROM to RAM
-  if(EE_ReadVariable(DEVICE_MODEL_OFFSET,&eeprom_data)==0)
+/*  if(EE_ReadVariable(DEVICE_MODEL_OFFSET,&eeprom_data)==0)
     ram_data[DEVICE_MODEL_OFFSET]=(uint8_t)(eeprom_data&0x00FF);
   if(EE_ReadVariable(DEVICE_MODEL_OFFSET+1,&eeprom_data)==0)
     ram_data[DEVICE_MODEL_OFFSET+1]=(uint8_t)(eeprom_data&0x00FF);
@@ -26,7 +26,7 @@ void ram_init(void)
   if(EE_ReadVariable(MM_PERIOD_OFFSET+1,&eeprom_data)==0)
     ram_data[MM_PERIOD_OFFSET+1]=(uint8_t)eeprom_data;
   if(EE_ReadVariable(RETURN_LEVEL_OFFSET,&eeprom_data)==0)
-    ram_data[RETURN_LEVEL_OFFSET]=(uint8_t)eeprom_data;
+    ram_data[RETURN_LEVEL_OFFSET]=(uint8_t)eeprom_data;*/
 }
 
 inline void ram_read_byte(uint8_t address,uint8_t *data)
diff --git a/src/stm32f1xx_hal_msp.c b/src/stm32f1xx_hal_msp.c
new file mode 100755
index 0000000000000000000000000000000000000000..1997e3bfc43114d24943e1d2686fbf100326b3fa
--- /dev/null
+++ b/src/stm32f1xx_hal_msp.c
@@ -0,0 +1,151 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_msp_template.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    15-December-2014
+  * @brief   HAL BSP module.
+  *          This file template is located in the HAL folder and should be copied 
+  *          to the user folder.
+  *         
+  @verbatim
+ ===============================================================================
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..]
+    This file is generated automatically by MicroXplorer and eventually modified 
+    by the user
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL_MSP HAL_MSP
+  * @brief HAL MSP module.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_MSP_Exported_Functions HAL MSP Exported Functions
+  * @{
+  */
+
+/**
+  * @brief  Initializes the Global MSP.
+  * @retval None
+  */
+void HAL_MspInit(void)
+{
+  /* NOTE : This function is generated automatically by MicroXplorer and eventually  
+            modified by the user
+   */ 
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  /* Set Interrupt Group Priority */
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_2);// 4 priorities, 4 subpriorities
+
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL2;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
+
+  __HAL_RCC_AFIO_CLK_ENABLE();
+}
+
+/**
+  * @brief  DeInitializes the Global MSP.
+  * @retval None
+  */
+void HAL_MspDeInit(void)
+{
+  /* NOTE : This function is generated automatically by MicroXplorer and eventually  
+            modified by the user
+   */
+}
+
+/**
+  * @brief  Initializes the PPP MSP.
+  * @retval None
+  */
+void HAL_PPP_MspInit(void)
+{
+  /* NOTE : This function is generated automatically by MicroXplorer and eventually  
+            modified by the user
+   */ 
+}
+
+/**
+  * @brief  DeInitializes the PPP MSP.
+  * @retval None
+  */
+void HAL_PPP_MspDeInit(void)
+{
+  /* NOTE : This function is generated automatically by MicroXplorer and eventually  
+            modified by the user
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/src/system_stm32f10x.c b/src/system_stm32f10x.c
deleted file mode 100755
index 315aac734d3c6c55ca81573907a31e20c086fef0..0000000000000000000000000000000000000000
--- a/src/system_stm32f10x.c
+++ /dev/null
@@ -1,1097 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x3000 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-
-  /* Configure the NVIC Preemption Priority Bits */
-  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *         and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *         and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *         and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *         and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *         and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *         and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/